Sic power MOS device and manufacturing method therefor

Abstract

The present invention provides a SiC power MOS device and a manufacturing method therefor. The SiC power MOS device comprises a semiconductor layer, a body area, source areas, contact areas, trenches, a shielding layer, a gate dielectric layer, a gate conductive layer, an interlayer dielectric layer, and electrodes, wherein the semiconductor layer comprises a current transport layer; the body area is located on the upper surface layer of the current transport layer; the source areas and the contact areas are located on the upper surface layer of the body area; the trenches run through the source areas and the body area; the contact areas are arranged adjacent to first walls and spaced apart from second walls, respectively; the shielding layer is located in the current transport layer at the bottoms of the trenches; the gate dielectric layer covers the second walls and the bottom surfaces of the trenches; the gate conductive layer covers the surface of the gate dielectric layer on the second walls; the interlayer dielectric layer covers the exposed surface of the gate conductive layer and the exposed surface of the gate dielectric layer; a source contact hole exposing the shielding layer and the first walls is formed in the interlayer dielectric layer; and the source electrode contact hole is filled with a source. According to the present invention, the shielding layer is formed at the bottoms of the trenches, and the source contact hole exposing the first walls and the shielding layer is formed, thereby improving the reliability of the gate dielectric layer.

Description

A SiC power MOS device and its preparation method Technical Field

[0001] The present invention belongs to the field of semiconductor integrated circuit manufacturing and relates to a SiC power MOS device and a preparation method thereof. Background Art

[0002] As a third-generation semiconductor material, silicon carbide (SiC) boasts a wider bandgap, making it an ideal material for power semiconductor devices. Silicon carbide metal oxide semiconductor field-effect transistors (SiC MOSFETs) feature low conduction losses, fast switching speeds, low switching losses, strong radiation resistance, and excellent high-temperature stability, making them a highly anticipated next-generation power semiconductor device. Limited by the high interface state density, the channel electron mobility of SiC power MOSFETs is significantly lower than that of silicon-based devices. For SiC MOSFETs operating at voltages of 650V and 1200V, the channel resistance contributes significantly to the device's overall on-resistance. Therefore, it is necessary to continuously reduce cell size and increase channel density to reduce the channel resistance contribution, thereby lowering the overall on-resistance of the device. Compared to planar-gate SiC MOSFETs, trench-gate SiC MOSFETs, by forming the channel in a vertical direction, can further increase the channel density within the same area, thereby reducing the channel resistance and, in turn, the overall on-resistance of the device.

[0003] However, for trench-gate SiC MOSFET devices, if the oxide layer at the bottom of the trench gate or at the corners is not protected, the oxide field at these locations will exceed 3MV / cm. This high electric field strength can cause gate oxide reliability issues, especially during high-temperature reverse bias (HTRB) testing. Currently, a common approach is to implant a heavily doped P-type region at the bottom of the trench gate to protect the oxide layer at the bottom of the trench gate. However, this P-type region must be grounded; otherwise, the holes in the P-type region will not be effectively replenished during the switching process, which will affect the device's on-resistance. To address this problem, Infineon Technologies has introduced a half-wrapped trench SiC MOSFET that implants a high-concentration P-type region into the bottom half of the gate oxide layer to protect the gate oxide. However, grounding the P-type region at the bottom of the trench requires high-energy ion implantation equipment, which is relatively expensive. Rohm has launched a dual-trench SiC MOSFET, which is divided into a source trench and a gate electrode trench. A P-type region is injected at the bottom of the source trench to protect the gate oxide layer from high electric field strength through the pinch-off effect. However, an additional process is required to etch the source trench during device manufacturing. In addition, since the oxide layer at the bottom of the gate electrode is not directly protected by the P-type region, the long-term reliability of the gate oxide layer also faces huge challenges.

[0004] In addition, due to the wide bandgap of SiC itself, the turn-on voltage of its PN junction diode is about 2.6V, which is much higher than the turn-on voltage of 0.7V of silicon-based PN. This will cause the SiC MOSFET in the half-bridge mode drive circuit to have high power consumption during the dead period. Moreover, since the PN junction is bipolar conductive, a large number of unbalanced carriers will be injected during its conduction process. These carriers will cause large reverse recovery losses during reverse recovery.

[0005] Therefore, there is an urgent need to find a method for preparing a SiC power MOS device that can improve the reliability of the gate dielectric layer of the SiC power MOS device and reduce the reverse recovery loss of the device.

[0006] Summary of the Invention

[0007] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a SiC power MOS device and a preparation method thereof, so as to solve the problems of poor gate dielectric layer reliability and large reverse recovery loss of SiC power MOS devices in the prior art.

[0008] To achieve the above-mentioned and other related objectives, the present invention provides a method for preparing a SiC power MOS device, comprising the following steps:

[0009] Providing a first conductive type semiconductor layer including a substrate, a drift region, and a current transport layer stacked in sequence, and forming a second conductive type body region on the upper surface of the current transport layer;

[0010] forming a plurality of spaced-apart second-conductivity-type contact regions in the body region and a first-conductivity-type source region located on an upper surface of the body region, wherein the contact regions are adjacent to the source regions above the contact regions and are spaced a predetermined distance from a lower surface of the body region;

[0011] forming a plurality of trenches spaced apart and penetrating the source region and the body region, wherein the contact region is adjacent to a first wall of the trench and spaced a preset distance from a second wall of the trench, the first wall and the second wall are disposed opposite each other, and a bottom surface of the trench is located in the current transport layer;

[0012] forming a second conductive type shielding layer in the current transport layer at the bottom of the trench to form a stacked structure covering the first wall and the second wall and including a gate dielectric layer and a gate conductive material layer stacked in sequence, wherein the stacked structures on the first wall and the second wall are separated by a predetermined distance;

[0013] forming an interlayer dielectric layer filling the trench and covering the upper surface of the stacked structure, forming a source contact hole in the interlayer dielectric layer above the trench, the bottom surface of which exposes the shielding layer, the inner wall of the source contact hole exposing the first wall and the interlayer dielectric layer, and the gate conductive material layer wrapped by the interlayer dielectric layer and the gate dielectric layer serving as a gate conductive layer;

[0014] A source electrode filling the source contact hole is formed, a gate electrode electrically connected to the gate conductive layer is formed, and a drain electrode electrically connected to the substrate is formed.

[0015] Optionally, the second wall is a C-plane of the semiconductor layer.

[0016] Optionally, the gate dielectric layer includes a buffer layer and a gate dielectric layer stacked in sequence.

[0017] Optionally, after forming the source contact hole and before forming the source, the method further includes forming a second conductive type doping region located below the contact region on the surface of the body region exposed on the inner wall of the source contact hole and the current transfer layer.

[0018] Optionally, the doping concentration of the doping region is not less than 1×10 18 cm -3 .

[0019] Optionally, the doped region is connected to the shielding layer and the contact region.

[0020] Optionally, a cross-sectional dimension of the source contact hole above the semiconductor layer is not smaller than a cross-sectional dimension of the source contact hole in the trench.

[0021] Optionally, the current transport layer exposed on the inner wall of the source contact hole forms a Schottky contact with the source to form a Schottky diode consisting of the source, the current transport layer, the drift region, the substrate and the drain.

[0022] Optionally, the barrier height of the Schottky diode ranges from 1eV to 1.5eV, and the turn-on voltage of the Schottky diode ranges from 0.7V to 1.2V.

[0023] The present invention also provides a SiC power MOS device, comprising:

[0024] The first conductive type semiconductor layer includes a substrate, a drift region and a current transfer layer stacked in sequence;

[0025] a second conductive type body region, a first conductive type source region, and a second conductive type contact region, wherein the body region is located on an upper surface of the current transmission layer, the source region is located on an upper surface of the body region, and a plurality of spaced contact regions are adjacent to the source region above the contact region and are spaced a preset distance from a lower surface of the body region;

[0026] a plurality of spaced trenches extending through the source region and the body region, wherein the contact region is adjacent to a first wall of the trench and spaced a predetermined distance from a second wall of the trench, the bottom surface of the trench being located in the current transport layer, and the first wall and the second wall being arranged opposite to each other;

[0027] a second conductive type shielding layer located in the current transmission layer at the bottom of the trench;

[0028] a gate dielectric layer, covering the second wall and bottom surface of the trench;

[0029] a gate conductive layer covering a surface of the gate dielectric layer on the second wall;

[0030] an interlayer dielectric layer covering the gate conductive layer and the exposed surface of the gate dielectric layer, wherein a source contact hole having a bottom surface exposing the shielding layer is provided in the interlayer dielectric layer above the trench, and an inner wall of the source contact hole exposing the first wall and the interlayer dielectric layer;

[0031] A source, a gate and a drain, wherein the source fills the source contact hole, the gate is electrically connected to the gate conductive layer, and the drain is electrically connected to the substrate.

[0032] As described above, the SiC power MOS device and the preparation method thereof of the present invention improve the structure of the device. After forming the trench penetrating the source region and the body region and with the bottom surface located in the current transmission layer, the shielding layer is formed in the current transmission layer below the bottom surface of the trench, and the first wall exposes the contact area adjacent to the source region and located below the source region, the contact area is spaced a preset distance from the second wall, the gate dielectric layer covers the second wall and the bottom surface of the trench, the gate conductive layer covers the surface of the gate dielectric layer on the second wall, and the interlayer dielectric layer covers the exposed gate conductive layer. The surface and the upper surface of the semiconductor layer, the source contact hole penetrates the interlayer dielectric layer and the inner wall and bottom surface respectively expose the first wall and the shielding layer, the shielding layer and the current transmission layer exposed in the source contact hole respectively form an ohmic contact and a Schottky contact with the source, the forward voltage applied to the device is borne by the PN junction between the shielding layer and the current transmission layer, so that the area where the current transmission layer and the shielding layer intersect forms a space charge region, so that the current transmission layer above the shielding layer is clamped, thereby realizing protection of the device, and because the voltage in the device is generated by the shielding layer and the current transmission layer The PN junction between the source electrode and the current transport layer is borne by the source electrode, thereby protecting the gate dielectric layer, and then the voltage resistance requirement of the gate dielectric layer can be reduced, thereby reducing the difficulty of the manufacturing process of the gate dielectric layer and improving the reliability of the gate dielectric layer; since the source electrode and the current transport layer exposed in the source contact hole form a Schottky contact, a Schottky diode with a low turn-on voltage composed of the source electrode, the semiconductor layer and the drain electrode is integrated in the device, reducing the size of the device, and at the same time achieving unipolar conductivity of the device, reducing the reverse recovery loss of the device, and the setting of the shielding layer can reduce the electric field strength borne by the Schottky diode, thereby protecting the Schottky diode; by The body region exposed by the source contact hole and the surface layer of the current transfer layer form the doped region, and the doped region forms an ohmic contact with the source, thereby avoiding complete depletion of carriers in the area where the doped region is located, while enhancing the depletion degree of the current transfer layer above the shielding layer, better protecting the device, and the PN junction turn-on voltage between the doped region and the current transfer layer is low, reducing the reverse recovery loss of the device; since the conductive channel of the device is located on the surface layer of the second wall, the cross-section of the conductive channel of the device is the C-plane of the semiconductor layer, which can improve the mobility of electrons in the conductive channel and has high industrial utilization value. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] FIG1 is a process flow chart showing a method for preparing a SiC power MOS device according to the present invention.

[0034] FIG2 is a schematic diagram showing the cross-sectional structure of a semiconductor layer in the method for preparing a SiC power MOS device according to the present invention.

[0035] FIG3 is a schematic diagram showing the cross-sectional structure of the SiC power MOS device after the body region is formed in the method for preparing the SiC power MOS device of the present invention.

[0036] FIG4 is a schematic diagram showing the cross-sectional structure of the SiC power MOS device manufacturing method after forming the source region and the contact region according to the present invention.

[0037] FIG5 is a schematic diagram showing the cross-sectional structure of the SiC power MOS device after the trench is formed in the method for preparing the SiC power MOS device of the present invention.

[0038] FIG6 is a schematic diagram showing the cross-sectional structure of the SiC power MOS device manufacturing method after forming the shielding layer according to the present invention.

[0039] FIG7 is a schematic diagram showing the cross-sectional structure of the SiC power MOS device manufacturing method after forming the gate conductive material layer according to the present invention.

[0040] FIG8 is a schematic diagram showing a cross-sectional structure of a SiC power MOS device after forming a stacked structure according to the method for preparing the SiC power MOS device of the present invention.

[0041] FIG9 is a schematic diagram showing the cross-sectional structure of the SiC power MOS device manufacturing method after forming the interlayer dielectric layer according to the present invention.

[0042] FIG10 is a schematic diagram showing the cross-sectional structure of the SiC power MOS device manufacturing method after forming the source contact hole according to the present invention.

[0043] FIG11 is a schematic diagram showing the cross-sectional structure of the SiC power MOS device after forming the doping region in the method for preparing the SiC power MOS device of the present invention.

[0044] FIG12 is a schematic diagram showing a cross-sectional structure of a SiC power MOS device after forming a drain electrode in the method for preparing the SiC power MOS device of the present invention.

[0045] FIG13 is another schematic diagram showing a cross-sectional structure of a SiC power MOS device after forming a drain electrode in the method for preparing the SiC power MOS device according to the present invention.

[0046] DESCRIPTION OF REFERENCE NUMERALS 1 semiconductor layer 11 substrate 12 drift region 13 current transport layer 14 body region 15 contact region 16 source region 17 shielding layer 18 doped region 2 trench 20 gate conductive material layer 21 gate dielectric layer 22 gate conductive layer 23 stacked structure 3 mask layer 4 interlayer dielectric layer 41 source contact hole 5 source electrode 6 drain electrode DETAILED DESCRIPTION

[0047] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0048] Please refer to Figures 1 to 13. It should be noted that the figures provided in this embodiment are merely schematic illustrations of the basic concept of the present invention. Therefore, the figures only show components relevant to the present invention and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the type, quantity, and proportion of each component may be varied arbitrarily, and the component layout may also be more complex.

[0049] Example 1

[0050] This embodiment provides a method for preparing a SiC power MOS device. FIG1 is a process flow chart of the method for preparing the SiC power MOS device, which includes the following steps:

[0051] S1: providing a first conductive type semiconductor layer including a substrate, a drift region, and a current transport layer stacked in sequence, and forming a second conductive type body region on an upper surface layer of the current transport layer;

[0052] S2: forming a plurality of spaced-apart second-conductivity-type contact regions in the body region and a first-conductivity-type source region located on an upper surface of the body region, wherein the contact regions are adjacent to the source regions above the contact regions and are spaced a predetermined distance from a lower surface of the body region;

[0053] S3: forming a plurality of trenches that are spaced apart and penetrate the source region and the body region, wherein the contact region is adjacent to a first wall of the trench and spaced a preset distance from a second wall of the trench, the first wall and the second wall are arranged opposite to each other, and the bottom surface of the trench is located in the current transport layer;

[0054] S4: forming a second conductive type shielding layer in the current transport layer at the bottom of the trench to form a stacked structure covering the first wall and the second wall and including a gate dielectric layer and a gate conductive material layer stacked in sequence, wherein the stacked structures on the first wall and the second wall are separated by a preset distance;

[0055] S5: forming an interlayer dielectric layer filling the trench and covering the upper surface of the stacked structure, forming a source contact hole in the interlayer dielectric layer above the trench, the bottom surface of which exposes the shielding layer, the inner wall of the source contact hole exposing the first wall and the interlayer dielectric layer, and the gate conductive material layer wrapped by the interlayer dielectric layer and the gate dielectric layer serving as a gate conductive layer;

[0056] S6: forming a source electrode filling the source contact hole, forming a gate electrode electrically connected to the gate conductive layer, and forming a drain electrode electrically connected to the substrate.

[0057] Please refer to Figures 2 to 4, and perform step S1 and step S2: provide a first conductive type semiconductor layer 1 including a substrate 11, a drift region 12 and a current transfer layer 13 stacked in sequence, and form a second conductive type body region 14 on the upper surface of the current transfer layer 13; form a plurality of second conductive type contact regions 15 spaced apart in the body region 14 and a first conductive type source region 16 located on the upper surface of the body region 14, the contact region 15 is adjacent to the source region 16 above the contact region 15 and is spaced a preset distance from the lower surface of the body region 14.

[0058] Specifically, the first conductivity type includes one of N-type doping or P-type doping, the second conductivity type includes one of N-type doping or P-type doping, and the first conductivity type is opposite to the second conductivity type. In this embodiment, the first conductivity type is N-type doping, and the second conductivity type is P-type doping.

[0059] Specifically, as shown in Figure 2, which is a schematic cross-sectional view of the semiconductor layer 1, the semiconductor layer 1 is made of silicon carbide or other suitable semiconductor materials. In this embodiment, a silicon carbide layer is used as the semiconductor layer 1.

[0060] Specifically, the current transport layer 13 may be formed by epitaxial growth on the upper surface of the drift region 12 or by ion implantation on the upper surface of the drift region 12. In this embodiment, the current transport layer 13 is formed by epitaxial growth on the upper surface of the drift region 12.

[0061] Specifically, as shown in Figures 3 and 4, they are schematic diagrams of the cross-sectional structure after the body region 14 is formed and schematic diagrams of the cross-sectional structure after the source region 16 and the contact region 15 are formed, respectively. The method of forming the body region 14 includes ion implantation or other suitable methods; the method of forming the contact region 15 includes ion implantation or other suitable methods; the method of forming the source region 16 includes ion implantation or other suitable methods.

[0062] Specifically, after the body region 14 is formed, the contact region 15 can be formed on the upper surface of the body region 14 first, and then the source region 16 located on the upper surface of the body region 14 is formed. During the formation of the source region 16, the area where the source region 16 and the contact region 15 overlap forms an inversion region; or the source region 16 can be formed first, and then the contact region 15 is formed by using higher energy ion implantation.

[0063] Specifically, the doping concentration of the body region 14 is lower than that of the contact region 15. While ensuring device performance, the thickness and doping concentration of the body region 14 can be selected based on actual conditions and are not subject to further restrictions. The size, thickness, and doping concentration of the contact region 15 can be selected based on actual conditions and are not subject to further restrictions. The distance between two adjacent contact regions 15 can be selected based on actual conditions and are not subject to further restrictions. The thickness and doping concentration of the source region 16 can be selected based on actual conditions and are not subject to further restrictions. The thickness here refers to the distance between the upper and lower surfaces of each region.

[0064] Specifically, while ensuring device performance, the distance between the lower surface of the contact region 15 and the lower surface of the body region 14 can be selected according to actual conditions and is not limited here.

[0065] Please refer to Figures 5 to 8 again, and perform step S3 and step S4: form a plurality of trenches 2 that are spaced apart and penetrate the source region 16 and the body region 14, the contact region 15 is adjacent to the first wall (not shown) of the trench 2 and is spaced apart from the second wall (not shown) of the trench 2 by a preset distance, the first wall and the second wall are arranged opposite to each other, and the bottom surface of the trench 2 is located in the current transfer layer 13; a second conductive type shielding layer 17 is formed in the current transfer layer 13 at the bottom of the trench 2, forming a stacked structure 23 covering the first wall and the second wall and including a gate dielectric layer 21 and a gate conductive material layer 20 stacked in sequence, and the stacked structure 23 on the first wall and the second wall is spaced apart by a preset distance. It should be noted that the source region 16 before the formation of the trench 2 can be understood as the source region layer, and the body region 14 before the formation of the trench 2 can be understood as the body region layer. The source region layer and the body region layer are penetrated by the trench 2 when the trench 2 is formed; after the two are penetrated by the trench 2, a plurality of sub-regions set at intervals are formed respectively, and these sub-regions are still referred to as the source region 16 or the body region 14 in the subsequent description.

[0066] Specifically, as shown in Figure 5, which is a schematic diagram of the cross-sectional structure after the groove 2 is formed, forming the groove 2 includes the following steps: forming a mask layer 3 on the upper surface of the semiconductor layer 1; patterning the mask layer 3, and forming the groove 2 based on the patterned mask layer 3.

[0067] Specifically, the method of forming the mask layer 3 includes chemical vapor deposition, physical vapor deposition or other suitable methods.

[0068] Specifically, the mask layer 3 is made of silicon nitride or other suitable materials that can prevent the etchant from etching the semiconductor layer 1. In this embodiment, a silicon nitride layer is used as the mask layer 3.

[0069] Specifically, the method for forming the patterned mask layer 3 is a common photolithography process method, which will not be described in detail here.

[0070] Specifically, the method of forming the trench 2 includes dry etching, wet etching or other suitable methods.

[0071] As an example, the second wall is the C-plane of the semiconductor layer 1, so that the conductive channel of the device is located on the surface of the second wall, and the cross-section of the conductive channel of the device is the C-plane of the semiconductor layer 1, achieving a larger channel electron mobility.

[0072] Specifically, while ensuring device performance, the distance between the bottom surface of the trench 2 and the bottom surface of the current transport layer 13 can be selected according to actual conditions and is not limited here.

[0073] Specifically, FIG6 is a schematic diagram of the cross-sectional structure after the shielding layer 17 is formed. The method for forming the shielding layer 17 includes ion implantation or other suitable methods. In this embodiment, Al ions are implanted into the bottom of the trench 2 based on the patterned mask layer 3 to form the shielding layer 17. During the ion implantation process, multiple ion implantations with different doses and energies are performed to form the shielding layer 17 with a predetermined doping concentration.

[0074] Specifically, after forming the shielding layer 17 and before forming the gate dielectric layer 21 , the step of removing the mask layer 3 is further included.

[0075] Specifically, the method of removing the mask layer 3 includes dry etching, wet etching or other suitable methods.

[0076] Specifically, the gate dielectric layer 21 is formed to cover the upper surface of the semiconductor layer 1 and the inner wall and bottom surface of the trench 2. The gate dielectric layer 21 is formed by thermal oxidation, chemical vapor deposition, physical vapor deposition or other suitable methods.

[0077] As an example, the gate dielectric layer 21 includes a buffer layer (not shown) and a gate dielectric layer (not shown) stacked in sequence. In this embodiment, in order to ensure the breakdown resistance of the device, it is necessary to form a relatively thick and high-quality gate dielectric layer. Therefore, after removing the mask layer 3 and before forming the conductive material layer 20, the buffer layer is grown on the upper surface of the semiconductor layer 1 and the exposed surface of the trench 2 by a thermal oxidation process, and then the gate dielectric layer is formed by a thermal oxidation or deposition process to ensure the breakdown resistance of the gate dielectric layer 21.

[0078] Specifically, the buffer layer is made of silicon oxide or other suitable dielectric materials; the gate dielectric layer is made of silicon nitride, silicon oxide, silicon oxynitride or other suitable dielectric materials. In this embodiment, the buffer layer and the gate dielectric layer are both made of silicon oxide.

[0079] Specifically, as shown in Figure 7, which is a schematic diagram of the cross-sectional structure after the gate conductive material layer 20 is formed, the gate conductive material layer 20 also covers the upper surface of the gate dielectric layer 21 located above the semiconductor layer 1. The method of forming the gate conductive material layer 20 includes chemical vapor deposition, physical vapor deposition or other suitable methods.

[0080] Specifically, the gate conductive material layer 20 completely covers the surface of the gate dielectric layer 21 located on the first wall and the second wall, and the sum of the thicknesses of the gate conductive material layer 20 and the gate dielectric layer 21 is less than half of the opening size of the groove 2 to ensure that a gap of a preset width is formed between the stacked structure 23 located on the first wall and the second wall.

[0081] Specifically, as shown in Figure 8, which is a schematic diagram of the cross-sectional structure after the stacked structure 23 is formed, after the gate conductive material layer 20 is formed and before the interlayer dielectric layer (see subsequent Figure 9) is formed, it also includes a step of removing the gate conductive material layer 20 located above the semiconductor layer 1 and below the gap in the trench 2 to form the stacked structure 23 consisting of two parts of the gate conductive material layer 20 and the gate dielectric layer 21, which respectively cover the gate dielectric layer 21 on the first wall and the gate dielectric layer 21 on the second wall.

[0082] Specifically, the method of removing the gate conductive material layer 20 located above the semiconductor layer 1 and below the gap in the trench 2 includes dry etching, wet etching or other suitable methods.

[0083] Specifically, while ensuring device performance, after removing the gate conductive material layer 20 located above the semiconductor layer 1 and below the gap in the trench 2, before forming the interlayer dielectric layer, the gate dielectric layer 21 on the upper surface of the semiconductor layer 1 and below the gap in the trench 2 can also be removed.

[0084] Specifically, while ensuring device performance, the thickness of the gate conductive material layer 20 can be selected according to actual conditions and is no longer restricted here; the distance between the gate conductive material layer 20 on the first wall and the gate conductive material layer 20 on the second wall (that is, the size of the gap formed between the stacked structures 23 in the groove 2) can be selected according to actual conditions and is no longer restricted here.

[0085] Specifically, the gate conductive material layer 20 is made of polysilicon or other suitable conductive materials.

[0086] Please refer to Figures 9 to 13, and perform steps S5 and S6: form an interlayer dielectric layer 4 that fills the trench 2 and covers the upper surface of the stacked structure 23, form a source contact hole 41 in the interlayer dielectric layer 4 above the trench 2, the bottom surface of which exposes the shielding layer 17, the inner wall of the source contact hole 41 exposes the first wall and the interlayer dielectric layer 4, and the gate conductive material layer 20 wrapped by the interlayer dielectric layer 4 and the gate dielectric layer 21 serves as a gate conductive layer 22; form a source 5 that fills the source contact hole 41, form a gate (not shown) electrically connected to the gate conductive layer 22, and form a drain 6 electrically connected to the substrate 11.

[0087] Specifically, as shown in Figure 9, it is a schematic diagram of the cross-sectional structure after the interlayer dielectric layer 4 is formed. The interlayer dielectric layer 4 also covers the upper surface of the gate dielectric layer 21 above the semiconductor layer 1. The method of forming the interlayer dielectric layer 4 includes chemical vapor deposition, physical vapor deposition or other suitable methods.

[0088] Specifically, as shown in FIG10 , which is a schematic diagram of the cross-sectional structure after forming the source contact hole 41, the method for forming the source contact hole 41 includes dry etching, wet etching, or other suitable methods. In this embodiment, since the material of the semiconductor layer 1 is silicon carbide, the material of the gate conductive material layer 20 is polysilicon, and the material of the interlayer dielectric layer 4 is silicon oxide, the strength of silicon carbide is much higher than that of polysilicon and silicon dioxide. When dry etching is used for etching, the etching ratio of polysilicon and silicon dioxide is much higher than that of silicon carbide. In the process of forming the source contact hole 41, overetching can be selected to completely remove the stacked structure 23 covering the first wall and expose the shielding layer 17 on the bottom surface of the trench 2. At the same time, damage to the semiconductor layer 1 is minimal and the etching process can be simplified.

[0089] As an example, as shown in Figure 11, which is a schematic diagram of the cross-sectional structure after the doping region 18 is formed, after the source contact hole 41 is formed and before the source 5 is formed, it also includes a step of forming a second conductive type doping region 18 located below the contact region 15 on the surface of the body region 14 and the current transfer layer 13 exposed on the inner wall of the source contact hole 41.

[0090] Specifically, the method of forming the doping region 18 includes ion implantation or other suitable methods.

[0091] As an example, the doping concentration of the doping region 18 is not less than 1×10 18 cm -3 , so that the doped region 18 forms an ohmic contact with the source 5 filling the source contact hole 41 .

[0092] As an example, the doping region 18 is connected to the shielding layer 17 and the contact region 15 .

[0093] Specifically, while ensuring device performance and connectivity between the doping region 18 and the shielding layer 17 and the contact region 15, the distance between the side wall of the doping region and the source contact hole 41 can be selected based on actual conditions and is no longer restricted here; the shape and bottom position of the doping region 18 can be selected based on actual conditions and are no longer restricted here.

[0094] As an example, the cross-sectional dimension of the opening of the source contact hole 41 in the interlayer dielectric layer 4 is not smaller than the cross-sectional dimension of the source contact hole 41 in the trench 2. In this embodiment, the hole filling effect of the source contact hole 41 is improved, the aspect ratio of the source contact hole 41 is reduced, and the quality of the subsequently formed source electrode 5 is improved. The opening dimension of the source contact hole 41 in the interlayer dielectric layer 4 is larger. Because the etching selectivity of the semiconductor layer 1 in the trench 2 is much smaller than the etching selectivity of the gate conductive material layer 20, the cross-sectional dimension of the source contact hole 41 in the trench 2 is smaller than the cross-sectional dimension of the source contact hole 41 in the interlayer dielectric layer 4.

[0095] Specifically, as shown in Figures 12 and 13, which are respectively a schematic diagram of a cross-sectional structure after the drain 6 is formed and another schematic diagram of a cross-sectional structure after the drain 6 is formed, the method for forming the source 5 includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition or other suitable methods; the method for forming the gate includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition or other suitable methods; the method for forming the drain 6 includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition or other suitable methods.

[0096] As an example, the current transport layer 13 exposed on the inner wall of the source contact hole 41 forms a Schottky contact with the source 5 to form a Schottky diode consisting of the source 5, the current transport layer 13, the drift region 12, the substrate 11 and the drain 6.

[0097] Specifically, by adjusting the composition of the source electrode 5 , the barrier height of the Schottky contact formed between the source electrode 5 and the current transport layer 13 can be adjusted.

[0098] As an example, the barrier height of the Schottky diode ranges from 1 eV to 1.5 eV, and the turn-on voltage of the Schottky diode ranges from 0.7 V to 1.2 V.

[0099] Specifically, by forming the shielding layer 17 in the current transport layer 13 at the bottom of the trench 2, and forming the gate conductive layer 22 covering the surface of the gate dielectric layer 21 located on the second wall, the source 5 forms an ohmic contact with the shielding layer 17, the source region 16 and the contact region 15 through the source contact hole 41, so that when a forward voltage is first applied to the source 5 and the drain 6, the voltage is borne by the PN junction formed by the shielding layer 17 and the current transport layer 13 and the PN junction formed by the body region 14 and the current transport layer 13. As the voltage between the source 5 and the drain 6 increases, the carriers in the current transport layer 13 between the shielding layer 17 are gradually consumed. As much as possible, a wider space charge region is formed, and the voltage in the device is borne by the shielding layer 17 and the current transfer layer 13. The current transfer layer 13 located above the shielding layer 17 is clamped, thereby avoiding damage to the device. At the same time, since the shielding layer 17 and the current transfer layer 13 bear the voltage in the device, the electric field strength borne by the gate dielectric layer 21 can be reduced, so that the electric field strength borne by the gate dielectric layer 21 is lower than 1MV / cm, which can reduce the withstand voltage requirement of the gate dielectric layer 21, reduce the difficulty of the manufacturing process of the gate dielectric layer 21 in the device, improve the performance of the device, and reduce the distance between two adjacent shielding layers 17, which can further reduce the electric field strength borne by the gate dielectric layer 21.

[0100] Specifically, by making the current transfer layer 13 exposed on the second wall form a Schottky contact with the source 5, and then integrating a Schottky diode with a low turn-on voltage composed of the source 5, the semiconductor layer 1 and the drain 6 inside the device (the turn-on voltage of the PN junction between the body region 14 and the current transfer layer 13 is not less than 2.6V), the area of ​​the device is reduced, the size of the device is reduced, and the reverse recovery loss of the device is reduced.

[0101] Specifically, when the device is forward-conducting, due to the setting of the shielding layer 17, the voltage of the current transfer layer 13 in the area above the shielding layer 17 is clamped, thereby protecting the Schottky diode formed by the source 5 and the semiconductor layer 1, and at the same time reducing the electric field strength to which the Schottky diode is subjected, so that the electric field strength to which the Schottky diode is subjected is lower than 1MV / cm, and by reducing the distance between two adjacent shielding layers 17, the electric field strength to which the Schottky diode is subjected can be further reduced, thereby improving the performance of the device.

[0102] Specifically, by making the gate conductive layer 22 cover the surface of the gate dielectric layer 21 located on the first wall, the conductive channel of the device is located on the surface of the second wall, and then the cross-section of the conductive channel is the C-plane of silicon carbide, thereby improving the electron mobility in the conductive channel and improving the performance of the device.

[0103] Specifically, by forming the doped region 13 on the surface of the body region 14 and the current transfer layer 13 exposed on the inner wall of the source contact hole 41, the leakage risk caused by introducing the source 5 to form a Schottky contact with the current transfer layer 13 can be reduced, and the carriers in the area where the doped region 18 is located are avoided from being depleted. At the same time, the depletion level of the carriers in the current transfer layer 13 above the shielding layer 17 is improved, thereby better protecting the device. Moreover, since the doping concentration of the doped region 18 is relatively high, the turn-on voltage of the PN junction between it and the current transfer layer 13 is relatively low, which can reduce the reverse recovery loss of the device.

[0104] The preparation method of the SiC power MOS device of this embodiment improves the manufacturing process of the device. After forming the trench 2, the shielding layer 17 is formed in the current transfer layer 13 at the bottom of the trench 2, and then the stacked structure 23, the interlayer dielectric layer 4 and the source contact hole 41 that exposes the first wall and the shielding layer 17 are formed in sequence. The source 5 forms an ohmic contact with the shielding layer 17 through the source contact hole 41, and the source 5 forms a Schottky contact with the current transfer layer 13 exposed by the first wall. When a forward voltage is applied to the device, the voltage is borne by the PN junction between the shielding layer 17 and the current transfer layer 13 and the PN junction between the body region 14 and the current transfer layer 13, and due to the depletion of carriers in the current transfer layer 13 between the shielding layer 17 The current transfer layer 13 above the shielding layer 17 is clamped to avoid damage to the device. At the same time, since the shielding layer 17 and the current transfer layer 13 withstand the voltage in the device, the gate dielectric layer 21 is protected by the shielding layer 17 electrically connected to the source 5, which can reduce the electric field strength borne by the gate dielectric layer 21, and then reduce the voltage resistance requirement of the gate dielectric layer 21, thereby reducing the difficulty of the manufacturing process of the gate dielectric layer 21 and improving the reliability of the gate dielectric layer 21, and reducing the distance between two adjacent shielding layers 17, which can further reduce the electric field strength borne by the gate dielectric layer 21; by forming a conductive channel located on the surface of the second wall, the cross-section of the conductive channel is made to be the C-plane of the semiconductor layer 1, thereby improving the electron mobility in the conductive channel, and then improving the device performance.

[0105] Example 2

[0106] The present embodiment provides a SiC power MOS device, as shown in Figures 12 and 13, which are respectively a schematic diagram of a cross-sectional structure of the SiC power MOS device and another schematic diagram of a cross-sectional structure of the SiC power MOS device, comprising a first conductive type semiconductor layer 1, a second conductive type body region 14, a first conductive type source region 16, a second conductive type contact region 15, a trench 2, a second conductive type shielding layer 17, a gate dielectric layer 21, a gate conductive layer 22, an interlayer dielectric layer 4, a source 5, a gate and a drain 6, wherein the semiconductor layer 1 comprises a substrate 11, a drift region 12 and a current transfer layer 13 stacked in sequence; the body region 14 is located on the upper surface layer of the current transfer layer 13, the source region 16 is located on the upper surface layer of the body region 14, a plurality of contact regions 15 spaced at a preset distance are adjacent to the source region 16 above the contact region 15 and are spaced at a preset distance from the lower surface of the body region 14; a plurality of trenches arranged at intervals are disposed at intervals. The trench 2 passes through the source region 16 and the body region 14, the contact region 15 is adjacent to the first wall of the trench 2 and is spaced a preset distance from the second wall of the trench 2, and the bottom surface of the trench 2 is located in the current transmission layer 13; the shielding layer 17 is located in the current transmission layer 13 at the bottom of the trench 2; the gate dielectric layer 21 covers the second wall and bottom surface of the trench 2; the gate conductive layer 22 covers the surface of the gate dielectric layer 21 on the second wall; the interlayer dielectric layer 4 covers the gate conductive layer 22 and the exposed surface of the gate dielectric layer 21, and a source contact hole 41 is provided in the interlayer dielectric layer 4 above the trench 2, the bottom surface of which exposes the shielding layer 17, and the inner wall of the source contact hole 41 in the trench 2 exposes the first wall and the interlayer dielectric layer 4; the source 5 fills the source contact hole 41, the gate is electrically connected to the gate conductive layer 22, and the drain 6 is electrically connected to the substrate 11.

[0107] Specifically, the semiconductor layer 1 is made of silicon carbide or other suitable semiconductor materials.

[0108] Specifically, the contact type between the source electrode 5 and the current transport layer 13 exposed on the inner wall of the source contact hole 41 is a Schottky contact. Under the premise of ensuring the performance of the device, the size, shape and thickness of the semiconductor layer 1 can be selected according to the actual situation and are not limited here; the size, shape, thickness and doping concentration of the substrate 11 can be selected according to the actual situation and are not limited here; the size, shape, thickness and doping concentration of the drift region 12 can be selected according to the actual situation and are not limited here; the size, shape, thickness and doping concentration of the current transport layer 13 can be selected according to the actual situation and are not limited here. In this embodiment, the doping concentration of the current transport layer 13 is 10 16 cm -3The magnitude of the source electrode 5 is such that the source electrode 5 forms a Schottky contact with the current transport layer 13 exposed on the inner wall of the source contact hole 41 .

[0109] Specifically, the thickness and doping concentration of the body region 14 can be selected according to actual conditions while ensuring device performance, and are not limited here. In this embodiment, the doping concentration of the body region 14 is 10 17 cm -3 Magnitude.

[0110] Specifically, the first wall and the second wall are respectively adjacent to the source region 16. While ensuring device performance and ensuring that the first wall and the second wall are respectively adjacent to and spaced from the contact region 15, the opening size and depth of the trench 2 can be selected based on actual conditions and are not subject to any restrictions. The distance between two adjacent trenches 2 can be selected based on actual conditions and is not subject to any restrictions. The distance between the second wall and the contact region 15 can be selected based on actual conditions and is not subject to any restrictions. The depth here refers to the distance between the bottom surface of the trench 2 and the opening of the trench 2.

[0111] Specifically, the first wall and the second wall are both the C-plane of the semiconductor layer 1 , so that the cross section of the conductive channel controlled by the gate conductive layer 22 is the C-plane of the semiconductor layer 1 , thereby improving the mobility of channel electrons in the conductive channel.

[0112] Specifically, the contact type between the source electrode 5 and the shielding layer 17 exposed on the bottom surface of the source contact hole 41 is an ohmic contact. Under the premise of ensuring the performance of the device, the size, thickness and doping concentration of the shielding layer 17 can be selected according to actual conditions and are not limited here. The thickness here refers to the distance between the bottom surface of the shielding layer 17 and the bottom surface of the groove 2. In this embodiment, the size of the shielding layer 17 is the same as the size of the bottom surface of the groove 2, and the doping concentration of the shielding layer 17 is not less than 10 19 cm -3 of magnitude, so that the shielding layer 17 forms an ohmic contact with the source electrode 5 .

[0113] Specifically, while ensuring the performance of the device, the distance between two adjacent shielding layers 17 can be selected according to actual conditions and is not limited here.

[0114] Specifically, the contact region 15 and the source region 16 are both located on the upper surface of the body region 14, and the contact region 15 is located below the source region 16 and adjacent to the lower surface of the source region 16. The source electrode 5 and the inner wall of the source contact hole 41 reveal that the contact type between the source region 16 and the contact region 15 is an ohmic contact. While ensuring the performance of the device, the thickness and doping concentration of the source region 16 can be selected according to actual conditions and are not limited here. The size, thickness and doping concentration of the contact region 15 can be selected according to actual conditions and are not limited here. In this embodiment, the doping concentration of the contact region 15 is not less than 10 19 cm -3 The doping concentration of the source region 16 is not less than 10 19 cm -3 of magnitude, so that the source electrode 5 forms ohmic contact with the source region 16 and the contact region 15 respectively.

[0115] Specifically, the gate dielectric layer includes a buffer layer and a gate dielectric layer stacked in sequence.

[0116] Specifically, while ensuring the breakdown resistance of the device, the thickness of the buffer layer can be selected according to actual conditions and is not limited here; the thickness of the gate dielectric layer can be selected according to actual conditions and is not limited here.

[0117] Specifically, the gate conductive layer 22 is made of polysilicon or other suitable conductive materials.

[0118] Specifically, the interlayer dielectric layer 4 also covers the upper surface of the gate dielectric layer 21 above the semiconductor layer 1. The material of the interlayer dielectric layer 4 includes silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials. In this embodiment, a silicon oxide layer is used as the interlayer dielectric layer 4.

[0119] Specifically, while ensuring device performance, the thickness of the interlayer dielectric layer 4 located above the semiconductor layer 1 and the stacked structure 23 can be selected according to actual conditions and is no longer restricted here; the thickness of the interlayer dielectric layer 4 covering the side walls of the gate conductive layer 22 can be selected according to actual conditions and is no longer restricted here.

[0120] Specifically, the current transport layer 13 exposed on the inner wall of the source contact hole 41 forms a Schottky contact with the source 5 to form a Schottky diode consisting of the source 5, the current transport layer 13, the drift region 12, the substrate 11 and the drain 6.

[0121] Specifically, by adjusting the material of the source electrode 5 , the barrier height between the source electrode 5 and the current transport layer 13 exposed on the inner wall of the source contact hole 41 can be controlled.

[0122] Specifically, the barrier height of the Schottky diode ranges from 1eV to 1.5eV, and the turn-on voltage of the Schottky diode ranges from 0.7V to 1.2V.

[0123] Specifically, the body region 14 exposed on the inner wall of the source contact hole 41 and the surface layer of the current transfer layer 13 are further provided with a second conductive type doping region 18 located below the contact region 17, and the doping region 18 forms an ohmic contact with the source 5 filling the source contact hole 41.

[0124] Specifically, the doping region 18 is connected to the shielding layer 17 and the contact region 15 , and a bottom surface of the doping region 18 is not lower than a bottom surface of the shielding layer 17 .

[0125] Specifically, the material of the source electrode 5 includes titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum or other suitable conductive materials; the material of the gate electrode includes titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum or other suitable conductive materials; the material of the drain electrode 6 includes titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum or other suitable conductive materials.

[0126] Specifically, since the shielding layer 17 is electrically connected to the source 5 through the source contact hole 41, when a forward voltage is applied to the device, the carriers in the current transfer layer 13 area at the junction with the shielding layer 17 are gradually depleted, generating a space charge region, so that the current transfer layer 13 above the shielding layer 17 is clamped, thereby avoiding device damage and protecting the device. In addition, the space charge region generated by the depletion of carriers in the current transfer layer 13 is used to withstand the voltage applied to the device, which can protect the gate dielectric layer 21 in the device, reduce the electric field strength to which the gate dielectric layer 21 is subjected, and then reduce the voltage withstand requirement of the gate dielectric layer 21 in the device.

[0127] Specifically, since the source electrode 5 forms a Schottky contact with the current transfer layer 13 in the source contact hole 41, a Schottky diode with a relatively low turn-on voltage is integrated inside the device without increasing the size of the device, while achieving unipolar conductivity of the device and reducing the reverse recovery loss of the device.

[0128] Specifically, due to the setting of the shielding layer 17, the device can clamp the voltage of the current transfer layer 13 in the area above the shielding layer 17, thereby protecting the Schottky diode formed by the source 5 and the semiconductor layer 1, and reducing the electric field strength to which the Schottky diode is subjected. By reducing the distance between two adjacent shielding layers 17, the electric field strength to which the Schottky diode is subjected can be further reduced, thereby protecting the safety of the Schottky diode.

[0129] Specifically, by setting the doping region 18 that forms an ohmic contact with the source 5 on the surface of the body region 14 exposed on the inner wall of the source contact hole 41 and the current transfer layer 13, the carriers in the area where the doping region 18 is located are prevented from being completely depleted, and at the same time, the depletion degree of the current transfer layer 13 above the shielding layer 17 is enhanced to better protect the device, and the turn-on voltage of the PN junction between the doping region 18 and the current transfer layer 13 is lower than the turn-on voltage of the PN junction between the body region 14 and the current transfer layer 13, thereby reducing the reverse recovery loss of the device.

[0130] The SiC power MOS device of this embodiment improves the structure of the device, and the shielding layer 17 is provided in the current transport layer 13 below the bottom surface of the trench 2. The inner wall of the source contact hole 41 exposes the first wall, and the source 5 forms a Schottky contact with the current transport layer 13 exposed by the source contact hole 41. Then, a Schottky diode with a low turn-on voltage is integrated in the device, which is composed of the source 5, the current transport layer 13, the drift region 12, the substrate 11 and the drain 6, without increasing the size of the device. At the same time, the unipolar conduction of the device is achieved, and the reverse recovery of the device is reduced. loss, and the setting of the shielding layer 17 can protect the Schottky diode and reduce the electric field strength to which the Schottky diode is subjected; in addition, the body region 14 exposed on the inner wall of the source contact hole 41 and the surface layer of the current transfer layer 13 can also be provided with the doped region 18 that forms an ohmic contact with the source 5, so as to avoid the carriers in the area where the doped region 18 is located from being completely depleted, and at the same time enhance the depletion degree of the current transfer layer 13 above the shielding layer 17, so as to better protect the device, and the PN junction turn-on voltage between the doped region 18 and the current transfer layer 13 is low, thereby reducing the reverse recovery loss of the device.

[0131] In summary, the SiC power MOS device and its preparation method of the present invention improve the structure of the device to form a trench that penetrates the source region and the body region and has a bottom surface located in the current transmission layer, and form a shielding layer in the current transmission layer below the bottom surface of the trench, the first wall of the trench exposes the contact area, and the contact area is spaced a preset distance from the second wall, the gate dielectric layer covers the second wall and the bottom surface of the trench, the gate conductive layer covers the surface of the gate dielectric layer located on the second wall, the interlayer dielectric layer covers the upper surface of the gate conductive layer and the semiconductor layer, the source contact hole penetrates the interlayer dielectric layer and the inner wall and bottom surface respectively expose the first wall and the shielding layer, the source and the shielding layer and the current transmission layer exposed in the source contact hole form an ohmic contact and a Schottky contact respectively, when a forward voltage is applied to the device, the PN junction between the shielding layer and the current transmission layer withstands the voltage in the device, and the carriers in the current transmission layer region intersecting with the shielding layer are gradually depleted, so that the current transmission layer above the shielding layer is clamped, thereby achieving protection of the device, and because the shielding layer and the current transmission layer withstand the high voltage in the device, the gate dielectric layer is protected, which can reduce the gate dielectric layer. The device meets the voltage withstand requirements of the dielectric layer, thereby reducing the difficulty of the gate dielectric layer manufacturing process and improving the reliability of the gate dielectric layer; because the source electrode and the current transport layer exposed in the source contact hole form a Schottky contact, a Schottky diode with a low turn-on voltage composed of the source electrode, the semiconductor layer and the drain electrode is integrated in the device without increasing the size of the device, while achieving unipolar conduction of the device and reducing the reverse recovery loss of the device; the provision of the shielding layer can reduce the electric field strength to which the Schottky diode is subjected, thereby protecting the Schottky diode; by providing a doped region that forms an ohmic contact with the source electrode on the body region exposed on the inner wall of the source contact hole and the surface layer of the current transport layer, the carriers in the area where the doped region is located can be prevented from being completely depleted, while the depletion degree of the current transport layer above the shielding layer can be enhanced, thereby better protecting the device, and the PN junction between the doped region and the current transport layer has a low turn-on voltage, thereby reducing the reverse recovery loss of the device; in addition, because the conductive channel of the device is located on the surface layer of the second wall, the cross section of the conductive channel is the C-plane of the semiconductor layer, which improves the mobility of electrons in the conductive channel and enhances the device performance. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0132] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A method for preparing a SiC power MOS device, characterized in that: The following steps are involved: Providing a first conductive type semiconductor layer including a substrate, a drift region and a current transport layer stacked in sequence, and forming a second conductive type body region on the upper surface layer of the current transport layer; Forming a plurality of second conductive type contact regions spaced apart in the body region and a first conductive type source region located on the upper surface of the body region, wherein the contact region is adjacent to the source region above the contact region and is spaced apart from the lower surface of the body region by a preset distance; forming a plurality of trenches arranged at intervals and penetrating the source region and the body region, wherein the contact region is adjacent to a first wall of the trench and is spaced a preset distance from a second wall of the trench, the first wall is arranged opposite to the second wall, and the bottom surface of the trench is located in the current transmission layer; forming a second conductive type shielding layer in the current transmission layer at the bottom of the trench to form a stacked structure covering the first wall and the second wall and including a gate dielectric layer and a gate conductive material layer stacked in sequence, wherein the stacked structure on the first wall and the second wall is spaced apart by a preset distance; forming an interlayer dielectric layer filling the trench and covering the upper surface of the stacked structure, forming a source contact hole whose bottom surface exposes the shielding layer in the interlayer dielectric layer above the trench, the inner wall of the source contact hole exposes the first wall and the interlayer dielectric layer, and the gate conductive material layer wrapped by the interlayer dielectric layer and the gate dielectric layer serves as a gate conductive layer; A source electrode filling the source contact hole is formed, a gate electrode electrically connected to the gate conductive layer is formed, and a drain electrode electrically connected to the substrate is formed.

2. The method for preparing a SiC power MOS device according to claim 1, characterized in that: The semiconductor layer is a silicon carbide layer.

3. The method for preparing a SiC power MOS device according to claim 1, characterized in that: The gate dielectric layer includes a buffer layer and a gate dielectric layer stacked in sequence.

4. The method for preparing a SiC power MOS device according to claim 1, characterized in that: After forming the source contact hole and before forming the source, the method further includes forming a second conductive type doping region located below the contact region on the surface of the body region and the current transmission layer exposed on the inner wall of the source contact hole.

5. The method for preparing a SiC power MOS device according to claim 4, characterized in that: The doping concentration of the doping region is not less than 1×10 18 cm -3 .

6. The method for preparing a SiC power MOS device according to claim 4, characterized in that: The doping region is in communication with the shielding layer and the contact region.

7. The method for preparing a SiC power MOS device according to claim 1, characterized in that: A cross-sectional dimension of the source contact hole above the semiconductor layer is not smaller than a cross-sectional dimension of the source contact hole in the trench.

8. The method for preparing a SiC power MOS device according to claim 1, characterized in that: The current transport layer exposed on the inner wall of the source contact hole forms a Schottky contact with the source to form a Schottky diode composed of the source, the current transport layer, the drift region, the substrate and the drain.

9. The method for preparing a SiC power MOS device according to claim 8, characterized in that: The barrier height of the Schottky diode ranges from 1eV to 1.5eV, and the turn-on voltage of the Schottky diode ranges from 0.7V to 1.2V.

10. The method for preparing a SiC power MOS device according to claim 1, characterized in that: The gate conductive material layer completely covers the gate dielectric layer located on the first wall and the second wall.

11. The method for preparing a SiC power MOS device according to claim 2, characterized in that: The second wall is a C-plane of the semiconductor layer.

12. The method for preparing a SiC power MOS device according to claim 1, characterized in that: The sum of the thicknesses of the gate conductive material layer and the gate dielectric layer is less than half of the size of the trench opening.

13. The method for preparing a SiC power MOS device according to claim 1, characterized in that: The source electrode forms an ohmic contact with the shielding layer, the source region and the contact region through the source contact hole.

14. The method for preparing a SiC power MOS device according to claim 1, characterized in that: The contact region is first formed on the upper surface of the body region, and then the source region is formed on the upper surface of the body region. During the formation of the source region, the region where the source region and the contact region overlap forms an inversion region.

15. A SiC power MOS device, characterized in that: include: The first conductive type semiconductor layer comprises a substrate, a drift region and a current transmission layer stacked in sequence; A second conductive type body region, a first conductive type source region and a second conductive type contact region, wherein the body region is located on the upper surface of the current transmission layer, the source region is located on the upper surface of the body region, and a plurality of spaced contact regions are adjacent to the source region above the contact region and are spaced from the lower surface of the body region by a preset distance; A plurality of grooves arranged at intervals, penetrating the source region and the body region, the contact region being adjacent to a first wall of the groove and spaced a preset distance from a second wall of the groove, the bottom surface of the groove being located in the current transmission layer, and the first wall being arranged opposite to the second wall; A second conductive type shielding layer located in the current transmission layer at the bottom of the trench; a gate dielectric layer, covering the second wall and bottom surface of the trench; a gate conductive layer, covering a surface of the gate dielectric layer on the second wall; an interlayer dielectric layer covering the gate conductive layer and the exposed surface of the gate dielectric layer, wherein a source contact hole having a bottom surface exposing the shielding layer is provided in the interlayer dielectric layer above the groove, and an inner wall of the source contact hole exposing the first wall and the interlayer dielectric layer; A source, a gate and a drain, the source fills the source contact hole, the gate is electrically connected to the gate conductive layer, and the drain is electrically connected to the substrate.

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