Thin film transistor and manufacturing method therefor, array substrate and display panel

Abstract

Disclosed in the present application are a thin film transistor and a manufacturing method therefor, an array substrate and a display panel. The thin film transistor provided in the present application comprises an active layer, the active layer comprises a plurality of sub-active layers, and the plurality of sub-active layers are stacked in a first direction. Each sub-active layer comprises a crystalline oxide material, and the atomic number proportions of indium elements in adjacent sub-active layers are different.

Description

Thin film transistor and manufacturing method thereof, array substrate and display panel

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese Patent Application No. 202311269711.4, filed on September 27, 2023, entitled “Thin Film Transistor, Preparation Method Thereof, Array Substrate, and Display Panel,” and the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present application belongs to the field of display technology, and in particular relates to a thin film transistor and a manufacturing method thereof, an array substrate and a display panel. Background Art

[0004] With the development of display technology, the performance requirements for display devices are becoming increasingly higher. Display devices include a light-emitting layer and a driving circuit. The driving circuit is used to drive the light-emitting layer to emit light. The driving circuit includes thin-film transistors. The higher the mobility and conductivity of the thin-film transistors, the stronger the light stability of the thin-film transistors, and the more stable the device performance. However, the thin-film transistors in related technologies cannot achieve both high mobility and light stability, so their overall performance cannot meet the requirements.

[0005] Summary of the Invention

[0006] The embodiments of the present application provide a thin film transistor and a method for manufacturing the same, an array substrate, and a display panel, which can achieve a balance between mobility and light stability, thereby improving the overall performance of the thin film transistor.

[0007] An embodiment of the first aspect of the embodiments of the present application provides a thin film transistor, including an active layer, wherein the active layer includes a plurality of sub-active layers, and the plurality of sub-active layers are stacked along a first direction, the sub-active layers include crystalline oxide materials, and the atomic number proportions of indium elements in adjacent sub-active layers are different.

[0008] An embodiment of the second aspect of the present application further provides a method for manufacturing a thin film transistor, comprising:

[0009] Crystalline oxide materials with different atomic ratios of indium are deposited successively to sequentially form multiple sub-active layers stacked along a first direction, wherein the atomic ratios of indium in adjacent sub-active layers are different, thereby forming an active layer.

[0010] An embodiment of the third aspect of the present application further provides an array substrate, comprising any one of the thin film transistors provided in the first aspect of the present application.

[0011] An embodiment of the fourth aspect of the present application further provides a display panel, comprising any array substrate provided by the third aspect of the present application.

[0012] The thin-film transistor provided herein includes an active layer, the active layer including multiple sub-active layers, the multiple sub-active layers being stacked along a first direction, the sub-active layers comprising a crystalline oxide material, and adjacent sub-active layers having different atomic ratios of indium. On the one hand, using a crystalline oxide material as the material for the active layer can impart high mobility and good light stability to the thin-film transistor. Furthermore, the better the crystallinity of the oxide material, the better the mobility and light stability of the thin-film transistor, thereby achieving a balance between mobility and light stability of the thin-film transistor. On the other hand, the better the crystallinity of the oxide material, the more difficult it is to etch. The sub-active layer with a lower atomic number ratio of indium is easy to be wet-etched, but has poor crystallinity and lower mobility than the sub-active layer with a higher atomic number ratio of indium; the sub-active layer with a higher atomic number ratio of indium has better crystallinity and higher mobility, but is not easy to be wet-etched; therefore, in this application, by setting up multiple sub-active layers and making the atomic number ratios of indium elements in adjacent sub-active layers different, the etching difficulty and crystallinity can be taken into account, so as to reduce the difficulty of patterning the active layer during the preparation process. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] FIG1 is a top view of a thin film transistor provided in an embodiment of the present application;

[0014] FIG2 is a cross-sectional view along PP' in FIG1;

[0015] FIG3 is a schematic structural diagram of an active layer in a thin film transistor provided in an embodiment of the present application;

[0016] FIG4 is a schematic structural diagram of another thin film transistor provided in an embodiment of the present application;

[0017] FIG5 is a schematic structural diagram of an active layer in another thin film transistor provided in an embodiment of the present application;

[0018] FIG6 is a schematic structural diagram of an active layer in another thin film transistor provided in an embodiment of the present application;

[0019] FIG7 is a schematic structural diagram of an active layer in another thin film transistor provided in an embodiment of the present application;

[0020] FIG8 is a schematic structural diagram of an active layer in another thin film transistor provided in an embodiment of the present application;

[0021] FIG9 is a flow chart of a method for manufacturing a thin film transistor according to an embodiment of the present application;

[0022] FIG10 is a schematic structural diagram of an array substrate provided in an embodiment of the present application;

[0023] FIG11 is a schematic structural diagram of a display panel provided in an embodiment of the present application. DETAILED DESCRIPTION

[0024] After research, the inventors found that the active layer of the thin film transistor in the related art is mainly composed of indium, gallium, zinc and doping elements. Among them, the mobility of the indium gallium zinc oxide active layer can be adjusted by adjusting the indium, gallium and zinc content, but the mobility and the light stability of the thin film transistor in indium gallium zinc oxide are in conflict with each other. The mobility is low and the light stability (NBTIS) is good, but the conductivity is poor; the mobility is high and the light stability is poor, so that the channel region of the thin film transistor is easily affected by light and affects its own performance. Therefore, it is difficult for the thin film transistor in the related art to achieve a balance between mobility and light stability, resulting in poor overall performance of the thin film transistor. Based on the study of the above problems, the inventors provide a thin film transistor and a preparation method thereof, an array substrate and a display panel to achieve a balance between mobility and light stability, thereby improving the overall performance of the thin film transistor.

[0025] In order to better understand the present application, the thin film transistor and its manufacturing method, array substrate and display panel according to the embodiments of the present application are described in detail below with reference to Figures 1 to 11.

[0026] Referring to Figures 1, 2, and 3, an embodiment of the present application provides a thin film transistor 1 including an active layer 11. The active layer 11 includes multiple sub-active layers 111 stacked along a first direction x. The sub-active layers 111 include a crystalline oxide material, and adjacent sub-active layers 111 have different atomic proportions of indium.

[0027] The thin film transistor 1 provided in the present application includes an active layer 11, which includes multiple sub-active layers 111. The multiple sub-active layers 111 are stacked along a first direction x. The sub-active layers 111 include a crystalline oxide material, and the atomic ratio of indium in adjacent sub-active layers 111 varies. On the one hand, using a crystalline oxide material as the material for the active layer 11 can enable the thin film transistor 1 to have high mobility and good light stability. The better the crystallinity of the oxide material, the better the mobility and light stability of the thin film transistor 1, thereby achieving a balance between the mobility and light stability of the thin film transistor 1. On the other hand, the better the crystallinity of the oxide material, the more difficult it is to etch. The sub-active layer 111 with a lower atomic number ratio of indium is easy to be wet-etched, but has poor crystallinity and lower mobility than the sub-active layer 111 with a higher atomic number ratio of indium; the sub-active layer 111 with a higher atomic number ratio of indium has better crystallinity and higher mobility, but is not easy to be wet-etched; therefore, in the present application, by providing multiple sub-active layers 111 and making the atomic number ratios of indium elements in adjacent sub-active layers 111 different, the etching difficulty and crystallinity can be taken into account, so as to reduce the difficulty of patterning the active layer 11 during the preparation process.

[0028] As shown in Figures 2 and 4, the thin film transistor 1 provided in the present application further includes a source-drain electrode layer 12 and a gate electrode 13. The active layer 11 includes a first side A1 and a second side A2, and the first side A1 and the second side A2 are arranged along a first direction x. The source-drain electrode layer 12 is formed on the first side A1 and is connected to the active layer 11. The gate electrode 13 is formed on the first side A1 or the second side A2 and is insulated from the active layer 11 and the source-drain electrode layer 12. Specifically, the thin film transistor 1 can be a top-gate structure or a bottom-gate structure. When the gate electrode 13 is located on the first side A1, it is a top-gate structure, and when the gate electrode 13 is located on the second side A2, it is a bottom-gate structure. This application does not specifically limit this.

[0029] In a feasible embodiment, as shown in Figure 2, the thin film transistor 1 has a top gate structure, the gate 13 is formed on the first side A1, the gate 13 is insulated from the active layer 11 by a first insulating layer 14, and also includes a second insulating layer 15, a light-shielding layer 16, a buffer layer 17 and a substrate 18 formed on the second side A2 and stacked in a direction away from the active layer 11, and the projection of the light-shielding layer 16 in the first direction x covers the projection of the gate 13 in the first direction x.

[0030] The light shielding layer 16 can be used to shield the channel region in the active layer 11 , thereby reducing the influence of light on the channel region and improving the stability of the thin film transistor 1 .

[0031] In another feasible embodiment, as shown in FIG. 4 , the thin film transistor 1 has a bottom-gate structure, the gate 13 is formed on the second side A2 , and the gate 13 is insulated from the active layer 11 by a first insulating layer 14 .

[0032] Specifically, the thin film transistor 1 may further include an interlayer dielectric layer 19 , and the source-drain electrode layer 12 may include source and drain electrodes, which are connected to the active layer 11 through vias penetrating the interlayer dielectric layer 19 .

[0033] In other feasible embodiments, the thin film transistor 1 may also have a dual-gate structure (not shown in the figure), in which case the gate 13 is formed simultaneously on the first side A1 and the second side A2, and the gate 13 formed on the first side A1 and the gate formed on the second side A2 are insulated from the active layer 11 by the first insulating layer 14.

[0034] In a feasible embodiment, the crystalline oxide material includes indium gallium oxide, and the ratio of the total number of atoms in the indium gallium oxide to the total number of atoms in the crystalline oxide material is 70%-100%.

[0035] In the above embodiment, the crystalline oxide material mainly includes indium gallium oxide. Indium gallium oxide can form a crystalline state. The higher the indium content, the better the crystallinity in the subsequent process and the higher the mobility of the thin film transistor 1. However, indium gallium zinc oxide material commonly used as the material of the active layer 11 cannot form a crystalline state.

[0036] The material of the sub-active layer 111 may only include crystalline oxide materials to enhance the balance between mobility and light stability.

[0037] Among them, the indium gallium oxide material includes indium gallium oxide, and the ratio of the total number of atoms in the indium gallium oxide to the total number of atoms in the crystalline oxide material is 70%-100%, specifically 70%, 72%, 79%, 80%, 85%, 90%, 92%, 94%, 97%, 100%, etc. This application does not specifically limit this. The higher the ratio of the total number of atoms in the indium gallium oxide to the total number of atoms in the crystalline oxide material, the better the mobility and light stability of the thin film transistor 1.

[0038] In a feasible embodiment, as shown in Figure 5, the multi-layer sub-active layer 111 includes at least one first sub-active layer 1111 and at least one second sub-active layer 1112, the atomic number ratio of the indium element in the first sub-active layer 1111 is smaller than the atomic number ratio of the indium element in the second sub-active layer 1112, and the atomic number ratio of the gallium element in the first sub-active layer 1111 is greater than the atomic number ratio of the gallium element in the second sub-active layer 1112.

[0039] In the above embodiment, the multi-layer sub-active layer 111 may include sub-active layers 111 with two atomic number ratios, namely the first sub-active layer 1111 and the second sub-active layer 1112; or, the multi-layer sub-active layer 111 may include sub-active layers 111 with multiple atomic number ratios, such as three sub-active layers 111 or more seed active layers 111, which is not particularly limited in the present application.

[0040] Specifically, the atomic number of indium in the first sub-active layer 1111 is smaller than the atomic number of indium in the second sub-active layer 1112, and the atomic number of gallium in the first sub-active layer 1111 is greater than the atomic number of gallium in the second sub-active layer 1112. Since the atomic number of indium is larger, the crystallinity is better in the subsequent process, and the mobility of the thin film transistor 1 is higher. However, the better the crystallinity of indium gallium oxide, the better the crystallization effect, which makes wet etching more difficult. Therefore, the crystallinity of the first sub-active layer 1111 is weaker than that of the second sub-active layer 1112, but The etching difficulty is lower than that of the second sub-active layer 1112. The crystallinity of the second sub-active layer 1112 is stronger than that of the first sub-active layer 1111, so the mobility and light stability are better, but the etching difficulty is greater than that of the first sub-active layer 1111. Therefore, by setting the active layer 11 to include a stacked first sub-active layer 1111 and a second sub-active layer 1112, the etching difficulty of the active layer 11 can be reduced through the first sub-active layer 1111 to improve the feasibility of preparation, and the mobility and light stability can be improved through the second sub-active layer 1112, so that the comprehensive improvement of the performance of the thin film transistor 1 itself can be achieved.

[0041] In a feasible embodiment, as shown in Figure 5, the first sub-active layer 1111 and the second sub-active layer 1112 are alternately arranged along the first direction x, the active layer 11 includes a first side A1 and a second side A2, the first side A1 and the second side A2 are arranged along the first direction x, wherein a layer of the first sub-active layer 1111 is close to the first side A1, and wherein a layer of the second sub-active layer 1112 is close to the second side A2.

[0042] In the above embodiment, one of the second sub-active layers 1112 is set to be close to the second side A2, and the second sub-active layer 1112 can be prepared first during the preparation process of the active layer 11. Since the atomic number of indium elements in the second sub-active layer 1112 accounts for a greater proportion than the atomic number of indium elements in the first sub-active layer 1111, high mobility and high crystallinity quality can be provided for the thin film transistor 1. During the preparation process, when the first sub-active layer 1111 is prepared above the second sub-active layer 1112, the second sub-active layer 1112 can induce crystallization of the first sub-active layer 1111 in contact with the second sub-active layer 1112, thereby improving the crystallinity and mobility of the upper first sub-active layer 1111, while maintaining the low etching difficulty of the first sub-active layer 1111, thereby reducing the patterning difficulty of the active layer 11. The first sub-active layer 1111 can supplement oxygen atoms for the second sub-active layer 1112 , regulate the carrier concentration of the second sub-active layer 1112 , and have better crystallinity and mobility under the induction of the second sub-active layer 1112 during the film formation process.

[0043] Specifically, in the above embodiment, the number of sub-active layers 111 can be odd or even. As shown in Figure 6, when the number of sub-active layers 111 is even, and when one of the second sub-active layers 1112 is close to the first side A1, one of the first sub-active layers 1111 is close to the second side A2; as shown in Figure 5, when one of the second sub-active layers 1112 is close to the second side A2, one of the first sub-active layers 1111 is close to the first side A1. As shown in Figure 7, when the number of sub-active layers 111 is odd, and when one of the second sub-active layers 1112 is close to the first side A1, another second sub-active layer 1112 is close to the second side A2; as shown in Figure 8, when one of the second sub-active layers 1112 is close to the second side A2, another second sub-active layer 1112 is close to the first side A1.

[0044] In a feasible embodiment, the number of atoms of indium element in the first sub-active layer 1111 is a1, the number of atoms of gallium element is b1, k1=a1 / (a1+b1), k2=b1 / (a1+b1), wherein 50%≤k1≤80%, 20%≤k2≤50%.

[0045] Specifically, k1 can be 50%, 55%, 57%, 63%, 68%, 70%, 72%, 79%, 80%, etc., and k2 can be 20%, 21%, 24%, 28%, 35%, 46%, 50%, etc. This application does not make any special restrictions on this and can be selected according to actual needs.

[0046] Specifically, within the above numerical range, k1 can be set to be smaller and k2 can be set to be larger in the first sub-active layer 1111 , so as to further reduce the difficulty of etching the active layer 11 .

[0047] In a feasible embodiment, the number of atoms of indium element in the second sub-active layer 1112 is a2, the number of atoms of gallium element is b2, k3=a2 / (a2+b2), k4=b2 / (a2+b2), wherein 80%≤k3≤100%, 0≤k4≤20%.

[0048] Specifically, k3 in the second sub-active layer 1112 can be 80%, 83%, 88%, 90%, 95%, 96%, 99%, 100%, etc., and k4 can be 5%, 8%, 10%, 11%, 15%, 18%, 20%, etc. This application does not make any special restrictions on this and can be selected according to actual needs.

[0049] Specifically, within the above numerical range, a larger k3 and a smaller k4 can be selected in the second sub-active layer 1112 to further improve the mobility of the active layer 11 .

[0050] In a feasible embodiment, as shown in FIG8 , a dimension D of the active layer 11 along the first direction x is 3 nm to 50 nm.

[0051] In the above embodiment, the size of the active layer 11 along the first direction x can be 3nm, 5nm, 10nm, 13nm, 17nm, 20nm, 26nm, 28nm, 30nm, 35nm, 40nm, 43nm, 48nm, 50nm, etc., and this application does not impose any special limitation on this.

[0052] When the size of the active layer 11 along the first direction x is small, the risk of breakage is easily increased, and it is not easy to ensure the yield of the thin film transistor 1. When the size of the active layer 11 along the first direction x is large, the preparation cost is high and it is not easy to etch. Therefore, setting the size of the active layer 11 along the first direction x within the above range can simultaneously take into account the yield and manufacturing cost of the active layer 11.

[0053] In a feasible implementation manner, as shown in FIG8 , the size of the first sub-active layer 1111 along the first direction x is 1 nm-10 nm.

[0054] Specifically, the size of the first sub-active layer 1111 along the first direction x may be 1 nm, 2 nm, 3 nm, 5 nm, 6 nm, 7 nm, 10 nm, etc., which is not particularly limited in the present application.

[0055] In a feasible implementation manner, as shown in FIG8 , the size of the second sub-active layer 1112 along the first direction x is 0.5 nm-5 nm.

[0056] Specifically, the size of the second sub-active layer 1112 along the first direction x may be 0.5 nm, 1 nm, 1.5 nm, 2 nm, 3 nm, 3.5 nm, 4.5 nm, 5 nm, etc., which is not particularly limited in the present application.

[0057] In a feasible embodiment, the size of the first sub-active layer 1111 along the first direction x can be set to be larger than the size of the second sub-active layer 1112 along the first direction x, and the first sub-active layer 1111 plays a dominant role in the difficulty of etching the active layer 11. The thicker the first sub-active layer 1111 is and the greater the proportion of the thickness of the first sub-active layer 1111 in the active layer 11 is, the lower the difficulty of etching the active layer 11 is; the second sub-active layer 1112 plays a dominant role in the mobility and light reliability of the active layer 11. The thicker the second active layer 11 is and the greater the proportion of the second active layer 11 in the thickness of the active layer 11 is, the better the mobility and light reliability of the active layer 11 are. That is, the above-mentioned setting method can make the etching difficulty, mobility and light reliability of the active layer 11 meet the requirements.

[0058] Specifically, the thickness of each sub-active layer 111 can be adjusted according to the difference in etching selectivity and the mobility requirement of the thin film transistor 1 .

[0059] In a feasible embodiment, in the active layer 11 , the atomic number ratio of indium elements in the sub-active layer 111 close to the first side A1 and / or close to the second side A2 is greater than or equal to the atomic number ratio of indium elements in any other sub-active layer 111 .

[0060] In the above embodiment, by making the atomic number ratio of the indium element in the sub-active layer 111 close to the first side A1 and / or close to the second side A2 greater than or equal to the atomic number ratio of the indium element in any other sub-active layer 111, the sub-active layer 111 with the largest atomic number ratio of the indium element in each sub-active layer 111 can be prepared first during the preparation process, and then the other sub-active layers 111 are prepared on the sub-active layer 111. Since the atomic number ratios of the indium element in the two adjacent sub-active layers 111 are different, the atomic number ratio of the indium element in the sub-active layer 111 located above and adjacent to the sub-active layer 111 is relatively small. The sub-active layer 111 can induce the crystallization of the other sub-active layers 111 above it, thereby improving the crystallinity and mobility of the sub-active layer 111 above it, and maintaining the easy etching property brought about by the low atomic number ratio of the indium element in the other sub-active layers 111 above it.

[0061] In a feasible embodiment, the active layer 11 further includes doping particles, and the ratio of the total number of atoms of the doping particles to the total number of atoms in the crystalline oxide material is greater than 0 and less than or equal to 30%.

[0062] In particular, the doping particles include tin and / or germanium.

[0063] In the above-described embodiment, the active layer 11 includes a crystalline oxide material and dopant particles. The dopant particles can enhance the diversity of the active layer 11. Easily available dopant particles can be selected based on actual preparation conditions. While ensuring crystallinity, lower-cost crystalline particles can be used to reduce the preparation cost of the active layer 11. Specifically, the dopant particles include tin and / or germanium, and the ratio of the total number of atoms in the dopant particles to the total number of atoms in the crystalline oxide material is greater than 0 and less than or equal to 30%. This ensures that the primary material of the active layer 11 is indium gallium oxide, thereby achieving a balance between mobility and light stability.

[0064] The present application also provides a method for preparing a thin film transistor 1, as shown in FIG9 , comprising:

[0065] S200, successively depositing crystalline oxide materials with different atomic ratios of indium elements to sequentially form a plurality of sub-active layers 111 stacked along a first direction x, wherein the atomic ratios of indium elements in adjacent sub-active layers 111 are different, thereby forming an active layer 11.

[0066] Specifically, the crystalline oxide material is deposited using an atomic layer deposition process.

[0067] In the method for fabricating the thin-film transistor 1 provided herein, the sub-active layer 111 is prepared using an atomic layer deposition process, which allows the atomic ratio of the film to be controlled according to the desired atomic ratio, thereby accurately forming the sub-active layer 111 with a predetermined atomic ratio. This method is simple and highly accurate.

[0068] Specifically, the active layer 11 includes a first side A1 and a second side A2, and the first side A1 and the second side A2 are arranged along a first direction x. The preparation method further includes:

[0069] S400 , forming a gate 13 on the first side A1 or the second side A2 , wherein the gate 13 is insulated from the active layer 11 .

[0070] S600 , forming a source-drain layer 12 on the first side A1 , wherein the source-drain layer 12 is connected to the active layer 11 and insulated from the gate 13 .

[0071] Before the above step S200, the process may further include S100: providing a substrate 18, and sequentially forming a buffer layer 17, a light shielding layer 16, and a second insulating layer 15 on the substrate 18; or providing a substrate 18, and sequentially forming a buffer layer 17, a gate 13, and a first insulating layer 14 on the substrate 18. This application does not specifically limit this.

[0072] The present application also provides an array substrate 2 , as shown in FIG10 , comprising any one of the thin film transistors 1 provided in the above embodiments of the present application.

[0073] In the array substrate 2 provided herein, the better the mobility and light stability of the thin-film transistor 1, the better the performance of the array substrate 2. Furthermore, the fabrication process of the thin-film transistor 1 in the array substrate 2 provided herein is relatively simple, ensuring both its own mobility and light stability while taking into account the difficulty of etching, thus helping to reduce fabrication costs.

[0074] The present application also provides a display panel 3 , as shown in FIG11 , comprising the array substrate 2 provided in the above embodiment of the present application.

[0075] The array substrate 2 in the display panel 3 provided in the present application has better performance and better driving effect, thereby making the performance of the display panel 3 better.

Claims

1. A thin film transistor, wherein: An active layer is included, wherein the active layer includes a plurality of sub-active layers, the plurality of sub-active layers are stacked along a first direction, the sub-active layers include crystalline oxide materials, and the atomic number ratios of indium elements in adjacent sub-active layers are different.

2. The thin film transistor according to claim 1, wherein: The crystalline oxide material includes indium gallium oxide, and the ratio of the total number of atoms in the indium gallium oxide to the total number of atoms in the crystalline oxide material is 70%-100%.

3. The thin film transistor according to claim 2, wherein: The multiple sub-active layers include at least one first sub-active layer and at least one second sub-active layer, the atomic number ratio of the indium element in the first sub-active layer is smaller than the atomic number ratio of the indium element in the second sub-active layer, and the atomic number ratio of the gallium element in the first sub-active layer is larger than the atomic number ratio of the gallium element in the second sub-active layer.

4. The thin film transistor according to claim 3, wherein: The first sub-active layer and the second sub-active layer are alternately arranged along the first direction, the active layer includes a first side and a second side, the first side and the second side are arranged along the first direction, one layer of the first sub-active layer is close to the first side, and one layer of the second sub-active layer is close to the second side.

5. The thin film transistor according to claim 3, wherein: The number of atoms of the indium element in the first active sub-layer is a1, the number of atoms of the gallium element is b1, k1=a1 / (a1+b1), k2=b1 / (a1+b1), wherein 50%≤k1≤80%, 20%≤k2≤50%.

6. The thin film transistor according to claim 3, wherein: The number of atoms of the indium element in the second active sub-layer is a2, the number of atoms of the gallium element is b2, k3=a2 / (a2+b2), k4=b2 / (a2+b2), wherein 80%≤k3≤100%, 0≤k4≤20%.

7. The thin film transistor according to claim 3, wherein: The size of the active layer along the first direction is 3nm-50nm.

8. The thin film transistor according to claim 7, wherein: The size of the first sub-active layer along the first direction is 1 nm-10 nm.

9. The thin film transistor according to claim 7, wherein: The size of the second sub-active layer along the first direction is 0.5 nm-5 nm.

10. The thin film transistor according to claim 4, wherein: In the active layer, the atomic number ratio of the indium element in the sub-active layer close to the first side and / or close to the second side is greater than or equal to the atomic number ratio of the indium element in any other sub-active layer.

11. The thin film transistor according to claim 1, wherein: The active layer further includes doping particles, and the ratio of the total number of atoms of the doping particles to the total number of atoms in the crystalline oxide material is greater than 0 and less than or equal to 30%.

12. The thin film transistor according to claim 11, wherein: The doping particles include tin and / or germanium.

13. The thin film transistor according to claim 1, wherein: The active layer includes a first side and a second side, the first side and the second side are arranged along the first direction, and the thin film transistor further includes: a source-drain electrode layer, formed on the first side and connected to the active layer; A gate is formed on the first side and / or the second side and is insulated from the active layer and the source and drain layer.

14. The thin film transistor according to claim 13, wherein: The gate is formed on the first side, and the gate is insulated from the active layer by a first insulating layer. The invention also includes a second insulating layer, a shading layer, a buffer layer and a substrate which are formed on the second side and stacked in a direction away from the active layer, wherein the orthographic projection of the shading layer on the substrate covers the orthographic projection of the gate on the substrate.

15. The thin film transistor according to claim 13, wherein: The gate is formed on the second side, and the gate is insulated from the active layer by a first insulating layer.

16. A method for preparing a thin film transistor, wherein: include: Crystalline oxide materials with different atomic ratios of indium are deposited successively to sequentially form multiple sub-active layers stacked along a first direction, wherein the atomic ratios of indium in adjacent sub-active layers are different, thereby forming an active layer.

17. The preparation method according to claim 16, wherein: The active layer includes a first side and a second side, the first side and the second side are arranged along the first direction, and the preparation method also includes: forming a gate on the first side or the second side, the gate is insulated from the active layer; forming a source-drain layer on the first side, the source-drain layer is connected to the active layer and is insulated from the gate.

18. The preparation method according to claim 16, wherein: The crystalline oxide material is deposited using an atomic layer deposition process.

19. An array substrate, wherein: Comprising a thin film transistor as described in any one of claims 1 to 15.

20. A display panel, wherein: Comprising the array substrate as claimed in claim 19.

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