Data processing method, memory controller and storage system

Abstract

Provided in at least one embodiment of the present disclosure are a data processing method, a memory controller and a storage system. The data processing method comprises: reading four pieces of burst data from a single memory channel; organizing the four pieces of burst data into a group of error correcting code words, the group of error correcting code words comprising k read-back data symbols and m read-back check symbols, and the total bit width of the m read-back check symbols being eight times the bit width of one symbol; and, on the basis of the group of error correcting code words, performing a decoding operation so as to obtain symbols of which errors have been corrected. By reading the four pieces of burst data from the single memory channel and executing one ECC operation, the data processing method can simultaneously correct errors of, for example, two or more symbols.

Description

Data processing method, memory controller and storage system

[0001] This application claims priority to Chinese Patent Application No. 202311247611.1 filed on September 25, 2023, and the contents of the above-mentioned Chinese patent application disclosure are hereby incorporated by reference in their entirety as a part of this application. Technical Field

[0002] Embodiments of the present disclosure relate to a data processing method, a memory controller, a storage system, an electronic device, and a storage medium. Background Art

[0003] Data is easily disturbed by environmental factors during transmission, communication, and storage, leading to data errors. For example, Double Data Rate (DDR) memory (e.g., DDR SDRAM or DDR memory) is inevitably disturbed by environmental factors such as electromagnetic interference during operation, which can cause memory errors. For users with high stability requirements, memory errors can cause fatal problems. For example, servers have relatively high requirements for DDR data reliability. DDR memory error correction technology can improve the stability and error correction capabilities of server memory. For example, memory modules that support Error Correcting Code (ECC) can improve the stability and error correction capabilities of server memory.

[0004] For some DDR memory, when a correctable error (CE) occurs, the memory DIMM does not need to be replaced immediately. However, if an uncorrectable error (UE) occurs, if two memory chips fail simultaneously, an uncorrectable error will be reported. In this case, data is generally lost and cannot be recovered. This data loss will affect the execution of corresponding operations by the processor or other computing units, causing related functions or applications to not operate normally, or even causing a system crash.

[0005] Summary of the Invention

[0006] A first aspect of the present disclosure provides a data processing method comprising: reading four bursts of data from a single storage channel; organizing the four bursts of data into a group of error correction codewords, wherein the group of error correction codewords includes k read-back data codewords and m read-back check codewords, and the total bit width of the m read-back check codewords is eight times the bit width of a codeword; and performing a decoding operation based on the group of error correction codewords to obtain error-corrected codewords.

[0007] A second aspect of the present disclosure provides a memory controller, comprising: a read unit configured to: read four bursts of data from a single storage channel; organize the four bursts of data into a group of error correction codewords, wherein the group of error correction codewords includes k read-back data codewords and m read-back check codewords, and the total bit width of the m read-back check codewords is eight times the bit width of a codeword; and a decoding unit configured to: perform a decoding operation based on the group of error correction codewords to obtain error-corrected codewords.

[0008] A third aspect of the present disclosure provides a storage system, including: the memory controller as described above; and a storage unit.

[0009] A fourth aspect of the present disclosure provides an electronic device comprising: one or more processors; a memory comprising one or more computer program modules; wherein the one or more computer program modules are stored in the memory and configured to be executed by the one or more processors to implement the processing method described above.

[0010] A fifth aspect of the present disclosure provides a non-transitory readable storage medium having computer-executable instructions stored thereon, wherein the computer-executable instructions, when executed by a processor, implement the processing method described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings of the embodiments of the present disclosure. Obviously, the drawings described below only relate to some embodiments of the present disclosure, and are not intended to limit the present disclosure.

[0012] FIG1 shows a flow chart of a method for processing data according to at least one embodiment of the present disclosure;

[0013] FIG2 shows a schematic diagram of a memory controller according to at least one embodiment of the present disclosure;

[0014] FIG3 shows a structural diagram of simultaneously correcting errors in multiple memory chips according to at least one embodiment of the present disclosure;

[0015] FIG4 shows a schematic diagram of a storage system according to at least one embodiment of the present disclosure;

[0016] FIG5 shows a schematic diagram of a memory subsystem according to at least one embodiment of the present disclosure;

[0017] FIG6 shows a schematic diagram of an electronic device according to at least one embodiment of the present disclosure; and

[0018] FIG. 7 shows a schematic diagram of a non-transitory readable storage medium according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0019] Reference will now be made in detail to specific embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Although the present disclosure will be described in conjunction with specific embodiments, it will be understood that the disclosure is not intended to be limited to the described embodiments. On the contrary, it is intended to cover variations, modifications, and equivalents within the spirit and scope of the present disclosure as defined by the appended claims. It should be noted that the method operations described herein can be implemented by any functional block or functional arrangement, and any functional block or functional arrangement can be implemented as a physical entity or a logical entity, or a combination of the two.

[0020] In order to enable those skilled in the art to better understand the present disclosure, the present disclosure is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0021] Note that the examples described below are merely specific examples and are not intended to limit the embodiments of the present disclosure to the specific configurations, hardware, connections, operations, values, conditions, data, sequences, etc. shown and described. Those skilled in the art can apply the concepts of the present disclosure to construct further embodiments not described herein by reading this specification.

[0022] The terms used in this disclosure are those commonly used in the art currently in consideration of the functions of the present disclosure, but these terms may vary according to the intentions of those skilled in the art, precedents, or new technologies in the art. In addition, specific terms may be selected by the applicant, and in such cases, their detailed meanings will be described in the detailed description of the present disclosure. Therefore, the terms used in the specification should not be understood as simple names, but rather as a general description based on the meaning of the terms and the present disclosure.

[0023] Flowcharts are used in this disclosure to illustrate the operations performed by the systems according to the embodiments of the present application. It should be understood that the preceding or following operations are not necessarily performed in exact order. Instead, the various steps may be processed in reverse order or simultaneously, as needed. Furthermore, other operations may be added to these processes, or one or more operations may be removed from these processes.

[0024] First, the abbreviations and related terms involved in this application are defined and explained.

[0025] Double-Symbol Correction (DSC): A technology that can correct two symbols at once.

[0026] DDR (Double Data Rate): Double data rate.

[0027] DDR SDRAM: Double data rate synchronous dynamic random access memory, commonly known as DDR.

[0028] Error Check Correction (ECC): A technology that can implement "error checking and correction" to improve the stability and reliability of computer operation.

[0029] RS (Reed-Solomon) code: also known as Reed-Solomon code or Reed-Solomon code (i.e. Reed-Solomon code), is a forward error correction channel code that is effective for polynomials generated by correcting oversampled data. RS code is a special type of non-binary BCH code with strong error correction capability. For any positive integer S, a corresponding q-based BCH code with a code length of n=qS-1 can be constructed, where q is a power of a prime number. When S=1 and q>2, the q-based BCH code with a code length of n=q-1 is called an RS code. When q=2 m (m>1), whose code element symbols are taken from F(2m), can be used to correct burst errors. It is the most commonly used RS code.

[0030] MDEC (Multi Device Error Correction): Multi-device error correction

[0031] SDDC (Single Device Data Correction): Corrects data on a single device

[0032] DDDC (Double Device Data Correction): Corrects data on two devices

[0033] Memory channel: abbreviated as channel. Each memory controller can have multiple memory channels. These memory channels are the data transmission paths between the memory and the memory controller on the processor (such as the CPU). For example, common memory channels include memory channel 0 and memory channel 1.

[0034] UE (Uncorrectable Error): Uncorrectable error.

[0035] CE (Correctable Error): Correctable error.

[0036] Data Device: A device that stores data. In DDR memory, it is also called a data memory device.

[0037] ECC Device: A device that stores parity bits. In DDR memory, it is also called an ECC device.

[0038] Storage granules: Data storage granules and parity storage granules are collectively referred to as storage granules. In DDR memory, storage granules are also called memory granules, and can be used as a collective term for data memory granules and parity memory granules.

[0039] Symbol: Also known as code element, it is the smallest unit used in ECC error correction. It usually has x4 and x8 particles, and the corresponding symbol is 4 bits and 8 bits of data.

[0040] ECC word (ECC Word), the target data for performing ECC operation, is embodied in the form of data bits + check information in a memory architecture that supports ECC.

[0041] It is understood that the terms defined above are merely exemplary definitions in specific application scenarios to facilitate a better understanding of the present application. For example, the exemplary definitions described above for a specific memory can be extended to other types of memory or other storage.

[0042] For memory (such as DDR memory), if two memory chips fail simultaneously, the current system will report an uncorrectable error, which cannot be corrected. Even after rereading, the uncorrectable error will still be detected, resulting in data loss and, in severe cases, system downtime. Using hardware to record information such as the location of previous correctable errors and using algorithms for post-processing to correct both memory chips individually can partially resolve the issue of two simultaneous errors. However, this requires a number of prerequisites and has a low coverage rate.

[0043] An exemplary mainstream method for correcting two errors is DDDC, which mainly includes the following points:

[0044] ● Lockstep needs to be enabled;

[0045] ● In terms of algorithm, ECC uses parity bit (Parity) + cyclic redundancy check code (CRC);

[0046] ●One algorithm operation can only correct one memory particle;

[0047] ●When correcting the second memory chip, the previously faulty memory chip must first be replaced and written into the redundant memory chip (spare device), and then the algorithm is used to find the second faulty memory chip.

[0048] ● Errors in two memory chips can only be corrected in a time-sharing manner. If two memory chips fail at the same time, DDDC technology is powerless and the system will report an uncorrectable error.

[0049] The hardware structure used in the technology provided by at least one embodiment of the present disclosure does not require any prerequisites. When random errors occur in multiple data particles, each particle has an error of 1 to 2 bits. There is no need to unlock lock synchronization, nor is there a need for hardware to record previous information. The hardware can complete multi-particle error correction, which can greatly improve the error correction capability. In addition, it can improve the reliability of storage (such as memory), further reducing the risk of data loss and system downtime.

[0050] At least one embodiment of the present disclosure provides a data processing method, memory controller, storage system, electronic device, and storage medium. For example, when multiple memory cell errors occur at any moment, with each cell having, for example, 1-2 bits of errors, the hardware structure of at least one embodiment of the present disclosure can simultaneously correct the errors without requiring software intervention or relying on historical data. This significantly improves memory reliability and reduces the risk of data loss and system downtime.

[0051] The following describes in detail a data processing method, a memory controller, a storage system, an electronic device, and a storage medium according to at least one embodiment of the present disclosure with reference to the accompanying drawings.

[0052] First, the data processing method of an embodiment of the present disclosure is introduced below. The data processing method can be applied to a memory controller, a storage system, an electronic device, and other suitable software or hardware, or a combination of hardware and software as further described below.

[0053] FIG1 shows a flowchart of a data processing method 100 according to at least one embodiment of the present disclosure. The data processing method may include steps S102 to S106 .

[0054] In step S102 , four burst data are read from a single storage channel.

[0055] In some embodiments, four bursts of data may correspond to encoded data stored in a single storage channel, the encoded data may be obtained by encoding k data symbols written into the single storage channel, the encoded data may include k data symbols and m check symbols, where the total bit width of the m check symbols is eight times the bit width of a symbol.

[0056] In some embodiments, depending on the arrangement of the data storage particles and the check storage particles corresponding to the storage channel, the data bits and check bits included in each burst of data may change. For example, in an exemplary DDR4 or DDR5, a single storage channel may correspond to 8 x4 data memory particles and 2 x4 check memory particles (ecc memory particles), and each burst of data (Burst) includes 8*4=32 bits of data bits and 2*4=8 bits of check bits. However, the present disclosure is not limited to this. However, it will be understood that in order to correct a codeword, a check codeword with a bit width twice that of a codeword is generally required. For example, the bit width of a codeword is 4 bits, and an 8-bit check codeword is generally required for error correction.

[0057] In some embodiments, the data symbols may be decoded and error-corrected (if necessary) during a decoding operation to obtain data or instructions for performing calculations to implement a predetermined function. Check symbols may provide information during decoding and error correction (if necessary) to ensure that correct data is obtained.

[0058] An exemplary memory channel may be one of two memory channels (memory channel 0 (Ch0) and memory channel 1 (Ch1)) such as in a memory controller used for, for example, DDR4 or DDR5.

[0059] In step S104 , the four burst data are organized into a set of error correction codewords, wherein the set of error correction codewords includes k read-back data symbols and m read-back check symbols, and the total bit width of the m read-back check symbols is eight times the bit width of one symbol.

[0060] In some embodiments, the four bursts of data (also referred to herein as readback coded data, which is essentially coded data read from a single storage channel) correspond to the coded data to obtain corresponding correct data. However, the coded data may be subject to interference from environmental factors such as electromagnetic interference during transmission or within the storage unit, resulting in data errors. Therefore, the k readback data symbols (i.e., data symbols read back from a single storage channel) and the m readback check symbols (i.e., check symbols read back from a single storage channel) may differ from the k data symbols and m check symbols included in the coded data.

[0061] In some embodiments, the storage unit may be a memory itself, such as a DDR memory or a DDR internal memory. In other embodiments, the storage unit may be a storage array in a memory.

[0062] In step S106, a decoding operation is performed based on a set of error correction codewords to obtain error-corrected codewords.

[0063] The decoding operation here may refer to performing an ECC operation on the above-mentioned set of error correction codewords to obtain error-corrected data codewords and / or error-corrected check codewords.

[0064] Thus, the data processing method according to at least one embodiment of the present disclosure can simultaneously correct errors in, for example, two or more symbols or code elements by reading four bursts of data from a single storage channel and performing a single ECC operation. For example, without disabling synchronization lock, it can effectively address the issue of multiple symbol half-chip errors occurring simultaneously.

[0065] In some examples, errors in two or more code elements or symbols may occur in two or more storage cells, and thus error correction of two or more storage cells may be implemented.

[0066] Other aspects of the data processing method according to at least one embodiment of the present disclosure are described in detail below.

[0067] For example, according to the data processing method of at least one embodiment of the present disclosure, four burst data are organized into a group of error correction codewords, including: combining the burst data corresponding to the same pin of the same storage particle in the four burst data read by a single storage channel into one of k read-back data code elements or m read-back check code elements to obtain k read-back data code elements and m read-back check code elements; and connecting the k read-back data code elements and the m read-back check code elements to obtain a group of error correction codewords.

[0068] For example, the burst data corresponding to the same pin of the same data storage particle in the four burst data read by a single storage channel are combined into one of k read-back data code elements, and the data corresponding to the same check storage particle in the four burst data read by a single storage channel are combined into one of m read-back check code elements, thereby obtaining k read-back data code elements or m read-back check code elements (collectively referred to as multiple symbols), and the multiple symbols are connected into a group of error correction code words (i.e., ECC words).

[0069] The inventors of the present disclosure have realized that the erroneous bits in multiple data sets usually correspond to the pins of the same storage particle, where one pin corresponds to one bit of a data set. For example, when an error occurs on a pin of a storage particle, the data corresponding to the pin from the multiple data sets are usually erroneous. Based on this, the data processing method according to at least one embodiment of the present disclosure takes the pins of the storage particles as units, combines the data corresponding to the same pins of the same storage particles in four bursts of data into one symbol (i.e., a 4-bit symbol), so as to obtain multiple symbols for a single storage channel, and connects the multiple symbols into a group of error correction codewords, i.e., forms a group of error correction codewords for a single storage channel. This organization method of ECC words based on the pins of the storage particles can reflect the erroneous data for the same pin in four bursts of data into a single symbol, thereby improving the error correction capability.

[0070] Of course, the embodiments of the present disclosure are not limited to this. The data corresponding to the same pin of the same storage particle in the four burst data can be divided into two or more units or combined into a symbol (i.e., a symbol of 8 bits or more bits) to obtain multiple symbols for a single storage channel, and the multiple symbols can be organized (for example, connected) into a group of error correction code words.

[0071] For example, according to the data processing method of at least one embodiment of the present disclosure, a single storage channel corresponds to 8 data storage particles and 2 check storage particles. Each of the 8 data storage particles and the 2 check storage particles has a bit width of 4 bits.

[0072] In this way, the data processing method according to at least one embodiment of the present disclosure can be applied to specific application scenarios. For example, a single storage channel can be one of Ch0 or Ch1 for DDR5 or other storage channels with the same structure to achieve error correction of multiple symbols of the corresponding memory.

[0073] Of course, the embodiment is not limited to this. In other variations, a single storage channel may correspond to a first number of data storage particles and a second number of verification storage particles. The bit width of each storage particle in the data storage particles and the verification storage particles may be the same or different, and the bit width may be 4 bits, 8 bits or other bits.

[0074] For example, according to the data processing method of at least one embodiment of the present disclosure, the same pin burst data corresponding to the same storage particle in four burst data read by a single storage channel are combined into a group of error correction codewords, including: performing the following operations on each storage particle in 8 data storage particles and 2 check storage particles to obtain data including 32 data symbols and 8 check symbols as a group of error correction codewords: organizing the data corresponding to the first bit of the 4 bits in the four burst data into a first symbol; organizing the data corresponding to the second bit of the 4 bits in the four burst data into a second symbol; organizing the data corresponding to the third bit of the 4 bits in the four burst data into a third symbol; and organizing the data corresponding to the fourth bit of the 4 bits in the four burst data into a fourth symbol.

[0075] In this way, the data processing method according to at least one embodiment of the present disclosure can implement the organization of ECC words with pins as units for 8 x4 data storage particles and 2 x4 parity storage particles.

[0076] Of course, the embodiment is not limited thereto. In other variations as described above, a group of error correction codewords can be similarly combined, as long as the data corresponding to the same bit in the plurality of bits in the four burst data are organized into one symbol.

[0077] For example, according to the data processing method of at least one embodiment of the present disclosure, the single storage channel is a single memory channel for DDR5. For example, the single memory channel can be Ch0 or Ch1 for DDR5.

[0078] In this way, the data processing method according to at least one embodiment of the present disclosure can be applied to DDR5.

[0079] For example, according to the data processing method of at least one embodiment of the present disclosure, encoding and decoding operations may use a Vandermonde matrix or RS code.

[0080] For Vandermonde-like matrix or RS code technology, see, for example, application publication number CN112688693A, entitled "A Memory Multi-Matrix Encoding Method, Error Correction Method, and Related Device," application publication number CN116092567A, entitled "Data Processing Method, Processing Device, and Storage System," application publication number CN116028260A, entitled "Data Processing Method, Processing Device, and Storage System," and application publication number CN110071727A, entitled "Encoding Method, Decoding Method, Error Correction Method, and Device." These applications are incorporated herein by reference and made a part hereof.

[0081] The following exemplary descriptions illustrate how encoding and decoding operations may utilize one or more aspects of Vandermonde-like matrices.

[0082] For example, according to at least one embodiment of the present disclosure, a data processing method for encoding k data symbols written into a single storage channel includes: encoding the k data symbols based on an encoding matrix; performing a decoding operation based on a set of error correction codewords to obtain error-corrected symbols, including: decoding the set of error correction codewords based on a decoding matrix to obtain syndrome data; and obtaining the error-corrected symbols using the syndrome data, wherein the encoding matrix is ​​a matrix having at least k+m rows and k columns and including a Vandermonde-like matrix, and the decoding matrix is ​​a matrix having at least m rows and k+m columns and including a Vandermonde-like matrix, wherein the Vandermonde-like matrix is ​​a matrix associated with the Vandermonde matrix, wherein k≤p n -1, m≤p n , where n is the number of bits in each symbol and p is the capacity of a single bit.

[0083] Thus, the data processing method according to at least one embodiment of the present disclosure is based on a Vandermonde-like matrix. Compared to RS codes, it can support more check symbols and data symbols, thereby increasing the code rate and thus improving error correction capabilities, and is easy to expand. However, the embodiments are not limited to this, and the above encoding and decoding can also be implemented using other methods.

[0084] In some embodiments, according to the processing method of at least one embodiment of the present disclosure, the coding matrix may include a first interval and a second interval, wherein the first interval may include a unit matrix of k rows and k columns, and the second interval may include a Vandermonde-like matrix of m rows and k columns; and encoding k data codewords based on the coding matrix may include: multiplying the k data codewords using the unit matrix of k rows and k columns to obtain k data codewords; and multiplying the k data codewords using the Vandermonde-like matrix of m rows and k columns to obtain m check codewords.

[0085] Thus, the processing method according to at least one embodiment of the present disclosure can form multiple encoding matrices, thereby increasing the flexibility of the generated encoding matrices. It is understood that the encoding matrix can also include other intervals, and 0, 1, or other suitable values ​​can be set in these intervals without affecting the implementation of the above encoding.

[0086] In some embodiments, according to the processing method of at least one embodiment of the present disclosure, the decoding matrix may include a third interval and a fourth interval, wherein the third interval may include a Vandermonde-like matrix with m rows and k columns, and the fourth interval may include an identity matrix with m rows and m columns; and decoding the readback encoded data based on the decoding matrix to obtain syndrome data may include: using the decoding matrix to multiply k readback data code elements and m readback check code elements to obtain syndrome data.

[0087] Thus, the processing method according to at least one embodiment of the present disclosure can form multiple decoding matrices, thereby increasing the flexibility of the formed decoding matrices. It is understood that the decoding matrix can also additionally include other intervals, and 0, 1, or other suitable values ​​can be set in these other intervals without affecting the implementation of the above decoding.

[0088] In some embodiments, according to a processing method according to at least one embodiment of the present disclosure, obtaining error-corrected codewords using syndrome data may include: reading syndrome data; in response to the syndrome data being all 0, outputting k readback data codewords as error-corrected codewords, wherein the syndrome data being all 0 may indicate that the k readback data codewords and the m readback check codewords have no errors; in response to the syndrome data having one 1, outputting k readback data codewords as error-corrected codewords, wherein the syndrome data having one 1 may indicate that the k readback data codewords have no errors and that the m readback check codewords have the same error. The readback check codeword corresponding to the companion data whose syndrome is 1 has an error; in response to the companion data having v 1s, the error codewords in the k readback data codewords and the m readback check codewords are corrected using the companion data to obtain error-corrected codewords, wherein the companion data having v 1s can indicate that v1 readback data codewords corresponding to the companion data whose syndrome is 1 in the k readback data codewords have errors and v2 readback check codewords corresponding to the companion data whose syndrome is 1 in the m readback check codewords have errors, wherein v≥2, v1≤m, v2≤m, and v1+v2=v.

[0089] In this way, the processing method according to at least one embodiment of the present disclosure can determine whether the readback data codewords and the readback check codewords are erroneous and the error locations based on the obtained syndrome data.

[0090] For example, according to the data processing method of at least one embodiment of the present disclosure, the Vandermonde-like matrix includes a Vandermonde matrix, a left-right flip of a Vandermonde matrix, an up-down flip of a Vandermonde matrix, or a transpose of a Vandermonde matrix.

[0091] For example, according to the data processing method of at least one embodiment of the present disclosure, the encoding and decoding operations can use the Vandermonde matrix. An exemplary Vandermonde matrix can have the following form:

[0092] For example, according to the data processing method of at least one embodiment of the present disclosure, the number of rows and columns of the Vandermonde-like matrix can be adaptively adjusted according to the ECC word.

[0093] Corresponding to the data processing method according to at least one embodiment of the present disclosure, the present disclosure also provides a memory controller.

[0094] FIG2 shows a schematic diagram of a memory controller 200 according to at least one embodiment of the present disclosure. As shown in FIG2 , the memory controller 200 includes a reading unit 210 and a decoding unit 220. The decoding unit can be a decoder or a part of a decoder. It is understood that the memory controller 200 can alternatively or additionally include other units, such as an encoding unit (or encoder) for performing encoding operations. For example, the reading unit 210 can be part of the transceiver unit of the memory controller, and the decoding unit 220 can be part of the codec unit of the memory controller.

[0095] The read unit 210 is configured to read four bursts of data from a single storage channel; organize the four bursts of data into a group of error correction codewords, wherein the group of error correction codewords includes k read-back data codewords and m read-back check codewords, and the total bit width of the m read-back check codewords is eight times the bit width of one codeword.

[0096] The decoding unit 220 is configured to perform a decoding operation based on a set of error correction codewords to obtain error-corrected codewords.

[0097] Thus, a data memory controller according to at least one embodiment of the present disclosure can simultaneously correct errors in, for example, two or more symbols or code elements by reading four bursts of data from a single memory channel through a single ECC operation. For example, without enabling synchronization lock, this effectively addresses the issue of multiple code element half-chip errors occurring simultaneously.

[0098] Other exemplary aspects of the memory controller according to at least one embodiment of the present disclosure are described in detail below.

[0099] For example, in a data memory controller according to at least one embodiment of the present disclosure, the read unit is further configured to: combine burst data corresponding to the same pin of the same storage particle in four burst data read by a single storage channel into one of k read-back data code elements or m read-back check code elements to obtain k read-back data code elements and m read-back check code elements; and connect the k read-back data code elements and the m read-back check code elements to obtain a set of error correction code words.

[0100] For example, in a data memory controller according to at least one embodiment of the present disclosure, a single storage channel corresponds to 8 data storage particles and 2 check storage particles, and the bit width of each of the 8 data storage particles and the 2 check storage particles is 4 bits.

[0101] For example, in a data memory controller according to at least one embodiment of the present disclosure, the reading unit is further configured to: perform the following operations on each of the 8 data storage particles and the 2 check storage particles to obtain data including 32 data symbols and 8 check symbols as a set of error correction codewords: organize the data corresponding to the first bit of the 4 bits in the four burst data into a first symbol; organize the data corresponding to the second bit of the 4 bits in the four burst data into a second symbol; organize the data corresponding to the third bit of the 4 bits in the four burst data into a third symbol; and organize the data corresponding to the fourth bit of the 4 bits in the four burst data into a fourth symbol.

[0102] For example, in a data memory controller according to at least one embodiment of the present disclosure, the single storage channel is a single memory channel for DDR5.

[0103] The above only describes a portion of the memory controller 200 according to at least one embodiment of the present disclosure in combination with Figure 2, and the remaining portions of the memory controller 200 can refer to various aspects of the data processing method 100 described in combination with Figure 1 of the present disclosure, and the effects of various aspects of the data processing method 100 described in combination with Figure 1 of the present disclosure can also be mapped to the memory controller 200 described in combination with Figure 2 of the present disclosure, which will not be repeated here.

[0104] For example, the memory controller 200 according to at least one embodiment of the present disclosure may alternatively or additionally include an encoding unit to perform the above encoding.

[0105] An example application scenario in which the data processing method or memory controller according to at least one embodiment of the present disclosure can be utilized is described below with reference to FIG3. It will be understood that the application scenario shown in FIG3 is merely exemplary and does not exhaustively illustrate all aspects of the data processing method or memory controller described above, and that the aspects described in conjunction with FIG3 may be referenced in conjunction with the aspects described in conjunction with FIG1 and FIG2 without exceeding the scope of the present disclosure.

[0106] In this example application scenario, using Ch0 for DDR5 (shown as DDR5 Ch0) as the single memory channel, if multiple memory chip errors occur at any time, with each chip failing with 1-2 bits, the hardware structure of the present invention can be used to simultaneously correct multiple memory chip errors without software involvement or relying on historical records. This significantly improves memory reliability and reduces the risk of data loss and system downtime.

[0107] FIG3 shows a structural diagram of simultaneously correcting errors in multiple memory cells according to at least one embodiment of the present disclosure.

[0108] In the application scenario shown in Figure 3, taking a memory chip with a one-bit error as an example, a single ECC operation can simultaneously correct errors in up to four memory chips. This method can achieve the following technical effects:

[0109] ●Can correct errors in 4 memory chips, with each memory chip having 1 bit of data error; and the error bit position is arbitrary.

[0110] ●Can correct errors in three memory chips, where two memory chips have a single-bit error and the other has a two-bit error. The error can occur in any memory chip and in any bit position.

[0111] ● It can correct errors in two memory chips. These errors can occur in two memory chips, two bits of data error each, one bit error in one memory chip, and three bits error in another. The error can occur in any memory chip, and the location of the error bit is also arbitrary.

[0112] ● A single memory chip error can be corrected, with a 4-bit error. This means the memory supports four-bit error correction (x4 chipkill). The error can be in any memory chip.

[0113] One or more aspects of the application scenario shown in FIG3 are described in detail below.

[0114] Referring to FIG. 3 , DDR5 Ch0 corresponds to 8 x4 data memory particles (8 memory particles shown as “x4” in FIG. 3 ) and 2 x4 check memory particles (2 memory particles shown as “ecc” in FIG. 3 ).

[0115] Read or receive four bursts of data: Burst0, Burst1, Burst2, and Burst3 from DDR5 Ch0. Among them, Burst0 includes data D0, D4, D8, D12, D16, D20, D24, D28 corresponding to 8 x4 data memory particles and data C0 and C4 corresponding to two x4 check memory particles; Burst1 includes data D1, D5, D9, D13, D17, D21, D25, D29 corresponding to 8 x4 data memory particles and data C1 and C5 corresponding to two x4 check memory particles; Burst2 includes data D2, D6, D10, D14, D18, D22, D26, D30 corresponding to 8 x4 data memory particles and data C2 and C6 corresponding to two x4 check memory particles; Burst3 includes data D3, D7, D11, D15, D19, D23, D27, D31 corresponding to 8 x4 data memory particles and data C3 and C7 corresponding to two x4 check memory particles.

[0116] For example, D0-D31 and C0-C7 of the four burst data may be generated by encoding the data corresponding to D0-D31. In the absence of an error, D0-D31 is consistent with the corresponding data, but in the event of an error, D0-D31 is inconsistent with the corresponding data.

[0117] In the example application scenario shown in Figure 3, using x4-bit memory chips as an example, multiple bit errors can be corrected without enabling the lock synchronization function. When writing data, a data entry is only written to a burst of four data entries per memory channel. In the DDR5 Ch0 shown in the figure, a data entry corresponds to or is reflected in Burst 0 / 1 / 2 / 3. The four data entries read from Burst 0 / 1 / 2 / 3 total 160 bits and form a single ECC word.

[0118] A group of ECC words is formed by organizing the data of the same pins (reflected as the same bits of the same storage particles) of the same storage particles (data memory particles and check memory particles) in four burst data into one symbol.

[0119] For example, the four 4×4 boxes shown in the middle of Figure 3 each illustrate a detailed schematic diagram of the data structure of four bursts of data from four x4-bit memory cells (i.e., the four dashed boxes in the upper portion of Figure 3). Each row in the 4×4 box corresponds to one of the four bursts of data from the corresponding x4-bit memory cell, and each column in the 4×4 box corresponds to one of the four bits of the corresponding x4-bit memory cell.

[0120] The bottom portion of FIG. 3 shows four 4-bit symbols, where each symbol is composed of data corresponding to the same bit in four bursts of data in a corresponding x4-bit memory cell.

[0121] Therefore, for the memory chip corresponding to DDR5 Ch0, the exemplary ECC word composition structure is:

[0122] Symbol 1 is a symbol composed of the highest bit 3 of D0 / D1 / D2 / D3 corresponding to the four data of Burst 0 / 1 / 2 / 3 of the first x4 data memory element;

[0123] Symbol 2 is a symbol composed of the bit 2 data of D0 / D1 / D2 / D3 corresponding to the four data of Burst0 / 1 / 2 / 3 of the first x4 data memory particle;

[0124] Symbol 3 is a symbol composed of the bit 1 data of D0 / D1 / D2 / D3 corresponding to the four data of Burst0 / 1 / 2 / 3 of the first x4 data memory particle;

[0125] Symbol 4 is a symbol composed of the bit 0 data of D0 / D1 / D2 / D3 corresponding to the four data of Burst 0 / 1 / 2 / 3 of the first x4 data memory particle;

[0126] …

[0127] DDR5 has a data bit width of 40 bits (8 data memory chips + 2 parity memory chips). Each data bit position (i.e., bit) corresponds to four data items, Burst 0 / 1 / 2 / 3. Each position has a total of 4 bits of data, forming a symbol. In this way, 32 data symbols + 8 parity symbols are formed.

[0128] After ECC is organized, the aforementioned Vandermonde matrix-based algorithm can be used to achieve a single ECC operation that can simultaneously correct four symbol errors. This does not require replacing particle chips like DDDC, nor does it require locking synchronization. While improving error correction capabilities and probabilities, it does not negatively impact DDR performance, and no software involvement is required.

[0129] In the above-mentioned example application scenario, it is possible to correct errors in multiple memory chips at the same time, effectively solving the problem of multiple chip errors reporting to the UE, thereby improving the reliability and robustness of the memory and reducing the risk of data loss and downtime. For example, referring to FIG3 , the application scenario of FIG3 illustrates an example of an error situation in four memory chips, wherein the data errors in the memory chips shown in the four dashed boxes in the upper part of FIG3 are respectively located in the second bit, the third bit, the third bit, and the third bit of the four bits in the corresponding data memory chips shown in the middle part of FIG3 (i.e., the erroneous bits are shown in dark gray). Thus, there are 4 erroneous symbols in the 32 data symbols + 8 check symbols organized. Furthermore, by, for example, using an algorithm based on the Vandermonde matrix, a single ECC operation can be performed to simultaneously correct four symbol errors, thereby achieving error correction for four data memory chips. Of course, the embodiment is not limited to this. The error can also be located in the check memory chip, or both the data memory chip and the check memory chip, the error can also be located in other bits, or the error can also be located in a single memory chip, two memory chips, three memory chips, etc., thereby achieving error correction for the corresponding number of memory chips. The above-mentioned example application scenario is only a part or additional aspect of implementing the data processing method and memory controller according to at least one embodiment of the present disclosure. Other aspects of the above-mentioned example application scenario can refer to the data processing method and memory controller and their additional aspects according to at least one embodiment of the present disclosure.

[0130] FIG4 shows a schematic diagram of a memory system 400 according to at least one embodiment of the present disclosure. As shown in FIG4 , the memory system 400 includes a memory controller 410 and a memory unit 420 .

[0131] Memory controller 410 may be the memory controller described with reference to FIG2 . Storage unit 420 may be any memory that implements data storage. In some embodiments, storage unit 420 may be a memory itself, such as a DDR memory or DDR RAM. In other embodiments, storage unit 420 may be a memory array within a memory.

[0132] 5 shows a schematic diagram of a memory subsystem 500 according to at least one embodiment of the present disclosure. The memory subsystem 500 may be an exemplary embodiment of the storage system 400 described above.

[0133] 5 , memory subsystem 500 may include a memory controller 510 and a memory unit 520. Memory controller 510 may be an exemplary embodiment of the memory controller described above, and memory unit 520 may be an exemplary embodiment of the storage unit described above. For example, the memory unit may be a DDR, such as the DDR5 described above. Memory controller 510 is also commonly referred to as a master control chip.

[0134] The memory unit 520 may include a DDR column group 525. The DDR column group 525 may be an exemplary instance of the DDR5 column group corresponding to the DDR5 Ch0 above. The DDR column group 525 may include a plurality of DRAM particles, such as DRAM particles 522, DRAM particles 524, and DRAM particles 526, etc. These DRAM particles may be an exemplary example of the data storage particles and verification storage particles or data memory particles and verification memory particles above. In addition, the DRAM particles may include encoders, decoders, etc. to perform corresponding encoding operations and ECC operations when reading and writing operations on the DRAM particles. The memory unit 520 may be a dual in-line memory unit (DIMM), a plurality of DRAM particles directly soldered on a circuit board (also called DRAM particle chips), or other forms.

[0135] Continuing with FIG5 , the memory controller 510 can interact with the memory unit 520 via a DDR channel. Although FIG5 illustrates a single DDR channel, embodiments are not limited thereto. The memory subsystem 500 may also include multiple DDR channels. Furthermore, the memory unit 520 may include multiple DDR ranks, although at least one embodiment of the present disclosure is not limited thereto.

[0136] FIG6 shows a schematic diagram of an electronic device 600 according to at least one embodiment of the present disclosure.

[0137] As shown in Figure 6, the electronic device 600 includes a processor 610 and a memory 620. The memory 620 includes one or more computer program modules 621. The one or more computer program modules 621 are stored in the memory 620 and are configured to be executed by the processor 610. The one or more computer program modules 621 include instructions for executing the data processing method according to at least one embodiment of the present disclosure. When executed by the processor 610, the one or more steps of the data processing method according to at least one embodiment of the present disclosure and its additional aspects can be executed. The memory 620 and the processor 610 can be interconnected through a bus system and / or other forms of connection mechanisms (not shown). For example, the bus can be a peripheral component interconnect standard (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The communication bus can be divided into an address bus, a data bus, a control bus, etc.

[0138] For example, the processor 610 may be a central processing unit (CPU), a digital signal processor (DSP), or other processing units with data processing capabilities and / or program execution capabilities, such as a field programmable gate array (FPGA). For example, the central processing unit (CPU) may be an X86 or ARM architecture, a RISC-V architecture, etc. The processor 610 may be a general-purpose processor or a dedicated processor, and may control other components in the electronic device 600 to perform desired functions.

[0139] Exemplarily, the memory 620 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), a hard disk, an erasable programmable read-only memory (EPROM), a portable compact disk read-only memory (CD-ROM), a USB memory, a flash memory, etc. One or more computer program modules 621 may be stored on the computer-readable storage medium, and the processor 610 may execute the one or more computer program modules 621 to implement various functions of the electronic device 600. The computer-readable storage medium may also store various applications and various data, as well as various data used and / or generated by the applications.

[0140] For example, the electronic device 600 may also include input devices such as a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; output devices such as a liquid crystal display, a speaker, a vibrator, etc.; storage devices such as a magnetic tape, a hard disk (HDD or SDD), etc.; and communication devices such as a network interface card such as a LAN card, a modem, etc. The communication device may allow the electronic device 600 to communicate with other devices wirelessly or by wire to exchange data, and perform communication processing via a network such as the Internet. A drive is connected to the I / O interface as needed. A removable storage medium, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive as needed so that a computer program read therefrom can be installed into the storage device as needed.

[0141] For example, the electronic device 600 may further include a peripheral interface (not shown in the figure). The peripheral interface may be various types of interfaces, such as a USB interface, a lightning interface, etc. The communication device may communicate with a network and other devices through wireless communication, such as the Internet, an intranet, and / or a wireless network such as a cellular telephone network, a wireless local area network (LAN), and / or a metropolitan area network (MAN). The wireless communication may use any of a variety of communication standards, protocols, and technologies, including but not limited to Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging, and / or short message service (SMS), or any other suitable communication protocol.

[0142] The electronic device 600 may be, for example, a system on a chip (SOC) or a device including the SOC, and may be any device such as a mobile phone, a tablet computer, a laptop computer, an e-book, a game console, a television, a digital photo frame, a navigation system, a home appliance, a communication base station, an industrial controller, a server, or the like. It may also be any combination of data processing devices and hardware, and the embodiments of the present disclosure are not limited thereto. The specific functions and technical effects of the electronic device 600 may be referred to the above description of the data processing method and its additional aspects according to at least one embodiment of the present disclosure, and will not be repeated here.

[0143] FIG. 7 shows a schematic diagram of a non-transitory readable storage medium 700 according to at least one embodiment of the present disclosure.

[0144] As shown in FIG7 , a non-transitory readable storage medium 700 stores computer instructions 710 , which, when executed by a processor, perform one or more steps of the data processing method and its additional aspects as described above.

[0145] Exemplarily, the non-transitory readable storage medium 700 can be any combination of one or more computer-readable storage media. For example, a computer-readable storage medium includes program code for reading four bursts of data from a single storage channel, program code for organizing the four bursts of data into a group of error correction codewords, and program code for performing a decoding operation based on the group of error correction codewords to obtain error-corrected codewords.

[0146] Exemplarily, when the program code is read by a computer, the computer may execute the program code stored in the computer storage medium and perform, for example, one or more steps of the data processing method and additional aspects thereof according to at least one embodiment of the present disclosure.

[0147] Exemplarily, the non-transitory readable storage medium may include a memory card of a smart phone, a storage component of a tablet computer, a hard disk of a personal computer, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a portable compact disk read-only memory (CD-ROM), a flash memory, and other non-transitory readable storage media or any combination thereof.

[0148] In the detailed description above, for the purpose of explanation rather than limitation, specific details are set forth in order to provide a thorough understanding of the various aspects and embodiments described in this disclosure. In some cases, detailed descriptions of well-known devices, components, circuits and methods are omitted to avoid obscuring the description of the embodiments disclosed herein with unnecessary details. All statements of the principles, aspects and embodiments disclosed herein, as well as their specific examples, are listed herein and are intended to cover both their structural equivalents and functional equivalents. In addition, such equivalents are intended to include currently known equivalents and equivalents developed in the future, that is, any element that performs the same function, regardless of the structure. Therefore, for example, it will be understood that the block diagrams herein may represent conceptual diagrams of illustrative circuit systems or other functional units that embody the principles of the described embodiments. Such functions and the functional blocks shown will be understood to be hardware-implemented and / or computer-implemented.

[0149] The various embodiments of the present disclosure are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0150] It should be noted that, in this article, relational terms such as first, second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. The terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device that includes a series of elements includes not only those elements, but also further includes other elements not explicitly listed, or further includes elements that are inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise..." do not exclude the presence of other identical elements in the process, method, article or device that includes the elements.

[0151] The above descriptions are merely preferred embodiments of the present disclosure and are not intended to limit the present disclosure; the scope of the present disclosure is determined by the claims.

Claims

1. A data processing method, comprising: Read four bursts of data from a single memory channel; Organizing the four burst data into a group of error correction codewords, wherein the group of error correction codewords includes k read-back data codewords and m read-back check codewords, and the total bit width of the m read-back check codewords is eight times the bit width of one codeword; as well as A decoding operation is performed based on the set of error correction codewords to obtain error-corrected codewords.

2. The processing method according to claim 1, wherein: Organizing the four burst data into the group of error correction code words includes: Combining the burst data corresponding to the same pin of the same storage particle among the four burst data read by the single storage channel into one of the k read-back data code elements or the m read-back verification code elements to obtain the k read-back data code elements and the m read-back verification code elements; and The k read-back data symbols and the m read-back check symbols are concatenated to obtain the set of error correction codewords.

3. The processing method according to claim 2, wherein: The single storage channel corresponds to 8 data storage particles and 2 verification storage particles, and the bit width of each storage particle in the 8 data storage particles and the 2 verification storage particles is 4 bits.

4. The processing method according to claim 3, wherein: Combining the same pin burst data corresponding to the same storage particle in the four burst data read by the single storage channel into a group of error correction code words, including: The following operation is performed on each of the eight data storage particles and the two check storage particles to obtain data including 32 data symbols and 8 check symbols as the set of error correction code words: Organizing data corresponding to a first bit of the 4 bits in the four burst data into a first symbol; Organizing data corresponding to a second bit of the 4 bits in the four burst data into a second symbol; Organizing data corresponding to a third bit of the 4 bits in the four burst data into a third symbol; and The data corresponding to the fourth bit of the 4 bits in the four burst data is organized The fourth symbol.

5. The processing method according to claim 3, wherein: The single storage channel is a single memory channel for DDR5.

6. The processing method according to any one of claims 1 to 5, wherein: Encoding k data symbols written into the single storage channel comprises: Encode k data symbols based on the encoding matrix; Performing a decoding operation based on the set of error correction codewords to obtain error-corrected codewords includes: Decoding the set of error correction codewords based on a decoding matrix to obtain syndrome data; and Using the syndrome data to obtain error-corrected codewords, The encoding matrix is ​​a matrix of at least k+m rows and k columns and includes a Vandermonde-like matrix, the decoding matrix is ​​a matrix of at least m rows and k+m columns and includes the Vandermonde-like matrix, wherein the Vandermonde-like matrix is ​​a matrix associated with the Vandermonde matrix, wherein k≤p n -1, m≤p n , where n is the number of bits in each symbol and p is the capacity of a single bit.

7. The processing method according to claim 6, wherein: The encoding matrix includes a first interval and a second interval, wherein the first interval includes a unit matrix with k rows and k columns, and the second interval includes a Vandermonde-like matrix with m rows and k columns; and Encoding k data symbols based on the encoding matrix includes: Multiplying the k data symbols by the k-row and k-column identity matrix to obtain the k data symbols; and The m check symbols are obtained by multiplying the k data symbols by the m-row and k-column Vandermonde-like matrix.

8. The processing method according to claim 6, wherein: The decoding matrix includes a third interval and a fourth interval, wherein the third interval includes a Vandermonde-like matrix with m rows and k columns, and the fourth interval includes an identity matrix with m rows and m columns; and Decoding the set of error correction codewords based on a decoding matrix to obtain syndrome data includes: The syndrome data is obtained by multiplying the k readback data symbols and the m readback check symbols using the decoding matrix.

9. The processing method according to claim 6, wherein: Obtaining the error-corrected codeword using the syndrome data comprises: Reading the companion data; In response to the syndrome data being all 0, outputting the k read-back data symbols as the error-corrected symbols, wherein the syndrome data being all 0 indicates that the k read-back data symbols and the m read-back check symbols have no errors; In response to the syndrome data having a 1, outputting the k readback data symbols as the error-corrected symbols, wherein the syndrome data having a 1 indicates that the k readback data symbols have no error and the readback check symbol corresponding to the syndrome data having a 1 among the m readback check symbols has an error; In response to the fact that the companion data has v 1s, the companion data is used to correct the error code elements in the k read back data code elements and the m read back check code elements to obtain the error-corrected code elements, wherein the companion data has v 1s indicating that v1 read back data code elements corresponding to the companion data of 1 among the k read back data code elements have errors and v2 read back check code elements corresponding to the companion data of 1 among the m read back check code elements have errors, wherein v≥2, v1≤m, v2≤m, and v1+v2=v.

10. The processing method according to any one of claims 6, wherein: The Vandermonde-like matrix includes a Vandermonde matrix, a left-right flip of a Vandermonde matrix, an up-down flip of a Vandermonde matrix, or a transpose of a Vandermonde matrix.

11. A memory controller comprising: The reading unit is configured as: Read four bursts of data from a single memory channel; Organizing the four burst data into a group of error correction codewords, wherein the group of error correction codewords includes k read-back data codewords and m read-back check codewords, and the total bit width of the m read-back check codewords is eight times the bit width of one codeword, and The decoding unit is configured as follows: A decoding operation is performed based on the set of error correction codewords to obtain error-corrected codewords.

12. The memory controller according to claim 11, wherein: The reading unit is further configured to: Combining the burst data corresponding to the same pin of the same storage particle among the four burst data read by the single storage channel into one of the k read-back data code elements or the m read-back verification code elements, so as to obtain the k read-back data code elements and the m read-back verification code elements; as well as The k read-back data symbols and the m read-back check symbols are concatenated to obtain the set of error correction codewords.

13. The memory controller according to claim 12, wherein: The single storage channel corresponds to 8 data storage particles and 2 verification storage particles, and the bit width of each storage particle in the 8 data storage particles and the 2 verification storage particles is 4 bits.

14. The memory controller according to claim 13, wherein: The reading unit is further configured to: The following operation is performed on each of the eight data storage particles and the two check storage particles to obtain data including 32 data symbols and 8 check symbols as the set of error correction code words: Organizing data corresponding to a first bit of the 4 bits in the four burst data into a first symbol; Organizing data corresponding to a second bit of the 4 bits in the four burst data into a second symbol; Organizing data corresponding to a third bit of the 4 bits in the four burst data into a third symbol; and The data corresponding to the fourth bit of the 4 bits in the four burst data are organized into a fourth symbol.

15. The memory controller according to claim 13, wherein: The single storage channel is a single memory channel for DDR5.

16. A storage system comprising: The memory controller according to claim 12; as well as Storage unit.

17. An electronic device comprising: one or more processors; a memory including one or more computer program modules; The one or more computer program modules are stored in the memory and are configured to be executed by the one or more processors to implement the processing method according to any one of claims 1-10.

18. A non-transitory readable storage medium having computer executable instructions stored thereon, in, When the computer executable instructions are executed by a processor, the processing method according to any one of claims 1 to 10 is implemented.

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