Semiconductor device, method for preparing semiconductor device, and chip

Abstract

The present application relates to the field of semiconductors. Provided are a semiconductor device, a method for preparing a semiconductor device, and a chip. The semiconductor device comprises a substrate layer, at least one fin field effect transistor, at least one connecting structure and an additional metal layer, wherein the additional metal layer is arranged above a gate structure and is connected to at least a portion of the at least one connecting structure, the height of an upper surface of the additional metal layer is less than or equal to the height of an upper surface of the connecting structure, and the height of a lower surface of the additional metal layer is greater than or equal to the height of an upper surface of the gate structure. In the semiconductor device, by utilizing a height difference between M0 and MG in a FinFET process, an additional metal layer is introduced to provide winding resources, such that the number of winding resources provided in a standard unit is increased, and the height of the standard unit is compressed and reduced while keeping the number of winding resources required by the standard unit unchanged, thus increasing the degree of integration of a chip.

Description

Semiconductor device, method for manufacturing semiconductor device, and chip

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on September 26, 2023, with application number 202311252868.6 and application name “Semiconductor device, method for manufacturing semiconductor device and chip”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of semiconductors, and more specifically, to a semiconductor device, a method for manufacturing a semiconductor device, and a chip. Background Art

[0003] In the semiconductor field, the integration density of a chip is primarily influenced by the size of the standard cell. The metal pitch and the gate pitch of the field-effect transistors (FETs) that comprise the standard cell are two key factors affecting the size of the standard cell in two different dimensions. The gate pitch limits the number of FETs that can be accommodated per unit size across the width of the standard cell. As the reduction in FET device size slows along Moore's Law, the reduction in gate pitch has also reached a bottleneck.

[0004] Metal pitch is the minimum spacing between the wiring resources connecting standard cells without interfering with each other. It limits the number of FETs that can be accommodated per unit size in the standard cell's height. Therefore, if more wiring resources can be provided per unit space while meeting the metal pitch limit, the standard cell's height can be reduced. Therefore, how to increase the number of wiring resources provided within a standard cell has become a pressing technical issue.

[0005] Summary of the Invention

[0006] Embodiments of the present application provide a semiconductor device, a method for manufacturing a semiconductor device, and a chip. By utilizing the height difference between the metal interconnect layer M0 and the metal gate MG in the fin field effect transistor (FinFET) process, an additional metal layer can be introduced between M0 and MG, and a power line M0G is arranged therein, thereby saving winding resources in other metal layers that would otherwise be needed to arrange the power lines, and increasing the number of winding resources provided within the standard cell.

[0007] In a first aspect, a semiconductor device is provided, characterized in that it includes: a substrate layer, at least one fin field effect transistor, at least one connection structure and an additional metal layer; the at least one fin field effect transistor includes at least one fin structure and at least one gate structure arranged on the upper surface of the substrate layer; the at least one connection structure spans at least part of the fin structure in the at least one fin structure and covers at least part of the surface of at least part of the fin structure; the additional metal layer is arranged above the gate structure and connected to at least part of the connection structure in the at least one connection structure, the height of the upper surface of the additional metal layer relative to the upper surface of the substrate layer is less than or equal to a first height, the height of the lower surface of the additional metal layer relative to the upper surface of the substrate layer is greater than or equal to a second height, the first height is the height of the upper surface of the at least one connection structure relative to the upper surface of the substrate layer, and the second height is the height of the upper surface of the at least one gate structure relative to the upper surface of the substrate layer.

[0008] Optionally, the additional metal layer comprises a conductive material.

[0009] Optionally, the conductive material includes at least one of the following: copper, cobalt.

[0010] According to the technical solution provided in the present application, by utilizing the height difference between the metal interconnect layer M0 and the metal gate MG in the fin field effect transistor (FinFET) process, an additional metal layer is inserted between the height of M0 and the height of MG to provide winding resources, thereby increasing the number of winding resources provided inside the standard cell, compressing and reducing the height of the standard cell while keeping the number of winding resources required for the standard cell unchanged, thereby improving the integration of the chip.

[0011] In combination with the first aspect, in certain implementations of the first aspect, the semiconductor device further includes: a first metal layer, wherein the height of the lower surface of the first metal layer relative to the upper surface of the substrate layer is greater than a first height; a dielectric layer, used to fill the gap between the lower surface of the first metal layer and the upper surface of the substrate layer; the first metal layer includes at least one winding resource extending in a direction parallel to the upper surface of the substrate layer, and the projection of the at least one winding resource on the upper surface of the substrate layer at least partially overlaps with the projection of at least one connection structure and / or at least one gate structure on the upper surface of the substrate layer; the dielectric layer includes at least one first contact hole along the second direction, used to connect at least one winding resource with at least one connection structure and / or at least one gate structure.

[0012] According to the above technical solution, the addition of the additional metal layer does not affect the original M1 being connected to M0 or MG through the first contact hole V0, so that all the original winding resources M1 on the first metal layer can be normally provided to the standard unit for use, thereby compressing and reducing the height of the standard unit while keeping the number of winding resources required by the standard unit unchanged, thereby improving the integration of the chip.

[0013] In combination with the first aspect, in certain implementations of the first aspect, at least one power line is arranged in the additional metal layer, at least one power line is electrically connected to at least part of the connection structure in at least one connection structure, and at least one power line is used to supply power to at least one fin field effect transistor.

[0014] According to the above technical solution, the power line MOG is laid out, so that other original metal layers can save the winding resources originally needed to lay out the power line, thereby increasing the number of winding resources provided inside the standard cell.

[0015] In combination with the first aspect, in some implementations of the first aspect, at least one power line extends in a direction parallel to the upper surface of the substrate layer and passes through the semiconductor device in the extending direction.

[0016] According to the above technical solution, the arrangement of the MOG in the additional metal layer can facilitate access to each standard cell, thereby saving space inside the standard cell.

[0017] In combination with the first aspect, in certain implementations of the first aspect, the extension direction of at least one power line is the same as the extension direction of at least one winding resource, and the projection of at least one winding resource on the upper surface of the substrate layer and the projection of at least one power line on the upper surface of the substrate layer at least partially overlap; the dielectric layer also includes at least one second contact hole along the second direction, for connecting at least one winding resource with at least one power line.

[0018] According to the above technical solution, by making the projections of M0G and M1 in the vertical direction overlap, M0G can also be connected to M1 through the contact hole V0, so that the idle part of the winding resources on the first metal layer can be provided to the power line, thereby reducing the overall equivalent resistance of the power line and further reducing the power consumption of the chip.

[0019] In combination with the first aspect, in certain implementations of the first aspect, the height of the lower surface of the additional metal layer relative to the upper surface of the substrate layer is equal to the second height; at least one gate structure includes at least one first gate structure and at least one second gate structure; at least one first gate structure does not contact the first power line; and the upper surface of at least one second gate structure is at least partially in contact with at least one power line.

[0020] According to the above technical solution, by making the bottom surface height of MOG level with MG, the height of MG can contact MOG, so that the size and position of the gate structure can be used to control whether the gate structure is connected to the power supply, and thus control whether the gate fails, thereby achieving single diffusion break (SDB) without introducing additional processes or sacrificing the available area of ​​the standard cell.

[0021] In a second aspect, a method for preparing a semiconductor device is provided, comprising: forming a substrate layer; forming at least one fin field effect transistor on the upper surface of the substrate layer, the at least one fin field effect transistor comprising at least one fin structure and at least one gate structure arranged on the upper surface of the substrate layer; forming at least one connecting structure, the at least one connecting structure spanning at least a portion of the fin structure in the at least one fin structure and covering at least a portion of the surface of at least a portion of the fin structure; forming an additional metal layer, the additional metal layer being arranged above the gate structure and connected to at least a portion of the connecting structure in the at least one connecting structure, the height of the upper surface of the additional metal layer relative to the upper surface of the substrate layer being less than or equal to a first height, the height of the lower surface of the additional metal layer relative to the upper surface of the substrate layer being greater than or equal to a second height, the first height being the height of the upper surface of the at least one connecting structure relative to the upper surface of the substrate layer, and the second height being the height of the upper surface of the at least one gate structure relative to the upper surface of the substrate layer.

[0022] In combination with the second aspect, in certain implementations of the second aspect, the preparation method further includes: forming a dielectric layer and a first metal layer, the height of the lower surface of the first metal layer relative to the upper surface of the substrate layer is greater than a first height, and the dielectric layer is used to fill the gap between the lower surface of the first metal layer and the upper surface of the substrate layer; wherein the first metal layer includes at least one winding resource extending in a direction parallel to the upper surface of the substrate layer, and the projection of the at least one winding resource on the upper surface of the substrate layer is at least partially overlapped with the projection of at least one connection structure and / or at least one gate structure on the upper surface of the substrate layer; the dielectric layer includes at least one first contact hole along the second direction, which is used to connect at least one winding resource with at least one connection structure and / or at least one gate structure.

[0023] In combination with the second aspect, in certain implementations of the second aspect, at least one power line is arranged in the additional metal layer, at least one power line is electrically connected to at least part of the connection structure in at least one connection structure, and at least one power line is used to supply power to at least one fin field effect transistor.

[0024] In combination with the second aspect, in some implementations of the second aspect, at least one power line extends in a direction parallel to the upper surface of the substrate layer and passes through the semiconductor device in the extending direction.

[0025] In combination with the second aspect, in certain implementations of the second aspect, the extension direction of at least one power line is the same as the extension direction of at least one winding resource, and the projection of at least one winding resource on the upper surface of the substrate layer and the projection of at least one power line on the upper surface of the substrate layer at least partially overlap; the dielectric layer also includes at least one second contact hole along the second direction, for connecting at least one winding resource with at least one power line.

[0026] In combination with the second aspect, in certain implementations of the second aspect, the height of the lower surface of the additional metal layer relative to the upper surface of the substrate layer is equal to the second height; at least one gate structure includes at least one first gate structure and at least one second gate structure; at least one first gate structure is not electrically connected to at least one first power line; and the upper surface of at least one second gate structure is at least partially electrically connected to at least one power line.

[0027] In a third aspect, a chip is provided, comprising the semiconductor device according to the first aspect or any possible implementation of the first aspect.

[0028] In a fourth aspect, an electronic device is provided, comprising the chip in the third aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] FIG1 is a schematic structural diagram of a semiconductor device 100 composed of a single FinFET.

[0030] FIG. 2 is a top view of a semiconductor device 200 composed of multiple FinFETs.

[0031] FIG3 is a cross-sectional view of a semiconductor device 300 composed of a plurality of FinFETs.

[0032] FIG4 is a top view of the first metal layer.

[0033] FIG5 is a schematic structural diagram of a semiconductor device 500 provided in an embodiment of the present application.

[0034] FIG6 is a perspective view of a semiconductor device 500 provided in an embodiment of the present application when viewed from above.

[0035] FIG7 is a perspective view of a semiconductor device 700 provided in an embodiment of the present application when viewed from above.

[0036] FIG8 is a schematic diagram of the principle of the second gate structure cutting off the diffusion region in an embodiment of the present application.

[0037] FIG9 is a perspective view of a semiconductor device 900 provided in an embodiment of the present application when viewed from above.

[0038] FIG10 is a schematic flow chart of a method for manufacturing a semiconductor device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0039] The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings.

[0040] This application will present various aspects, embodiments, or features around systems including multiple devices, components, modules, etc. It should be understood and appreciated that each system may include additional devices, components, modules, etc., and / or may not include all of the devices, components, modules, etc. discussed in conjunction with the figures. Furthermore, combinations of these aspects may also be used.

[0041] Additionally, in the embodiments of this application, words such as "exemplary" and "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described in this application as "exemplary" should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of the word "exemplary" is intended to present concepts in a concrete manner.

[0042] In the embodiments of the present application, “corresponding” and “relevant” may sometimes be used interchangeably. It should be noted that when the distinction between them is not emphasized, the meanings they intend to express are consistent.

[0043] The network architecture and business scenarios described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. A person skilled in the art will appreciate that, with the evolution of the network architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of the present application are equally applicable to similar technical problems.

[0044] References to "one embodiment" or "some embodiments" in this specification mean that a particular feature, structure, or characteristic described in conjunction with that embodiment is included in one or more embodiments of the present application. Thus, phrases such as "in one embodiment," "in some embodiments," "in other embodiments," and "in yet other embodiments" appearing in various places in this specification do not necessarily refer to the same embodiment, but rather mean "one or more but not all embodiments," unless otherwise specifically emphasized. The terms "including," "comprising," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0045] In this application, "at least one" means one or more, and "more" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: including the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, c can be single or multiple.

[0046] The technical solutions in the embodiments of the present application can be applied to semiconductor devices including fin field-effect transistors (FinFETs). The semiconductor devices in the embodiments of the present application can include at least one FET, and the embodiments of the present application do not limit the type, positional relationship, or connection relationship of the at least one FET.

[0047] Figure 1 is a schematic diagram of the structure of a semiconductor device 100 comprising a single FinFET. As shown in Figure 1 , the FinFET is disposed on the upper surface of a substrate layer 110. The present embodiment does not specifically limit the type or composition of the substrate layer. For example, substrate layer 110 may be a silicon substrate, or may be made of single crystal silicon, gallium arsenide, gallium nitride, silicon carbide, silicon germanium, or other semiconductor materials.

[0048] Specifically, the FinFET is composed of a fin structure 120 and a gate structure 130. The fin structure 120 is a protruding structure grown from the upper surface of the substrate layer 110. The fin structure 120 extends in a direction parallel to the upper surface of the substrate layer 110 and is in contact with the upper surface of the substrate layer 110. The gate structure 130 spans the fin structure 120 and covers at least part of the surface of the fin structure. In other words, the fin structure 120 passes through the gate structure 130 in its extension direction. The gate structure 130 extends in another direction parallel to the upper surface of the substrate layer 110. Optionally, the extension directions of the fin structure 120 and the gate structure 130 on the upper surface of the substrate layer 110 are perpendicular. For example, in Figure 1, the fin structure 120 extends in the Y direction and the gate structure 130 extends in the X direction, wherein the X direction and the Y direction are perpendicular to each other and are both parallel to the upper surface of the substrate layer 110, and the Z direction is perpendicular to the upper surface of the substrate layer 110.

[0049] In the FinFET, the gate structure 130 constitutes a gate, and the fin structure 120 can respectively constitute a source and a drain in the extension direction with the gate structure 130 as the dividing line. For example, in FIG1 , the fin structure 120 located along the Y direction on the first side of the gate structure close to the screen can be the source of the FinFET, and the location located along the Y direction on the second side of the gate structure away from the screen can be the drain of the FinFET. Alternatively, the fin structure 120 located along the Y direction on the first side of the gate structure close to the screen can be the drain of the FinFET, and the location located along the Y direction on the second side of the gate structure away from the screen can be the source of the FinFET.

[0050] Optionally, the upper surface of the substrate layer 110 may further be covered with an oxide layer 140. The lower surface of the oxide layer 140 contacts the upper surface of the substrate layer 110, and the upper surface of the oxide layer 140 contacts the lower surface of the gate structure. In the embodiments of the present application, the type or composition of the insulating layer is not specifically limited. For example, the oxide layer 140 may be silicon dioxide, or the oxide layer 140 may also be made of other metal oxides.

[0051] A standard cell is a semiconductor device that implements the smallest function in a chip. It includes, but is not limited to, inverter gates, AND gates, registers, selectors, and other basic units. Each standard cell contains at least one FinFET, where multiple FinFETs can be arranged along the X and / or Y directions in Figure 1.

[0052] For example, the gate structures 130 of multiple wide fin structures 120 may be included in the Y direction along which the fin structure 120 extends, thereby forming multiple FinFETs arranged in parallel along the Y direction. In a standard cell, the Y direction is generally referred to as the length direction of the standard cell, and the size of the standard cell along the Y direction is generally referred to as the length of the standard cell.

[0053] For another example, multiple parallel fin structures 120 may be arranged in the X direction, and the gate structure 130 may span across the multiple fin structures 120, thereby forming multiple FinFETs arranged in parallel along the X direction. In a standard cell, the X direction is generally referred to as the height direction of the standard cell, and the dimension of the standard cell along the Y direction is generally referred to as the height of the standard cell.

[0054] In order for the standard cell to work properly, it is necessary to connect the source, drain and / or gate of a specific FinFET to a power supply or other standard cells through wires according to the circuit design diagram. However, with the development of the FinFET manufacturing process, the width of the fin structure 120 in the X direction has gradually decreased, which is not conducive to direct connection with the wire. Therefore, in the existing FinFET advanced manufacturing process, the semiconductor device also includes a connection structure. The connection structure spans at least one of the fin structures of the semiconductor device and covers at least a portion of the surface of the fin structure spanned.

[0055] Fig. 2 shows a top view of a semiconductor device 200 composed of a plurality of FinFETs. The X direction and the Y direction shown in Fig. 2 correspond to those in Fig. 1 .

[0056] As shown in FIG2 , the gate structure 130 extends along the X direction across six fin structures 120. The six fin structures extend in parallel along the Y direction, with each three fin structures grouped together. For example, one group of fin structures 120 may be fins of an N-type FinFET, and another group of fin structures 120 may be fins of a P-type FinFET. Each connecting structure 150 diffracts along the X direction, spanning the source portion or drain portion of a group of three fin structures 120. The upper surfaces of the gate structure 130 and the connecting structure 150 are higher in the Z direction, which is perpendicular to the X and Y directions, relative to the upper surface of the substrate layer 110, than the upper surface of the fin structure 120 is higher in the Z direction relative to the upper surface of the substrate layer 110. Therefore, in the top view of FIG2 , the gate structure 130 and the connecting structure 150 both cover at least a portion of the upper surface of the fin structure 120.

[0057] In the traditional solution, the wires are distributed in a metal layer that is higher than the height of the gate structure and the connection structure in the Z direction. Wires extending along the X direction or along the Y direction can be laid out in the metal layer. An insulating dielectric layer is filled between metal layers at different heights in the Z direction, and the wires of different layers can be connected through through-holes running through the dielectric layer in the Z direction at overlapping positions projected along the Z-axis direction. The through-holes are filled with conductive material so that the circuits between different metal layers can be connected. According to the height of the metal layer in the Z direction, they can be named the first metal layer, the second metal layer, the third metal layer, etc., in sequence, and the positions where the wires can be laid out are referred to as M1, M2, and M3. The through-hole connecting M1 and M2 can be named the first through-hole V1, the through-hole connecting M2 and M3 can be named the second through-hole V2, and so on.

[0058] The first metal layer is the metal layer closest to the standard cell in the Z direction. The height of the lower surface of the first metal layer relative to the upper surface of the substrate layer 110 in the Z direction is greater than the height of the upper surfaces of the gate structure 130 and the connection structure 150 relative to the upper surface of the substrate layer 110 in the Z direction. Therefore, the gap between the lower surface of the first metal layer and the upper surface of the substrate layer 110 is also filled with a dielectric layer. The dielectric layer includes a first contact hole extending along the Z direction, which is used to connect the gate structure 130 and / or the connection structure 150 to M1 of the first metal layer at a position where they overlap when projected along the Z axis.

[0059] Figure 3 shows a cross-sectional view of a semiconductor device 300. Figure 3 is a cross-sectional view of the fin structure 120 of the semiconductor device 300 cut along a plane formed by the Y direction and the Z direction, wherein the Y direction and the Z direction correspond to the coordinate system described above.

[0060] The connection structure 150 may be made of a conductive material, such as a metal material. Therefore, the area in the Z direction occupied by the conductive material constituting the connection structure 150, from the height of the upper surface of the fin structure 120 in the Z direction to the height of the upper surface of the connection structure 150 in the Z direction, is also referred to as the metal interconnection layer M0, as shown in FIG3 .

[0061] The portion of the gate structure 130 that contacts the fin structure 120 can be made of a high-k dielectric material (HK), such as hafnium dioxide. The remaining portion, including the top surface, can be made of a conductive material, such as a metal. Therefore, the portion of the gate structure 130 occupied in the Z direction by the conductive material, from the height of the top surface of the fin structure 120 in the Z direction to the height of the top surface of the gate structure 130 in the Z direction, is referred to as the metal gate (MG), as shown in FIG3 .

[0062] As shown in Figure 3, in the current advanced FinFET fabrication process, the height of M0 in the Z direction is higher than MG. That is, the height of the upper surface of the connection structure 150 relative to the upper surface of the substrate layer 110 in the Z direction is greater than the height of the upper surface of the gate structure 130 relative to the upper surface of the substrate layer 110 in the Z direction. For simplicity, in the embodiments below, the height of the upper surface of the connection structure 150 relative to the upper surface of the substrate layer 110 in the Z direction is collectively referred to as the first height h1, and the height of the upper surface of the gate structure 130 relative to the upper surface of the substrate layer 110 in the Z direction is collectively referred to as the second height h2, where the first height is greater than the second height.

[0063] As shown in Figure 3, M1 is located above the FinFET in the standard cell in the Z direction, that is, the height of the lower surface of M1 is greater than the first height. M0 and MG can be connected to M1 through a first contact hole (V0 or V0G). The contact hole used to connect M1 to M0 is called V0, and the contact hole used to connect M1 to MG is called V0G.

[0064] Metal pitch is the minimum distance between conductors required for normal operation without interfering with each other. Due to the limitations of metal pitch, the number of locations per unit area within each metal layer where conductors can be placed is limited. The locations within a metal layer where conductors can be placed are referred to as the wiring resources provided by the metal layer.

[0065] Figure 4 shows a top view of the first metal layer. As shown in Figure 4, for example, in the first metal layer, a maximum of 4 winding resources M1 can be provided in the unit size along the X direction, each winding resource extends along the Y direction, and the distance between each winding resource is set according to the metal spacing. In this case, if the standard cell needs to lay out a total of 6 wires extending along the Y direction (including a power line and a ground line), a first metal layer with a size greater than 1 unit (for example, 1.5 unit sizes) is required in the X direction. Therefore, the minimum height of the standard cell in the height direction (X direction) is limited to not less than 1.5 unit sizes.

[0066] It should be understood that the above example uses only M1 wiring. For multi-layer metal layer wiring, given a fixed metal pitch and number of metal layers, the amount of wiring resources available per unit area is fixed and limited. This limited number of wiring resources limits further increases in chip integration, so increasing the number of wiring resources available within standard cells is a pressing technical challenge.

[0067] The wires connecting standard cells can be divided into power lines and signal lines based on their functions. Signal lines connect standard cells to other standard cells and transmit electrical signals between them; power lines connect standard cells to a power source and provide power to the standard cells. Since each standard cell requires power, traditional solutions typically require an entire winding resource to be laid out in the metal layer. Therefore, if power lines can be laid out in locations outside of the existing metal layer's winding resources within the space occupied by existing semiconductor devices, this can save on metal layer winding resources.

[0068] In view of this, an embodiment of the present application provides a semiconductor device, which utilizes the height difference between the metal interconnect layer M0 and the metal gate MG in the existing FinFET production process, introduces an additional metal layer located between M0 and MG in the mid-stage process of semiconductor device preparation, and lays out the power line M0G in the additional metal layer, thereby saving winding resources that were originally required to lay out the power line in other metal layers, and increasing the number of winding resources provided inside the standard unit.

[0069] Figure 5 shows a schematic structural diagram of a semiconductor device 500 provided in an embodiment of the present application. Semiconductor device 500 includes a substrate layer 510, at least one FinFET fin structure 520, at least one FinFET gate structure 530, at least one connection structure 540, and an additional metal layer 550. Figure 5 is a cross-sectional view of the fin structure 520 of semiconductor device 500 cut along a plane defined by the Y and Z directions, where the Y and Z directions correspond to the coordinate system described above.

[0070] At least one FinFET consisting of a fin structure 520 and a gate structure 530 is disposed on the upper surface of the substrate layer 510, and at least one connecting structure 540 spans at least a portion of the fin structure 520 in the at least one fin structure 520 and covers at least a portion of the surface of the at least portion of the fin structure 520. Optionally, the substrate layer 510, the fin structure 520, the gate structure 530, and the connecting structure 540 correspond to the substrate layer 110, the fin structure 120, the gate structure 130, and the connecting structure 150 described above, respectively, and have the same structure and positional relationship. The specific structure and positional relationship can be referred to Figures 1 to 4 and the relevant description above, and will not be repeated here.

[0071] The height of the upper surface of the additional metal layer 550 relative to the upper surface of the substrate layer 510 is less than or equal to a first height h1. The additional metal layer is disposed above the gate structure and connected to at least a portion of the at least one connection structure. The height of the lower surface of the additional metal layer 550 relative to the upper surface of the substrate layer 510 is greater than or equal to a second height h2. The first height is the height of the upper surface of the connection structure 540 relative to the upper surface of the substrate layer 510, and the second height is the height of the upper surface of the gate structure 530 relative to the upper surface of the substrate layer.

[0072] At least one power line MOG extending in a direction parallel to the upper surface of the substrate layer is arranged in the additional metal layer 550. The power line is electrically connected to at least a portion of the at least one connection structure 540 of the standard cell and is used to power the FinFET in the standard cell. The power line can be divided into a positive power line Vdd and a negative power line Vss. Vdd provides a drain power supply voltage and is generally connected to the connection structure 540 to which the drain of a P-type metal-oxide semiconductor field-effect transistor (MOS) is connected. Vss provides a source power supply voltage and is generally connected to the connection structure 540 to which the source of an N-type MOS is connected. In the case of a single power supply, Vss provides zero voltage or ground, and therefore Vss is also called a ground line in some embodiments.

[0073] Optionally, the additional metal layer includes a conductive material, including but not limited to at least one of the following: copper and cobalt.

[0074] Optionally, the semiconductor device 500 further includes at least one metal layer including a first metal layer. A lower surface of M1 in the first metal layer is greater than the first height relative to an upper surface of the substrate layer 510. M1 is connected to at least a portion of the at least one connection structure 540 via V0 in the dielectric layer, and / or is connected to at least a portion of the at least one gate structure 530 via V0G in the dielectric layer.

[0075] As can be seen from Figure 6, M0G and M1 are located in two parallel planes with different heights. In addition, since the height of M0G in the Z direction is lower than the height of M0 in the Z direction, the minimum distance of M0G relative to M1 in the Z direction is greater than the minimum distance of M0 relative to M1 in the Z direction. Therefore, in the case where M0 does not interfere with M1, M0G will not interfere with M1. The position of M0G on the plane formed by the X and Y directions can also ignore the position of M1 on the plane formed by the X and Y directions, so that the projections of M0G and M1 on the plane formed by the X and Y directions can partially overlap or even completely overlap. That is, the addition of M0G does not affect the design of the original metal layer, so that all winding resources M1 can still be normally provided to the standard unit without changing the existing first metal layer structure.

[0076] It should be understood that the cross-sectional view shown in Figure 5 is intended only to illustrate the height relationship of the MOG relative to the MO and MG in the Z direction and does not limit the shape and position of the projection of the MOG on the plane defined by the X and Y directions. The shape and position of the projection of the MOG on the plane defined by the X and Y directions can be adjusted based on the direction and position of the power cable routing. A schematic diagram of a power cable routing scenario is provided below.

[0077] Figure 6 shows a perspective view from above of a semiconductor device 500 provided in an embodiment of the present application. Figure 6 shows the projections of related elements, such as the first metal layer, additional metal layers, and standard cells, located in multiple planes at different heights in the Z direction, on a plane defined by the X and Y directions. For the sake of simplicity, elements not relevant to the illustration are omitted.

[0078] As shown in FIG6 , since there is a height difference between M0G and M1 in the Z direction perpendicular to the X and Y directions, the distance between the projections of M0G and M1 on the plane formed by the X and Y directions can be smaller than the metal spacing limit or even overlap.

[0079] For example, assume the same constraints as those shown in Figure 4, that is, the first metal layer can accommodate four M1s per unit size along the X direction, and the standard cell still requires six wires extending along the Y direction. In this case, as shown on the left side of Figure 6, since two of the six wires can use the M0G in the additional metal layer, only the four M1s provided by the first metal layer, which are one unit size, need to be used in the X direction for other wires. This allows the minimum height of the standard cell in the height direction (X direction) to be reduced to one unit size, which is less than the 1.5 unit size limit in traditional solutions.

[0080] For another example, as shown on the right side of Figure 6, the size of the standard cell in the height direction (X direction) remains unchanged, and is still 1.5 unit sizes. In this case, the first metal layer can provide more than 4 M1s, for example 5 or more, and the two M0Gs provided by the additional metal layer make the winding resources available to the standard cell exceed 6. In addition, there is no additional height in the Z direction compared to the traditional solution, so it is equivalent to providing more winding resources within the unit space of the semiconductor device, so that more FinFETs can be accommodated in the standard cell.

[0081] To sum up, the technical solution provided in the embodiment of the present application utilizes the height difference between the metal interconnect layer M0 and the metal gate MG in the FinFET process of the fin field effect transistor, and inserts an additional metal layer between the height of M0 and the height of MG for laying out the power line M0G, so that other original metal layers can save the winding resources originally required for laying out the power line, thereby increasing the number of winding resources provided inside the standard unit, compressing and reducing the height of the standard unit while keeping the number of winding resources required for the standard unit unchanged, thereby improving the integration of the chip.

[0082] When planning the arrangement of FinFETs in standard cells, in order to save space, multiple gate structures with extension directions perpendicular to the extension direction of the fin structure are usually arranged in parallel in the extension direction of the active area composed of a set of parallel fin structures, thereby dividing multiple FinFETs. In order for the multiple FinFETs formed in the above manner to work normally, the active areas of different FinFETs need to be isolated. The technology in which two FinFETs are isolated by a dummy gate structure is called single diffusion break (SDB). The existing method of implementing SBD generally requires the design of a special isolation structure under the dummy gate structure, which requires the addition of additional processes in the semiconductor device preparation process and the sacrifice of part of the standard cell area.

[0083] In view of this, the embodiment of the present application can achieve the SBD effect based on the semiconductor device shown in FIG5 without introducing additional processes or sacrificing area.

[0084] In some possible embodiments, the height of the lower surface of the additional metal layer relative to the upper surface of the substrate layer is equal to the second height, and the second height is equal to the height of the upper surface of the gate structure relative to the upper surface of the substrate layer, that is, the lower surface of the MOG can contact the upper surface of the MG.

[0085] In this case, Figure 7 shows a perspective view of a semiconductor device 700 provided in an embodiment of the present application from a top view. Similarly, Figure 7 also only shows the projection of the portion relevant to the content to be explained on the plane formed by the X and Y directions, omitting other irrelevant portions.

[0086] As shown in Figure 7, OD represents the active area of ​​the FinFET, that is, the area forming the source and drain of the FinFET. In Figure 7, the two ODs extend along the Y direction. Each OD may include a fin structure extending along the Y direction, or a group of parallel fin structures extending along the Y direction. For simplicity, the specific number of fin structures is not shown in the figure.

[0087] M0G represents two power rails extending along the Y direction provided on the additional metal layer. Optionally, the two M0Gs can consist of a power rail providing Vdd and a ground rail providing Vss. For example, in Figure 7, the upper M0G can be the power rail, and the lower M0G can be the ground rail.

[0088] M0 represents a metal interconnect layer that spans the fin structure included in the OD. The top surface of M0 is higher than the height of the fin structure in the OD in the Z direction. That is, M0 covers a portion of the OD surface in a top view. M0 extends along the X direction, and at least a portion of M0 extends to contact M0G, thereby powering the FinFET in the standard cell through M0G.

[0089] MG represents the metal gate portion of the gate structure. The gate structure spans a portion of the upper surface of the fin structure, and therefore, in Figure 7 , MG is shown extending in the X direction and covering a portion of OD. Furthermore, since the lower surface of the MOG and the upper surface of the MG are at the same height in the Z direction in this embodiment, the MG intersecting the MOG in the top view of Figure 7 can actually contact the MG. Therefore, the gate structure can be divided into a first gate structure and a second gate structure based on whether or not it contacts the MOG.

[0090] The first gate structure is not electrically connected to the MOG, such as the two MGs across the two ODs in the figure. The upper surface of the second gate structure is electrically connected to the MOG, such as the two MGs located in the middle of the Y direction in Figure 7. Since the first gate structure is not in contact with the power line, the potential of the gate structure can be controlled by other wires, thereby controlling the switching state of the MOS. Therefore, the source and drain on the left and right sides of the first gate structure constitute a MOS that can operate normally. Since the second gate structure is directly connected to the power line, the potential on the second gate structure is equal to the source potential or the drain potential. Therefore, the carrier channel between the source and drain separated by the second gate structure is always in a closed state, so that no current flows, achieving the effect of separating two adjacent MOSs in the Y direction by a single second gate structure.

[0091] Figure 8 illustrates the principle of the second gate structure shutting off the diffusion region in an embodiment of the present application. As shown in Figure 8 , for a P-type MOS (PMOS), when the gate is connected to the power rail, the gate always has the same high potential as the drain, equivalent to a PMOS that is always in the off state, thereby shutting off carrier diffusion. Similarly, for an N-type MOS (NMOS), when the gate is connected to the ground rail, the gate always has the same low potential as the source, equivalent to a NMOS that is always in the off state, thereby shutting off carrier diffusion.

[0092] Through the above solution, the height of MG can be in contact with MOG, so that whether the gate structure is connected to the power supply and whether the gate fails can be controlled only by the size and position of the gate structure, thereby achieving the SDB effect without introducing additional processes or sacrificing the available area of ​​the standard cell.

[0093] The resistance of the power line is one of the factors that affect the power consumption of the semiconductor device. By reducing the resistance of the power line, the power consumption of the semiconductor device can be reduced.

[0094] In some possible implementations, the projection of M0G of the semiconductor device provided in the embodiment of the present application on the upper surface of the substrate layer may at least partially overlap with the projection of M1 on the upper surface, so that M0G can be connected to M1 through a second contact hole V0 that runs through the dielectric layer from top to bottom, thereby allowing the idle M1 and M0G in the first metal layer that are not used for laying wires to be used together as power lines to reduce the equivalent resistance of the power lines.

[0095] In this case, Figure 9 shows a perspective view from above of a semiconductor device 900 provided by an embodiment of the present application. The two segments of M1 depicted in Figure 9 represent the idle portions of M1 used as power lines. The projection of the idle portion of M1 on the plane defined by the X and Y directions falls within the projection of M0G on the plane defined by the X and Y directions. The shaded rectangle indicates the location where M1 and M0G are connected via the second contact hole V0.

[0096] It should be understood that the M1 shown in Figure 9 is only an idle winding resource used for the power line and does not represent all the winding resources in the first metal layer. The winding resource M1 in the first metal layer, not shown in the figure, can still be connected to M0 or MG through the first contact hole to route signal lines. In other words, the idle M1 used as a power line does not affect the normal use of other winding resources.

[0097] In Figure 9, the area between the two second contact holes corresponds to the shared power line between M0G and M1. This section connects the fin structure to M0, M0 to M0G, M0G to V0, and V0 to M1. The equivalent resistance of this power line section is equivalent to the resistance of M0G plus the sum of the resistance of M1 and V0 in parallel. Compared to when only the additional metal layer is used, this resistance is the resistance of M0G in this section, reducing the resistance of the power line.

[0098] Through the above solution, M0G can also be connected to M1 through the contact hole V0, so that the idle part of the winding resources on the first metal layer can be provided to the power line, thereby reducing the overall equivalent resistance of the power line and further reducing the power consumption of the chip.

[0099] Figure 10 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present application. As shown in Figure 10 , the method includes the following steps.

[0100] S1010: forming a substrate layer.

[0101] For example, in step S1010, a substrate layer for preparing a FinFET structure may be provided. The substrate may be of various forms, such as a silicon substrate, a bulk semiconductor material substrate, a semiconductor-on-insulator substrate, a compound semiconductor substrate, etc., and the present embodiment is not limited thereto. The substrate may be similar to substrate layer 510 in FIG. 5 .

[0102] S1020: forming at least one fin field-effect transistor on the upper surface of the substrate layer.

[0103] For example, in step S1020, a FinFET structure may be prepared on the substrate layer. The FinFET includes at least one fin structure and at least one gate structure disposed on the upper surface of the substrate layer. The specific preparation process of the FinFET may refer to existing process flows, and this application does not specifically limit the formation method of the FinFET. The at least one fin structure may be similar to the fin structure 520 in FIG. 5 , and the at least one gate structure may be similar to the gate structure 530 in FIG. 5 .

[0104] S1030: Form at least one connection structure.

[0105] For example, in step S1030, a connection structure may be prepared at the source and drain portions of the FinFET. At least one connection structure spans at least a portion of the fin structure in at least one fin structure and covers at least a portion of the surface of at least the portion of the fin structure spanned. The preparation process of the connection structure may refer to the existing process flow, which is not specifically limited in this application, but the height of the upper surface of the connection structure relative to the upper surface of the substrate layer should be greater than the height of the upper surface of the gate structure relative to the upper surface of the substrate layer. At least one connection structure may be similar to the connection structure 540 in FIG. 5 .

[0106] S1040: forming an additional metal layer.

[0107] For example, in step S1040, an additional metal layer for providing a power line MOG may be provided. The additional metal layer is disposed above the gate structure and connected to at least a portion of the at least one connection structure. The height of the upper surface of the additional metal layer relative to the upper surface of the substrate layer is less than or equal to a first height, and the height of the lower surface of the additional metal layer relative to the upper surface of the substrate layer is greater than or equal to a second height. The first height is the height of the upper surface of the connection structure relative to the upper surface of the substrate layer, and the second height is the height of the upper surface of the gate structure relative to the upper surface of the substrate layer. For the specific structure of the additional metal layer, reference may be made to additional metal layer 550 in FIG. 5 .

[0108] Optionally, at least one power line MOG is disposed in the additional metal layer. The MOG is electrically connected to at least part of the at least one connection structure for supplying power to the FinFET. Optionally, the MOG extends in a direction parallel to the upper surface of the substrate layer.

[0109] In some possible implementations, MOG may be formed by MO epitaxial growth. Optionally, epitaxial growth methods (or deposition methods) include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), molecular beam epitaxy (MBE), and metal organic chemical vapor deposition (MOCVD).

[0110] Optionally, MOG may be made of a conductive material, including but not limited to at least one of the following: copper, cobalt.

[0111] In some possible embodiments, the method may further include: forming a dielectric layer and a first metal layer, wherein the height of the lower surface of the first metal layer relative to the upper surface of the substrate layer is greater than a first height, and the dielectric layer is used to fill the gap between the lower surface of the first metal layer and the upper surface of the substrate layer; wherein the first metal layer includes at least one winding resource extending in a direction parallel to the upper surface of the substrate layer, and the projection of the at least one winding resource on the upper surface of the substrate layer is at least partially overlapped with the projection of at least one connection structure and / or at least one gate structure on the upper surface of the substrate layer; and the dielectric layer includes at least one first contact hole along the second direction, which is used to connect the at least one winding resource with the at least one connection structure and / or at least one gate structure.

[0112] Optionally, the extension direction of at least one power line is the same as the extension direction of at least one winding resource, and the projection of at least one winding resource on the upper surface of the substrate layer and the projection of at least one power line on the upper surface of the substrate layer at least partially overlap; the dielectric layer also includes at least one second contact hole along the second direction, for connecting at least one winding resource with at least one power line.

[0113] Optionally, the height of the lower surface of the additional metal layer relative to the upper surface of the substrate layer is equal to a second height; at least one gate structure includes at least one first gate structure and at least one second gate structure; at least one first gate structure is not electrically connected to at least one first power line; and the upper surface of at least one second gate structure is at least partially electrically connected to at least one power line.

[0114] The embodiment of the present application further provides a chip, which includes the semiconductor device shown in FIG5 , or the semiconductor device in the chip is prepared by the method shown in FIG10 .

[0115] An embodiment of the present application further provides an electronic device comprising the above chip.

[0116] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the protection scope of the technical solutions of the embodiments of the present application.

Claims

1. A semiconductor device, characterized in that: include: A substrate layer (510), at least one fin field effect transistor, at least one connection structure (540), and an additional metal layer (550); The at least one fin field effect transistor comprises at least one fin structure (520) and at least one gate structure (530) disposed on the upper surface of the substrate layer (510); The at least one connection structure (540) spans over at least a portion of the fin structure (520) of the at least one fin structure (520) and covers at least a portion of the surface of the at least portion of the fin structure (520); The additional metal layer (550) is arranged above the gate structure (530) and is connected to at least part of the connection structures (540) in the at least one connection structure (540); the height of the upper surface of the additional metal layer (550) relative to the upper surface of the substrate layer (510) is less than or equal to a first height; the height of the lower surface of the additional metal layer (550) relative to the upper surface of the substrate layer (510) is greater than or equal to a second height; the first height is the height of the upper surface of the at least one connection structure (540) relative to the upper surface of the substrate layer (510); and the second height is the height of the upper surface of the at least one gate structure (530) relative to the upper surface of the substrate layer (510).

2. The semiconductor device according to claim 1, wherein: The semiconductor device further comprises: a first metal layer, wherein the height of the lower surface of the first metal layer relative to the upper surface of the substrate layer (510) is greater than the first height; A dielectric layer, used to fill the gap between the lower surface of the first metal layer and the upper surface of the substrate layer (510); The first metal layer comprises at least one winding resource extending in a direction parallel to the upper surface of the substrate layer (510), and a projection of the at least one winding resource on the upper surface of the substrate layer (510) at least partially overlaps with a projection of the at least one connection structure (540) and / or the at least one gate structure (530) on the upper surface of the substrate layer (510); The dielectric layer comprises at least one first contact hole along the second direction, which is used to connect the at least one winding resource with the at least one connection structure (540) and / or at least one gate structure (530).

3. The semiconductor device according to claim 2, characterized in that At least one power line is arranged in the additional metal layer (550), the at least one power line is electrically connected to at least part of the connection structure (540) in the at least one connection structure (540), and the at least one power line is used to supply power to the at least one fin field effect transistor.

4. The semiconductor device according to claim 3, characterized in that The at least one power line extends in a direction parallel to the upper surface of the substrate layer (510) and passes through the semiconductor device in the extending direction.

5. The semiconductor device according to claim 4, characterized in that The extension direction of the at least one power line is the same as the extension direction of the at least one winding resource, and the projection of the at least one winding resource on the upper surface of the substrate layer (510) and the projection of the at least one power line on the upper surface of the substrate layer (510) at least partially overlap; The dielectric layer also includes at least one second contact hole along the second direction, which is used to connect the at least one winding resource and the at least one power line.

6. The semiconductor device according to any one of claims 3 to 5, characterized in that: The height of the lower surface of the additional metal layer (550) relative to the upper surface of the substrate layer (510) is equal to the second height; The at least one gate structure (530) includes at least one first gate structure (530) and at least one second gate structure (530); The at least one first gate structure (530) is not electrically connected to the at least one first power line; An upper surface of the at least one second gate structure (530) is at least partially electrically connected to the at least one power line.

7. A method for preparing a semiconductor device, characterized in that: include: forming a substrate layer; forming at least one fin field effect transistor on the upper surface of the substrate layer, wherein the at least one fin field effect transistor comprises at least one fin structure and at least one gate structure disposed on the upper surface of the substrate layer; forming at least one connection structure, the at least one connection structure spanning over at least a portion of the at least one fin structure and covering at least a portion of a surface of the at least portion of the fin structure; An additional metal layer is formed, the additional metal layer is arranged above the gate structure and connected to at least part of the at least one connection structure, the height of the upper surface of the additional metal layer relative to the upper surface of the substrate layer is less than or equal to a first height, the height of the lower surface of the additional metal layer relative to the upper surface of the substrate layer is greater than or equal to a second height, the first height is the height of the upper surface of the at least one connection structure relative to the upper surface of the substrate layer, and the second height is the height of the at least one gate structure The height of the upper surface relative to the upper surface of the substrate layer.

8. The preparation method according to claim 7, characterized in that: The preparation method further comprises: forming a dielectric layer and a first metal layer, wherein the height of the lower surface of the first metal layer relative to the upper surface of the substrate layer is greater than the first height, and the dielectric layer is used to fill the gap between the lower surface of the first metal layer and the upper surface of the substrate layer; The first metal layer includes at least one winding resource extending in a direction parallel to the upper surface of the substrate layer, and a projection of the at least one winding resource on the upper surface of the substrate layer at least partially overlaps with a projection of the at least one connection structure and / or at least one gate structure on the upper surface of the substrate layer; The dielectric layer includes at least one first contact hole along the second direction, which is used to connect the at least one winding resource with the at least one connection structure and / or at least one gate structure.

9. The preparation method according to claim 8, characterized in that: At least one power line is arranged in the additional metal layer, the at least one power line is electrically connected to at least part of the at least one connection structure, and the at least one power line is used to supply power to the at least one fin field effect transistor.

10. The preparation method according to claim 9, characterized in that: The at least one power line extends in a direction parallel to the upper surface of the substrate layer and passes through the semiconductor device in the extending direction.

11. The preparation method according to claim 10, characterized in that: The extension direction of the at least one power line is the same as the extension direction of the at least one winding resource, and the projection of the at least one winding resource on the upper surface of the substrate layer and the projection of the at least one power line on the upper surface of the substrate layer at least partially overlap; The dielectric layer also includes at least one second contact hole along the second direction, which is used to connect the at least one winding resource and the at least one power line.

12. The preparation method according to any one of claims 9 to 11, characterized in that: The height of the lower surface of the additional metal layer relative to the upper surface of the substrate layer is equal to the second height; The at least one gate structure includes at least one first gate structure and at least one second gate structure; The at least one first gate structure is not electrically connected to the at least one first power line; An upper surface of the at least one second gate structure is at least partially electrically connected to the at least one power line.

13. A chip, characterized in that: A semiconductor device comprising the semiconductor device as claimed in any one of claims 1 to 6.

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