P-type crystalline silicon thin film, preparation method therefor, and semiconductor device

Abstract

The present disclosure provides a p-type crystalline silicon thin film, a preparation method therefor, and a semiconductor device. The preparation method comprises: preparing on a substrate a polycrystalline silicon material layer having a crystallization rate of ≤35%, and performing heat treatment on the polycrystalline silicon material layer, to form a p-type polycrystalline silicon layer having a crystallization rate of 90% or higher.

Description

P-type crystalline silicon thin film and preparation method thereof, and semiconductor device

[0001] This application claims priority to the Chinese patent application filed with the Patent Office of China on September 27, 2023, with application number CN202311268055.6 and public name “p-type crystalline silicon thin film, preparation method thereof, and semiconductor device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present disclosure relates to the field of semiconductor technology, and in particular to a p-type crystalline silicon thin film and a preparation method thereof, and a semiconductor device. Background Art

[0003] Semiconductors play an important role in our current production and life. For example, field-effect transistors and solar cells are common semiconductor devices.

[0004] Silicon is a common semiconductor material. Pure silicon is an intrinsic semiconductor. When silicon atoms in the silicon lattice are replaced by donor impurities or acceptor impurities, a doped semiconductor can be formed. The carrier mobility of a doped semiconductor is directly related to the impurity concentration. Due to factors such as solid solubility and conductive mechanism, the carrier mobility of p-type semiconductors is generally low and needs to be further improved. Traditionally, the carrier mobility of p-type semiconductors is usually improved by increasing the doping concentration of the p-type dopant element. However, if the doping concentration is too high, an impurity-rich layer will form on the surface, affecting the etching performance of the semiconductor material.

[0005] Summary of the Invention

[0006] According to some embodiments of the present disclosure, a method for preparing a p-type crystalline silicon thin film is provided, comprising the following steps:

[0007] Preparing a polysilicon material layer with a crystallization rate of ≤35% on a substrate;

[0008] The polysilicon material layer is an intrinsic polysilicon material layer, and a p-type doping element is doped into the intrinsic polysilicon material layer and heat-treated to form a p-type polysilicon layer with a crystallization rate of more than 90%; or

[0009] The polysilicon material layer is a doped polysilicon material layer containing a p-type doping element, and the doped polysilicon material layer is heat-treated to form a p-type polysilicon layer with a crystallization rate of more than 90%.

[0010] In some embodiments of the present disclosure, the polysilicon material layer is an intrinsic polysilicon material layer, and the intrinsic polysilicon material layer is prepared by chemical vapor deposition. In the step of preparing the intrinsic polysilicon material layer, reaction raw materials including a silicon source are introduced into a deposition chamber.

[0011] In some embodiments of the present disclosure, the intrinsic polysilicon material layer is prepared by low-pressure chemical vapor deposition.

[0012] In some embodiments of the present disclosure, in the step of preparing the intrinsic polysilicon material layer, the gas pressure in the deposition chamber is controlled to be 100 mTorr to 500 mTorr, and the deposition temperature is controlled to be 490° C. to 610° C.

[0013] In some embodiments of the present disclosure, the step of doping the intrinsic polysilicon material layer with a p-type dopant element and performing a heat treatment includes:

[0014] placing the substrate prepared with the intrinsic polysilicon material layer in a diffusion chamber, introducing a doping source containing the p-type doping element into the diffusion chamber, and forming a diffusion layer containing the p-type doping element on the intrinsic polysilicon layer;

[0015] The intrinsic polysilicon material layer and the diffusion layer are heated to perform a push-junction process, during which the p-type doping element is diffused and doped into the intrinsic polysilicon material layer to form the p-type polysilicon layer.

[0016] In some embodiments of the present disclosure, during the process of forming the diffusion layer containing the p-type doping element on the intrinsic polysilicon layer, the temperature in the diffusion chamber is controlled to be 700° C. to 890° C.

[0017] In some embodiments of the present disclosure, during the push-bonding process, the push-bonding temperature is controlled to be 850° C. to 960° C.

[0018] In some embodiments of the present disclosure, the polysilicon material layer is a doped polysilicon material layer containing a p-type doping element, and the doped polysilicon material layer is prepared by chemical vapor deposition. In the step of preparing the doped polysilicon material layer, reaction raw materials including a silicon source and a doping source are introduced into a deposition chamber, and the doping source includes the p-type doping element.

[0019] In some embodiments of the present disclosure, the doped polysilicon material layer is prepared by low-pressure chemical vapor deposition.

[0020] In some embodiments of the present disclosure, in the step of preparing the doped polysilicon material layer, the gas pressure in the deposition chamber is controlled to be 100 mTorr to 500 mTorr, and the deposition temperature is controlled to be 490° C. to 610° C.

[0021] In some embodiments of the present disclosure, the doped polysilicon material layer is prepared by plasma enhanced chemical vapor deposition.

[0022] In some embodiments of the present disclosure, in the step of preparing the doped polysilicon material layer, the gas pressure in the deposition chamber is controlled to be 1000mTorr~5000mTorr, the deposition temperature is controlled to be 300℃~550℃, and the deposition power is controlled to be 5000W~15000W.

[0023] In some embodiments of the present disclosure, during the heat treatment of the doped polysilicon material layer, the heat treatment temperature is controlled to be 800° C. to 1000° C.

[0024] In some embodiments of the present disclosure, the p-type doping element is selected from one or more of boron and gallium.

[0025] In some embodiments of the present disclosure, the substrate includes an n-type silicon wafer and a tunneling oxide layer stacked on the n-type silicon wafer, and the polysilicon material layer is prepared on a side of the tunneling oxide layer away from the n-type silicon wafer.

[0026] In another aspect, the present disclosure further provides a p-type crystalline silicon thin film, comprising a p-type polycrystalline silicon layer, wherein the p-type polycrystalline silicon layer contains a p-type doping element, and the crystallization rate of the p-type polycrystalline silicon layer is above 90%.

[0027] In some embodiments of the present disclosure, the method for preparing the p-type crystalline silicon thin film includes the following steps:

[0028] Preparing a polysilicon material layer with a crystallization rate of ≤35% on a substrate;

[0029] The polysilicon material layer is an intrinsic polysilicon material layer, and a p-type doping element is doped into the intrinsic polysilicon material layer and heat-treated to form a p-type polysilicon layer with a crystallization rate of more than 90%; or

[0030] The polysilicon material layer is a doped polysilicon material layer containing a p-type doping element, and the doped polysilicon material layer is heat-treated to form a p-type polysilicon layer with a crystallization rate of more than 90%.

[0031] In some embodiments of the present disclosure, the polysilicon material layer is an intrinsic polysilicon material layer, and the intrinsic polysilicon material layer is prepared by chemical vapor deposition. In the step of preparing the intrinsic polysilicon material layer, reaction raw materials including a silicon source are introduced into a deposition chamber.

[0032] In some embodiments of the present disclosure, the intrinsic polysilicon material layer is prepared by low-pressure chemical vapor deposition.

[0033] In some embodiments of the present disclosure, in the step of preparing the intrinsic polysilicon material layer, the gas pressure in the deposition chamber is controlled to be 100 mTorr to 500 mTorr, and the deposition temperature is controlled to be 490° C. to 610° C.

[0034] In some embodiments of the present disclosure, the step of doping the intrinsic polysilicon material layer with a p-type dopant element and performing a heat treatment includes:

[0035] placing the substrate prepared with the intrinsic polysilicon material layer in a diffusion chamber, introducing a doping source containing the p-type doping element into the diffusion chamber, and forming a diffusion layer containing the p-type doping element on the intrinsic polysilicon layer;

[0036] The intrinsic polysilicon material layer and the diffusion layer are heated to perform a push-junction process, during which the p-type doping element is diffused and doped into the intrinsic polysilicon material layer to form the p-type polysilicon layer.

[0037] In some embodiments of the present disclosure, during the process of forming the diffusion layer containing the p-type doping element on the intrinsic polysilicon layer, the temperature in the diffusion chamber is controlled to be 700° C. to 890° C.

[0038] In some embodiments of the present disclosure, during the push-bonding process, the push-bonding temperature is controlled to be 850° C. to 960° C.

[0039] In some embodiments of the present disclosure, the polysilicon material layer is a doped polysilicon material layer containing a p-type doping element, and the doped polysilicon material layer is prepared by chemical vapor deposition. In the step of preparing the doped polysilicon material layer, reaction raw materials including a silicon source and a doping source are introduced into a deposition chamber, and the doping source includes the p-type doping element.

[0040] In some embodiments of the present disclosure, the doped polysilicon material layer is prepared by low-pressure chemical vapor deposition.

[0041] In some embodiments of the present disclosure, in the step of preparing the doped polysilicon material layer, the gas pressure in the deposition chamber is controlled to be 100 mTorr to 500 mTorr, and the deposition temperature is controlled to be 490° C. to 610° C.

[0042] In some embodiments of the present disclosure, the doped polysilicon material layer is prepared by plasma enhanced chemical vapor deposition.

[0043] In some embodiments of the present disclosure, in the step of preparing the doped polysilicon material layer, the gas pressure in the deposition chamber is controlled to be 1000mTorr~5000mTorr, the deposition temperature is controlled to be 300℃~550℃, and the deposition power is controlled to be 5000W~15000W.

[0044] In some embodiments of the present disclosure, during the heat treatment of the doped polysilicon material layer, the heat treatment temperature is controlled to be 800° C. to 1000° C.

[0045] In some embodiments of the present disclosure, the p-type doping element is selected from one or more of boron and gallium.

[0046] In some embodiments of the present disclosure, the substrate includes an n-type silicon wafer and a tunneling oxide layer stacked on the n-type silicon wafer, and the polysilicon material layer is prepared on a side of the tunneling oxide layer away from the n-type silicon wafer.

[0047] In yet another aspect, the present disclosure further provides a semiconductor device, comprising the p-type crystalline silicon thin film described in any of the above embodiments.

[0048] In some embodiments of the present disclosure, the semiconductor device is a solar cell or a field effect transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] FIG1 is a schematic diagram of the steps of a method for preparing a p-type crystalline silicon thin film;

[0050] FIG. 2 is a schematic diagram showing the steps of another method for preparing a p-type crystalline silicon thin film. DETAILED DESCRIPTION

[0051] To facilitate understanding of the present disclosure, a more comprehensive description is provided below. Preferred embodiments of the present disclosure are provided herein. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0052] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this disclosure pertains. The terms used herein in the specification of this disclosure are for the purpose of describing specific embodiments only and are not intended to limit this disclosure. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0053] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part.

[0054] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a," "an," and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including," when used in this specification, identify the presence of features, integers, steps, operations, elements, and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0055] The present disclosure provides a method for preparing a p-type crystalline silicon thin film, comprising the following steps: preparing a polycrystalline silicon material layer having a crystallization rate of ≤35% on a substrate. The polycrystalline silicon material layer is an intrinsic polycrystalline silicon material layer, p-type doping elements are doped into the intrinsic polycrystalline silicon material layer, and heat treatment is performed to form a p-type polycrystalline silicon layer having a crystallization rate of greater than 90%. Alternatively, the polycrystalline silicon material layer is a doped polycrystalline silicon material layer containing a p-type doping element, and the doped polycrystalline silicon material layer is heat treated to form a p-type polycrystalline silicon layer having a crystallization rate of greater than 90%.

[0056] In conventional technology, the carrier mobility of doped semiconductors is usually increased by increasing the doping concentration. The present disclosure takes a different approach and improves the carrier mobility by increasing the crystallization rate of doped polysilicon.

[0057] Specifically, in the method for preparing the crystalline silicon film, an intrinsic polysilicon material layer or a doped polysilicon material layer with a crystallization rate of ≤35% is prepared on the substrate in advance, and then the intrinsic polysilicon material layer is doped and heat-treated, or the doped polysilicon material layer is heat-treated. The present disclosure has found through research that for a p-type doped polysilicon material layer, the lower the crystallization rate of the polysilicon material layer before the heat treatment, the higher the crystallization rate of the polysilicon material layer after the heat treatment. As the crystallization rate increases, the continuity of the lattice of the p-type crystalline silicon film also increases, and the grain boundaries and defects also decrease, which can reduce the scattering of carriers within the lattice, thereby improving the carrier mobility of the p-type crystalline silicon film.

[0058] The method for preparing the p-type crystalline silicon thin film disclosed herein can be implemented in various ways.

[0059] Figure 1 is a schematic diagram of the steps of a method for preparing a p-type crystalline silicon thin film. Referring to Figure 1 , the p-type crystalline silicon thin film includes steps S1.1 to S1.3.

[0060] Step S1.1, preparing an intrinsic polysilicon material layer on a substrate.

[0061] In some examples of this embodiment, a substrate is used to support the intrinsic polysilicon material layer. The substrate material may include one or more of glass, quartz, sapphire, silicon, silicon-germanium alloy, gallium nitride, or gallium arsenide. Alternatively, the substrate may be an intermediate product for certain devices, and the ultimately formed p-type polysilicon layer may contribute to the formation of the device.

[0062] For example, if the device to be manufactured is a solar cell, in some examples of this embodiment, the substrate may include an n-type silicon wafer, and the intrinsic polysilicon material layer may be directly formed on the n-type silicon wafer to ultimately form a pn junction. Furthermore, in some examples of this embodiment, the substrate may also include a tunneling oxide layer disposed on the n-type silicon wafer. The intrinsic polysilicon material layer may also be formed on the tunneling oxide layer to ultimately form a passivation contact structure located on the n-type silicon wafer.

[0063] In some examples of this embodiment, the tunneling oxide layer can be formed on the n-type silicon wafer by deposition or thermal oxidation. For example, the n-type silicon wafer can be placed in a thermal oxidation chamber, and oxygen can be introduced into the thermal oxidation chamber to form a tunneling oxide layer on the surface of the n-type silicon wafer. In this embodiment, the thickness of the tunneling oxide layer can be 1 nm to 2 nm.

[0064] In some examples of this embodiment, in the step of preparing the tunnel oxide layer, the temperature in the thermal oxidation chamber can be controlled to be 500°C to 640°C, the reaction time can be controlled to be 2min to 60min, and the oxygen flow rate can be controlled to be 1000sccm to 30000sccm.

[0065] In this embodiment, the crystallization rate of the prepared intrinsic polycrystalline silicon material layer is ≤35%. For example, the crystallization rate of the prepared intrinsic polycrystalline silicon material layer is 0.1%, 1%, 3%, 5%, 10%, 15%, 20%, 25%, or 35%, or the crystallization rate of the intrinsic polycrystalline silicon material layer can be within a range between any two of the above crystallization rates.

[0066] The specific process conditions for preparing the intrinsic polysilicon material layer can be controlled to ensure a low crystallization rate of the prepared intrinsic polysilicon material layer. It is understood that the crystallization rate can be characterized by Raman testing.

[0067] In some examples of this embodiment, the intrinsic polysilicon material layer may be prepared by chemical vapor deposition. In the step of preparing the intrinsic polysilicon material layer, a reaction raw material including a silicon source is introduced into a deposition chamber.

[0068] In some examples of this embodiment, the silicon source may be a silicon-containing compound that can form silicon upon thermal decomposition. Furthermore, the silicon source may be a silicon hydride. Silicon hydrides may include, but are not limited to, one or more of SiH4 and Si2H6. Silicon hydrides can decompose under thermal conditions to produce silicon atoms, which are deposited on the substrate and aggregate to form an intrinsic polycrystalline silicon material layer.

[0069] In some examples of this embodiment, the method for preparing the intrinsic polysilicon material layer can be a low-pressure chemical vapor deposition method. Furthermore, in the step of preparing the intrinsic polysilicon material layer, the gas pressure in the deposition chamber is controlled to be 100mTorr to 500mTorr, and the deposition temperature is controlled to be 490°C to 610°C. Optionally, the deposition temperature can be controlled to be 490°C to 590°C. By simultaneously controlling the gas pressure and deposition temperature in the deposition chamber, the crystallization rate of the prepared intrinsic polysilicon material layer can be made below 35%.

[0070] Furthermore, in some examples of this embodiment, during the step of preparing the intrinsic polycrystalline silicon material layer, the pressure in the deposition chamber can be controlled to be 100 mTorr, 150 mTorr, 200 mTorr, 250 mTorr, 300 mTorr, 400 mTorr, or 500 mTorr, or the pressure in the deposition chamber can be controlled to be within a range between any two of the above pressures. By controlling the pressure in the deposition chamber within the above range, the crystallization rate of the intrinsic polycrystalline silicon material layer can be reduced while maximizing the deposition rate of silicon atoms.

[0071] Furthermore, in some examples of this embodiment, in the step of preparing the intrinsic polysilicon material layer, the deposition temperature can be controlled to be 490° C., 500° C., 510° C., 520° C., 530° C., 540° C., 550° C., 560° C., 570° C., 580° C., 585° C., or 590° C., or the deposition temperature can be controlled within a range between any two of the above temperatures. By controlling the deposition temperature within the above range, the crystallization rate of the intrinsic polysilicon material layer can be reduced while the deposition rate of silicon atoms can be increased as much as possible.

[0072] In addition, during the step of preparing the intrinsic polysilicon material layer, the deposition temperature can be selected according to the pressure in the deposition chamber. When the pressure in the deposition chamber is high, the deposition temperature can also be set higher to increase the deposition rate while ensuring a low crystallization rate.

[0073] In some examples of this embodiment, in the step of preparing the intrinsic polysilicon material layer, the flow rate of the silicon source can be controlled to be 100 sccm to 800 sccm. Further, the flow rate of the silicon source can be controlled to be 100 sccm, 200 sccm, 300 sccm, 400 sccm, 500 sccm, 600 sccm, 700 sccm, or 800 sccm, or the flow rate of the silicon source can be controlled to be within a range between any two of the above flow rates.

[0074] In some examples of this embodiment, the deposition time can be controlled to be 30 minutes to 800 minutes. For example, the deposition time can be controlled to be 30 minutes, 50 minutes, 100 minutes, 200 minutes, 300 minutes, 500 minutes, 700 minutes, or 800 minutes. Alternatively, the deposition time can be controlled to be within a range between any two of the above deposition times.

[0075] Step S1.2, adding p-type doping elements into the intrinsic polysilicon material layer.

[0076] In some examples of this embodiment, the method of doping the p-type doping element into the intrinsic polysilicon material layer may be diffusion, and this step may be performed in a diffusion chamber.

[0077] In some examples of this embodiment, the step of doping the intrinsic polysilicon material layer with a p-type doping element includes: placing a substrate prepared with the intrinsic polysilicon material layer in a diffusion chamber, introducing a doping source containing the p-type doping element into the diffusion chamber, and forming a diffusion layer containing the p-type doping element on the intrinsic polysilicon layer.

[0078] The doping source can be selected based on the p-type doping element to be doped. In some examples of this embodiment, the p-type doping element can be selected from one or more of boron and gallium. In this embodiment, the p-type doping element can be boron. Correspondingly, in this embodiment, the doping source can be one or more of boron trichloride and boron tribromide. The doping source can be carried into the diffusion chamber by a carrier gas.

[0079] In some examples of this embodiment, during the process of forming a diffusion layer containing a p-type dopant element on the intrinsic polysilicon layer, the temperature in the diffusion chamber can be controlled to be between 700° C. and 890° C. For example, the temperature in the diffusion chamber can be controlled to be 700° C., 710° C., 720° C., 730° C., 740° C., 750° C., 760° C., 770° C., 780° C., 790° C., 800° C., 810° C., 820° C., 830° C., 840° C., 850° C., 860° C., 870° C., 880° C., or 890° C., or the temperature in the diffusion chamber can be controlled to be within a range between any two of the above temperatures. Controlling the temperature in the diffusion chamber to a higher level not only facilitates the formation of the diffusion layer on the intrinsic polysilicon material layer, but more importantly, ensures that the intrinsic polysilicon material layer with a lower crystallization rate can be converted into a p-type polysilicon layer with a higher crystallization rate.

[0080] In some examples of this embodiment, during the process of preparing a diffusion layer containing a p-type dopant element on the intrinsic polysilicon layer, the flow rate of the carrier gas carrying the dopant source may be controlled to be 100 sccm to 400 sccm.

[0081] In some examples of this embodiment, an oxidizing gas, such as oxygen, may be introduced into the diffusion chamber during the diffusion process. The oxidizing gas may have a flow rate of 400 sccm to 1000 sccm. It will be appreciated that the oxidizing gas may react with the dopant source to form an oxide material containing a p-type dopant element, such as boron oxide. This oxide material may serve as a component of the diffusion layer.

[0082] In some examples of this embodiment, during the diffusion process, the gas pressure in the diffusion chamber may be controlled to be 100 mbar to 400 mbar.

[0083] Step S1.3, performing heat treatment on the intrinsic polysilicon material layer and the diffusion layer.

[0084] In some examples of this embodiment, the p-type doping element in the diffusion layer is diffused into the intrinsic polysilicon material layer during the heat treatment to form a p-type polysilicon layer.

[0085] Among them, heat treatment refers to a treatment method in which the intrinsic polysilicon material layer is heated and then cooled. Heat treatment can rearrange the silicon atoms in the intrinsic polysilicon material layer and improve its crystallization rate. However, in traditional technology, the solid solubility of p-type doping elements is low. The presence of p-type doping elements hinders the rearrangement of silicon atoms and limits the improvement of the crystallization rate, resulting in the crystallization rate of p-type polysilicon always being difficult to reach more than 90%. Even if a pre-annealing or post-annealing process is performed, it is actually difficult to effectively improve the carrier mobility of doped polysilicon. This embodiment first prepares an intrinsic amorphous silicon layer with a low crystallization rate, and then performs corresponding diffusion treatment and heat treatment, which can significantly improve the crystallization rate of the final p-type polysilicon layer.

[0086] In some examples of this embodiment, the step of heat treating the intrinsic polysilicon material layer and the diffusion layer includes: heating the intrinsic polysilicon material layer and the diffusion layer to perform a push-junction process, and during the push-junction process, the p-type doping element is diffused into the intrinsic polysilicon material layer to form a p-type polysilicon layer.

[0087] In some examples of this embodiment, during the push-junction process, the push-junction temperature can be controlled to be 850° C. to 960° C. By controlling the temperature of the diffusion chamber and the push-junction temperature during the push-junction process, the crystallization rate of the final p-type polysilicon layer can be guaranteed while allowing the p-type dopant element to diffuse into the intrinsic polysilicon material layer.

[0088] In some examples of this embodiment, during the push-bonding process, the push-bonding temperature can be controlled to 850°C, 860°C, 870°C, 880°C, 890°C, 900°C, 910°C, 920°C, 930°C, 940°C, 950°C, or 960°C, or the push-bonding temperature can be controlled to be within a range between any two of the above temperatures.

[0089] It can be understood that steps S1.1 to S1.3 complete the preparation of the p-type polycrystalline silicon layer. In this embodiment, an intrinsic polycrystalline silicon material layer containing no doping elements is first prepared, and then the p-type doping element is doped into the intrinsic polycrystalline silicon material layer, i.e., this method is ex-situ doping. The p-type crystalline silicon thin film disclosed herein can include this p-type polycrystalline silicon layer.

[0090] Figure 2 is a schematic diagram of another method for preparing a p-type crystalline silicon thin film. Referring to Figure 2 , the method for preparing a p-type crystalline silicon thin film includes steps S2.1 to S2.2.

[0091] Step S2.1, preparing a doped polysilicon material layer on a substrate.

[0092] In some examples of this embodiment, a substrate is used to support the intrinsic polysilicon material layer. The substrate can be selected with reference to the substrate in step S1.1, and will not be described in detail here.

[0093] In this embodiment, the doped polysilicon material layer contains a p-type doping element. In some examples of this embodiment, the p-type doping element can be selected from one or more of boron and gallium.

[0094] In this embodiment, the crystallization rate of the prepared doped polysilicon material layer is less than 35%. For example, the crystallization rate of the prepared doped polysilicon material layer is 0.1%, 1%, 3%, 5%, 10%, 15%, 20%, 25%, or 35%, or the crystallization rate of the doped polysilicon material layer can be within a range between any two of the above crystallization rates.

[0095] The specific process conditions for preparing the doped polysilicon material layer can be controlled so that the crystallization rate of the prepared doped polysilicon material layer is low.

[0096] In some examples of this embodiment, the doped polysilicon material layer can be prepared by chemical vapor deposition, and the p-type dopant element can be in-situ doped into the doped polysilicon material layer during the silicon atom deposition process. In the step of preparing the doped polysilicon material layer, a reaction raw material including a silicon source and a dopant source is introduced into a deposition chamber, and the dopant source includes the p-type dopant element.

[0097] In some examples of this embodiment, the silicon source may be a silicon-containing compound that can be thermally decomposed to form silicon. Further, the silicon source may be a silicon hydride compound. The silicon hydride compound may include, but is not limited to, one or more of SiH4 and Si2H6.

[0098] The doping source can be selected based on the p-type doping element to be doped and the specific preparation process. In this embodiment, the p-type doping element can be boron. Accordingly, in this embodiment, the doping source can include a borohydride, for example, the doping source can include borane. The doping source can be introduced into the deposition chamber together with the silicon source. The doping source and the silicon source decompose to produce silicon atoms and doping atoms, which are deposited together on the substrate and aggregated to form a doped polysilicon material layer.

[0099] Furthermore, the method for preparing the doped polysilicon material layer may be a low pressure chemical vapor deposition method or a plasma enhanced chemical vapor deposition method.

[0100] In this embodiment, a doped polysilicon material layer may be prepared by low-pressure chemical vapor deposition. In the step of preparing the doped polysilicon material layer, the gas pressure in the deposition chamber is controlled to be 100mTorr to 500mTorr, and the deposition temperature is controlled to be 490°C to 580°C.

[0101] Furthermore, in some examples of this embodiment, in the step of preparing the doped polysilicon material layer, the gas pressure in the deposition chamber can be controlled to be 100mTorr, 150mTorr, 200mTorr, 250mTorr, 300mTorr, 400mTorr, or 500mTorr, or the gas pressure in the deposition chamber can be controlled to be within the range between any two of the above pressures.

[0102] Furthermore, in some examples of this embodiment, in the step of preparing the doped polysilicon material layer, the preferred deposition temperature can be controlled to be 490°C, 500°C, 510°C, 520°C, 530°C, 540°C, 550°C, 560°C, 570°C, 580°C, 580°C, 590°C, or the deposition temperature can be controlled within the range between any two of the above temperatures.

[0103] In some examples of this embodiment, in the step of preparing the doped polysilicon material layer, the flow rate of the silicon source may be controlled to be 100 sccm to 800 sccm, and the flow rate of the doping source may be controlled to be 100 sccm to 500 sccm.

[0104] Furthermore, in some examples of this embodiment, the flow rate of the silicon source can be controlled to be 100 sccm, 200 sccm, 300 sccm, 400 sccm, 500 sccm, 600 sccm, 700 sccm, or 800 sccm, or the flow rate of the silicon source can be controlled within the range between any two of the above flow rates.

[0105] Furthermore, in some examples of this embodiment, in the step of preparing the doped polysilicon material layer, the flow rate of the doping source can be controlled to 100sccm, 150sccm, 200sccm, 300sccm, 350sccm, 400sccm, 450sccm, 500sccm, or the flow rate of the doping source can be controlled within the range between any two of the above flow rates.

[0106] In some examples of this embodiment, the deposition time can be controlled to be 30 min to 800 min. For example, the deposition time can be controlled to be 30 min, 50 min, 100 min, 200 min, 300 min, 500 min, 700 min, 800 min, or the deposition time can be controlled to be within the range between any two of the above deposition times.

[0107] Alternatively, in this embodiment, plasma enhanced chemical vapor deposition can also be used to prepare the doped polysilicon material layer. In the step of preparing the doped polysilicon material layer, the gas pressure in the deposition chamber is controlled to be 1000mTorr~5000mTorr, the deposition temperature is controlled to be 300℃~550℃, and the deposition power is controlled to be 5000W~15000W.

[0108] Furthermore, in some examples of this embodiment, in the step of preparing the doped polysilicon material layer, the gas pressure in the deposition chamber can be controlled to 1000mTorr, 1200mTorr, 1500mTorr, 2000mTorr, 2500mTorr, 3000mTorr, 3500mTorr, 4000mTorr, 4500mTorr, or 5000mTorr, or the gas pressure in the deposition chamber can be controlled to be within the range between any two of the above pressures.

[0109] Furthermore, in some examples of this embodiment, in the step of preparing the doped polysilicon material layer, the deposition temperature can be controlled to 300°C, 350°C, 400°C, 450°C, 500°C, 550°C, or the deposition temperature can be controlled within the range between any two of the above temperatures.

[0110] In some examples of this embodiment, the deposition power can be controlled to be 5000W to 15000W. For example, the deposition time can be controlled to be 5000W, 6000W, 7000W, 8000W, 9000W, 10000W, 11000W, 12000W, 13000W, 14000W, or 15000W. Alternatively, the deposition power can be controlled to be within a range between any two of the above deposition powers. By controlling the deposition power to be lower, the crystallization rate of the prepared polysilicon material layer can also be lowered.

[0111] In some examples of this embodiment, the flow rate of the silicon source is controlled to be 1000 sccm to 5000 sccm, and the flow rate of the doping source is controlled to be 100 sccm to 1000 sccm.

[0112] Furthermore, in the step of preparing the doped polysilicon material layer, the flow rate of the silicon source can be controlled to be 1000 sccm, 2000 sccm, 3000 sccm, 4000 sccm, 5000 sccm, or the flow rate of the silicon source can be controlled to be within the range between any two of the above flow rates.

[0113] Furthermore, in the step of preparing the doped polysilicon material layer, the flow rate of the doping source can be controlled to 100 sccm, 200 sccm, 300 sccm, 400 sccm, 500 sccm, 600 sccm, 700 sccm, 800 sccm, 900 sccm, or 1000 sccm, or the flow rate of the doping source can be controlled within the range between any two of the above flow rates.

[0114] It can be understood that the above-mentioned low-pressure chemical vapor deposition method or plasma deposition method can prepare a doped polysilicon material layer with a crystallization rate below 35%, and the p-type doping element is in-situ doped into the doped polysilicon material layer.

[0115] Step S2.2, performing heat treatment on the doped polysilicon material layer.

[0116] The heat treatment refers to a process of heating the doped polysilicon material layer and then cooling it. In some examples of this embodiment, the heat treatment process can redistribute the silicon atoms and dopant atoms in the doped polysilicon material layer, thereby effectively improving the crystallization rate of the prepared p-type polysilicon layer.

[0117] In some examples of this embodiment, during the heat treatment of the doped polysilicon material layer, the heat treatment temperature is controlled to be 800° C. to 1000° C. By controlling the heat treatment temperature during the heat treatment, the crystallization rate of the final p-type polysilicon layer can be ensured while the dopant atoms are embedded in the silicon lattice.

[0118] In some examples of this embodiment, during the heat treatment of the doped polysilicon material layer, the heat treatment temperature can be controlled to 800°C, 820°C, 850°C, 880°C, 900°C, 920°C, 950°C, 980°C, or 1000°C, or the annealing temperature can be controlled to be within the range between any two of the above temperatures.

[0119] It can be understood that through steps S2.1 to S2.2, the preparation of the p-type polysilicon layer can be completed. The p-type crystalline silicon thin film disclosed herein may include the p-type polysilicon layer.

[0120] Furthermore, the present disclosure also provides a p-type crystalline silicon thin film, which includes a p-type polycrystalline silicon layer. The p-type polycrystalline silicon layer contains a p-type dopant element, and the crystallization rate of the p-type polycrystalline silicon layer is greater than 90%. Furthermore, the crystallization rate of the p-type polycrystalline silicon layer can be 90%, 91%, 92%, 93%, 94%, 95%, 96%, 97%, 98%, or 99%, or the thickness of the p-type polycrystalline silicon layer can also be within the range between any two of the above thicknesses.

[0121] Furthermore, the p-type crystalline silicon thin film can be prepared by the method for preparing the p-type crystalline silicon thin film in any of the above embodiments.

[0122] Furthermore, the present disclosure provides a semiconductor device that may include a p-type crystalline silicon thin film as described in any of the above embodiments. It is understood that the p-type crystalline silicon thin film can serve as a functional layer in the semiconductor device, having a high crystallinity and high carrier mobility, thereby improving the electrical performance of the semiconductor device.

[0123] In some examples of this embodiment, the semiconductor device may be a solar cell or a field effect transistor. Furthermore, the solar cell may be a crystalline silicon solar cell, and its specific structure may be designed with reference to the structure of existing solar cells, which will not be described in detail here.

[0124] In order to facilitate the description of the method for preparing the p-type crystalline silicon thin film and its advantages, the present disclosure further provides the following embodiments and comparative examples.

[0125] Prepare the substrate

[0126] Providing an n-type single crystal silicon wafer, performing a damage removal treatment and a polishing treatment using a KOH solution with a mass concentration of 10%, with a process time of 2 to 10 minutes and a process temperature of 50 to 80° C., and cleaning the n-type single crystal silicon wafer;

[0127] The cleaned silicon wafer is placed in a thermal oxidation chamber, oxygen gas with a flow rate of 10,000 sccm is introduced, the thermal oxidation chamber is heated to 600°C, and the reaction is maintained for 30 minutes to form a tunneling oxide layer on the surface of the n-type single crystal silicon wafer, which serves as a substrate.

[0128] Example 1

[0129] Placing the substrate in a deposition chamber of a low-pressure chemical vapor deposition device, and introducing silane into the deposition chamber;

[0130] Controlling the gas pressure in the deposition chamber to 300 mTorr, controlling the deposition temperature in the deposition chamber to 570° C., controlling the silane flow rate to 500 sccm, and controlling the deposition time to 100 minutes to form an intrinsic polysilicon material layer;

[0131] The substrate was transferred to a diffusion chamber, the temperature of the diffusion chamber was controlled at 850°C, boron trichloride was introduced into the diffusion chamber using nitrogen as a carrier gas, and oxygen was introduced into the diffusion chamber at a flow rate of 200 sccm for the carrier gas and 800 sccm for the oxygen. The pressure of the diffusion chamber was controlled at 200 mbar, and a boron oxide diffusion layer was formed on the surface of the intrinsic polysilicon material layer.

[0132] The temperature of the diffusion chamber is controlled to rise to 950° C. to perform a push-in process, so that boron atoms diffuse into the intrinsic polysilicon material layer. The diffusion chamber is cooled naturally to complete the annealing process and form a p-type polysilicon layer.

[0133] Example 2

[0134] Placing the substrate in a deposition chamber of a low-pressure chemical vapor deposition device, and introducing silane into the deposition chamber;

[0135] Controlling the gas pressure in the deposition chamber to 200 mTorr, controlling the deposition temperature in the deposition chamber to 540° C., controlling the silane flow rate to 500 sccm, and controlling the deposition time to 300 minutes to form an intrinsic polysilicon material layer;

[0136] The substrate was transferred to a diffusion chamber, the temperature of the diffusion chamber was controlled at 850°C, boron trichloride was introduced into the diffusion chamber using nitrogen as a carrier gas, and oxygen was introduced into the diffusion chamber at a flow rate of 200 sccm for the carrier gas and 800 sccm for the oxygen. The pressure of the diffusion chamber was controlled at 200 mbar, and a boron oxide diffusion layer was formed on the surface of the intrinsic polysilicon material layer.

[0137] The temperature of the diffusion chamber is controlled to rise to 950° C. to perform a push-in process, so that boron atoms diffuse into the intrinsic polysilicon material layer. The diffusion chamber is cooled naturally to complete the annealing process and form a p-type polysilicon layer.

[0138] Example 3

[0139] Placing the substrate in a deposition chamber of a low-pressure chemical vapor deposition device, and introducing silane into the deposition chamber;

[0140] Controlling the gas pressure in the deposition chamber to 300 mTorr, controlling the deposition temperature in the deposition chamber to 580° C., controlling the silane flow rate to 500 sccm, and controlling the deposition time to 100 minutes to form an intrinsic polysilicon material layer;

[0141] The substrate was transferred to a diffusion chamber, the temperature of the diffusion chamber was controlled at 850°C, boron trichloride was introduced into the diffusion chamber using nitrogen as a carrier gas, and oxygen was introduced into the diffusion chamber at a flow rate of 200 sccm for the carrier gas and 800 sccm for the oxygen. The pressure of the diffusion chamber was controlled at 200 mbar, and a boron oxide diffusion layer was formed on the surface of the intrinsic polysilicon material layer.

[0142] The temperature of the diffusion chamber is controlled to rise to 950° C. to perform a push-in process, so that boron atoms diffuse into the intrinsic polysilicon material layer. The diffusion chamber is cooled naturally to complete the annealing process and form a p-type polysilicon layer.

[0143] Example 4

[0144] placing the substrate in a deposition chamber of a low-pressure chemical vapor deposition device, and introducing silane and borane into the deposition chamber;

[0145] Controlling the gas pressure in the deposition chamber to 300 mTorr, controlling the deposition temperature in the deposition chamber to 570° C., controlling the silane flow rate to 500 sccm, controlling the borane flow rate to 300 sccm, and controlling the deposition time to 300 minutes to form a boron-doped polysilicon material layer;

[0146] The substrate is transferred to an annealing furnace tube, and the temperature of the annealing furnace tube is controlled to rise to 980° C., and then the diffusion chamber is cooled naturally to complete the annealing process and form a p-type polysilicon layer.

[0147] Comparative Example 1

[0148] Placing the substrate in a deposition chamber of a low-pressure chemical vapor deposition device, and introducing silane into the deposition chamber;

[0149] Controlling the gas pressure in the deposition chamber to 300 mTorr, controlling the deposition temperature in the deposition chamber to 620° C., controlling the silane flow rate to 500 sccm, and controlling the deposition time to 100 minutes to form an intrinsic polysilicon material layer;

[0150] The substrate was transferred to a diffusion chamber, the temperature of the diffusion chamber was controlled at 850°C, boron trichloride was introduced into the diffusion chamber using nitrogen as a carrier gas, and oxygen was introduced into the diffusion chamber at a flow rate of 200 sccm for the carrier gas and 800 sccm for the oxygen. The pressure of the diffusion chamber was controlled at 200 mbar, and a boron oxide diffusion layer was formed on the surface of the intrinsic polysilicon material layer.

[0151] The temperature of the diffusion chamber is controlled to rise to 950° C. to perform a push-in process, so that boron atoms diffuse into the intrinsic polysilicon material layer. The diffusion chamber is cooled naturally to complete the annealing process and form a p-type polysilicon layer.

[0152] Comparative Example 2

[0153] Placing the substrate in a deposition chamber of a low-pressure chemical vapor deposition device, and introducing silane into the deposition chamber;

[0154] Controlling the gas pressure in the deposition chamber to 300 mTorr, controlling the deposition temperature in the deposition chamber to 630° C., controlling the silane flow rate to 500 sccm, and controlling the deposition time to 100 minutes to form an intrinsic polysilicon material layer;

[0155] The substrate was transferred to a diffusion chamber, the temperature of the diffusion chamber was controlled at 850°C, boron trichloride was introduced into the diffusion chamber using nitrogen as a carrier gas, and oxygen was introduced into the diffusion chamber at a flow rate of 200 sccm for the carrier gas and 800 sccm for the oxygen. The pressure of the diffusion chamber was controlled at 200 mbar, and a boron oxide diffusion layer was formed on the surface of the intrinsic polysilicon material layer.

[0156] The temperature of the diffusion chamber is controlled to rise to 950° C. to perform a push-in process, so that boron atoms diffuse into the intrinsic polysilicon material layer. The diffusion chamber is cooled naturally to complete the annealing process and form a p-type polysilicon layer.

[0157] Comparative Example 3

[0158] Placing the substrate in a deposition chamber of a low-pressure chemical vapor deposition device, and introducing silane into the deposition chamber;

[0159] Controlling the gas pressure in the deposition chamber to 700 mTorr, controlling the deposition temperature in the deposition chamber to 620° C., controlling the silane flow rate to 500 sccm, and controlling the deposition time to 100 minutes to form an intrinsic polysilicon material layer;

[0160] The substrate was transferred to a diffusion chamber, the temperature of the diffusion chamber was controlled at 850°C, boron trichloride was introduced into the diffusion chamber using nitrogen as a carrier gas, and oxygen was introduced into the diffusion chamber at a flow rate of 200 sccm for the carrier gas and 800 sccm for the oxygen. The pressure of the diffusion chamber was controlled at 200 mbar, and a boron oxide diffusion layer was formed on the surface of the intrinsic polysilicon material layer.

[0161] The temperature of the diffusion chamber is controlled to rise to 950° C. to perform a push-in process, so that boron atoms diffuse into the intrinsic polysilicon material layer. The diffusion chamber is cooled naturally to complete the annealing process and form a p-type polysilicon layer.

[0162] Comparative Example 4

[0163] Placing the substrate in a deposition chamber of a low-pressure chemical vapor deposition device, and introducing silane into the deposition chamber;

[0164] Controlling the gas pressure in the deposition chamber to 700 mTorr, controlling the deposition temperature in the deposition chamber to 620° C., controlling the silane flow rate to 500 sccm, and controlling the deposition time to 100 minutes to form an intrinsic polysilicon material layer;

[0165] The substrate was transferred to a diffusion chamber, the temperature of the diffusion chamber was controlled at 850°C, boron trichloride was introduced into the diffusion chamber using nitrogen as a carrier gas, and oxygen was introduced into the diffusion chamber at a flow rate of 200 sccm for the carrier gas and 800 sccm for the oxygen. The pressure of the diffusion chamber was controlled at 200 mbar, and a boron oxide diffusion layer was formed on the surface of the intrinsic polysilicon material layer.

[0166] The temperature of the diffusion chamber is controlled to rise to 950° C. to perform a push-in process, so that boron atoms diffuse into the intrinsic polysilicon material layer. The diffusion chamber is cooled naturally to complete the annealing process and form a p-type polysilicon layer.

[0167] Comparative Example 5

[0168] Placing the substrate in a deposition chamber of a low-pressure chemical vapor deposition device, and introducing silane into the deposition chamber;

[0169] Controlling the gas pressure in the deposition chamber to 700 mTorr, controlling the deposition temperature in the deposition chamber to 595° C., controlling the silane flow rate to 500 sccm, and controlling the deposition time to 100 minutes to form an intrinsic polysilicon material layer;

[0170] The substrate was transferred to a diffusion chamber, the temperature of the diffusion chamber was controlled at 850°C, boron trichloride was introduced into the diffusion chamber using nitrogen as a carrier gas, and oxygen was introduced into the diffusion chamber at a flow rate of 200 sccm for the carrier gas and 800 sccm for the oxygen. The pressure of the diffusion chamber was controlled at 200 mbar, and a boron oxide diffusion layer was formed on the surface of the intrinsic polysilicon material layer.

[0171] The temperature of the diffusion chamber is controlled to rise to 950° C. to perform a push-in process, so that boron atoms diffuse into the intrinsic polysilicon material layer. The diffusion chamber is cooled naturally to complete the annealing process and form a p-type polysilicon layer.

[0172] Experiment: The crystallization rate 1 of the polysilicon material layer and the crystallization rate 2 of the p-type polysilicon layer prepared in the above embodiments and comparative examples were tested, and the carrier mobility of the p-type polysilicon layer prepared in the above embodiments and comparative examples was tested. The results can be seen in Table 1.

[0173] Table 1

[0174] As shown in Table 1, the crystallization rates of the polysilicon material layers prepared in Examples 1 to 3 are all controlled below 35%. Accordingly, the crystallization rate of the p-type polysilicon layer obtained after heat treatment can reach more than 90%. The crystallization rates of the polysilicon material layers prepared in Comparative Examples 1 to 5 are significantly higher, but the crystallization rate of the p-type polysilicon layer obtained after heat treatment is relatively limited or basically cannot be significantly improved. Therefore, by controlling the crystallization rate of the initially prepared polysilicon material layer to be relatively low, the crystallization rate of the finally prepared p-type polysilicon layer can be made to be more than 90%. Please note that the above embodiments are for illustrative purposes only and are not meant to limit the present disclosure.

[0175] It should be understood that, unless otherwise expressly stated herein, there is no strict order restriction for the execution of steps, and these steps may be executed in other orders. Furthermore, at least a portion of the steps in the preparation process may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed and completed at the same time, but may be executed at different times. The order of execution of these sub-steps or stages is not necessarily sequential, but may be executed in rotation or alternation with other steps or at least a portion of the sub-steps or stages of other steps.

[0176] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0177] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

Claims

1. A method for preparing a p-type crystalline silicon thin film, comprising the following steps: Preparing a polysilicon material layer with a crystallization rate of ≤35% on a substrate; The polysilicon material layer is an intrinsic polysilicon material layer, and a p-type doping element is doped into the intrinsic polysilicon material layer and heat-treated to form a p-type polysilicon layer with a crystallization rate of more than 90%; or, The polysilicon material layer is a doped polysilicon material layer containing a p-type doping element, and the doped polysilicon material layer is heat-treated to form a p-type polysilicon layer with a crystallization rate of more than 90%.

2. According to the method for preparing a p-type crystalline silicon thin film according to claim 1, the polycrystalline silicon material layer is an intrinsic polycrystalline silicon material layer, and the intrinsic polycrystalline silicon material layer is prepared by chemical vapor deposition. In the step of preparing the intrinsic polycrystalline silicon material layer, a reaction raw material including a silicon source is introduced into a deposition chamber. 3 . The method for preparing a p-type crystalline silicon thin film according to claim 2 , wherein the intrinsic polycrystalline silicon material layer is prepared by a low pressure chemical vapor deposition method. 4 . The method for preparing a p-type crystalline silicon thin film according to claim 3 , wherein in the step of preparing the intrinsic polysilicon material layer, the gas pressure in the deposition chamber is controlled to be 100 mTorr to 500 mTorr, and the deposition temperature is controlled to be 490° C. to 610° C.

5. The method for preparing a p-type crystalline silicon thin film according to any one of claims 1 to 4, wherein the step of doping the intrinsic polycrystalline silicon material layer with a p-type doping element and performing a heat treatment comprises: Placing the substrate prepared with the intrinsic polysilicon material layer in a diffusion chamber, introducing a doping source containing the p-type doping element into the diffusion chamber, and forming a diffusion layer containing the p-type doping element on the intrinsic polysilicon layer; The intrinsic polysilicon material layer and the diffusion layer are heated to perform a push-junction process, during which the p-type doping element is diffused and doped into the intrinsic polysilicon material layer to form the p-type polysilicon layer. 6 . The method for preparing a p-type crystalline silicon thin film according to claim 5 , wherein during the process of forming the diffusion layer containing the p-type doping element on the intrinsic polysilicon layer, the temperature in the diffusion chamber is controlled to be 700° C. to 890° C.

7. The method for preparing a p-type crystalline silicon thin film according to claim 5 or 6, wherein during the push-junction treatment, the push-junction temperature is controlled to be 850°C to 960°C.

8. According to the method for preparing a p-type crystalline silicon thin film according to claim 1, the polycrystalline silicon material layer is a doped polycrystalline silicon material layer containing a p-type doping element, and the doped polycrystalline silicon material layer is prepared by chemical vapor deposition. In the step of preparing the doped polycrystalline silicon material layer, reaction raw materials including a silicon source and a doping source are introduced into a deposition chamber, and the doping source includes the p-type doping element. 9 . The method for preparing a p-type crystalline silicon thin film according to claim 8 , wherein the doped polysilicon material layer is prepared by low pressure chemical vapor deposition.

10. The method for preparing a p-type crystalline silicon thin film according to claim 9, wherein in the step of preparing the doped polysilicon material layer, the gas pressure in the deposition chamber is controlled to be 100mTorr-500mTorr, and the deposition temperature is controlled to be 490°C-610°C. 11 . The method for preparing a p-type crystalline silicon thin film according to claim 8 , wherein the doped polysilicon material layer is prepared by plasma enhanced chemical vapor deposition.

12. According to the method for preparing a p-type crystalline silicon thin film according to claim 11, in the step of preparing the doped polysilicon material layer, the gas pressure in the deposition chamber is controlled to be 1000mTorr~5000mTorr, the deposition temperature is controlled to be 300℃~550℃, and the deposition power is controlled to be 5000W~15000W.

13. The method for preparing a p-type crystalline silicon thin film according to any one of claims 1 to 12, wherein during the heat treatment of the doped polysilicon material layer, the heat treatment temperature is controlled to be 800°C to 1000°C.

14. The method for preparing a p-type crystalline silicon thin film according to any one of claims 1 to 13, wherein the p-type doping element is selected from one or more of boron and gallium.

15. The method for preparing a p-type crystalline silicon thin film according to any one of claims 1 to 14, wherein the substrate comprises an n-type silicon wafer and a tunneling oxide layer stacked on the n-type silicon wafer, and the polysilicon material layer is prepared on a side of the tunneling oxide layer away from the n-type silicon wafer.

16. A p-type crystalline silicon thin film, comprising a p-type polycrystalline silicon layer, wherein the p-type polycrystalline silicon layer contains a p-type doping element, and the crystallization rate of the p-type polycrystalline silicon layer is above 90%.

17. The p-type crystalline silicon thin film according to claim 16, wherein the method for preparing the p-type crystalline silicon thin film comprises the following steps: Preparing a polysilicon material layer with a crystallization rate of ≤35% on a substrate; The polysilicon material layer is an intrinsic polysilicon material layer, and a p-type doping element is doped into the intrinsic polysilicon material layer and heat-treated to form a p-type polysilicon layer with a crystallization rate of more than 90%; or, The polysilicon material layer is a doped polysilicon material layer containing a p-type doping element, and the doped polysilicon material layer is heat-treated to form a p-type polysilicon layer with a crystallization rate of more than 90%.

18. According to the p-type crystalline silicon thin film of claim 17, the polycrystalline silicon material layer is an intrinsic polycrystalline silicon material layer, and the intrinsic polycrystalline silicon material layer is prepared by chemical vapor deposition. In the step of preparing the intrinsic polycrystalline silicon material layer, a reaction raw material including a silicon source is introduced into a deposition chamber. 19 . The p-type crystalline silicon thin film according to claim 18 , wherein the intrinsic polycrystalline silicon material layer is prepared by low pressure chemical vapor deposition.

20. The p-type crystalline silicon thin film according to claim 19, in the step of preparing the intrinsic polycrystalline silicon material layer, the gas pressure in the deposition chamber is controlled to be 100mTorr-500mTorr, and the deposition temperature is controlled to be 490°C-610°C.

21. The p-type crystalline silicon thin film according to any one of claims 17 to 20, wherein the step of doping the intrinsic polycrystalline silicon material layer with a p-type doping element and performing a heat treatment comprises: Placing the substrate prepared with the intrinsic polysilicon material layer in a diffusion chamber, introducing a doping source containing the p-type doping element into the diffusion chamber, and forming a diffusion layer containing the p-type doping element on the intrinsic polysilicon layer; The intrinsic polysilicon material layer and the diffusion layer are heated to perform a push-junction process, during which the p-type doping element is diffused and doped into the intrinsic polysilicon material layer to form the p-type polysilicon layer.

22. The p-type crystalline silicon thin film according to claim 21, wherein during the process of forming the diffusion layer containing the p-type doping element on the intrinsic polysilicon layer, the temperature in the diffusion chamber is controlled to be 700°C to 890°C.

23. The p-type crystalline silicon thin film according to claim 21 or 22, wherein during the push-junction process, the push-junction temperature is controlled to be 850°C to 960°C.

24. According to the p-type crystalline silicon thin film according to claim 17, the polycrystalline silicon material layer is a doped polycrystalline silicon material layer containing a p-type doping element, and the doped polycrystalline silicon material layer is prepared by chemical vapor deposition. In the step of preparing the doped polycrystalline silicon material layer, reaction raw materials including a silicon source and a doping source are introduced into a deposition chamber, and the doping source includes the p-type doping element. 25 . The p-type crystalline silicon thin film according to claim 24 , wherein the doped polysilicon material layer is prepared by low pressure chemical vapor deposition. 26 . The p-type crystalline silicon thin film according to claim 25 , wherein in the step of preparing the doped polysilicon material layer, the gas pressure in the deposition chamber is controlled to be 100 mTorr to 500 mTorr, and the deposition temperature is controlled to be 490° C. to 610° C. 27 . The p-type crystalline silicon thin film according to claim 26 , wherein the doped polysilicon material layer is prepared by plasma enhanced chemical vapor deposition.

28. According to the p-type crystalline silicon thin film of claim 27, in the step of preparing the doped polysilicon material layer, the gas pressure in the deposition chamber is controlled to be 1000mTorr~5000mTorr, the deposition temperature is controlled to be 300℃~550℃, and the deposition power is controlled to be 5000W~15000W.

29. The p-type crystalline silicon thin film according to any one of claims 17 to 28, wherein during the heat treatment of the doped polysilicon material layer, the heat treatment temperature is controlled to be 800°C to 1000°C.

30. The p-type crystalline silicon thin film according to any one of claims 17 to 29, wherein the p-type doping element is selected from one or more of boron and gallium.

31. The p-type crystalline silicon thin film according to any one of claims 17 to 30, wherein the substrate comprises an n-type silicon wafer and a tunneling oxide layer stacked on the n-type silicon wafer, and the polysilicon material layer is prepared on a side of the tunneling oxide layer away from the n-type silicon wafer.

32. A semiconductor device, comprising the p-type crystalline silicon thin film according to any one of claims 17 to 31.

33. The semiconductor device according to claim 32, wherein the semiconductor device is a solar cell or a field effect transistor.

Images