Method for forming isolation trench, preparation method for semiconductor device, and process device

Abstract

The present application provides a method for forming an isolation trench, a preparation method for a semiconductor device, and a process device. The method for forming an isolation trench comprises: providing an object to be etched, said object comprising a substrate, and a gate structure and an isolation dielectric layer which are located on one side surface of the substrate, and the gate structure extending in a first direction and being arranged on the same layer as the isolation dielectric layer; and alternately and cyclically etching the isolation dielectric layer and the gate structure to form a first isolation trench, the first isolation trench penetrating the gate structure in a second direction, and the first direction and the second direction being perpendicular to each other. The solution of the present application enables the isolation trench to meet the high aspect ratio and etching morphology design requirements of the semiconductor device while further reducing the feature size of the semiconductor device, which is beneficial for improving the level of integration of an integrated circuit.

Description

Method for forming isolation trench, method for preparing semiconductor device and process equipment Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for forming an isolation trench, a method for preparing a semiconductor device, and process equipment. Background Art

[0002] With the advancement of semiconductor technology, integrated circuits are moving towards smaller sizes and higher integration densities. The gate size of field-effect transistors (FETs) continues to shrink, and FETs are gradually evolving from planar FETs to more efficient fin FETs (Fin FETs).

[0003] Currently, gates are mostly fabricated using a gate-last process, which typically involves first forming a dummy gate on a substrate, then performing ion implantation to form a doped region. The dummy gate is then removed by high-temperature annealing. Finally, a gate dielectric layer and a gate material are sequentially deposited in the region where the dummy gate has been removed, forming the gate. In a gate-last process, the dummy gate is typically designed based on the location and size of the actual gate. However, as field-effect transistors continue to shrink in size, dimensional deviations and dielectric damage are more likely to occur when removing the dummy gate in locations with smaller design dimensions and larger aspect ratios. This can lead to voids during subsequent metal filling, reducing device reliability.

[0004] To address this issue, one process involves first forming a gate structure and a dielectric layer on a substrate, exposing the top wall of the gate structure. Isolation trenches are then etched separately from the dielectric layer and gate structure to form isolation trenches. This isolation trench divides the gate structure into multiple gates, eliminating the need for dummy gate formation and removal, while meeting the requirements for small size and high aspect ratio. However, as device feature sizes shrink further, for example from 14nm to 10nm, this process fails to meet device design requirements, hindering the integration of integrated circuits.

[0005] Summary of the Invention

[0006] The present application provides a method for forming an isolation trench, a method for preparing a semiconductor device, and process equipment to solve the problem in related technologies that when the characteristic size of the device is further reduced, the design requirements of the device cannot be met, which is not conducive to improving the integration of integrated circuits.

[0007] A first aspect of the present application provides a method for forming an isolation trench, comprising:

[0008] Providing an object to be etched, the object to be etched comprising a substrate, a gate structure located on a surface of one side of the substrate, and an isolation dielectric layer, wherein the gate structure extends along a first direction and is disposed in the same layer as the isolation dielectric layer;

[0009] The isolation dielectric layer and the gate structure are etched alternately and cyclically to form a first isolation trench, which penetrates the gate structure along a second direction, and the first direction and the second direction are perpendicular to each other; wherein, in each cycle, the isolation dielectric layer is first etched to a predetermined depth to expose a portion of the gate structure, and then the exposed gate structure is etched to make the gate structure roughly flush with the top surface of the isolation dielectric layer.

[0010] In one embodiment, the object to be etched includes an interlayer dielectric layer located between the substrate and the gate structure, and the first isolation trench exposes a top wall of the interlayer dielectric layer. After forming the first isolation trench, the method further includes:

[0011] A portion of the interlayer dielectric layer exposed by the first isolation trench is etched to form a second isolation trench. The first isolation trench and the second isolation trench are connected to each other to form a target isolation trench.

[0012] In one embodiment, the alternate cyclic etching of the isolation dielectric layer and the gate structure includes: alternately and cyclically performing the isolation dielectric layer etching step and the gate structure etching step until the gate structure is cut off.

[0013] In one embodiment, a mask layer is provided on the side of the isolation dielectric layer facing away from the substrate, and the method further includes: before each cycle of executing the isolation dielectric layer etching step and the gate structure etching step, performing a sacrificial layer deposition step to deposit a sacrificial layer on the side of the mask layer facing away from the substrate, and the sacrificial layer is consumed during the execution of the isolation dielectric layer etching step and the gate structure etching step.

[0014] In one embodiment, a mask layer is provided on a side of the isolation dielectric layer facing away from the substrate, the mask layer having a mask opening, and an orthographic projection of the mask opening on the substrate and an orthographic projection of the gate structure on the substrate are perpendicular to each other and partially overlap;

[0015] Etching the interlayer dielectric layer includes: alternately and cyclically executing a sacrificial layer deposition step and an interlayer dielectric layer etching step until the interlayer dielectric layer is etched to a target depth; the sacrificial layer deposition step is used to deposit a sacrificial layer on the side of the mask layer away from the substrate, and the sacrificial layer is consumed during the execution of the interlayer dielectric layer etching step.

[0016] In one embodiment, the sacrificial layer deposition step and the alternate cyclic etching steps of the isolation dielectric layer and the gate structure are performed in the same process chamber.

[0017] In one embodiment, the process conditions of the sacrificial layer deposition step include: the process gas includes a silicon-containing gas, and the process gas further includes at least one of an oxygen-containing gas and a nitrogen-containing gas.

[0018] In one embodiment, the process conditions of the sacrificial layer deposition step further include: an upper electrode power range of 100 W to 400 W, and a pressure range of 5 mTorr to 30 mTorr inside the process chamber.

[0019] In one embodiment, the process conditions of the isolation dielectric layer etching step include that the process gas includes a fluorine-containing gas; and / or the process conditions of the gate structure etching step include that the process gas includes a chlorine-containing gas.

[0020] In one embodiment, the fluorine-containing gas includes tetrafluoromethane and perfluorobutadiene; and / or the chlorine-containing gas includes boron trichloride gas and chlorine gas.

[0021] In one embodiment, the object to be etched includes a plurality of discrete fins located between a substrate and a gate structure, the plurality of fins extending along a second direction, the gate structure spanning the plurality of fins and covering a portion of the top wall and a portion of the side wall of each fin; forming a first isolation trench includes: forming a first isolation trench between adjacent fins.

[0022] A second aspect of the present application provides a method for preparing a semiconductor device, comprising: forming a plurality of semiconductor devices, wherein gate structures of the plurality of semiconductor devices are connected to each other;

[0023] By adopting the method for forming the isolation trench in any of the above embodiments, the gate structures of adjacent semiconductor devices are cut off, so that the gate structure is formed into a plurality of gates.

[0024] The third aspect of the present application provides a semiconductor process equipment, including: a process chamber, an air intake assembly, an exhaust assembly, an upper electrode assembly, a lower electrode assembly and a controller, the controller including at least one processor and at least one memory, the memory storing a computer program, and when the computer program is executed by the processor, it implements a method as described in any one of the embodiments of the first aspect above.

[0025] The advantages or beneficial effects of the above technical solution include at least: by alternately etching the isolation dielectric layer and the gate structure, the isolation dielectric layer and the gate structure can be simultaneously etched, forming a narrower and deeper first isolation trench. Furthermore, this etching method can precisely control the etching depth and sidewall morphology of the first isolation trench. As the feature size of semiconductor devices further decreases, the design requirements for high aspect ratios and etching morphology of the isolation trench can be met, thereby facilitating an increase in the integration density of integrated circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present application, and together with the description, serve to explain the principles of the present application. In addition, these drawings and the description are not intended to limit the scope of the concept of the present application in any way, but rather to illustrate the concept of the present application for those skilled in the art by reference to specific embodiments.

[0027] 1A to 1E are schematic structural diagrams showing steps in a method for forming an isolation trench in the related art.

[0028] FIG. 2 is a schematic flow chart showing a method for forming an isolation trench according to an embodiment of the present application.

[0029] 3A to 3C are schematic three-dimensional structural diagrams showing steps of a method for forming an isolation trench according to an embodiment of the present application.

[0030] 4A to 9B are schematic cross-sectional views showing steps of a method for forming an isolation trench according to an embodiment of the present application.

[0031] FIG10 is a schematic structural diagram of a semiconductor process equipment according to an embodiment of the present application. DETAILED DESCRIPTION

[0032] Hereinafter, only certain exemplary embodiments are briefly described. As will be appreciated by those skilled in the art, the described embodiments may be modified in various ways without departing from the spirit or scope of the present application. Therefore, the drawings and description are to be regarded as illustrative in nature and not restrictive.

[0033] Figures 1A to 1E are schematic diagrams of the various steps of a method for forming an isolation trench according to the related art. Figure 1A is a schematic diagram of the cross-sectional structure of the object to be etched according to the related art from a first viewing angle. Figure 1B is a schematic diagram of the cross-sectional structure of Figure 1A from a second viewing angle. Figure 1C is a schematic diagram of the cross-sectional structure of Figure 1A after etching the isolation dielectric layer. Figure 1D is a schematic diagram of the cross-sectional structure of Figure 1C after etching the gate structure. Figure 1E is a schematic diagram of the cross-sectional structure of Figure 1D after etching the isolation dielectric layer and the gate structure.

[0034] The method for forming an isolation trench includes: as shown in Figures 1A and 1B, providing a substrate 110, having a gate structure 120, an interlayer dielectric layer 130 and an isolation dielectric layer 140 on one side surface of the substrate 110, the gate structure 120 extending along a first direction D1, the gate structure 120 and the isolation dielectric layer 140 are both located on the interlayer dielectric layer 130, and the isolation dielectric layer 140 exposes the top wall of the gate structure 120. Among them, a plurality of discrete fins 150 are also arranged between the substrate 110 and the gate structure 120, and the plurality of fins 150 all extend along a second direction, which is perpendicular to the first direction D1; the gate structure 120 spans the plurality of fins 150; as shown in Figure 1C, a first isolation trench 171 is formed in the isolation dielectric layer 140 using a mask layer 160, and the first isolation trench 171 exposes the sidewalls of the gate structure 120 and the interlayer dielectric layer 130; as shown in Figures 1D and 1E, the gate structure 120 exposed by the first isolation trench 171 is removed, and a second isolation trench (not marked in Figures 1D and 1E) is formed in the gate structure 120, and the second isolation trench exposes the top wall of the interlayer dielectric layer 130 and is adjacent to and connected to the first isolation trench 171, forming a target isolation trench 170.

[0035] During the implementation process, the inventors found that: the above-mentioned related technology adopts the method of first etching the isolation dielectric layer 140 to form the first isolation trench 171, and then etching the gate structure 120 to form the second isolation trench, and using the second isolation trench to connect with the first isolation trench 171 to form the target isolation trench 170, so that the target isolation trench 170 has a smaller aspect ratio. This etching method is more suitable for semiconductor devices with a feature size greater than 14nm and above. When the feature size of the semiconductor device is further reduced, for example, the feature size is reduced from 14nm to 10nm, the isolation trench needs to be reduced simultaneously to meet the high aspect ratio requirement of the device. Therefore, the formation of the related technology cannot meet the high aspect ratio requirement of the device. In addition, please refer to Figures 1C to 1D. After the first isolation trench 171 is formed in the related technology, the first isolation trench 171 will expose the interlayer dielectric layer 130. The top wall of the target isolation groove 170 and the side wall of the isolation dielectric layer 140 cause the interlayer dielectric layer 130 to be etched downward along the first isolation groove 171 and the isolation dielectric layer 140 to be etched laterally during the etching process of the gate structure 120, so that the interlayer dielectric layer 130 forms a first groove 131 that is concave downward and the isolation dielectric layer 140 forms a second groove 141 that is concave laterally. Therefore, it is difficult for the related art method to accurately control the etching depth and sidewall morphology of the target isolation groove 170, resulting in the etching morphology of the target isolation groove 170 being unable to meet the design requirements of the device.

[0036] In view of this, the present application provides a method for forming an isolation trench. This method can meet the device's high aspect ratio and etching profile requirements as the feature size of semiconductor devices further decreases, making it suitable for use in the fabrication of semiconductor devices with even smaller feature sizes, thereby facilitating increased integration of integrated circuits. The following describes embodiments of the present application in detail with reference to the accompanying drawings.

[0037] The method for forming an isolation trench according to an embodiment of the present application is performed in a semiconductor processing apparatus 200 shown in FIG10 . For illustration, the semiconductor processing apparatus 200 is an inductively coupled plasma (ICP) etching apparatus. The semiconductor processing apparatus 200 includes an RF coil 21 located at the top of a process chamber 20 and outside a dielectric cylinder (not shown), and a carrier 22 located within the process chamber 20. The RF coil 21 is electrically connected to an upper RF power supply 23 via an upper matcher 25. The upper RF power supply 23 is configured to apply upper electrode power to the RF coil 21 via the upper matcher 25, causing the RF coil 21 to excite the process gas within the process chamber 20 into a plasma. The carrier 22 is configured to support the object 100 to be etched. The carrier 22 is electrically connected to a lower RF power supply 24 via a lower matcher 26. The lower RF power supply 24 applies lower electrode power to the carrier 22 via the lower matcher 26, providing an RF bias voltage to the carrier 22.

[0038] FIG2 is a schematic flow chart of a method for forming an isolation trench according to an embodiment of the present application. FIG3A through FIG3C are schematic three-dimensional structural diagrams illustrating the various steps of the method for forming an isolation trench according to an embodiment of the present application. FIG4A through FIG9B are schematic cross-sectional structural diagrams illustrating the various steps of the method for forming an isolation trench according to an embodiment of the present application. FIG3A through FIG3C omit the isolation dielectric layer 140, mask layer 160, and sacrificial layer 180 shown in FIG4A through FIG9B.

[0039] As shown in FIG. 2 , the method for forming the isolation trench includes the following steps S310 to S320 .

[0040] In step S310, please refer to Figures 3A, 4A and 4B, and provide an object 100 to be etched. The object 100 to be etched includes a substrate 110 and a gate structure 120 and an isolation dielectric layer 140 located on one surface of the substrate 110. The gate structure 120 extends along a first direction D1 and is arranged in the same layer as the isolation dielectric layer 140.

[0041] In step S320, referring to Figures 3B and 6A to 7B, the isolation dielectric layer 140 and the gate structure 120 are etched alternately and cyclically to form a first isolation trench 171. The first isolation trench 171 extends through the gate structure 120 along a second direction D2. The first direction D1 and the second direction D2 are perpendicular to each other. In each cycle, the isolation dielectric layer 140 is first etched to a predetermined depth to expose a portion of the gate structure. The exposed gate structure 120 is then etched until the gate structure 120 is substantially flush with the top surface of the isolation dielectric layer 140.

[0042] Exemplarily, the alternating cyclic etching of the isolation dielectric layer 140 and the gate structure 120 may be as follows: as shown in FIG6A , the isolation dielectric layer 140 is first etched downward to a predetermined depth to expose the top wall and a portion of the side wall of the gate structure 120; as shown in FIG6B , the portion of the gate structure 120 exposed from the isolation dielectric layer 140 is further etched downward to complete one cycle; referring to FIG6A , the isolation dielectric layer 140 is then etched downward to a predetermined depth to expose the top wall and a portion of the side wall of the remaining gate structure 120; referring to FIG6B , the portion of the remaining gate structure 120 exposed from the remaining isolation dielectric layer 140 is then further etched downward to complete another cycle; the isolation dielectric layer 140 and the gate structure 120 are alternately etched in this manner for multiple cycles, wherein, after each cycle, the gate structure 120 is approximately flush with the top surface of the isolation dielectric layer 140. This alternating cyclic etching method allows the isolation dielectric layer 140 and the gate structure 120 to be etched downward simultaneously, forming a first isolation trench 171 with a narrower width and a deeper depth, which can meet the high aspect ratio requirements of the device. Moreover, compared with the related art, since the interlayer dielectric layer 130 is not exposed and the exposed area of ​​the isolation dielectric layer 140 is smaller during the etching of the gate structure 120, the interlayer dielectric layer 130 is not consumed downward during the etching of the gate structure 120, and the lateral consumption of the isolation dielectric layer 140 is relatively small. Therefore, during the etching process, the etching depth and sidewall morphology of the first isolation trench 171 can be precisely controlled, meeting the etching morphology design requirements of the device. As shown in Figures 3B, 7A, and 7B, the width L of the first isolation trench 171 is the minimum distance between the two sidewalls of the first isolation trench 171 in the first direction D1, and the depth H of the first isolation trench 171 is the maximum height of the first isolation trench 171 in the direction D3 perpendicular to the substrate 110.

[0043] In addition, please refer to Figure 3B, Figure 7A and Figure 7B together. The first isolation trench 171 is formed inside the isolation dielectric layer 140 and inside the gate structure 120, and penetrates the gate structure 120 along the second direction D2, so that the gate structure 120 can be completely cut off in the second direction D2 to form a plurality of gates 120A.

[0044] The above-described solution, through alternating cycles of etching the isolation dielectric layer 140 and the gate structure 120, can achieve simultaneous etching of the isolation dielectric layer 140 and the gate structure 120, forming a narrower and deeper first isolation trench 171. Furthermore, this etching method can precisely control the etching depth and sidewall morphology of the first isolation trench 171. This can meet the high aspect ratio design requirements and etching morphology design requirements for isolation trenches in semiconductor devices as the feature size of semiconductor devices further decreases, thereby facilitating increased integration of integrated circuits. The above-described solution is particularly suitable for advanced process semiconductor devices or integrated circuit designs with feature sizes of less than 10 nm or less.

[0045] In one embodiment, referring to Figures 3B, 3C, and 8A to 9B, the object 100 to be etched further includes an interlayer dielectric layer 130 located between the substrate 110 and the gate structure 120, and the first isolation trench 171 exposes the top wall of the interlayer dielectric layer 130. Following step S320, the process further includes step S330 of etching the portion 130A of the interlayer dielectric layer 130 exposed by the first isolation trench 171 to form a second isolation trench 172 within the interlayer dielectric layer 130. The second isolation trench 172 is interconnected with the first isolation trench 171 to form the target isolation trench 170.

[0046] It should be noted that, as shown in Figures 3B, 7A and 7B, the first isolation trench 171 formed in step S320 can cut off the gate structure 120 just along the direction D3 perpendicular to the substrate 110 to form multiple gates 120A, but it cannot ensure that there is no electrical connection between adjacent gates 120A. Therefore, step S330 is used to continue etching the portion 130A of the interlayer dielectric layer 130 exposed by the first isolation trench 171 to form a second isolation trench 172, which can ensure that the gate structure 120 is completely cut off along the direction D3 perpendicular to the substrate 110, thereby avoiding electrical connection between adjacent gates 120A.

[0047] Figure 4A is a schematic diagram of the cross-sectional structure of Figure 3A along the direction of the cut line A1-A2, and Figure 4B is a schematic diagram of the cross-sectional structure of Figure 3A along the direction of the cut line B1-B2, wherein the mask layer 160 in Figures 4A and 4B is omitted in Figure 3A. Figure 5A is a schematic diagram of the cross-sectional structure of Figure 4A after the first deposition of the sacrificial layer, and Figure 5B is a schematic diagram of the cross-sectional structure of Figure 4B after the first deposition of the sacrificial layer. Figure 6A is a schematic diagram of the cross-sectional structure of Figure 5A after the first etching of the isolation dielectric layer. Figure 6B is a schematic diagram of the cross-sectional structure of Figure 5A after the first etching of the gate structure. Figure 7A is a schematic diagram of the cross-sectional structure of Figure 6A after etching the isolation dielectric layer and gate structure exposed through the mask opening. Figure 7B is a schematic diagram of the cross-sectional structure of Figure 4B after etching the gate structure exposed through the mask opening.

[0048] In one embodiment, as shown in FIG4A and FIG4B , a mask layer 160 is disposed on a side of the isolation dielectric layer 140 facing away from the substrate 110. The mask layer 160 has a mask opening 161. The orthographic projection of the mask opening 161 on the substrate 110 is perpendicular to and partially overlaps with the orthographic projection of the gate structure 120 on the substrate 110. In this manner, portions of the top wall of the isolation dielectric layer 140 and the top wall of the gate structure 120 can be exposed through the mask opening 161, allowing etching of the isolation dielectric layer 140 and the gate structure 120 along the mask opening 161.

[0049] In step S320, alternately and cyclically etching the isolation dielectric layer 140 and the gate structure 120 includes: as shown in FIG7A to FIG8B , alternately and cyclically performing the isolation dielectric layer etching step and the gate structure etching step until the gate structure 120 is severed. In this manner, the isolation dielectric layer etching step can be performed to a certain depth in the isolation dielectric layer 140, and the gate structure etching step can be performed to a depth similar to the etching depth of the isolation dielectric layer 140. Such continuous cycles facilitate accurate severing of the gate structure 120, thereby forming a first isolation trench 171 having a high aspect ratio.

[0050] In one embodiment, referring to the film layer variations of FIG. 4A and FIG. 5A , a mask layer 160 is provided on a side of the isolation dielectric layer 140 facing away from the substrate 110 . The forming method further includes:

[0051] Before each cycle of performing the isolation dielectric layer etching step and the gate structure etching step, a sacrificial layer deposition step is performed to form a sacrificial layer 180 on the side of the mask layer 160 facing away from the substrate 110, so that the sacrificial layer 180 is consumed during the execution of the isolation dielectric layer etching step and the gate structure etching step, as shown in Figures 6A to 6B.

[0052] For example, referring to the film layer changes from FIG. 4A to FIG. 5A and the film layer changes from FIG. 4B to FIG. 5B , the orthographic projection of sacrificial layer 180 on substrate 110 overlaps with the orthographic projection of mask layer 160 on substrate 110. Sacrificial layer 180 has an opening 181. Opening 181 of sacrificial layer 180 communicates with mask opening 161, and the orthographic projection of opening 181 of sacrificial layer 180 on substrate 110 overlaps with the orthographic projection of mask opening 161 on substrate 110. Thus, during the isolation dielectric layer etching step and the gate structure etching step, plasma can be directed along opening 181 of sacrificial layer 180 into mask opening 161, thereby contacting isolation dielectric layer 140 and gate structure 120.

[0053] The material for the isolation dielectric layer 140 can be a silicide material such as silicon oxide (SiO2) or silicon nitride (SiN), while the material for the mask layer 160 is often silicon nitride (SiN). Since both are silicide materials, and their materials can be the same or similar, a significant amount of the mask layer 160 is consumed when etching the isolation dielectric layer 140 using an etching gas. For example, in practical applications, when a silicide material is used for the isolation dielectric layer 140, a fluorine-containing gas is typically used to etch the isolation dielectric layer 140. Since the etching gas has a relatively low selectivity for silicon nitride, a significant amount of the mask layer 160 is consumed during the etching process of the isolation dielectric layer 140, resulting in the inability to accurately transfer patterns such as the mask opening 161 to subsequent etching processes.

[0054] In this regard, referring to Figures 5A, 6A, and 6B, by forming a sacrificial layer 180 on the side of the mask layer 160 facing away from the substrate 110, the sacrificial layer 180 is partially consumed during the isolation dielectric layer etching step and completely consumed after the gate structure etching step. During the simultaneous downward etching of the isolation dielectric layer 140 and the gate structure 120, the sacrificial layer 180 is consumed to protect the mask layer 160, thereby preventing excessive consumption of the mask layer 160 and thereby reducing the accuracy of pattern transfer, such as the mask opening 161. Furthermore, because the sacrificial layer 180 protects the mask layer 160, the accuracy of pattern transfer can be further improved by reducing the thickness of the mask layer 160.

[0055] Please refer to Figure 7A and Figure 7B together. After the isolation dielectric layer etching step and the gate structure etching step are alternately performed, the isolation dielectric layer 140 and the gate structure 120 exposed from the mask opening 161 are completely etched to form a first isolation trench 171. The mask opening 161 exposes the interlayer dielectric layer 130.

[0056] In one embodiment, the number of cycles of performing the isolation dielectric layer etching step and the gate structure etching step is between 4 and 12 times. Exemplarily, the number of cycles can be any value of 4, 6, 8, and 12 times. The number of cycles can be selected and adjusted according to the thickness of the gate structure 120. For example, when the thickness of the gate structure 120 is thicker, the number of cycles can be set to 12 times, and when the thickness of the gate structure 120 is thinner, the number of cycles can be set to 4 times. It should be noted that the number of cycles can also be selected and adjusted according to other factors, such as the thickness of the mask layer 160, the process parameters of the plasma etching equipment, etc., and the embodiments of the present application are not limited thereto.

[0057] Figure 8A is a schematic diagram of the cross-sectional structure of the interlayer dielectric layer shown in Figure 7A after etching the portion of the interlayer dielectric layer exposed through the mask opening. Figure 8B is a schematic diagram of the cross-sectional structure of the interlayer dielectric layer shown in Figure 7B after etching the portion of the interlayer dielectric layer exposed through the mask opening. Figure 8A is a schematic diagram of the cross-sectional structure of the interlayer dielectric layer shown in Figure 7A with a second isolation trench formed therein. Figure 8B is a schematic diagram of the cross-sectional structure of the interlayer dielectric layer shown in Figure 7B with a second isolation trench formed therein.

[0058] In one embodiment, referring to Figures 8A to 9B , in step S330 , etching the portion 130A of the interlayer dielectric layer 130 exposed by the first isolation trench 171 includes alternating cycles of a sacrificial layer deposition step and an interlayer dielectric layer etching step until the interlayer dielectric layer 130 is etched to a target depth. The sacrificial layer deposition step deposits a sacrificial layer 180 on a side of the mask layer 160 facing away from the substrate 110. The orthographic projection of the sacrificial layer 180 on the substrate 110 overlaps with the orthographic projection of the mask layer 160 on the substrate 110. The sacrificial layer 180 is consumed during the etching of the interlayer dielectric layer 130. The target depth can be controlled by controlling the number of cycles of the sacrificial layer deposition step and the interlayer dielectric layer etching step and the thickness of the sacrificial layer 180.

[0059] In step S330, the sacrificial layer deposition step and the interlayer dielectric layer etching step are performed alternately, which facilitates the formation of a second isolation trench 172 having a high aspect ratio within the interlayer dielectric layer 130. The formation and consumption of the sacrificial layer 180 are based on the same principles as those of the aforementioned step S320 embodiment. Therefore, reference may be made to the aforementioned step S320 embodiment and will not be repeated here.

[0060] The above scheme forms a second isolation trench 172 with a high aspect ratio by alternately and cyclically executing the sacrificial layer deposition step and the interlayer dielectric layer etching step, thereby further ensuring that the target isolation trench 170 finally formed satisfies the high aspect ratio design; and, in the process of etching the interlayer dielectric layer 130 downward, the sacrificial layer 180 is consumed to protect the mask layer 160, thereby avoiding the reduction in accuracy of pattern transfer such as the mask opening 161 due to excessive consumption of the mask layer 160, which is beneficial to ensuring that the target isolation trench 170 finally formed satisfies the high aspect ratio condition.

[0061] In one embodiment, the sacrificial layer deposition step and the interlayer dielectric layer etching step are performed for a number of cycles between 3 and 10. For example, the number of cycles can be any value among 3, 5, 7, and 10. The number of cycles can be selected and adjusted based on the thickness of the interlayer dielectric layer 130, the thickness of the mask layer 160, the process parameters of the plasma etching equipment, etc., and the embodiments of the present application are not limited thereto.

[0062] In one embodiment, the sacrificial layer deposition step and the alternate cyclic etching step of the isolation dielectric layer and the gate structure are performed in the same process chamber. For example, the sacrificial layer deposition step and the alternate cyclic etching step of the isolation dielectric layer and the gate structure can both be performed in the process chamber 20 shown in FIG. 2 .

[0063] It should be noted that the different process steps of the related art are usually performed in different process chambers, so the process chamber needs to be replaced during the execution. However, in the process of replacing the process chamber, it is necessary to purge and vacuum the interior of the process chamber, and use a robot to take the object to be etched out of one process chamber and then put it into another process chamber. This operation of replacing the process chamber will reduce production capacity. Compared with the related art, the embodiment of the present application performs the sacrificial layer deposition step and the alternating cyclic etching of the isolation dielectric layer and the gate structure in the same process chamber, which can save the related operations of replacing the process chamber and help improve production capacity.

[0064] In one embodiment, the process conditions of the sacrificial layer deposition step include: the process gas includes a silicon-containing gas, and the process gas further includes at least one of an oxygen-containing gas and a nitrogen-containing gas.

[0065] For example, if the process gas includes a silicon-containing gas and an oxygen-containing gas, the silicon-containing gas and the oxygen-containing gas can react within the process chamber of the plasma etching equipment to form silicon oxide. Similarly, if the process gas includes a silicon-containing gas and a nitrogen-containing gas, silicon nitride can be formed. If the process gas includes a silicon-containing gas, an oxygen-containing gas, and a nitrogen-containing gas, silicon oxynitride can be generated. Silicon oxide, silicon nitride, and silicon oxynitride can all serve as sacrificial layers.

[0066] In one embodiment, referring to FIG. 10 , the process conditions of the sacrificial layer deposition step further include: an upper electrode power range of 100 W to 400 W, and a pressure range of 5 mTorr to 30 mTorr inside the process chamber 20 .

[0067] For example, as shown in FIG. 4A and FIG. 5A , during the deposition process, by controlling the deposition speed, deposition thickness, and deposition position of the sacrificial layer 180 , it is possible to ensure that the generated sacrificial layer 180 meets the process requirements.

[0068] Specifically, regarding the deposition rate: if the deposition rate is too fast, the formed sacrificial layer 180 may easily clog the mask opening 161, resulting in poor uniformity and flatness of the sacrificial layer 180; if the deposition rate is too slow, the sacrificial layer 180 may lack density. In practical applications, when the upper electrode power is between 100W and 400W (inclusive), the deposition rate of the sacrificial layer 180 is positively correlated with the upper electrode power; when the pressure within the process chamber 20 is between 5mTorr and 30mTorr (inclusive), the deposition rate of the sacrificial layer 180 is positively correlated with the pressure within the process chamber 20. Therefore, by setting the upper electrode power range to 100W to 400W and the pressure range within the process chamber 20 to 5mTorr to 30mTorr, it is beneficial to control the deposition rate of the sacrificial layer 180, ensuring that the sacrificial layer 180 is formed at an appropriate deposition rate, so that the sacrificial layer 180 has good uniformity and flatness, and is less likely to clog the mask opening 161. Furthermore, by controlling the bias power range to be 1 W to 100 W (including the end points), the density of the sacrificial layer 180 is increased.

[0069] It should be noted that the deposition rate of the sacrificial layer 180 is also related to the flow rate and ratio of the process gas and the deposition time.

[0070] The process conditions of the sacrificial layer deposition step include: the process gases include silicon nitride gas (SiCl4), oxygen (O2) and helium (He), the flow rate range of silicon nitride gas is 30sccm~100sccm, the flow rate range of oxygen is 30sccm~300sccm, the ratio of silicon nitride gas to oxygen is 1:1~1:3, the flow rate range of helium is 50sccm~200sccm; the deposition time range is 10s~30s.

[0071] For example, referring to FIG10 , an object to be etched 100 is placed on a carrier 22 located inside a process chamber 20, and the carrier 22 adsorbs the object to be etched 100. After silicon chloride gas and oxygen are introduced into the process chamber 20, a sacrificial silicon dioxide layer is formed on the side of the mask layer 160 facing away from the substrate 110 under the action of plasma. The main reaction equation for deposition is shown in equation (1):

[0072] SiCl4+O2→SiO2+2Cl2 Reaction formula (1);

[0073] The chlorine gas (Cl 2 ) generated during the deposition process is extracted from the interior of the process chamber 20 to the exterior of the process chamber 20 as a by-product.

[0074] In controlling process conditions, the silicon nitride gas flow rate and the ratio of silicon nitride gas to oxygen are also positively correlated with the deposition rate of sacrificial layer 180. That is, the greater the silicon nitride gas flow rate and the greater the silicon nitride gas to oxygen ratio, the faster the deposition rate of sacrificial layer 180, which can easily lead to clogging of mask opening 161. Therefore, by controlling the silicon nitride gas flow rate within the range of 30 sccm to 100 sccm and the silicon nitride gas to oxygen ratio within the range of 1:1 to 1:3, it is possible to further ensure that sacrificial layer 180 is formed at an appropriate deposition rate, resulting in good uniformity and flatness of sacrificial layer 180 and less likely to cause clogging of mask opening 161. Furthermore, helium gas introduced into process chamber 20 as a dilution gas can also control the deposition rate of sacrificial layer 180. Controlling the helium gas flow rate within the range of 50 sccm to 200 sccm also facilitates formation of sacrificial layer 180 at an appropriate deposition rate.

[0075] Regarding the deposition thickness, in addition to controlling the silicon nitride gas, oxygen, helium, and plasma etching equipment to meet the aforementioned conditions, it is also necessary to control the deposition time to be within a range of 10s to 30s. This allows the sacrificial layer 180 to have a sufficient thickness without blocking the mask opening 161, thereby reducing the number of subsequent alternating etching cycles of the isolation dielectric layer 140 and the gate structure 120, as well as the number of subsequent etching cycles of the interlayer dielectric layer 130.

[0076] As for the deposition position, controlling the silicon nitride gas, oxygen, helium and plasma etching equipment to meet the above conditions can minimize the deposition on the side walls of the mask opening 161, the top wall of the isolation dielectric layer 140 exposed by the mask opening 161, and the top wall of the gate structure 120 exposed by the mask opening 161, so that the deposition is mainly carried out on the surface of the side of the mask layer 160 facing away from the substrate 110, so as to form the required sacrificial layer 180 on the side of the mask layer 160 facing away from the substrate 110.

[0077] In one embodiment, referring to both FIG. 5A and FIG. 6A , the process conditions for etching the isolation dielectric layer include: the process gas includes a fluorine-containing gas. Since the isolation dielectric layer 140 is mostly made of a silicide material, selecting a fluorine-containing gas as the etching gas can achieve a good etching effect on the isolation dielectric layer 140. In one example, the process gases for the isolation dielectric layer etching step include tetrafluoromethane (CF4), perfluorobutadiene (C4F6) and argon (Ar), the flow rate range of tetrafluoromethane is 5sccm to 50sccm (including endpoint values), the flow rate range of perfluorobutadiene is 30sccm to 200sccm (including endpoint values), and the flow rate range of argon is 100sccm to 300sccm (including endpoint values); the pressure range inside the process chamber 20 is 5mTorr to 30mTorr (including endpoint values); the upper electrode power range is 500W to 1000W (including endpoint values); the lower electrode power range is 100W to 500W (including endpoint values); and the etching time range is 5s to 30s (including endpoint values).

[0078] The isolation dielectric layer etching step may include: evacuating the interior of the process chamber 20 to maintain the pressure inside the process chamber 20 between 5mTorr and 30mTorr; introducing tetrafluoromethane, perfluorobutadiene and argon into the interior of the process chamber 20, wherein the flow rate of tetrafluoromethane is between 5sccm and 50sccm, the flow rate of perfluorobutadiene is between 30sccm and 200sccm, and the flow rate of argon is between 100sccm and 300sccm; controlling the upper electrode power between 500W and 1000W to generate plasma, and controlling the lower electrode power between 100W and 500W to guide the plasma to vertically bombard the exposed portion of the top wall of the isolation dielectric layer 140 along the mask opening 161 to achieve etching of the isolation dielectric layer 140; maintaining the etching time between 5s and 30s to achieve the desired etching effect.

[0079] The isolation dielectric layer 140 is often made of silicon dioxide, so tetrafluoromethane and perfluorobutadiene are used as etching gases to meet the etching requirements of the isolation dielectric layer 140. Argon is used as the carrier gas and dilution gas because its high molecular weight can promote plasma ionization and vertical bombardment capabilities.

[0080] The upper electrode power controls the ionization rate of the etching gas. A higher upper electrode power increases the ionization rate of the etching gas and increases the plasma density. The lower electrode power controls the plasma's bombardment capability. A higher lower electrode power increases the acceleration of the plasma and increases the vertical bombardment of the top wall of the isolation dielectric layer 140.

[0081] The above solution controls the process parameters of the isolation dielectric layer etching step to meet the above conditions, thereby controlling the etching morphology of the first isolation trench 171 to meet the high aspect ratio design requirements.

[0082] In one embodiment, referring to both FIG. 6A and FIG. 6B , the process conditions for the gate structure etching step include: the process gas includes a chlorine-containing gas. Since the gate structure 120 can be made of a metal material, the chlorine-containing gas is selected as the etching gas for the gate structure 120 , which can adapt to the etching requirements of the gate structure 120 and achieve a good etching effect.

[0083] Exemplarily, the process gases include chlorine (Cl2), boron trichloride (BCl3) and nitrogen (N2), the flow rates of chlorine and boron trichloride are both in the range of 30 sccm to 150 sccm (inclusive of endpoint values), and the flow rate of nitrogen is in the range of 5 sccm to 100 sccm (inclusive of endpoint values); the pressure inside the process chamber 20 is in the range of 5 mtorr to 30 mtorr (inclusive of endpoint values); the power of the upper electrode is in the range of 500 W to 1000 W (inclusive of endpoint values); the power of the lower electrode is in the range of 100 W to 500 W (inclusive of endpoint values); and the etching time is in the range of 5 s to 30 s (inclusive of endpoint values). It should be noted that the gate structure etching step is similar to the isolation dielectric layer etching step, so the specific implementation steps of the gate structure etching step can refer to the embodiment of the isolation dielectric layer etching step mentioned above, which will not be repeated here.

[0084] Exemplarily, the gate structure 120 may include a metal gate layer 121 and a high-K dielectric layer 122. The high-K dielectric layer 122 is located between the metal gate layer 121 and the substrate 110, the interlayer dielectric layer 130, and the isolation dielectric layer 140. The metal gate layer 121 may be made of, but not limited to, aluminum (Al), titanium nitride (TiN), titanium (Ti), or tungsten (W). The high-K dielectric layer 122 may be made of, but not limited to, hafnium oxide (HfO2). Chlorine and boron trichloride gases may be used as etching gases to etch the metal gate layer 121. Because boron trichloride has a strong bombardment effect, the high-K dielectric layer 122 is simultaneously bombarded and etched during the etching of the metal gate layer 121, resulting in the simultaneous etching of both the metal gate layer 121 and the high-K dielectric layer 122. Furthermore, because chlorine has a high selectivity for the sacrificial layer 180, the gate structure etching step consumes less sacrificial layer 180 than the isolation dielectric layer etching step.

[0085] The above solution can control the etching morphology of the first isolation trench 171 to meet the high aspect ratio design requirements by controlling the gate structure etching step to meet the above process conditions.

[0086] In one embodiment, referring to Figures 8A to 9B and 10 , the interlayer dielectric layer etching step is performed in a plasma etching apparatus. The process conditions for this interlayer dielectric layer etching step include: the process gas includes a fluorine-containing gas. Since the material of the interlayer dielectric layer 130 is mostly a silicide material, the use of a fluorine-containing gas as the etching gas can achieve a good etching effect on the interlayer dielectric layer 130.

[0087] For example, the process gases include tetrafluoromethane, perfluorobutadiene, argon and oxygen, the flow rate range of tetrafluoromethane is 5sccm~50sccm (including endpoint values), the flow rate range of perfluorobutadiene is 30sccm~200sccm (including endpoint values), the flow rate range of argon is 100sccm~300sccm (including endpoint values), and the flow rate range of oxygen is 5sccm~30sccm (including endpoint values); the pressure range inside the process chamber 20 is 5mTorr~30mTorr (including endpoint values); the upper electrode power range is 500W~1000W (including endpoint values); the lower electrode power range is 100W~500W (including endpoint values); the etching time range is 5s~30s (including endpoint values). It should be noted that the interlayer dielectric layer etching step is similar to the isolation dielectric layer etching step, so the specific implementation process of the interlayer dielectric layer etching step can refer to the above embodiment of the isolation dielectric layer etching step and will not be repeated here.

[0088] Compared with the isolation dielectric layer etching step, in the above example, oxygen is also introduced into the process chamber 20 in the interlayer dielectric layer etching step. By controlling the oxygen flow rate range to 5 sccm to 30 sccm, by-products can be prevented from being deposited on the sidewalls of the first isolation trench 171, ensuring that the plasma can enter the interior of the first isolation trench 171 through the mask opening 161 and contact the interlayer dielectric layer 130 to etch the interlayer dielectric layer 130 to form a second isolation trench 172.

[0089] The above solution can control the etching morphology of the second isolation trench 172 by controlling the interlayer dielectric layer etching step to meet the above process conditions, thereby ensuring that the formed second isolation trench 172 meets the design requirements.

[0090] It should be noted that the isolation dielectric layer etching step, the gate structure etching step and the interlayer dielectric layer etching step are all performed in a plasma etching device, which is beneficial to simplifying the process steps and thus improving the etching efficiency.

[0091] In one embodiment, referring to Figures 3A to 3C , the object 100 to be etched further includes a plurality of discrete fins 150 located between the substrate 110 and the gate structure 120. The fins 150 extend along a second direction D2. The gate structure 120 spans the fins 150 and covers a portion of the top wall and sidewalls of each fin 150. Forming the first isolation trench 171 includes forming the first isolation trench 171 between adjacent fins 150.

[0092] In one example, the gate structure 120 may be one, and a first isolation trench 171 may be formed between adjacent fins 150 to divide the gate structure 120 into two gates 120A, thereby forming two independent fin field-effect transistors.

[0093] In another example, there may be multiple (two or more) gate structures 120, each of which is separate and extends along the first direction D1. Each gate structure 120 spans across the multiple fins 150 and covers a portion of the top wall and sidewall of each fin 150. The first isolation trench 171 formed between adjacent fins 150 can simultaneously penetrate the multiple gate structures 120 along the second direction D2, dividing each gate structure 120 into two gates 120A. This achieves the effect of severing multiple gate structures 120 at once, which helps improve the formation efficiency of the gates 120A.

[0094] In the above solution, by forming the first isolation trench 171 between adjacent fins 150 , the method for forming the isolation trench can be applied to the fabrication of FinFETs.

[0095] This application also provides a method for fabricating a semiconductor device, comprising: forming a plurality of semiconductor devices, wherein the gate structures of the plurality of semiconductor devices are interconnected; employing the method for forming isolation trenches described in any of the above embodiments to sever the gate structures of adjacent semiconductor devices, thereby forming a plurality of gates from the gate structures; wherein the plurality of gates correspond one-to-one with the plurality of semiconductor devices. Because the method for fabricating a semiconductor device utilizes all of the technical solutions of all of the above embodiments, it possesses at least all of the beneficial effects brought about by the technical solutions of the above embodiments, and therefore will not be further elaborated upon herein.

[0096] FIG10 is a schematic structural diagram of a semiconductor process equipment according to an embodiment of the present application.

[0097] As shown in FIG10 , the semiconductor process equipment 200 includes a process chamber 20, an inlet assembly 20A, an exhaust assembly (not shown in FIG10 ), an upper electrode assembly 20B, a lower electrode assembly 20C, and a controller (not shown in FIG10 ). The controller includes at least one processor and at least one memory, wherein the memory stores a computer program. When the computer program is executed by the processor, the method of any of the above embodiments is implemented.

[0098] For example, the controller can be either a host computer or a slave computer. Specifically, the controller can control the opening of the valve of the gas inlet assembly 20A to introduce the corresponding process gas into the process chamber 20. The controller can also control the opening and closing of the valve of the gas inlet assembly 20A to control the flow rate of the process gas. The controller can also control the pressure inside the process chamber 20 by controlling the exhaust assembly to exhaust the gas inside the process chamber 20.

[0099] The upper electrode assembly 20B includes an RF coil 21, an upper RF power supply 23, and an upper matcher 25. The controller is further configured to control the upper RF power supply 23 to provide upper electrode power to the RF coil 21 via the upper matcher 25, so that the RF coil 21 excites the process gas inside the process chamber 20 to generate plasma.

[0100] The lower electrode assembly 20C includes a carrier 22, a lower RF power supply 24, and a lower matcher 26. The controller is further configured to control the lower RF power supply 24 to provide lower electrode power to the lower electrode of the carrier 22 via the lower matcher 26, thereby providing an RF bias to the lower electrode of the carrier 22 to attract plasma above the object 100 to bombard the object 100.

[0101] The semiconductor process equipment 200 of the embodiment of the present application can be an inductively coupled plasma (ICP) etching equipment or a capacitively coupled plasma (CCP) etching equipment. The embodiment of the present application does not limit the type of the semiconductor process equipment 200.

[0102] Furthermore, in this application, unless otherwise expressly specified or limited, terms such as "connected," "connected," and "stacked" should be interpreted broadly. For example, they may refer to fixed connections, detachable connections, or integration; they may refer to direct connections or indirect connections through an intermediate medium; they may refer to internal communication between two elements or interaction between two elements. Those skilled in the art will understand the specific meanings of these terms in this application based on the specific circumstances.

[0103] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. Moreover, the specific features, structures, materials or characteristics described can be combined in an appropriate manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples, unless otherwise expressly specified. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "multiple" is two or more, unless otherwise clearly specified.

[0104] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A method for forming an isolation trench, characterized in that: include: Providing an object to be etched, the object to be etched comprising a substrate, and a gate structure and an isolation dielectric layer located on a surface of one side of the substrate, the gate structure extending along a first direction and being arranged in the same layer as the isolation dielectric layer; Alternately and cyclically etching the isolation dielectric layer and the gate structure to form a first isolation trench, wherein the first isolation trench penetrates the gate structure along a second direction, and the first direction is perpendicular to the second direction; In each cycle, the isolation dielectric layer is first etched to a predetermined depth to expose a portion of the gate structure, and then the exposed gate structure is etched to make the gate structure substantially flush with the top surface of the isolation dielectric layer.

2. The method according to claim 1, characterized in that The object to be etched further includes an interlayer dielectric layer between the substrate and the gate structure, and the first isolation groove exposes a top wall of the interlayer dielectric layer; After forming the first isolation trench, the method further includes: A portion of the interlayer dielectric layer exposed by the first isolation trench is etched to form a second isolation trench, and the first isolation trench and the second isolation trench are connected to each other to form a target isolation trench.

3. The method according to claim 1, characterized in that The alternate cyclic etching of the isolation dielectric layer and the gate structure comprises: alternately and cyclically performing an isolation dielectric layer etching step and a gate structure etching step until the gate structure is cut off.

4. The method according to claim 3, characterized in that A mask layer is disposed on a side of the isolation dielectric layer facing away from the substrate, and the method further comprises: Before each cycle of performing the isolation dielectric layer etching step and the gate structure etching step, a sacrificial layer deposition step is performed to form a sacrificial layer on the side of the mask layer away from the substrate; the sacrificial layer The layer is consumed during the process of performing the isolation dielectric layer etching step and the gate structure etching step.

5. The method according to claim 2, characterized in that: A mask layer is disposed on a side of the isolation dielectric layer facing away from the substrate, the mask layer having a mask opening, and an orthographic projection of the mask opening on the substrate is perpendicular to and partially overlaps with an orthographic projection of the gate structure on the substrate; The etching of the interlayer dielectric layer comprises: alternately and cyclically performing a sacrificial layer deposition step and an interlayer dielectric layer etching step until the interlayer dielectric layer is etched to a target depth; The sacrificial layer deposition step is used to deposit a sacrificial layer on a side of the mask layer away from the substrate, and the sacrificial layer is consumed during the interlayer dielectric layer etching step.

6. The method according to claim 4 or 5, characterized in that: The sacrificial layer deposition step and the alternate cyclic etching step of the isolation dielectric layer and the gate structure are performed in the same process chamber.

7. The method according to claim 6, characterized in that The process conditions of the sacrificial layer deposition step include: the process gas includes a silicon-containing gas, and the process gas further includes at least one of an oxygen-containing gas and a nitrogen-containing gas.

8. The method according to claim 7, characterized in that The process conditions of the sacrificial layer deposition step also include: the upper electrode power range is 100W to 400W, and the pressure range inside the process chamber is 5mTorr to 30mTorr.

9. The method according to claim 3, characterized in that: The process conditions of the isolation dielectric layer etching step include that the process gas includes a fluorine-containing gas; and / or, the process conditions of the gate structure etching step include that the process gas includes a chlorine-containing gas.

10. The method according to claim 9, characterized in that The fluorine-containing gas includes tetrafluoromethane and perfluorobutadiene; and / or the chlorine-containing gas includes boron trichloride gas and chlorine gas.

11. The method according to claim 1, characterized in that: The object to be etched includes a plurality of discrete fins located between the substrate and the gate structure, the plurality of fins all extend along the second direction, and the gate structure spans the plurality of fins and covers a portion of the top wall and a portion of the side wall of each of the fins; The forming of the first isolation trench includes: forming the first isolation trench between adjacent fins.

12. A method for preparing a semiconductor device, characterized in that: include: forming a plurality of semiconductor devices, wherein gate structures of the plurality of semiconductor devices are connected to each other; The method for forming an isolation trench according to any one of claims 1 to 11 is used to cut off the gate structure of adjacent semiconductor devices so that the gate structure is formed into a plurality of gates.

13. A semiconductor process equipment, characterized in that: include: A process chamber, an air inlet assembly, an upper electrode assembly, a lower electrode assembly and a controller, wherein the controller comprises at least one processor and at least one memory, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, the method as described in any one of claims 1 to 11 is implemented.

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