Component carrier with fillers at an interface, and manufacture method

Abstract

There is described a component carrier (100), wherein the component carrier (100) comprises a stack (101) comprising a plurality of electrically insulating layer structures (110, 120) and at least one electrically conductive layer structure (104), i) wherein at least one of said electrically insulating layer structures (110) comprises a main material (112) having fillers (111) embedded therein, ii) wherein a further one of said electrically insulating layer structures (120) is provided on one of the main surfaces (115) of the at least one electrically insulating layer structure (110), and iii) wherein on said main surface (115), the fillers (111) of the electrically insulating layer structures (110) are exposed, and the material (122) of the further electrically insulating layer structure (120) is embedded in the spaces between the exposed fillers (111).

Description

[0001] Component carrier with fillers at an interface, and manufacture method

[0002] Technical Field

[0003] The invention relates to a component carrier with a stack having an electrically insulating layer structure with fillers and a further electrically insulating layer structure on top, wherein material of the further electrically insulating layer structure is embedded in the spaces between exposed fillers. Further, the invention relates to a method of manufacturing the component carrier.

[0004] Thus, the invention may relate to the technical field of manufacturing a component carrier such as a printed circuit board or an IC substrate.

[0005] Technical Background

[0006] In the context of growing product functionalities of component carriers equipped with one or more electronic components and increasing miniaturization of such electronic components as well as a rising number of electronic components to be mounted on the component carriers such as printed circuit boards, increasingly more powerful array-like components or packages having several electronic components are being employed, which have a plurality of contacts or connections, with ever smaller spacing between these contacts. Removal of heat generated by such electronic components and the component carrier itself during operation becomes an increasing issue. Also an efficient protection against electromagnetic interference becomes an increasing issue. At the same time, component carriers shall be mechanically robust and electrically and magnetically reliable so as to be operable even under harsh conditions.

[0007] For example, there may be applied a so-called desmear process during component carrier manufacture. This process may be used to clean component carrier preform (so-called panels) surfaces and bore holes, in particular by removing resin smears. This process may provide a surface roughness that

[0008] AD: JP: pl can be required to improve the adhesion for a further layer, e.g. a copper layer, to the surface to be desmeared. But sometimes the roughness increased might not improve the adhesion, but cause a copper-remaining issue.

[0009] Conventionally, the desmear process is performed as a wet process, in particular by etching (e.g. using permanganate) the component carrier preform surface. However, in case that the component carrier layer at the surface to be etched comprises embedded particles, several drawbacks may occur. For example, the etching can affect a resin material (significantly) stronger than the filler material. In the case of silicon dioxide (SiCh) filler particles, these are generally not affected by etching, while the resin, in which they are embedded, is removed by the etching.

[0010] Figures 4A and 4B respectively show a conventional interface 251 of a circuit board 200. The conventional circuit board 200 comprises two insulating layers stacked on top of each other, wherein each insulating layer comprises filler particles embedded in a matrix material. There is a poor adhesion between the lower surface of the upper layer and the upper surface of the lower layer caused by poor adhesion between resin / filler material of the upper layer and fillers of the lower layer. In particular, after a surface treatment process, such as a desmear process, the filler particles of the lower layer protrude even higher from the matrix material or at least partially expose on the external surface, thereby providing a high surface roughness that causes an even weaker adhesion to the upper layer due to more resin etched and more filler particles without roughening of surface for the filler particles exposed to the interface. Additionally, the interface of resin might become weak being likely to crack due to high roughness, so the adhesion might become weak as well.

[0011] Figure 4A: due to weak adhesion, there is a gap (visible as a black line) at the interface 250 between the two insulating layers after cutting or dicing the product.

[0012] Figure 4B: further due to the weak adhesion, a delamination 251 between the insulating layers has occurred, thereby significantly lowering the quality of the circuit board 200. Summary of the Invention

[0013] There may be a need to provide an efficient and robust interface between electrically insulating layer structures of a component carrier.

[0014] A component carrier, and a manufacture method are provided.

[0015] According to an aspect of the invention, there is described a component carrier (e.g. a printed circuit board or an IC substrate), wherein the component carrier comprises a (multi-layer) stack comprising a plurality (at least two) of electrically insulating layer structures and at least one electrically conductive layer structure. i) at least one of said electrically insulating layer structures comprises a main material (a matrix material, for example a resin) having fillers (e.g. filler particles such as SiO?) embedded therein (preferably non-homogenously distributed); ii) a further one of said electrically insulating layer structures (in particular comprising a further main material with further fillers embedded therein or an insulating material without fillers) is provided on one of the main surfaces of the at least one electrically insulating layer structure; and iii) on said main surface, (at least some of) the fillers of the electrically insulating layer structure are exposed (protrude beyond the external surface of the main material), and (a part of) the (further) material (e.g. resin and / or filler) of the further electrically insulating layer structure is embedded in the spaces between the exposed fillers.

[0016] According to a further aspect of the invention, there is described a method of manufacturing a component carrier comprising a stack comprising a plurality of electrically insulating layer structures and at least one electrically conductive layer structure, the method comprising: i) providing at least one of said electrically insulating layer structures comprising a main material having fillers embedded therein; ii) providing a further electrically insulating layer structure, wherein one of the main surfaces of the electrically insulating layer structure is treated (e.g. by a desmear treatment and / or a plasma treatment) so that the fillers are at least partially exposed; and iii) providing the further electrically insulating layer structure on said main surface of the electrically insulating layer structure, so that material of the further electrically insulating layer structure is embedded in the spaces between the exposed fillers.

[0017] In the context of the present document, the term "filler" may in particular refer to a material suitable to be embedded in electrically insulating material (e.g. resin). The filler may hereby be configured to provide a specific functionality in the insulating material, for example mechanical stabilization for the products, and the filler can also impact the dielectric property of the insulating material such as Dk, Df regarding the electrical performance. In an example, a filler may be configured as a particle such as a bead. While in an example the filler may be rather spherical, in another example, the filler may be formed as a fiber. In a preferred embodiment, spherical fillers are applied in the insulating (resin) material. A specific example of the electrically insulating layer structure may be an Ajinomoto Build-up Film (ABF), or solder resist film or solder resist ink, where spherical particles are embedded in a resin layer. In a further example, the filler material may be (essentially) not affected by a wet desmear process, in particular etching. In a specific example, the filler material comprises silicon dioxide. The filler can be solid or hollow. The filler can comprise a coating or no coating.

[0018] In the context of the present document, the term "main material" may in particular refer to a matrix material that is suitable to embed a filler as described above. Preferably, the main material is an insulating material such as a resin, for example epoxy resin.

[0019] In the context of the present document, the term "component carrier" may particularly denote any support structure which is capable of accommodating one or more components thereon and / or therein for providing mechanical support and / or electrical connectivity and / or thermal conductivity. In other words, a component carrier may be configured as a mechanical and / or electronic and thermal carrier for components. In particular, a component carrier may be one of a printed circuit board, an organic interposer, a metal core substrate, an inorganic substrate and an IC (integrated circuit) substrate. A component carrier may also be a hybrid board combining different ones of the above mentioned types of component carriers. It may comprise at least one electrically insulating structure and electrically conductive structure.

[0020] The term "component carrier preform" (under manufacture) may refer to a semi-finished product that will result, after several process steps, in a final component carrier. A preform may e.g. be a panel that comprises a plurality of (semi-finished) component carriers that will be separated in a further manufacturing step.

[0021] In the context of the present document, the term "embedded in the spaces between" may particularly understood as a structural feature of material (for example resin and / or filler) of the further electrically insulating layer structure being embedded / arranged between fillers (i.e. the spaces between fillers) of the electrically insulating layer structure at the interface region of these two electrically insulating layer structures. In other words, the fillers of the electrically insulating layer structure extend / protrude beyond the external surface of the main material (matrix) and into the material of the further electrically insulating layer structure. Like in a peak and valley surface, in between said protruding fillers (peaks), there are spaces (valleys). These spaces may be occupied (in particular fully occupied) by the further material of the further electrically insulating layer structure. This structural feature may enable a high adhesion between the electrically insulating layer structures at the interface region. This structure might be formed by the bonding between two dielectric layers with the chemical bonding.

[0022] According to an exemplary embodiment, the invention may be based on the idea that an efficient and robust interface between electrically insulating layer structures of a component carrier may be provided, when the interface between said layers is configured so that material of one of the electrically insulating layer structures is embedded in spaces between exposed / protruding fillers of the other electrically insulating layer structure (like in valleys of a peak-and-valley surface). It has been found by the inventors that in this specific arrangement, the material of the further electrically insulating layer structure may adhere in a stable manner to the exposed filler surfaces of the electrically insulating layer structure. Conventionally (see the examples of Figures 4A and 4B above), there remains a gap or even a delamination between stacked electrically insulating layer structures, in particular when at least one of them comprises embedded filler particles, due to weak adhesion. This effect may be even more pronounced when a desmear process is performed that may further expose the filler particles (which are generally of a more stable material than the embedding matrix).

[0023] In contrast, the described component carrier has an interface region, wherein the fillers of one electrically insulating layer structures protrude into material of the other electrically insulating layer structure, thereby providing a dense and compact connection that may significantly enhance the adhesion between the layers. The adhesion may be further enhanced, when for example the material of the further electrically insulating layer structure is pressed / arranged below a portion of an exposed filler (undercut). In a specific example, a plasma treatment step is applied (in particular after a desmear process and before a lamination step), in order to optimize the filler surfaces for achieving the described advantageous adhesion effects.

[0024] Exemplary Embodiments

[0025] According to an embodiment, the further electrically insulating layer structure adheres with the electrically insulating layer structure through the material of said further electrically insulating layer structure embedded in the spaces between the exposed fillers. In this manner, the material of the further electrically insulating layer structure in the spaces between the fillers may be used an anchor to enable a stable and reliable interconnection between the layers at the interface region.

[0026] According to a further embodiment, at least 50%, in particular at least 75%, of the surface of the (further) material of the further electrically insulating layer structure, adhering with / to the main surface of the electrically insulating layer structure, is in (physical) contact with the exposed surface of the fillers. By having such a high amount of the material of the further electrically insulating layer structure in contact with exposed filler surfaces (in other words: within the spaces), an especially high adhesion (anchor function) may be enabled.

[0027] According to a further embodiment, the fillers occupy a total volume of a ratio between 40 to 80%, in particular between the 60 to 80%, more in particular around 75% (e.g. between 70 and 80%) of the entire volume of the electrically insulating layer structure. Such a high amount of fillers may provide a high stability (in particular against warpage) and better electrical performance in term of the dielectric property (low loss, high frequency), and may be for example fulfilled by an ABF. The high amount of fillers may further increase the adhesion, since more and smaller spaces between the exposed fillers are provided. Thereby, the material of the further electrically insulating layer structure may adhere to more exposed surfaces, hence increasing the overall stability.

[0028] According to a further embodiment, the further electrically insulating layer structure comprises a (further) main material having further fillers (similar or different from the fillers) embedded therein. Thereby, the stability advantages may also be provided to the further electrically insulating layer structure. Further, the fillers of the further electrically insulating layer might also move downwards to the electrically insulating layer (e.g. ABF) during processing (e.g. with heat press). Therefore the fillers of the two layers might merge into with each other in the interface of two layers.

[0029] According to a further embodiment, said further fillers occupy a total volume ratio in the further electrically insulating layer structure that is (equal or) lower (e.g. 75 % or more, in particular 80% or more) than the total volume ratio occupied by the fillers in the electrically insulating layer structure. In other words, the further fillers are smaller and / or there is a lower number of further fillers than fillers. This may provide the advantage that more of the further main material is present and may infiltrate the spaces between the fillers even more efficiently to fulfill the anchor functionality. In an example, the fillers can move towards the further insulating material easier during the processing |like hot press| and merge more into the further insulating material to have better adhesion of two layers. According to a further embodiment, the main surface electrically insulating layer structure (and / or the further electrically insulating layer structure) comprises a surface with a roughness at least partially defined by peaks and / or by valleys or by the variation of surface flatness from point to point. In particular, the peaks are realized by exposed fillers, while the valleys are spaces in between the exposed fillers, exposing the external surface of the main material (matrix). Such a peak-and-valley (rough) surface may enable efficient intrusion of further main material into the valleys to increase the adhesion. This process may be comparable to a rough metal (copper) surface that may enable the adhesion of an insulating material within the valleys.

[0030] According to a further embodiment, undercuts are formed in some of said valleys (the spaces in between). In this context the term "undercut" may particularly refer to a region at the interface of the electrically insulating layer structures that is located in the vertical direction (z, along the stack thickness direction) in between a filler and the main material of the electrically insulating layer structure. In other words, the undercut may be a space between exposed filler and associated main material external surface. In an embodiment, said undercut is filled with (further main) material of the further electrically insulating layer structure. This may provide the advantage that the adhesion (in particular the anchor functionality of the further electrically insulating layer structure material) is further enhanced. Such an undercut structure may be obtained on purpose, for example by selecting specific shapes of the fillers or by increasing the exposure of fillers (e.g. by a desmear process).

[0031] According to a further embodiment, the material of the further electrically insulating layer structure, embedded in the spaces between the exposed fillers, is (at least) partially embedded in the undercuts (see above).

[0032] According to a further embodiment, the further electrically insulating layer structure can be formed by ink, wherein the ink is coated or screened on the electrically insulating material (e.g. the ABF layer). In particular, by the coating or screening, the ink can be (fully) filled in the spaces between the exposed fillers, e.g. by rolled coating or screen printing. According to a further embodiment, the component carrier comprises an interface penetration between the electrically insulating layer structure and the further electrically insulating layer structure, in particular wherein at least one interface penetration structure (at the interface penetration) is at least 50 nm, in particular at least 300 nm, more in particular at least 600 nm.

[0033] According to a further embodiment, the interface penetration is formed between the two electrically insulating layer structures after the application of temperature / pressure (e.g. hot press; lamination) on the further insulating material. Such an interface penetration can be formed e.g. when heat is applied on the further insulating material, when the material is laminated on the insulating material. Hereby, the fillers in the two electrically insulating layer structures are moved towards each other and the resin of said layer structures is merged together due to the force and the counter force in the (vacuum) lamination to the two materials.

[0034] According to a further embodiment, the exposed fillers and the embedded material (in the spaces) are configured to avoid the detachment of the electrically insulating layer structure and the further electrically insulating layer structure in a non-destructive manner (avoiding e.g. delamination).

[0035] According to a further embodiment, the fillers comprise non-fibrous fillers, in particular filler particles, more in particular with a spherical and / or oval shape. In an example, diameters of the fillers can be in a range 0.1 pm to 5 pm, in particular 0.5 to 5 pm. In comparison to fibrous fillers, non-fibrous fillers (e.g. spherical particles) may enable a higher flexibility (bendability) of the electrically insulating layer structure. Furthermore, non-fibrous particles may enable an improved surface adhesion for the (further main) material of the further electrically insulating layer structure.

[0036] According to a further embodiment, the fillers have a diameter in a range from 10 nm to 15 pm. This range may be especially efficient for stabilizing the insulating material, yet allowing a certain flexibility / bendability. In an example, depending on the molding (matrix) material, the maximum filler size may be around 10 pm or a bit higher. Considering nanofiller ABF, the filler size range may be in the range 10 nm to 15 pm. According to a further embodiment, the main surface comprises a surface with a roughness at least partially defined by rounded peaks and / or by rounded valleys. In an example, at least 70%, in particular at least 80%, more in particular at least 95%, of the surface is defined by rounded peaks and / or by rounded valleys. The rounded peaks may be realized by round (in particular spherical) filler particles. Rounded valleys may be formed during a treatment (e.g. desmear) process and / or by fallen-out of round filler particles that leave a round valley behind. The round shapes at the main surface may improve the adhesion of the further electrically insulating layer structure.

[0037] According to a further embodiment, the material of the further electrically insulating layer structure, embedded in the spaces between the exposed fillers, is located in a depth within the range between 50 nm and 700 nm along the thickness direction (z) of the stack. Such a depth may enable an especially robust interconnection and adhesion.

[0038] According to a further embodiment, the main surface of the electrically insulating layer structure comprises a roughness higher than the roughness of the opposed main surface. In other words, the size / shape / number of fillers at the main surfaces is different. For example, the further electrically insulating layer structure may comprise no fillers or less fillers or smaller fillers than the electrically insulating layer structure. Thereby, the roughness, in particular peak-and-valley structure, of the surfaces may be different. By providing a lower roughness for the further electrically insulating layer structure, intrusion of material into the spaces between exposed fillers may be improved.

[0039] According to a further embodiment, the exposed fillers result in protrusions merging from the electrically insulating layer structure and extending away from the main surface of the electrically insulating layer structure. Thereby, the protruding fillers may be located deep into further material of the further electrically insulating layer structure, and thus enhance the anchor functionality at the interface.

[0040] According to a further embodiment, the protrusions extend along a straight direction, in particular a direction perpendicular to the orientation of the main surface (i.e. along the vertical z direction). Also in this manner, the anchor functionality at the interface may be enhanced. According to a further embodiment, the material of the electrically insulating layer structure comprises organic material, in particular epoxy resin. Thus, established and industrially highly relevant materials and their manufacturing processes may be directly implemented.

[0041] According to a further embodiment, the filler comprises or consists of inorganic material (for example ceramic or silicon / glass). In this manner, established and highly reliable materials (and their manufacture proceses9 may be directly applied.

[0042] The fillers comprise silicon dioxide or other (combined compound of) inorganic material (the inorganic filler may be used alone or in combination with two or more kinds at an arbitrary ratio, with which the thermal expansion coefficient of the cured material obtained by curing the resin composition can be reduce and warpage can be controlled). The filler particles can get the depth of the recessed portion of the polishing surface of resin smaller and get the dielectric loss tangent of a cured material obtained by curing the resin composition reduced. Additionally, it may help to reduce the tensile elastic modulus of the cured material. Moreover, the filler particles may be preferably surface-treated with a suitable surface treatment as the surface treatment can suppress the aggregation of the particles of the filler or the detachment of the particles of the filler from the polished surface and it may get a better uniformity on the resin sheet surface and improve the moisture resistance and dispersibility of the particle fillers. The surface treatment can also help modify the property of material surface for better adhesion between the two different layers. Said material may efficiently stabilize the insulating material but leads to drawbacks in the desmear etching process (see above) and the filler with different material inside or different shape or even different size will impact the dielectric property of the insulating material regarding the electrical performance. However, by treating the exposed surface portions of the silicon dioxide fillers and the insulating material together (in particular by laser ablation), the advantages of high stabilisation and surface roughness conformity can be combined. In a further embodiment, the filler may comprise a conductive particle, e.g. inside is plastic, outside coated with conductive metal such as gold, nickel, etc.

[0043] According to a further embodiment, the (further main material of the) further electrically insulating layer structure comprises organic material, in particular epoxy resin. More in particular, the organic material (e.g. epoxy resin) is embedded between the spaces of the protrusions (exposed filler particles). Preferably, the organic materials of the two electrically insulating layer structures are different (or similar). A resin material may be at least partially viscous during a lamination process, so that the further main material may be provided in an easy but efficient manner into the spaces between the protruding fillers.

[0044] According to a further embodiment, the further electrically insulating layer structure comprises or consists of a photosensitive layer. Thereby, a structuring / patterning of said layer may be enabled in an established manner. For example, the further electrically insulating layer structure may function as a solder resist layer and should hence be patterned so cover only specific region of the component carrier surface.

[0045] According to a further embodiment, the electrically insulating layer structure is a layer of a (component carrier layer stack) built-up structure and / or wherein the further electrically insulating layer structure is an external surface layer, in particular a solder resist and / or a surface finishing layer. Such an external surface layer may be important for component carrier protection, so that the described enhanced adhesion may be highly favourable.

[0046] According to a further embodiment, the treatment of the main surface of the electrically insulating layer structure comprises a desmear treatment. This established process may improve the main surface quality. In particular, the exposed filler particles may protrude even more out of the matrix material after a desmear process.

[0047] In the context of the present document, the term "desmear process / treatment" may particularly denote a process in a component carrier manufacture that applies a desmear operation, i.e. a surface cleaning and / or roughening of a component carrier preform. In particular, resin surfaces and bore holes may be cleaned and surfaces may be roughened to improve adhesion properties. The desmear process may comprise wet desmear and / or dry desmear. The wet desmear uses the chemistry treating the surface and the dry desmear might use gas attacking the surface.

[0048] According to a further embodiment, the treatment of the main surface of the electrically insulating layer structure comprises plasma treatment, in particular after the desmear of said main surface (and before a lamination of the further electrically insulating layer structure). Said plasma treatment may be performed according to established procedures and may preferably improve surface adhesion of the exposed fillers by treating the filler surfaces.

[0049] According to a further embodiment, the treatment of the main surface of the electrically insulating layer structure comprises excimer treatment. With the excimer treatment, the roughness of the insulating material surface can achieve a better uniformity or it can obtain desired roughness by the predesigned mask applied with the excimer. Additionally the protrusion of fillers inside of the insulating material can be controlled with requirement and the penetration with the further insulating material might be predetermined. Therefore the adhesion between the two layers can be improved significantly.

[0050] In an embodiment, the component carrier is shaped as a plate. This contributes to the compact design, wherein the component carrier nevertheless provides a large basis for mounting components thereon. Furthermore, in particular a naked die as example for an embedded electronic component, can be conveniently embedded, thanks to its small thickness, into a thin plate such as a printed circuit board.

[0051] In an embodiment, the component carrier is configured as one of the group consisting of a printed circuit board, a substrate (in particular an IC substrate), and an interposer.

[0052] In the context of the present application, the term "printed circuit board" (PCB) may particularly denote a plate-shaped component carrier which is formed by laminating several electrically conductive layer structures with several electrically insulating layer structures, for instance by applying pressure and / or by the supply of thermal energy. As preferred materials for PCB technology, the electrically conductive layer structures are made of copper, whereas the electrically insulating layer structures may comprise for example resin and / or glass fibers, so-called prepreg or FR4 material, PID, or ABF. The various electrically conductive layer structures may be connected to one another in a desired way by forming holes through the laminate, for instance by laser drilling or mechanical drilling, and by partially or fully filling them with electrically conductive material (in particular copper), thereby forming vias or any other through-hole connections. The filled hole either connects the whole stack, (through-hole connections extending through several layers or the entire stack), or the filled hole connects at least two electrically conductive layers, called via. Similarly, optical interconnections can be formed through individual layers of the stack in order to receive an electro- optical circuit board (EOCB). Apart from one or more components which may be embedded in a printed circuit board, a printed circuit board is usually configured for accommodating one or more components on one or both opposing surfaces of the plate-shaped printed circuit board. They may be connected to the respective main surface by soldering. A dielectric part of a PCB may be composed of resin with reinforcing fibers (such as glass fibers).

[0053] In the context of the present application, the term "substrate" may particularly denote a small component carrier. A substrate may be a, in relation to a PCB, comparably small component carrier onto which one or more components may be mounted and that may act as a connection medium between one or more chip(s) and a further PCB. For instance, a substrate may have substantially the same size as a component (in particular an electronic component) to be mounted thereon (for instance in case of a Chip Scale Package (CSP)). In another embodiment, the substrate may be substantially larger than the assigned component (for instance in a flip chip ball grid array, FCBGA, configuration). More specifically, a substrate can be understood as a carrier for electrical connections or electrical networks as well as component carrier comparable to a printed circuit board (PCB), however with a considerably higher density of laterally and / or vertically arranged connections. Lateral connections are for example conductive paths, whereas vertical connections may be for example drill holes. These lateral and / or vertical connections are arranged within the substrate and can be used to provide electrical, thermal and / or mechanical connections of housed components or unhoused components (such as bare dies), particularly of IC chips, with a printed circuit board or intermediate printed circuit board. Thus, the term "substrate" also includes "IC substrates". A dielectric part of a substrate may be composed of resin with reinforcing particles (such as reinforcing spheres, in particular glass spheres).

[0054] The substrate or interposer may comprise or consist of at least a layer of glass, silicon (Si) and / or a photoimageable or dry-etchable organic material like epoxy-based build-up material (such as epoxy-based build-up film) or polymer compounds (which may or may not include photo- and / or thermosensitive molecules) like polyimide or polybenzoxazole.

[0055] In an embodiment, the at least one electrically insulating layer structure comprises at least one of the group consisting of a resin or a polymer, such as epoxy resin, cyanate ester resin, benzocyclobutene resin, bismaleimide-tria- zine resin, polyphenylene derivate (e.g. based on polyphenylenether, PPE), polyimide (PI), polyamide (PA), liquid crystal polymer (LCP), polytetrafluoroethylene (PTFE) and / or a combination thereof. Reinforcing structures such as webs, fibers, spheres or other kinds of filler particles, for example made of glass (multilayer glass) in order to form a composite, could be used as well. A semi-cured resin in combination with a reinforcing agent, e.g. fibers impregnated with the above-mentioned resins is called prepreg. These prepregs are often named after their properties e.g. FR4 or FR5, which describe their flame retardant properties. Although prepreg particularly FR4 are usually preferred for rigid PCBs, other materials, in particular epoxy-based build-up materials (such as build-up films) or photoimageable dielectric materials, may be used as well. For high frequency applications, high-frequency materials such as polytetrafluoroethylene, liquid crystal polymer and / or cyanate ester resins, may be preferred. Besides these polymers, low temperature cofired ceramics (LTCC) or other low, very low or ultra-low DK materials may be applied in the component carrier as electrically insulating structures.

[0056] In an embodiment, the at least one electrically conductive layer structure comprises at least one of the group consisting of copper, aluminum, nickel, silver, gold, palladium, tungsten, magnesium, carbon, (in particular doped) silicon, titanium, and platinum. Although copper is usually preferred, other materials or coated versions thereof are possible as well, in particular coated with supra-conductive material or conductive polymers, such as graphene or poly(3,4-ethylenedioxythiophene) (PEDOT), respectively.

[0057] At least one further component may be embedded in and / or surface mounted on the stack. The component and / or the at least one further component can be selected from a group consisting of an electrically non-conductive inlay, an electrically conductive inlay (such as a metal inlay, preferably comprising copper or aluminum), a heat transfer unit (for example a heat pipe), a light guiding element (for example an optical waveguide or a light conductor connection), an electronic component, or combinations thereof. An inlay can be for instance a metal block, with or without an insulating material coating (IMS-inlay), which could be either embedded or surface mounted for the purpose of facilitating heat dissipation. Suitable materials are defined according to their thermal conductivity, which should be at least 2 W / mK. Such materials are often based, but not limited to metals, metal-oxides and / or ceramics as for instance copper, aluminium oxide (AI2O3) or aluminum nitride (AIN). In order to increase the heat exchange capacity, other geometries with increased surface area are frequently used as well. Furthermore, a component can be an active electronic component (having at least one p-n-junction implemented), a passive electronic component such as a resistor, an inductance, or capacitor, an electronic chip, a storage device (for instance a DRAM or another data memory), a filter, an integrated circuit (such as field-programmable gate array (FPGA), programmable array logic (PAL), generic array logic (GAL) and complex programmable logic devices (CPLDs)), a signal processing component, a power management component (such as a field-effect transistor (FET), metal- oxide-semiconductor field-effect transistor (MOSFET), complementary metal- oxide-semiconductor (CMOS), junction field-effect transistor (JFET), or insulated-gate field-effect transistor (IGFET), all based on semiconductor materials such as silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), gallium oxide (Ga2O3), indium gallium arsenide (InGaAs), indium phosphide (InP) and / or any other suitable inorganic compound), an optoelectronic interface element, a light emitting diode, a photocoupler, a voltage converter (for example a DC / DC converter or an AC / DC converter), a cryptographic component, a transmitter and / or receiver, an electromechanical transducer, a sensor, an actuator, a microelectromechanical system (MEMS), a microprocessor, a capacitor, a resistor, an inductance, a battery, a switch, a camera, an antenna, a logic chip, and an energy harvesting unit. However, other components may be embedded in the component carrier. For example, a magnetic element can be used as a component. Such a magnetic element may be a permanent magnetic element (such as a ferromagnetic element, an antiferromagnetic element, a multiferroic element or a ferrimagnetic element, for instance a ferrite core) or may be a paramagnetic element. However, the component may also be a IC substrate, an interposer or a further component carrier, for example in a board-in-board configuration. The component may be surface mounted on the component carrier and / or may be embedded in an interior thereof. Moreover, also other components, in particular those which generate and emit electromagnetic radiation and / or are sensitive with regard to electromagnetic radiation propagating from an environment, may be used as component.

[0058] In an embodiment, the component carrier is a laminate-type component carrier. In such an embodiment, the component carrier is a compound of multiple layer structures which are stacked and connected together by applying a pressing force and / or heat.

[0059] After processing interior layer structures of the component carrier, it is possible to cover (in particular by lamination) one or both opposing main surfaces of the processed layer structures symmetrically or asymmetrically with one or more further electrically insulating layer structures and / or electrically conductive layer structures. In other words, a build-up may be continued until a desired number of layers is obtained.

[0060] After having completed formation of a stack of electrically insulating layer structures and electrically conductive layer structures, it is possible to proceed with a surface treatment of the obtained layers structures or component carrier.

[0061] In particular, an electrically insulating solder resist may be applied to one or both opposing main surfaces of the layer stack or component carrier in terms of surface treatment. For instance, it is possible to form such a solder resist on an entire main surface and to subsequently pattern the layer of solder resist so as to expose one or more electrically conductive surface portions which shall be used for electrically coupling the component carrier to an electronic periphery. The surface portions of the component carrier remaining covered with solder resist may be efficiently protected against oxidation or corrosion, in particular surface portions containing copper.

[0062] It is also possible to apply a surface finish selectively to exposed electrically conductive surface portions of the component carrier in terms of surface treatment. Such a surface finish may be an electrically conductive cover material on exposed electrically conductive layer structures (such as pads, conductive tracks, etc., in particular comprising or consisting of copper) on a surface of a component carrier. If such exposed electrically conductive layer structures are left unprotected, then the exposed electrically conductive component carrier material (in particular copper) might oxidize, making the component carrier less reliable. A surface finish may then be formed for instance as an interface between a surface mounted component and the component carrier. The surface finish has the function to protect the exposed electrically conductive layer structures (in particular copper circuitry) and enable a joining process with one or more components, for instance by soldering. Examples for appropriate materials for a surface finish are Organic Solderability Preservative (OSP), Electroless Nickel Immersion Gold (ENIG), Electroless Nickel Immersion Palladium Immersion Gold (ENIPIG), Electroless Nickel Electroless Palladium Immersion Gold (ENEPIG), gold (in particular hard gold), chemical tin (chemical and electroplated), nickel-gold, nickel-palladium, etc. Also nickel-free materials for a surface finish may be used, in particular for high-speed applications. Examples are ISIG (Immersion Silver Immersion Gold), and EPAG (Eletroless Palladium Autocatalytic Gold). Brief Description of the Drawings

[0063] The aspects defined above and further aspects of the invention are apparent from the examples of embodiment to be described hereinafter and are explained with reference to these examples of embodiment.

[0064] Figure 1 shows a cross-section through a component carrier according to an exemplary embodiment of the invention.

[0065] Figure 2 shows a microscopic image of the interface of the component carrier according to an exemplary embodiment of the invention.

[0066] Figures 3A to 3C show a method of manufacturing the component carrier according to an exemplary embodiment of the invention.

[0067] Figures 4A and 4B respectively show a conventional interface of a circuit board.

[0068] Figures 5A, 5B, and 6 respectively show detailed microscopic image of the interface of the component carrier according to an exemplary embodiment of the invention.

[0069] Detailed Description of the Drawings

[0070] The illustrations in the drawings are schematic. In different drawings, similar or identical elements are provided with the same reference signs.

[0071] Figure 1 shows a component carrier 100 according to an exemplary embodiment of the invention. The component carrier 100 comprises a stack 101 with a plurality of electrically insulating layer structures 110, 120 (in this example two layers are shown) and at least one electrically conductive layer structure 104 (in this example arranged below the insulating layer structures 110, 120).

[0072] The lower electrically insulating layer structure 110 comprises a main material 112 having fillers 111 embedded therein. In this example, the fillers 111 are filler particles that are non-homogenously distributed in the main material (the matrix) 112. The fillers 111 are non-fibrous fillers with a spherical and / or oval shape .The fillers 111 occupy a total volume of a ratio between 40 to 80% of the entire volume of the electrically insulating layer structure 110.

[0073] A further (the upper) electrically insulating layer structure 120 is provided on the upper main surfaces 115 of the (lower) electrically insulating layer structure 110 and comprises a further main material 122 with further fillers 121 embedded therein. Said further fillers 121 occupy a total volume ratio in the further electrically insulating layer structure 120 that is lower than the total volume ratio occupied by the fillers 111 in the electrically insulating layer structure 110. In other words, the electrically insulating layer structure

[0074] 110 comprises more (regarding size may be larger, smaller, or the same) fillers than the further electrically insulating layer structure 120.

[0075] In between the electrically insulating layer structures 110, 120, there is an interface region 150, extending in the horizontal direction (x, y plane), perpendicular to the stacking direction (z).

[0076] On the main surface 115, being at the interface region 150, the fillers

[0077] 111 of the (lower) electrically insulating layer structure 110 are exposed, i.e. extend / protrude beyond the main surface 115 of the main material 112. Hereby, a part of the main material 122 of the further electrically insulating layer structure 120 is embedded in the spaces between the exposed fillers 111 of the (lower) electrically insulating layer structure 110. In another wording, exposed fillers 111 of the electrically insulating layer structure 110 extend / protrude into the further electrically insulating layer structure 120, while further fillers 121 of the further electrically insulating layer structure 120 extend / protrude into the electrically insulating layer structure 110.

[0078] The further electrically insulating layer structure 120 adheres with the electrically insulating layer structure 110 through the material 122 of said further electrically insulating layer structure 120 embedded in the spaces between the exposed fillers 111. In other words, further matrix material 122 adheres to the exposed surfaces of the fillers 111, while matrix material 112 adheres to the exposed surfaces of the further fillers 121.

[0079] In this design, the exposed fillers 111 and the embedded further material 122 are configured to avoid the detachment of the electrically insulating layer structure 110 and the further electrically insulating layer structure 120 in a non-destructive manner.

[0080] For example, at least 75% of the surface of the further material 122 of the further electrically insulating layer structure 120, adhering with the main surface 115 of the electrically insulating layer structure 110, is in contact with the exposed surface of the fillers 111.

[0081] It is schematically shown that the main surface 115 comprises a surface with a roughness at least partially defined by (rounded) peaks and / or by (rounded) valleys, and wherein undercuts 130 (see also Figure 5B) are formed in some of said valleys. It follows that further material 122 of the further electrically insulating layer structure 120, which is embedded in the spaces between the exposed fillers 111, is partially embedded in the undercuts 130.

[0082] The material 122 of the further electrically insulating layer structure 120 is embedded in the spaces between the exposed fillers 111 in a depth within the range between 50 and 700 nm along the thickness direction (z) of the stack 101. The main surface 115 of the electrically insulating layer structure 110 comprises a roughness higher than the roughness of the opposed main surface (lower main surface of further electrically insulating layer structure 120). In other words, there are more / larger fillers 111 than further fillers 121. The exposed fillers 111 result in protrusions merging from the electrically insulating layer structure 110 and extending away from the main surface 115 of the electrically insulating layer structure 110, wherein the protrusions extend along a straight direction perpendicular to the orientation of the main surface 115.

[0083] In this example, the material 112 of the electrically insulating layer structure 110 comprises epoxy resin, while the fillers 111 comprise inorganic material. The further electrically insulating layer structure 120 comprises a photosensitive layer. The electrically insulating layer structure 110 is a layer of a (layer stack) built-up structure and the further electrically insulating layer structure 120 is a solder resist and / or a surface finishing layer.

[0084] Figure 2 shows a microscopic image of the interface 150 between the electrically insulating layer structure 110 and the further electrically insulating layer structure 120 of the component carrier according to an exemplary embodiment of the invention. In comparison to the conventional example (see Figures 4A and 4B), there is no delamination and no gap (black line) visible at the interface 150 between the electrically insulating layer structure 110 and the further electrically insulating layer structure 120.

[0085] Figures 3A to 3C show a method of manufacturing the component carrier 100 according to an exemplary embodiment of the invention.

[0086] Figure 3A: there is provided the electrically insulating layer structure 110 which comprises a matrix material 112 with embedded fillers 111, in this example an Ajinomoto build-up film with SiO? filler particles. At the upper main surface 115, fillers 111 are exposed and protrude beyond the matrix material 112 external surface. In particular after a desmear treatment, the protrusion of the exposed fillers is even more pronounced. With such kind of situation, there will be bad adhesion between the insulating material and further insulating material. Afterwards the delamination between the two layers would happen in a following process, especially for those products which apply the low Dk and Df dielectric material with high volume of fillers for high performance computing application.

[0087] Figure 3B: the treatment of the main surface 115 of the electrically insulating layer structure 110 comprises a plasma treatment 160, which is performed after the desmear treatment of said main surface 115. The property of the surface might be changed to improve the adhesion of the two layers due to the chemical bonding feature being formed.

[0088] Figure 3C: after the plasma treatment 160, the further electrically insulating layer structure 120 is formed (laminated) on top of the main surface 115. Thereby, an interface 150 is formed at the main surface 115, whereby the exposed fillers 111 of the electrically insulating layer structure 110 protrude into the further electrically insulating layer structure 120, and wherein (matrix) material 122 of the further electrically insulating layer structure 120 is embedded in the spaces between the exposed fillers 111.

[0089] Figures 5A and 5B show detailed microscopic images of the interface 150 of the component carrier 100 according to an exemplary embodiment of the invention, wherein Figure 5B is a detailed view of a specific region of Figure 5A. Indicated in the detailed view are undercut 130 structures that are formed from material 122 of the further electrically insulating layer structure

[0090] 120 that is formed below a portion of a filler particle of the electrically insulating layer structure 110.

[0091] Figure 6 shows a detailed microscopic image of the interface 150 of the component carrier 100 according to an exemplary embodiment of the invention. As an exemplary example, some distances between filler particles 111 of the electrically insulating layer structure 110 and further filler particles

[0092] 121 of the further electrically insulating layer structure 120 are indicated (from left to right): 354 nm, 472 nm, 389 nm, 129 nm, and 366 nm.

[0093] Reference signs

[0094] 100 Component carrier

[0095] 101 Stack

[0096] 104 Electrically conductive layer structure

[0097] 110 Electrically insulating layer structure

[0098] 111 Filler

[0099] 112 Electrically insulating layer structure material, matrix

[0100] 115 Main surface

[0101] 120 Further electrically insulating layer structure

[0102] 121 Further filler

[0103] 122 Further electrically insulating layer structure material, matrix

[0104] 130 Undercut

[0105] 150 Interface

[0106] 160 Plasma treatment

[0107] 200 Conventional circuit board

[0108] 250 Conventional interface

[0109] 251 Conventional delamination

Claims

Claims1. A component carrier (100), wherein the component carrier (100) comprises: a stack (101) comprising a plurality of electrically insulating layer structures (110, 120) and at least one electrically conductive layer structure (104), wherein at least one of said electrically insulating layer structures (110) comprises a main material (112) having fillers (111) embedded therein, wherein a further one of said electrically insulating layer structures (120) is provided on one of the main surfaces (115) of the at least one electrically insulating layer structure (110), and wherein, on said main surface (115), at least a part of the fillers (111) of the electrically insulating layer structure (110) are exposed, and wherein material (122) of the further electrically insulating layer structure (120) is embedded in the spaces between the exposed fillers (111).

2. The component carrier (100) according to claim 1, wherein the further electrically insulating layer structure (120) adheres with the electrically insulating layer structure (110) through the material (122) of said further electrically insulating layer structure (120) embedded in the spaces between the exposed fillers (111).

3. The component carrier (100) according to any of claims 1 to 2, wherein at least 50%, in particular at least 75% of the surface of the material (122) of the further electrically insulating layer structure (120), adhering with the main surface (115) of the electrically insulating layer structure (110), is in contact with the exposed surface of the fillers (111).

4. The component carrier (100) according to any of claims 1 to 3, wherein the fillers (111) occupy a total volume of a ratio between 40 to 80%, in particular between the 60 to 80%, of the entire volume of the electrically insulating layer structure (110).

5. The component carrier (100) according to any of claims 1 to 4, wherein the the further electrically insulating layer structure (120) comprises a main material (122) having further fillers (121) embedded therein, in particular said further fillers (121) occupy a total volume ratio in the further electrically insulating layer structure (120) that is lower than the total volume ratio occupied by the fillers (111) in the electrically insulating layer structure (110).

6. The component carrier (100) according to any of claims 1 to 5, wherein the main surface (115) comprises a surface with a roughness at least partially defined by peaks and / or by valleys.

7. The component carrier (100) according to claim 6, wherein undercuts (130) are formed in some of said valleys.

8. The component carrier (100) according to claim 7, wherein the material (122) of the further electrically insulating layer structure (120) embedded in the spaces between the exposed fillers (111) is partially embedded in the undercuts (130).

9. The component carrier (100) according to any of claims 6 to 8, wherein the exposed fillers (111) and the embedded material (122) are configured to avoid the detachment of the electrically insulating layer structure (110) and the further electrically insulating layer structure (120) in a nondestructive manner.

10. The component carrier (100) according to any of claims 1 to 9, wherein the fillers (111) comprise non-fibrous fillers, in particular filler particles, more in particular with a spherical and / or oval shape; and / or wherein a least a part of the fillers (111) comprise a diameter in the range 0.1 pm to 5 pm, in particular 0.5 pm to 5 pm.

11. The component carrier (100) according to claim 10, wherein the main surface (115) comprises a surface with a roughness at least partially defined by rounded peaks and / or by rounded valleys.

12. The component carrier (100) according to any of claims 1 to 11, wherein the material (122) of the further electrically insulating layer structure (120) in embedded in the spaces between the exposed fillers (111) in a depth within the range between 50 nm and 700 nm along the thickness direction (z) of the stack (101).

13. The component carrier (100) according to any of claims 1 to 12, wherein the main surface (115) of the electrically insulating layer structure (110) comprises a roughness higher than the roughness of the opposed main surface.

14. The component carrier (100) according to any of claims 1 to 13, wherein the exposed fillers (111) result in protrusions merging from the electrically insulating layer structure (110) and extending away from the main surface (115) of the electrically insulating layer structure (110).

15. The component carrier (100) according to claim 14, wherein the protrusions extend along a straight direction, in particular a direction perpendicular to the orientation of the main surface (115).

16. The component carrier (100) according to any of claims 1 to 15, wherein the material (112) of the electrically insulating layer structure (110) comprises organic material, in particular epoxy resin.

17. The component carrier (100) according to any of claims 1 to 16, wherein the filler (111) comprises or consists of inorganic material.

18. The component carrier (100) according to any of claims 1 to 17, wherein the further electrically insulating layer structure (120) comprises organic material, in particular epoxy resin.

19. The component carrier (100) according to any of claims 1 to 18, wherein the further electrically insulating layer structure (120) comprises or consists of a photosensitive layer.

20. The component carrier (100) according to any of claims 1 to 19, wherein the electrically insulating layer structure (110) is a layer of a built-up structure and / or wherein the further electrically insulating layer structure (120) is a solder resist and / or a surface finishing layer.

21. The component carrier (100) according to any of claims 1 to 20, further comprising: an interface penetration between the electrically insulating layer structure (110) and the further electrically insulating layer structure (120), in particular wherein at least one interface penetration structure is at least 50 nm, in particular at least 300 nm, more in particular at least 600 nm.

22. A method of manufacturing a component carrier (100) comprising a stack (101) comprising a plurality of electrically insulating layer structures (110, 120) and at least one electrically conductive layer structure (104), the method comprising: providing at least one of said electrically insulating layer structures (110) comprising a main material (112) having fillers (111) embedded therein; providing a further electrically insulating layer structure (120), wherein one of the main surfaces (115) of the electrically insulating layer structure (110) is treated so that the fillers (111) are at least partially exposed; and providing the further electrically insulating layer structure (120) on said main surface (115) of the electrically insulating layer structure (110),so that material (122) of the further electrically insulating layer structure (120) is embedded in the spaces between the exposed fillers (111).

23. The method according to claim 22, wherein the treatment of the main surface (115) of the electrically insulating layer structure (110) comprises a desmear treatment.

24. The method according to any of claims 22 to 23, wherein the treatment of the main surface (115) of the electrically insulating layer structure (110) comprises plasma treatment, in particular after the desmear treatment of said main surface (115).

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