Methods and apparatus providing multiplexed output signals from single photon detectors

Abstract

Output signals from plural single photon detectors such as superconducting nanowire single photon detectors are delivered to a time-resolved measurement system together with delayed versions of the output signals in a combined output signal. Output signals from different photon detectors are delayed by different amounts. The time differences between original and delayed output signals indicates the photon detectors at which photons were detected. The combined signal made up of output signals from plural photon detectors may be carried in a single signal conductor.

Description

METHODS AND APPARATUS PROVIDING MULTIPLEXED OUTPUT SIGNALS FROM SINGLE PHOTON DETECTORSCross-Reference to Related Application

[0001] This application claims priority from US application No. 63 / 585704 filed 27 September 2023 entitled METHODS AND APPARATUS PROVIDING MULTIPLEXED OUTPUT SIGNALS FROM SINGLE PHOTON DETECTORS which is hereby incorporated herein by reference for all purposes. For purposes of the United States of America, this application claims the benefit under 35 U.S.C. §119 of US application No. 63 / 585704 filed 27 September 2023 entitled METHODS AND APPARATUS PROVIDING MULTIPLEXED OUTPUT SIGNALS FROM SINGLE PHOTON DETECTORS which is hereby incorporated herein by reference for all purposes.Field

[0002] The present technology relates to photon detectors. Specific embodiments provide methods and apparatus for multiplexing outputs of plural superconducting nanowire single photon detectors (SNSPDs).Background

[0003] There are various applications in which it is desirable to detect single photons. For example, certain designs of apparatus for manipulating quantum information may include a large number of single photon detectors. Such apparatus is typically operated at cryogenic temperatures to reduce the rate of decoherence of stored quantum information.

[0004] A Superconducting Nanowire Single Photon Detector (SNSPD) is one type of single photon detector. SNSPDs have applications in quantum computing, scientific research, extremely low light imaging and other fields. SNSPDs may be constructed to have high efficiency, high photon count rate, low dark count rate and low timing jitter.

[0005] A SNSPD includes an element that carries a bias current. The element is typically in the form of a nanowire that is made of a material that is superconducting at temperatures below a critical temperature. The SNSPD is operated at temperatures that are below the critical temperature so that the element is normally superconducting. SNSPDs are generally operated at cryogenic temperatures that areclose to absolute zero (0 Kelvin).

[0006] Absorption of a photon can cause a portion of the element to become non- superconducting, thereby causing the element to exhibit an electrical resistance. This causes a voltage drop across the element. The voltage drop serves as an output signal that indicates the detection of a photon.

[0007] Maintaining components of an apparatus at very low temperatures requires good thermal isolation of the components. In many cases it is necessary to provide electrical conductors for carrying electrical signals and / or electrical power to or from components in a cryogenic system. Unfortunately, most materials that are good electrical conductors are also good conductors of heat. For efficient cooling to cryogenic temperatures there is a general desire to limit the number of electrical conductors that extend between a cold part of a cryogenic system and warmer locations.Summary

[0008] This invention has a number of aspects. These aspects include, without limitation: apparatus for detecting photons; methods for detecting photons; methods for combining output signals from plural photon detectors, apparatus for combining output signals from plural photon detectors; and methods and apparatus for processing a combined signal comprising photon detection features from plural photon detectors.

[0009] One aspect of the present invention provides apparatus for photon detection. The apparatus comprises a plurality of photon detectors. Each of the photon detectors is operative to generate a photon detector output signal that indicates photon detections. Each of the plurality of photon detectors is associated with a corresponding delay circuit connected to receive the photon detector output signal from the corresponding photon detector and to present the received output signal at first and second outputs of the delay circuit as first and second differentially delayed output signals respectively. The second differentially delayed output signal is delayed relative to the first differentially delayed output signal by a corresponding delay amount. The delay amounts for the delay circuits corresponding to each of the plurality of photon detectors are different from one another. The apparatus includes one or more signal combiners each operable to combine a plurality of output signals made up of one or more of the first differentially delayed output signals and one ormore of the second differentially delayed output signals into a combined output signal.

[0010] In some embodiments the one or more signal combiners comprises one signal combiner connected to receive, from all of the plurality of delay circuits, the first differentially delayed output signal and the second differentially delayed output signal and to combine all of these first differentially delayed output signals and second differentially delayed output signals into the combined output signal.

[0011] In some embodiments each of the delay circuits comprises: a splitter having an input connected to receive the photon detector output signal from the corresponding photon detector and first and second outputs, each of the splitters operative to present the photon detector output signal received at the input at both of the first and second outputs; and a delay unit connected to receive the photon detector signal presented at the second output of the splitter, delay the photon detector signal, and present the delayed photon detector signal as the second differentially delayed output signal.

[0012] In some embodiments the delay unit comprises a delay line comprising a conductor having a length corresponding to the delay amount.

[0013] In some embodiments the delay amounts associated with each of the delay circuits are in the range of about 10 ps to about 500 ps.

[0014] In some embodiments the photon detectors comprise superconducting nanowire single photon detectors (SNSPDs). In some embodiments the apparatus comprises at least one power supply connected to deliver bias current to each of the SNSPDs, the bias current for each of the SNSPDs being individually settable.

[0015] In some embodiments the delay amounts for the delay circuits corresponding to each of the plurality of photon detectors have a property that none of the delay amounts is equal to the sum of any two other ones of the delay amounts.

[0016] In some embodiments the delay amounts for the delay circuits corresponding to each of the plurality of photon detectors have a property that none of the delay amounts is equal to the sum of any two or more other ones of the delay amounts.

[0017] In some embodiments the apparatus comprises a logic unit configured to receive the combined signal, determine time differences between photon detection features in the combined signal, compare the time differences to the delay amounts, and, based on the comparisons of the time differences to the delay amounts, associate each of the photon detection features with one of the plurality of photon detectors.

[0018] In some embodiments the apparatus comprises a deserializer connected to receive and deserialize the combined signals.

[0019] In some embodiments the delay circuits and one or more signal combiners are made entirely of passive components.

[0020] In some embodiments the apparatus comprises an amplifier connected to amplify the combined signal output by the one or more signal combiners.

[0021] In some embodiments the apparatus comprises a cryogenic cooling system operable to maintain the photon detectors at a first cryogenic temperature. In some embodiments the cryogenic cooling system is operable to maintain the amplifier at a second cryogenic temperature that is higher than the first cryogenic temperature while the photon detectors are being maintained at the first cryogenic temperature.

[0022] Another aspect of the invention provides a photon detection method. The method comprises: receiving output signals from a plurality of photon detectors, for each of the output signals creating a corresponding delayed output signal by delaying the output signal by a delay amount, and combining the output signals and the delayed output signals into a combined signal. The delay amount applied to each of the output signals is different. At least some of the output signals comprise photon detection features.

[0023] In some embodiments the method comprises processing the combined signal to determine time differences between the photon detection features in the combined signal, compare the time differences to the delay amounts, and, based on the comparisons of the time differences to the delay amounts, associate each of the photon detection features with one of the plurality of photon detectors.

[0024] Further aspects and example embodiments are illustrated in the accompanying drawings and / or described in the following description.

[0025] It is emphasized that the invention relates to all combinations of the above features, even if these are recited in different claims.Brief Description of the Drawings

[0026] The accompanying drawings illustrate non-limiting example embodiments of the invention.

[0027] Fig. 1 is a graph that schematically shows an output signal from a photon detector (e.g. a SNSPD) that has detected a photon according to an example embodiment.

[0028] Fig. 1A is a schematic illustration of the relationship of a pulse of a nondelayed output signal and pulses that are delayed by different amounts relative to the pulse of the non-delayed output signal according to an example embodiment.

[0029] Fig. 2 is a flow chart that illustrates a method for providing a combined output signal that incorporates photon detection features from output signals of plural single photon detectors according to an example embodiment.

[0030] Fig. 3 is a block diagram showing an apparatus that comprises a plurality of photon detectors according to an example embodiment.

[0031] Fig. 4 is a schematic drawing showing an apparatus according to another example embodiment.

[0032] Fig. 5 is a schematic drawing showing an apparatus according to another example embodiment.Detailed Description

[0033] Throughout the following description, specific details are set forth in order to provide a more thorough understanding of the invention. However, the invention may be practiced without these particulars. In other instances, well known elements have not been shown or described in detail to avoid unnecessarily obscuring the invention. Accordingly, the specification and drawings are to be regarded in an illustrative, rather than a restrictive sense.

[0034] In general, a single photon detector experiences photon detection events. In each photon detection event, a photon interacts with the single photon detector (e.g. by being absorbed in the detector). As a result of the photon detection event, a photon detection feature (e.g. a pulse) is provided in an output signal of the photon detector.

[0035] Fig. 1 is a graph that schematically shows an output signal from a photon detector (e.g. a SNSPD) that has detected a photon. Detection of a photon results in a photon detection feature 10 in the output signal. In this example, photon detection feature 10 has the form of a pulse that has a leading edge 11A that exhibits a very fast rise time and a trailing edge 11 B that tends to fall more slowly than leading edge 1 1 A rises. Leading edge 11 A corresponds to transition of a part of a superconducting nanowire that becomes non-superconducting in response to absorbing a photon. T railing edge 11 B corresponds to an increase in electrical conductivity of the nanowire as the nanowire cools to the critical temperature at which point the nanowire again becomes superconducting. The decay time of trailing edge 11 B results from acombination of inductance and thermal effects.

[0036] Fig. 2 is a flow chart that illustrates a method 20 according to an example embodiment of the present invention. Method 20 obtains output signals 21-1 , 21-2, ... , 21-N (where N represents an integer and N > 2) from each of a plurality of photon detectors at blocks S21-1 , S21-2, ..., S21-N respectively. At each of blocks S22-1 , S22-2, ... , S22N, a delay is applied to a corresponding one of output signals 21-1 , 21- 2, ..., 21-N to yield a corresponding delayed output signal 22-1 , 22-2, ... , 22-N. The magnitude of the delays (“delay amounts”) are different in each of blocks S22-1 , S22- 2, ..., S22N. In some embodiments, each distinct delay amount is associated with a corresponding photon detector in a one-to-one relationship.

[0037] Fig. 1 A schematically illustrates the relationship of a photon detection feature 10 of a non-delayed output signal and example photon detection features 10A, 10B, 10C and 10D that are delayed by different amounts relative to photon detection feature 10.

[0038] For example, where photon detection feature 10 is a pulse that is output when a first photon detector detects a photon, then the corresponding delayed output signal may include a pulse WA that is delayed by 50 ps relative to pulse 10. Where pulse 10 is output when a second photon detector detects a photon then the corresponding delayed output signal may include a pulse 10B that is delayed by 100 ps relative to pulse 10 and so on. In the following discussion photon detection features are referred to as pulses for ease of reading. However, it should be understood that photon detection features may have other forms.

[0039] Returning to FIG. 2, at block S23, output signals 21-1 , 21-2, ... , 21 -N and delayed output signals 22-1 , 22-2, ..., 22-N are combined into a combined output signal 23.

[0040] At block S24, combined output signal 23 is processed to identify a detector that corresponds to each pulse 10 in combined output signal 23 and the time at which that pulse 10 was emitted. Block S24 may for example, analyze the combined output signal by determining time differences between pairs of pulses 10 in the combined output signal and comparing those time differences to the delay amounts applied at blocks S22-1 , S22-2, ..., S22-N (which correspond to signals originating from photon detectors 1 , 2 ..., N respectively). Where the time difference between two pulses in combined output signal 23 matches one of the delay amounts applied in blocks S22- 1 , S22-2, ..., S22-N then that pair of pulses is identified as a candidate forcorresponding to a photon detected by the photon detector corresponding to the delay amount.

[0041] In some applications, it could be possible that two different photons may be detected (at the same photon detector or different photon detectors) at times that coincidentally differ by one of the delay amounts applied in blocks S22-1 , S22-2, ... , S22-N. In such applications, block S24 may apply logic to identify those pairs of pulses that correspond to the same photon e.g. the time difference between the members of the pair of pulses arises from the delay amount introduced at one of blocks S22-1 , S22-2, ..., S22-N. The logic may exploit the fact that every photon detection corresponds to two pulses in combined signal 23 which are separated in time by a delay amount applied in one of blocks S22-1 , S22-2, ..., S22-N. If two pulses 10 that correspond to different photon detection events are mistakenly identified as belonging to the same photon detection event (e.g. because they coincidentally are separated by a time difference that matches a delay amount applied in one of blocks S22-1 , S22-2, ..., S22-N), then the likely result is that there will be ‘left over’ pulses 10 in combined signal 23 that are not separated from any other unpaired pulse by a delay amount applied in one of blocks S22-1 , S22-2, ... , S22-N. The logic may pair pulses 10 in such a way that the number of paired pulses 10 in combined signal 23 is maximized.

[0042] Block S24 outputs information 24 regarding the timing of photons detected at detectors 1 , 2, ..., N.

[0043] The time delays applied at blocks S22-1 , S22-2, ..., S22-N may be selected to facilitate identifying pairs of pulses 10 in combined signal 23 that correspond to the same photon detection event. For example, the delay amounts may be selected such that:• none of the delay amounts is equal to the sum of any two other ones of the delay amounts (e.g. the delay amounts may correspond to odd numbers) ; or• none of the delay amounts is equal to the sum of any number of the other delay amounts (e.g. the delay amounts may be given by 1 , 3, 5, 7 etc.).

[0044] Fig. 3 is a block diagram showing an apparatus 30 that comprises a plurality of photon detectors according to an example embodiment of the present invention. The apparatus 30 may be operable to implement the method 20, for example. Apparatus 30 includes N photon detectors 32-1 to 32-N (collectively and generally photon detectors 32). Photon detectors 32 may comprise single photon detectors such as, forexample, SNSPDs. In apparatus 30, each of the photon detectors 32 receives a bias current from a corresponding bias current supply 33-1 , 33-2, ..., 33-N (collectively and generally bias current supplies 33).

[0045] Providing a separately settable bias current supply 33 for each photon detector allows the bias current to be optimized for each photon detector 32. Optimizing the bias current for each photon detector may reduce noise and cross-talk, while maintaining detector sensitivity. In other implementations of apparatus 30, each of the photon detectors 32 might not have a separately settable bias current supply 33.

[0046] In the circuit(s) that supply bias currents for photon detectors 32, it is not necessary for photon detectors 32 to be connected in series (although embodiments in which photon detectors 32 are connected in series are possible). Bias current circuit(s) may be configured to connect photon detectors 32 in parallel to carry bias current sourced from one or more power supplies. Apparatus 30 is an example of an embodiment in which photon detectors 32 are connected in parallel.

[0047] Advantages of providing bias current to photon detectors 32 by parallel connected circuits include facilitating independent adjustment of bias current for individual photon detectors 32 and fault tolerance (i.e. a failure of one of one of photon detectors 32 such as an open circuit or excess resistance in a bias current path of the photon detector 32 will not affect operation of other ones of photon detectors 32 that are parallel connected or connected to completely separate bias current supplies).

[0048] Output signals from photon detectors 32 are coupled by suitable couplers 34 (e.g. capacitors) to a corresponding delay circuit 356. Each delay circuit 356 has first and second outputs which respectively carry a first differentially delayed output signal and a second differentially delayed output signal. The second differentially delayed output signal is delayed by a delay amount relative to the first differentially delayed output signal. The delay amount is different for each of delay circuits 356.

[0049] In apparatus 30, each delay circuit 356 includes a signal splitter 35. Signal splitters 35 have two outputs. One copy of the output signal from the corresponding photon detector is present at each of the outputs of the corresponding splitter 35.

[0050] One of the outputs of each splitter 35 is provided to a corresponding delay unit 36 (Fig. 3 shows delay units 36-1 , 36-2, ..., 36-N). Each delay unit 36 delays signals that pass through the delay unit 36 by a corresponding delay amount to yield a delayed output signal. In an example implementation the delay amounts are 50 ps,100 ps, 200 ps, ... . The delay amounts may, for example, be in the range of about 10 ps to about 500 ps.

[0051] In some embodiments, delay units 36 each comprise a delay line comprising a signal conductor that has a length selected such that the time required for a signal to propagate to the end of the signal conductor is equal to the desired delay time. An example implementation of a delay line is a trace on a printed circuit board (PCB). For example, a delay line implemented by a trace of length 25mm on a printed circuit board (PCB) made from FR-4 may delay signals by 170ps. In general, the relationship between delay line length and time delay may depend on the implementation of the delay line.

[0052] Apparatus 30 includes a signal combiner 37 that is connected to receive the second differentially delayed output signals from delay units 36 and to receive the first differentially delayed output signals from signal splitters 35. Signal combiner 37 has an output which carries a combined output signal. In apparatus 30, one signal combiner 37 is connected to receive, from all of the plurality of delay circuits, the first differentially delayed output signal and the second differentially delayed output signal, and to combine all of these first differentially delayed output signals and second differentially delayed output signals into the combined output signal. In other implementations of apparatus 30, one signal combiner may be connected to receive the second differentially delayed output signals from delay units 36 and another signal combiner may be connected to receive the first differentially delayed output signals from signal splitters 35.

[0053] In apparatus 30 the combined output signal is amplified by an amplifier 38. Amplifier 38 may, for example, comprise a low noise operational amplifier. The amplified combined signal output by amplifier 38 is passed to a logic unit 39 which processes the combined output signal to determine which photon detectors detected photons and when those photons were detected.

[0054] Logic unit 39 may, for example process the combined output signal to identify pulses that correspond to photon detection events and to identify pairs of the pulses that are separated by a time that corresponds to the delay amount provided by one of the delay units. That is, the logic unit 39 may determine time differences between the pulses in the combined signal, compare the time differences to the delay amounts, and, based on the comparisons of the time differences to the delay amounts, associate each of the pulses with one of the plurality of photon detectors. Logic unit39 may, for example, comprise a time-to-digital converter (T DC) or other time- resolved measurement system.

[0055] In some embodiments logic unit 39 is required to detect arrival times of pulses corresponding to photons with a high temporal resolution. For example, delay times may be short (e.g. on the order of picoseconds or tens of picoseconds or hundreds of picoseconds in some embodiments) and / or photon detection events may occur at a high rate. In some embodiments logic unit 39 comprises a deserializer for deserializing the combined signals. The deserializer operates to detect pulses in the combined signal by comparing the combined signal to a threshold for successive time slices. Such a deserializer may output binary words that contain a desired number of bit values which each indicate whether or not a pulse was present in a time slice corresponding to the binary values. In some embodiments, the time slices are separated by times in the range of about 10 ps to about 50 ps. For example, where the time slices are separated by 30 ps (corresponding to a clock rate of about 33 GHz) and the deserializer outputs 16 bit words, then the deserializer may present words for analysis at a rate of about 2 GHz.

[0056] In some embodiments, logic unit 39 comprises a field programmable gate array (FPGA) or other configurable logic device that uses logic gates to detect pairs of temporally spaced pulses that correspond to the same photon detection event. For example, where apparatus 30 includes a delay unit 36 that applies a delay amount equal to 5 time slices, then logic unit 14 may include AND gates having inputs connected to compare bit values separated by 5 bits. A TRUE output of any of the AND gates indicates the presence of a pair of pulses separated by the delay amount.

[0057] In some embodiments, amplifier 38 and / or logic unit 39 may be provided separately to the rest of the apparatus 30.

[0058] In apparatus 30, each of the delay circuits 356 includes a respective coupler 34, splitter 35 and a delay unit 36. It will be appreciated that this is one example implementation of the delay circuits 356 and other implementations of the delay circuits 356 may have more, fewer, or different, components.

[0059] In apparatus 30, no delay is applied to the first differentially delayed signal. That is, each splitter 35 outputs one signal that is delayed by the delay line 36 to obtain the second differentially delayed signal and another signal which is the first differentially delayed signal. Thus, the second differentially delayed signal is delayed with respect to the first differentially delayed signal. In general, a delay might or mightnot be applied to the first differentially delayed signal, provided the second differentially delayed signal is delayed with respect to the first differentially delayed signal.

[0060] Fig. 4 is a schematic drawing showing an apparatus 40 according to an example implementation of the present technology. Apparatus 40 includes photon detectors 42-1 , 42-2, ... , 42-N (generally and collectively photon detectors 42). Photon detectors 42 may comprise SNSPDs, for example.

[0061] A bias power supply 43 has independently controllable outputs 43-1 , 43-2, ..., 43-N that are each connected to deliver an appropriate bias current to a corresponding one of photon detectors 42. In some embodiments, the bias power supply 43 comprises a plurality of resistors connected to a shared power supply. The resistors are connected in parallel such that each of the resistors connects the shared power supply to a respective one of the outputs 43-1 , 43-2, ... , 43-N. Each resistor may have a resistance that is specific to (e.g. has been tailored to) the photon detector 42 that is connected to its respective one of the outputs 43-1 , 43-2,..., 43-N. That is, each of the resistors may be used to constrain the current provided by the shared power supply to a respective photon detector 42 to match a desired bias current for that photon detector 42. In this way, the shared power supply may be used to provide the appropriate bias current to each of the photon detectors 42.

[0062] When a photon detector 42 detects a photon, a pulse is coupled by a corresponding capacitor 44, which serves as a coupler, to a corresponding one of splitters 45-1 , 45-2, ... , 45-N (generally and collectively splitters 45). Using capacitors as couplers is particularly advantageous because each capacitor 44 isolates the biasing provided by the respective bias power supply 43-1 , 43-2, ... , 43-N to the respective photon detectors 42-1 , 42-2, ... , 42-N. That is, the capacitors 44-1 , 44-2, ... , 44-N prevent the biasing from reaching the splitters 45-1 , 45-2, ... , 45-N. In apparatus 40, each of splitters 45 is provided by a resistor network. In other embodiments, one or more of the splitters 45 may be implemented differently e.g. by a transformer, a lumped element splitter etc.

[0063] One output of each splitter 45 is connected to a corresponding one of delay units 46-1 , 46-2, ... , 46-N (collectively and generally delay units 46). As with delay units 36 of apparatus 30, each delay unit 46 operates to delay a signal by a corresponding delay amount. Different ones of delay units 46 are configured to delay signals by different delay amounts.

[0064] Apparatus 40 includes a signal combiner 47, an amplifier 48 and a logic unit 49 which perform in substantially the same manner as signal combiner 37, amplifier 38 and logic unit 39 of apparatus 30.

[0065] Fig. 5 shows an apparatus 50 according to an example embodiment.Apparatus 50 may for example, include components as illustrated in apparatus 30, as shown, or apparatus 40.

[0066] Apparatus 50 includes a multi stage cryogenic cooler 51 that cools a first zone 51 A to a first temperature and cools a second zone 51 B to a second temperature lower than the first temperature. Second zone 51 B may, for example, be cooled to a liquid helium temperature (temperature of 4 Kelvin and below). In some embodiments second zone 51 B is cooled to a temperature of 1 Kelvin or less. First zone 51 A may, for example, be cooled to a temperature that is greater than the temperature of the second zone 51 B, but less than room temperature. For example, first zone 51 A may be cooled to a temperature between 40-100K, such as 50K.

[0067] A photonic circuit chip 53 that integrates a number of photon detectors 32 is located in second zone 51 B. Photonic circuit chip 53 may include photon sources, for example, atoms, color centers, luminescence centers or the like. In some embodiments the photon emitters comprise matter-based qubits that have quantum states that may be controlled to store and manipulate quantum information.

[0068] Delay circuits 356 (which may comprise couplers 34, splitters 35 and / or delay units 36) and a signal combiner 37 may also be located in second zone 51 B. Since all of these elements may be made with passive components that generate substantially no heat when operating, the presence of these elements in second zone 51 B does not interfere significantly with cooling second zone 51 B to desired cryogenic temperatures.

[0069] The combined signal is carried from signal combiner 37 to amplifier 38 by a signal conductor 54 which may, for example, comprise a coaxial cable. A single signal conductor 54 may carry output signals from plural photon detectors, thereby reducing heat conduction into zone 51 B as compared to the case where a separate signal conductor is provided to carry output signals from each photon detector 32.

[0070] Amplifier 38 may be located in first zone 51 A. Cooling amplifier 38 to a temperature well below room temperature may beneficially reduce noise in the signal output by amplifier 38.

[0071] Logic unit 39 may, for example, be located in a room temperatureenvironment.

[0072] Depending on the number of photon detectors 32 and on performance characteristics required of the system, it may be desirable to carry original and delayed signals from each photon detector using a number of signal carriers (e.g. plural coaxial cables). In such embodiments, each of the signal conductors may be connected to receive a portion of the combined signal from a signal combiner. Each signal combiner may be connected to receive a number of original and / or delayed photon detector output signals. For example, each signal combiner may be connected to receive six or more original and / or delayed photon detector output signals.

[0073] Where a component (e.g. a software module, processor, assembly, device, circuit, etc.) is referred to herein, unless otherwise indicated, reference to that component (including a reference to a “means”) should be interpreted as including as equivalents of that component any component which performs the function of the described component (i.e. , that is functionally equivalent), including components which are not structurally equivalent to the disclosed structure which performs the function in the illustrated exemplary embodiments of the invention.

[0074] Logic units and / or control systems for apparatus in embodiments of the invention may, for example, be implemented using specifically designed hardware, configurable hardware, programmable data processors configured by the provision of software (which may optionally comprise “firmware”) capable of executing on the data processors, special purpose computers or data processors that are specifically programmed, configured, or constructed to perform one or more steps in a method as explained in detail herein and / or combinations of two or more of these. Examples of specifically designed hardware are: logic circuits, application-specific integrated circuits (“ASICs”), large scale integrated circuits (“ LSI s”), very large scale integrated circuits (“VLSIs”), and the like. Examples of configurable hardware are: one or more programmable logic devices such as programmable array logic (“PALs”), programmable logic arrays (“PLAs”), and field programmable gate arrays (“FPGAs”). Examples of programmable data processors are: microprocessors, digital signal processors (“DSPs”), embedded processors, graphics processors, math coprocessors, general purpose computers, server computers, cloud computers, mainframe computers, computer workstations, and the like. For example, one or more data processors in a control circuit for a device may implement methods as described herein by executing software instructions in a program memory accessible to theprocessors.

[0075] Processing may be centralized or distributed. Where processing is distributed, information including software and / or data may be kept centrally or distributed. Such information may be exchanged between different functional units by way of a communications network, such as a Local Area Network (LAN), Wide Area Network (WAN), or the Internet, wired or wireless data links, electromagnetic signals, or other data communication channel.

[0076] The invention may also be provided in the form of a program product. The program product may comprise any non-transitory medium which carries a set of computer-readable instructions which, when executed by a data processor, cause the data processor to execute a method of the invention. Program products according to the invention may be in any of a wide variety of forms. The program product may comprise, for example, non-transitory media such as magnetic data storage media including floppy diskettes, hard disk drives, optical data storage media including CD ROMs, DVDs, electronic data storage media including ROMs, flash RAM, EPROMs, hardwired or preprogrammed chips (e.g., EEPROM semiconductor chips), nanotechnology memory, or the like. The computer-readable signals on the program product may optionally be compressed or encrypted.

[0077] Certain aspects of the present invention may be implemented in software. For greater clarity, “software” includes any instructions executed on a processor, and may include (but is not limited to) firmware, resident software, microcode, code for configuring a configurable logic circuit, applications, apps, and the like. For example, a software application may be provided to analyze a combined output signal to determine when photons were detected at different ones of a plurality of photon detectors.

[0078] Both processing hardware and software may be centralized or distributed (or a combination thereof), in whole or in part, as known to those skilled in the art. For example, software and other modules may be accessible via local memory, via a network, via a browser or other application in a distributed computing context, or via other means suitable for the purposes described above.Interpretation of Terms

[0079] Unless the context clearly requires otherwise, throughout the description and the claims:“comprise”, “comprising”, and the like are to be construed in an inclusivesense, as opposed to an exclusive or exhaustive sense; that is to say, in the sense of “including, but not limited to”;• “connected”, “coupled”, or any variant thereof, means any connection or coupling, either direct or indirect, between two or more elements; the coupling or connection between the elements can be physical, logical, or a combination thereof;• “herein”, “above”, “below”, and words of similar import, when used to describe this specification, shall refer to this specification as a whole, and not to any particular portions of this specification;• “or”, in reference to a list of two or more items, covers all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list;• the singular forms “a”, “an”, and “the” also include the meaning of any appropriate plural forms. These terms (“a”, “an”, and “the”) mean one or more unless stated otherwise;• “and / or” is used to indicate one or both stated cases may occur, for example A and / or B includes both (A and B) and (A or B);• “approximately” when applied to a numerical value means the numerical value ± 10%;• where a feature is described as being “optional” or “optionally” present or described as being present “in some embodiments” it is intended that the present disclosure encompasses embodiments where that feature is present and other embodiments where that feature is not necessarily present and other embodiments where that feature is excluded. Further, where any combination of features is described in this application this statement is intended to serve as antecedent basis for the use of exclusive terminology such as "solely," "only" and the like in relation to the combination of features as well as the use of "negative" limitatio n(s)” to exclude the presence of other features; and• “first” and “second” are used for descriptive purposes and cannot be understood as indicating or implying relative importance or indicating the number of indicated technical features.

[0080] Words that indicate directions such as “vertical”, “transverse”, “horizontal”, “upward”, “downward”, “forward”, “backward”, “inward”, “outward”, “left”, “right”, “front”,“back”, “top”, “bottom”, “below”, “above”, “under”, and the like, used in this description and any accompanying claims (where present), depend on the specific orientation of the apparatus described and illustrated. The subject matter described herein may assume various alternative orientations. Accordingly, these directional terms are not strictly defined and should not be interpreted narrowly.

[0081] Where a range for a value is stated, the stated range includes all sub-ranges of the range. It is intended that the statement of a range supports the value being at an endpoint of the range as well as at any intervening value to the tenth of the unit of the lower limit of the range, as well as any subrange or sets of sub ranges of the range unless the context clearly dictates otherwise or any portion(s) of the stated range is specifically excluded. Where the stated range includes one or both endpoints of the range, ranges excluding either or both of those included endpoints are also included in the invention.

[0082] Certain numerical values described herein are preceded by "about". In this context, "about" provides literal support for the exact numerical value that it precedes, the exact numerical value ±5%, as well as all other numerical values that are near to or approximately equal to that numerical value. Unless otherwise indicated a particular numerical value is included in “about” a specifically recited numerical value where the particular numerical value provides the substantial equivalent of the specifically recited numerical value in the context in which the specifically recited numerical value is presented. For example, a statement that something has the numerical value of “about 10” is to be interpreted as: the set of statements:• in some embodiments the numerical value is 10;• in some embodiments the numerical value is in the range of 9.5 to 10.5; and if from the context the person of ordinary skill in the art would understand that values within a certain range are substantially equivalent to 10 because the values with the range would be understood to provide substantially the same result as the value 10 then “about 10” also includes:• in some embodiments the numerical value is in the range of C to D where C and D are respectively lower and upper endpoints of the range that encompasses all of those values that provide a substantial equivalent to the value 10.

[0083] Specific examples of systems, methods and apparatus have been described herein for purposes of illustration. These are only examples. The technology providedherein can be applied to systems other than the example systems described above. Many alterations, modifications, additions, omissions, and permutations are possible within the practice of this invention. This invention includes variations on described embodiments that would be apparent to the skilled addressee, including variations obtained by: replacing features, elements and / or acts with equivalent features, elements and / or acts; mixing and matching of features, elements and / or acts from different embodiments; combining features, elements and / or acts from embodiments as described herein with features, elements and / or acts of other technology; and / or omitting combining features, elements and / or acts from described embodiments.

[0084] As will be apparent to those of skill in the art upon reading this disclosure, each of the individual embodiments described and illustrated herein has discrete components and features which may be readily separated from or combined with the features of any other described embodiment(s) without departing from the scope of the present invention.

[0085] Any aspects described above in reference to apparatus may also apply to methods and vice versa.

[0086] Any recited method can be carried out in the order of events recited or in any other order which is logically possible. For example, while processes or blocks are presented in a given order, alternative examples may perform routines having steps, or employ systems having blocks, in a different order, and some processes or blocks may be deleted, moved, added, subdivided, combined, and / or modified to provide alternative or subcombinations. Each of these processes or blocks may be implemented in a variety of different ways. Also, while processes or blocks are at times shown as being performed in series, these processes or blocks may instead be performed in parallel, simultaneously or at different times.

[0087] Various features are described herein as being present in “some embodiments”. Such features are not mandatory and may not be present in all embodiments. Embodiments of the invention may include zero, any one or any combination of two or more of such features. All possible combinations of such features are contemplated by this disclosure even where such features are shown in different drawings and / or described in different sections or paragraphs. This is limited only to the extent that certain ones of such features are incompatible with other ones of such features in the sense that it would be impossible for a person of ordinary skill in the art to construct a practical embodiment that combines such incompatiblefeatures. Consequently, the description that “some embodiments” possess feature A and “some embodiments” possess feature B should be interpreted as an express indication that the inventors also contemplate embodiments which combine features A and B (unless the description states otherwise or features A and B are fundamentally incompatible). This is the case even if features A and B are illustrated in different drawings and / or mentioned in different paragraphs, sections or sentences.

[0088] It is therefore intended that the following appended claims and claims hereafter introduced are interpreted to include all such modifications, permutations, additions, omissions, and sub-combinations as may reasonably be inferred. The scope of the claims should not be limited by the preferred embodiments set forth in the examples, but should be given the broadest interpretation consistent with the description as a whole.

Claims

WHAT IS CLAIMED IS:1 . Apparatus for photon detection, the apparatus comprising: a plurality of photon detectors each operative to generate a photon detector output signal that indicates photon detections; each of the plurality of photon detectors associated with a corresponding delay circuit connected to receive the photon detector output signal from the corresponding photon detector and to present the received output signal at first and second outputs of the delay circuit as first and second differentially delayed output signals respectively, wherein the second differentially delayed output signal is delayed relative to the first differentially delayed output signal by a corresponding delay amount, and the delay amounts for the delay circuits corresponding to each of the plurality of photon detectors are different from one another; and one or more signal combiners each operable to combine a plurality of output signals made up of one or more of the first differentially delayed output signals and one or more of the second differentially delayed output signals into a combined output signal.

2. The apparatus according to claim 1 wherein the one or more signal combiners comprises one signal combiner connected to receive from all of the plurality of delay circuits the first differentially delayed output signal and the second differentially delayed output signal and to combine all of these first differentially delayed output signals and second differentially delayed output signals into the combined output signal.

3. The apparatus according to claim 1 or 2 wherein each of the delay circuits comprises: a splitter having an input connected to receive the photon detector output signal from the corresponding photon detector, and first and second outputs, each of the splitters operative to present the photon detector output signal received at the input at both of the first and second outputs; and a delay unit connected to receive the photon detector signal presented at the second output of the splitter, delay the photon detector signal, and present the delayed photon detector signal as the second differentially delayed output signal.

4. The apparatus according to claim 3 wherein the delay unit comprises a delay line comprising a conductor having a length corresponding to the delay amount.

5. The apparatus according to any of the preceding claims wherein the delay amounts associated with each of the delay circuits are in the range of about 10 ps to about 500 ps.

6. The apparatus according to any of the preceding claims wherein the photon detectors comprise superconducting nanowire single photon detectors (SNSPDs).

7. The apparatus according to claim 6 comprising at least one power supply connected to deliver bias current to each of the SNSPDs, the bias current for each of the SNSPDs being individually settable.

8. The apparatus according to any of the preceding claims wherein the delay amounts for the delay circuits corresponding to each of the plurality of photon detectors have a property that none of the delay amounts is equal to the sum of any two other ones of the delay amounts.

9. The apparatus according to any one of claims 1 to 7, wherein the delay amounts for the delay circuits corresponding to each of the plurality of photon detectors have a property that none of the delay amounts is equal to the sum of any two or more other ones of the delay amounts.

10. The apparatus according to any of the preceding claims comprising a logic unit configured to receive the combined signal, determine time differences between photon detection features in the combined signal, compare the time differences to the delay amounts, and, based on the comparisons of the time differences to the delay amounts, associate each of the photon detection features with one of the plurality of photon detectors.1 1 . The apparatus according to claim 10 comprising a deserializer connected to receive and deserialize the combined signals.

12. The apparatus according to any of the preceding claims wherein the delay circuits and one or more signal combiners are made entirely of passive components.

13. The apparatus according to any of the preceding claims comprising an amplifier connected to amplify the combined signal output by the one or more signal combiners.

14. The apparatus according to claim 13 comprising a cryogenic cooling system operable to maintain the photon detectors at a first cryogenic temperature.

15. The apparatus according to claim 14 wherein the cryogenic cooling system is operable to maintain the amplifier at a second cryogenic temperature that is higher than the first cryogenic temperature while the photon detectors are being maintained at the first cryogenic temperature.

16. A photon detection method comprising: receiving output signals from a plurality of photon detectors, at least some of the output signals comprising photon detection features, for each of the output signals creating a corresponding delayed output signal by delaying the output signal by a delay amount wherein the delay amount applied to each of the output signals is different; combining the output signals and the delayed output signals into a combined signal.

17. The method according to claim 16 comprising processing the combined signal to determine time differences between the photon detection features in the combined signal, compare the time differences to the delay amounts, and, based on the comparisons of the time differences to the delay amounts, associate each of the photon detection features with one of the plurality of photon detectors.

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