Laminate, transistor, laminate manufacturing method, and transistor manufacturing method

Abstract

A laminate comprising a substrate, an amine generation layer, a copper wiring layer, and a copper wiring protection layer in this order.

Description

Stacked body, transistor, manufacturing method of stacked body, and manufacturing method of transistor

[0001] The present invention relates to a laminate, a transistor, a method for manufacturing a laminate, and a method for manufacturing a transistor.

[0002] In recent years, in the manufacture of microdevices such as semiconductor elements, integrated circuits, and devices for organic EL displays, a method has been proposed in which patterns with different surface properties are formed on a substrate and the differences in surface properties are utilized to create microdevices.

[0003] One example of a pattern formation method that utilizes differences in surface properties on a substrate is to form a region in which chemically active substituents are generated on a part of the substrate, which allows a metal material, organic material, or inorganic material to adhere to that part of the substrate.

[0004] Electroless plating is a technique for adhering a metal material to a substrate to form a metal film. For example, Patent Document 1 discloses a technique for forming fine wiring by electroless plating. Specifically, Patent Document 1 discloses a technique for using a catalyst activation layer and a photoresist to perform photopatterning by etching or lift-off after plating the entire surface.

[0005] Japanese Patent Application Laid-Open No. 2006-2201

[0006] A first aspect of the present invention is a laminate comprising a substrate, an undercoat layer, a copper wiring layer, and a copper wiring protection layer in this order, the undercoat layer comprising an amine generating layer.

[0007] FIG. 1 is a schematic cross-sectional view of an example of a laminate of the present embodiment; FIG. 2 is a schematic cross-sectional view of an example of a transistor of the present embodiment; FIG. 3 is a schematic view for explaining steps in an example of a method for manufacturing the laminate of the present embodiment; FIG. 4 is a schematic view for explaining steps in an example of a method for manufacturing the laminate of the present embodiment; FIG. 5 is a diagram showing a source / drain electrode structure manufactured in Example 1; FIG. 6 is a diagram showing the results of a transfer characteristic evaluation of the transistor manufactured in Example 1; FIG. 7 is a diagram showing fine wiring manufactured in Example 2; FIG. 8 is a diagram showing a source / drain electrode structure manufactured in Example 2; FIG. 9 is a diagram showing the results of a transfer characteristic evaluation of the transistor manufactured in Example 2.

[0008] The laminate and the method for manufacturing the laminate of the present embodiment will be described below with reference to the drawings. Note that in all the drawings below, the dimensions and proportions of the components are appropriately changed to make the drawings easier to understand.

[0009] <Laminate> One aspect of the present invention is a laminate comprising, in this order, a substrate, an amine generating layer, a copper wiring layer, and a copper wiring protection layer. Figure 1 is a schematic cross-sectional view of laminate 1 of this embodiment. Laminate 1 comprises substrate 10, amine generating layer 12, copper wiring layer 14C, and copper wiring protection layer 16. In Figure 1, gate insulating layer 11 and first catalyst layer 13 are optional.

[0010] Amine generating layer 12 and optional gate insulating layer 11 are formed over the entire surface of one main surface of substrate 10. Copper wiring layer 14C is a fine copper wiring pattern formed on amine generating layer 12. Copper wiring layer 14C is protected by copper wiring protection layer 16. Copper wiring protection layer 16 is a conductive protective film.

[0011] The laminate 1 can be suitably used as a patterned electrode of a transistor. When the laminate 1 is used as a patterned electrode of a transistor, the copper wiring layer 14C forms a source electrode or a drain electrode, respectively.

[0012] The substrate 10 may be either optically transparent or non-optically transparent, and may be made of, for example, inorganic materials such as glass, quartz glass, silicon, or silicon nitride, or organic polymers (resins) such as acrylic resin, polycarbonate resin, or polyester resins such as PET (polyethylene terephthalate) or PBT (polybutylene terephthalate).

[0013] The amine contained in the amine generating layer 12 is, for example, a primary amine (—NH ２ -), and secondary amine (-NH-).

[0014] When the stack 1 constitutes a bottom-gate transistor, it is preferable to provide a gate insulating layer 11 on the substrate 10. The gate insulating layer 11 contains, for example, a methoxysilane coupling agent or polymethoxychalcone. As an optional configuration, a metal wiring pattern including a gate electrode may be provided on the entire or part of one main surface of the substrate 10, below the gate insulating layer 11. This metal wiring pattern may be made of, for example, a conductive material containing molybdenum and aluminum, and is a fine metal wire of MAM (a three-layer structure of Mo (molybdenum), Al (aluminum), and Mo (molybdenum)).

[0015] Copper wiring layer 14C is a metal wiring formed on the surface of amine generating layer 12. Laminate 1 is manufactured by the laminate manufacturing method of this embodiment, which will be described later. In the manufacturing method of this embodiment, first catalyst layer 13 may remain under copper wiring layer 14C as a trace of the step of removing the first catalyst layer present in the openings of the photoresist layer. First catalyst layer 13 may be a layer containing palladium.

[0016] The top and side surfaces of the copper wiring layer 14C are protected by a copper wiring protection layer 16. The copper wiring protection layer 16 is a protective film having electrical conductivity, and specific constituent materials thereof are nickel phosphorus, nickel boron, or palladium.

[0017] When the laminate 1 constitutes a transistor, it is preferable to provide a gold plating layer on the copper wiring protection layer. Fig. 2 shows a schematic cross-sectional view of a transistor including the laminate of this embodiment and an organic semiconductor layer.

[0018] 2 , the transistor 2 includes a substrate 10, an amine generating layer 12, a source electrode 32, a drain electrode 31, and an organic semiconductor layer 33. The source electrode 32 and the drain electrode 33 each include a copper wiring layer 14C, a copper wiring protection layer 16, and a gold plating layer 17. The transistor 2 shown in FIG. 2 further includes a gate insulating layer 11 and a first catalyst layer 13.

[0019] The gold plating layer 17 is a metal wiring formed by electroless plating, similar to the copper wiring layer 14C.

[0020] The copper wiring layer 14C serves as a first electrode constituting the source electrode 32 or the drain electrode 31, and the gold plating layer 17 serves as a second electrode constituting the source electrode 32 or the drain electrode 31. In relation to the HOMO / LUMO levels of the material forming the organic semiconductor layer 33, the material constituting the second electrode is preferably gold (work function: 5.4 eV), which is a metal material having a work function that facilitates electron (or hole) movement.

[0021] For the above reasons, conventional wiring using nickel phosphorus as the first electrode and gold as the second electrode has been considered. However, when nickel phosphorus is used, the resistance increases when the transistor is enlarged, so a material with lower resistance has been sought.

[0022] The inventors aimed to manufacture a low-resistance transistor and used copper for the first electrode. However, when the copper wiring of the first electrode was coated with gold, migration occurred when the transistor was driven, and the copper wiring was exposed and oxidized. This was a problem.

[0023] Therefore, the inventors came up with the idea of ​​protecting the copper wiring layer with a copper wiring protection layer, and completed the present invention.

[0024] In the laminate of this embodiment, the copper wiring layer is protected by the copper wiring protection layer, so even if a gold plating layer is further formed to drive the transistor, migration does not occur and a transistor with reduced resistance can be provided.

[0025] The organic semiconductor material used in the transistor is not particularly limited, and examples thereof include p-type semiconductors such as copper phthalocyanine (CuPc), pentacene, rubrene, tetracene, and P3HT (poly(3-hexylthiophene-2,5-diyl)), n-type semiconductors such as fullerenes such as C60 and perylene derivatives such as PTCDI-CH (N,N'-dioctyl-3,4,9,10-perylene tetracarboxylic diimide), and Ph-BTBT-10 (2-decyl-7-phenyl[1]benzothieno[3,2-b][1]benzothiophene). Among these, soluble pentacenes such as TIPS pentacene (6,13-Bis(triisopropylsilylethylenyl)pentacene), organic semiconductor polymers such as P3HT, and Ph-BTBT-10 are preferred because they are soluble in organic solvents such as toluene and allow the formation of organic semiconductor layers by wet processes. The HOMO level of TIPS pentacene is 5.2 eV, and the HOMO level of Ph-BTBT-10 is −5.6 eV.

[0026] <Method for manufacturing laminate> A method for manufacturing a laminate according to one embodiment of the present invention will be described with reference to the drawings. The step shown in FIG. 3A is an optional step, but when manufacturing a laminate constituting a transistor, it is preferable to form a gate insulating layer 11 on the surface of a substrate 10.

[0027] The gate insulating layer 11 can be formed by applying, for example, a methoxysilane coupling agent to the entire surface of one main surface of the substrate 10. The gate insulating layer 11 is preferably formed by applying the methoxysilane coupling agent, then further applying a photosensitive polymer material such as polymethoxychalcone, and irradiating it with ultraviolet light.

[0028] Furthermore, as an optional step, a step of forming a metal wiring pattern on the entire or part of one main surface of the substrate 10, below the gate insulating layer 11, may be included. This metal wiring pattern may be made of, for example, a conductive material containing molybdenum and aluminum, and may be formed as fine metal wires of MAM (a three-layer structure of Mo (molybdenum), Al (aluminum), and Mo (molybdenum)).

[0029] Next, as shown in Fig. 3, symbol 3B, a photosensitive surface treatment agent is applied to substrate 10 or optionally formed gate insulating layer 11 to form photosensitive resin film 12A. Photosensitive resin film 12A is exposed to light to form amine generating layer 12 having an amine generating region in the exposed portion (Fig. 3, symbol 3C).

[0030] The photosensitive resin film 12A may be exposed to light over the entire surface or may be exposed to light in a pattern through a mask. However, from the viewpoint of forming a copper plating layer over the entire surface of the substrate 10 in a later step, it is preferable to expose the entire surface.

[0031] The photosensitive surface treatment agent for forming the photosensitive resin film 12A is not limited as long as it is a material that can eliminate a protecting group and generate an amine upon irradiation with light. For example, a photosensitive surface treatment agent containing the following photosensitive polymer 1 (polyisopropylnitrobenzyl carbamate) is preferred.

[0032]

[0033] When the photosensitive resin film 12A is exposed to light, amines are generated in the exposed areas, forming the amine generating layer 12 having amine generating regions 12X (FIG. 3, reference numeral 3C). The amines are, for example, primary amines (—NH ２ -), and secondary amine (-NH-).

[0034] 3, reference numeral 3D, a first catalyst layer 13 is formed on the amine generating layer 12, and electroless copper plating is performed to form a copper plating layer 14. The first catalyst layer 13 is composed of an electroless plating catalyst. The electroless plating catalyst is a catalyst that reduces metal ions contained in the plating solution for electroless plating, and examples of such catalysts include silver and palladium.

[0035] Amino groups are exposed on the surface of amine generating layer 12. The amino groups are capable of capturing and reducing the electroless plating catalyst described above. Therefore, the electroless plating catalyst is captured on amine generating layer 12, forming first catalyst layer 13. In addition, the electroless plating catalyst can be one that can support amino groups.

[0036] The catalyst used to form the first catalyst layer 13 is not limited as long as it is a catalyst for electroless copper plating and can support an amine, but is preferably a metal catalyst having a pH of 3 to 12 at a measurement temperature of 20° C. An example of a commercially available catalyst of this kind is Activator 7331 manufactured by Melplate, which is a palladium catalyst having a pH of 3.5 to 6.5 at a measurement temperature of 20° C.

[0037] After forming the first catalytic layer 13, it is preferable to perform an optional process of activating the first catalytic layer 13 before forming the copper plating layer 14. The activation process of the first catalytic layer 13 is a process of reducing metal chlorides contained in the applied catalyst to metals. For example, this is a process of reducing palladium chloride contained in the applied catalyst to metallic palladium, or a process of reducing silver chloride to metallic silver.

[0038] The treatment for activating the first catalyst layer 13 is a known method, and an acid or alkaline solution called an accelerator can be used, specifically, a commercially available activator (for example, OPC-150 Crystal RW manufactured by Okuno Chemical Industries Co., Ltd.) can be used. Activating the first catalyst layer 13 metallizes the metal chloride, thereby improving the deposition and adhesion of electroless copper plating.

[0039] After forming first catalyst layer 13, electroless plating is performed to form copper plating layer 14. In the electroless plating, substrate 10 is immersed in an electroless plating bath to reduce metal ions on the surface of first catalyst layer 13, thereby depositing copper plating layer 14. Formation of amine generating layer 12 supports a sufficient amount of catalyst, allowing the formation of copper plating layer 14 with high adhesion to substrate 10.

[0040] Next, as shown in Fig. 4, reference numeral 4A, a photoresist material 15A is applied onto the copper plating layer 14, and the photoresist material 15A is pattern-exposed through a mask M to form exposed portions corresponding to the pattern of the copper wiring layer. Thereafter, as shown in Fig. 4, reference numeral 4B, the photoresist in the unexposed portions is removed to form a photoresist layer 15.

[0041] The photoresist material 15A may be any known material, such as a positive photoresist material.

[0042] 4, a copper wiring layer 14C is formed by removing a portion of the copper plating layer 14. Through this process, a preliminary pattern P including a photoresist layer 15 is formed on the copper wiring layer 14C.

[0043] Next, as shown in Figure 4, reference numeral 4D, a catalyst remover is brought into contact with the preliminary pattern P to remove the first catalyst layer 13 present in the photoresist openings. One method for removing the first catalyst layer 13 is to immerse the substrate 10 in the catalyst remover. The catalyst remover is preferably an aqueous solution containing an organic amine.

[0044] When substrate 10 is immersed in an aqueous solution containing an organic amine, the metal catalyst constituting first catalyst layer 13 and the organic amine form a complex, which improves the solubility of the metal catalyst and enables removal of first catalyst layer 13. At this time, photoresist layer 15 does not dissolve in the aqueous solution containing an organic amine, so first catalyst layer 13 can be removed while leaving photoresist layer 15 intact.

[0045] The aqueous solution containing an organic amine is preferably an aqueous solution containing ethylenediamine. An example of such a commercially available product is ICP Postdip RP manufactured by Okuno Chemical Industries Co., Ltd.

[0046] When forming the copper plating layer 14 over the entire surface of one main surface of the substrate 10, it is preferable to use a neutral metal catalyst having a pH of 3.5 to 6.5 at a measurement temperature of 20° C., which can precipitate a large amount of copper in order to enhance adhesion between the substrate 10 and the copper plating layer 14. However, if the neutral metal catalyst remains, the metal components that constitute the copper wiring protection layer will be excessively precipitated in the subsequent step of forming the copper wiring protection layer, resulting in an increase in resistance value.

[0047] For this reason, it is necessary to remove the first catalyst layer 13 present in the photoresist openings. However, since the organic amine that constitutes the catalyst remover also forms a complex with copper, simply immersing the substrate 10 in an aqueous solution containing the organic amine will dissolve the copper that constitutes the copper wiring layer 14C, damaging the copper wiring.

[0048] In this embodiment, by contacting the preliminary pattern P with a catalyst remover, the photoresist layer 15 protects the copper wiring layer 14C from the catalyst remover, and the first catalyst layer 13 can be removed without damaging the copper wiring layer 14C.

[0049] Although the top surface of the copper wiring in copper wiring layer 14C is protected by photoresist layer 15, the side surfaces are not protected. However, since the area ratio of the side surfaces to the entire copper wiring layer 14C is small, damage to the side surfaces caused by the catalyst remover is unlikely to become apparent.

[0050] Furthermore, after removing the first catalyst layer 13 present in the photoresist openings, the photoresist layer 15 is removed as shown in Fig. 5, reference numeral 5A. The photoresist layer 15 may be removed using a known developer.

[0051] Furthermore, as shown in Fig. 5B, a second catalyst layer 20 is formed on the copper wiring layer 14C, and electroless plating is then performed to form a copper wiring protection layer 16 (Fig. 5C). The copper wiring protection layer 16 is formed so as to cover the top and side surfaces of the copper wiring in the copper wiring layer 14C. The copper wiring protection layer 16 is a protective film having electrical conductivity, and specific constituent materials are nickel phosphorus, nickel boron, or palladium.

[0052] To form copper wiring protection layer 16, second catalyst layer 20 is formed on copper wiring layer 14C. The catalyst constituting the second catalyst layer is an electroless plating catalyst different from the electroless plating catalyst constituting first catalyst layer 13, and the catalyst used here is preferably an acidic metal catalyst having a pH of 2 or less at a measurement temperature of 20°C. An example of such a catalyst is Activator 352 manufactured by Melplate, which is an acidic palladium catalyst having a pH of 1 or less at a measurement temperature of 20°C.

[0053] By forming the conductive protective layer 16, the gold that constitutes the electroless gold plating layer and the copper that constitutes the copper wiring layer, which will be formed in a later optional process, are less likely to migrate, making it less likely that short circuits will occur due to reduced migration.

[0054] Furthermore, as an optional step, a gold plating layer 17 may be formed (FIG. 5, reference numeral 3D). The gold plating layer 17 may be formed by electroless plating, similar to the copper plating layer 14.

[0055] <Method for manufacturing transistor> The method for manufacturing a transistor of the present embodiment includes a step of forming an organic semiconductor layer in contact with opposing surfaces of the source electrode and the drain electrode, after performing the steps up to the step of providing a gold plating layer by the method for manufacturing a laminate of the present embodiment described above.

[0056] The present invention will be described in more detail below with reference to examples, but the present invention is not limited to the following examples.

[0057] Example 1 [Step of Forming an Amine Generating Layer] A silicon wafer with a thermally oxidized film was subjected to surface treatment by forming a film of a cyclopentanone solution of MCSC ((E)-4-(3-(4-methoxyphenyl)acryloyl)phenyl(3-(trimethoxysilyl)propyl)carbamate) by spin coating. A 5 wt % cyclopentanone solution of PMC (Poly(4-Methoxychalcone)) was then applied by spin coating (MS-A150, manufactured by Mikasa Co., Ltd.) at 1000 rpm), and then dried at 100°C for 20 minutes. UV light with a wavelength of 365 nm was applied at 1200 mJ / cm. ２ A gate insulating layer serving as a base was formed by irradiating the silicon wafer with light and heating it for 60 minutes at 150° C. In this Example 1, the silicon wafer functions as a gate electrode of a transistor.

[0058] The structures of MCSC and PMC are shown below.

[0059]

[0060] Next, a 0.3 wt % solution of PiPrNBC-AEMA (polyisopropyl nitrobenzyl carbamate) in cyclopentanone was applied by spin coating (MS-A150, manufactured by Mikasa Co., Ltd.) at 1000 rpm, and heated at 100° C. for 20 minutes to form a photosensitive polymer layer.

[0061] The structure of PiPrNBC-AEMA is shown below.

[0062]

[0063] Next, the substrate on which the photosensitive polymer layer was formed on the entire surface was irradiated with light of 365 nm wavelength at 1000 mJ / cm ２ The photopolymer layer was exposed to light to form an amine-generating layer.

[0064] [Step of forming a copper plating layer] Next, the substrate was immersed in a catalyst solution for electroless plating (Melplate Activator 7331, manufactured by Meltex) at room temperature for 10 minutes, thereby attaching a catalyst (Pd) to the amine-generating portion. After rinsing the surface with water, the substrate was immersed in a catalyst activation solution (OPC-150 Crystal RW, manufactured by Okuno Pharmaceutical Industries) at room temperature for 1 minute, thereby attaching and activating the catalyst (Pd) to the amine-generating portion. This formed a first catalyst layer. Subsequently, the substrate was immersed in an electroless plating solution (OPC Copper HFS, manufactured by Okuno Pharmaceutical Industries) at 40°C for 3 minutes, thereby depositing electroless copper on the catalyst to form a copper plating layer.

[0065] [Photoresist Process] A photoresist (PFI-34, manufactured by Sumitomo Chemical Co., Ltd.) was applied by spin coating (MS-A150, manufactured by Mikasa Co., Ltd.) at 1500 rpm and heated at 105°C for 8 minutes to form a photoresist layer. UV light with a wavelength of 365 nm was irradiated through a photomask at 100 mJ / cm. ２ After irradiation and post-baking at 105° C. for 3 minutes, the exposed photoresist was removed by immersion in a developer (NMD-3, 2.38% tetramethylammonium hydroxide, manufactured by Tokyo Ohka Kogyo Co., Ltd.) for 1 minute.

[0066] [Step of forming a preliminary pattern] The copper plating layer was partially removed by heating at 105° C. for 5 minutes and immersing in a copper etching solution (acetic acid / hydrogen peroxide / water=1 / 1 / 20) at 30° C. for 40 seconds, thereby forming a preliminary pattern comprising a photoresist layer on the copper wiring layer.

[0067] [Step of Removing the First Catalyst Layer] Subsequently, the substrate was immersed in a catalyst remover (ICP Postdip RP-C, manufactured by Okuno Chemical Industries Co., Ltd.) at 50° C. for 15 minutes to remove the palladium, which was the first catalyst layer, present in the openings of the photoresist.

[0068] [Step of Removing Photoresist Layer] The substrate was immersed in a resist remover (N-342, manufactured by Nagase ChemteX Corporation) at room temperature for 4 minutes to remove the photoresist, thereby forming a copper fine wiring layer.

[0069] [Step of forming copper wiring protective layer] The substrate was immersed in a catalyst solution for electroless plating (Melplate Activator 352, manufactured by Meltex) at 30°C for 40 seconds, then immersed in a catalyst remover (ICP Postdip RP-C, manufactured by Okuno Chemical Industries Co., Ltd.) at 25°C for 1 minute, and then immersed in an electroless plating solution (Melplate NI-867, manufactured by Meltex) at 73°C for 3 minutes, whereby nickel phosphorus was deposited on the copper plating to produce fine plated wiring with a copper wiring protective layer, and a laminate was obtained.

[0070] [Gold Plating Step] The substrate was then immersed in an electroless plating solution (Flash Gold NC, manufactured by Okuno Chemical Industries Co., Ltd.) at 55° C. for 4 minutes to deposit displacement gold plating, thereby producing fine plated wiring as source / drain electrodes.

[0071] The electrode surface was ultrasonically cleaned (45 kHz, 4 minutes) in cyclopentanone, xylene, and IPA, followed by heating and drying at 120°C for 60 minutes. This was followed by UV cleaning for 8 minutes and ultrasonic cleaning in IPA (45 kHz, 3 minutes), and then heating and drying at 120°C for 60 minutes. The substrate was then immersed in a 0.75 wt% ethanol solution of TFTFMBT (2,3,5,6-tetrafluoro-4-(trifluoromethyl)benzenethiol, manufactured by Tokyo Chemical Industry Co., Ltd.) at room temperature for 5 minutes, removed, rinsed with ethanol, and dried with a nitrogen spray, forming a gold-thiol SAM film on the electrode surface.

[0072] Next, a 0.1 / 0.45 wt % xylene solution of polystyrene (manufactured by Merck) / organic semiconductor (Ph-BTBT-10, 2-decyl-7-phenyl[1]benzothieno[3,2-b][1]benzothiophene, manufactured by Tokyo Chemical Industry Co., Ltd.) was applied using a heated spin coater at 145°C and 3000 rpm, and dried at 120°C for 10 minutes and then at 100°C for 60 minutes to prepare an organic semiconductor layer, and the transistor of Example 1 was obtained.

[0073] The fabricated source / drain electrode structure is shown in Figure 6. It was confirmed that detailed writing was possible for all shapes with inter-electrode distances of 10, 20, 35, 50, and 80 μm.

[0074] The results of the transfer characteristic evaluation of the OTFTs (channel lengths L=10, 20, 35, 50, and 80 μm, channel width W=500 μm) shown in Fig. 7 are shown in Fig. 7. It was confirmed that all of them operated normally, regardless of the channel length.

[0075] In Example 1, a thin copper plating of approximately 200 nm was used, which is susceptible to the effects of chemicals that reduce conductivity. By removing the palladium underneath the copper plating while leaving the resist in place, it was possible to deposit an excellent Au plating without damaging the copper plating. While the sheet resistance after copper plating was 0.19 Ω / □, it was possible to maintain a 0.22 Ω / □ after Au deposition.

[0076] Comparative Example 1 A transistor of Comparative Example 1 was manufactured in the same manner as in Example 1, except that the step of forming a photoresist layer was not performed and a step of immersing the substrate in a catalyst remover (ICP Post-Dip RP-C, manufactured by Okuno Chemical Industries Co., Ltd.) at 25°C for 2 minutes was added before forming a copper wiring protection layer on the copper plating layer.

[0077] The sheet resistance after copper plating was 0.38 Ω / □, while after Au lamination it was 0.72 Ω / □, confirming a decrease in conductivity. It has been confirmed that immersion in a catalyst remover without resist protection leads to an increase in resistance, so it is advisable to avoid exposing the copper to chemicals before applying a catalyst to the copper surface.

[0078] Comparative Example 2 A transistor of Comparative Example 2 was manufactured in the same manner as in Comparative Example 1, except that the copper plating layer was immersed in a catalyst remover (ICP Post-Dip RP-C, manufactured by Okuno Chemical Industries Co., Ltd.) at 25°C for 1 minute before forming a copper wiring protection layer on the copper plating layer.

[0079] The sheet resistance after copper plating was 0.34 Ω / □, while after Au lamination, the conductivity was confirmed to be 1.02 Ω / □. It has been confirmed that immersion in a catalyst remover without resist protection leads to an increase in resistance, so it is desirable to avoid exposing the copper to chemicals before applying a catalyst to the copper surface.

[0080] Comparative Example 3 A transistor of Comparative Example 3 was manufactured in the same manner as in Comparative Example 1, except that the copper plating layer was immersed in a catalyst remover (ICP Post-Dip RP-C, manufactured by Okuno Chemical Industries Co., Ltd.) at 25°C for 4 minutes before forming a copper wiring protection layer on the copper plating layer.

[0081] The sheet resistance after copper plating was 0.41 Ω / □, while after Au lamination it was 1.58 Ω / □, confirming a decrease in conductivity. It has been confirmed that immersion in a catalyst remover without resist protection leads to an increase in resistance, so it is advisable to avoid exposing the copper to chemicals before applying a catalyst to the copper surface.

[0082] The results of Example 1 and Comparative Examples 1, 2, and 3 are summarized in the table below.

[0083]

[0084] Example 2 [Process for Forming an Amine Generating Layer] A MAM (Mo / Al / Mo) film was dry-formed on a PEN (Teonex, polyethylene terephthalate, manufactured by Teijin) film, and fine wiring of the MAM was formed by photolithography to form a gate electrode. After UV / O3 cleaning for 3 minutes, a 0.2 wt % cyclopentanone solution of MCSC ((E)-4-(3-(4-methoxyphenyl)acryloyl)phenyl(3-(trimethoxysilyl)propyl)carbamate) was spin-coated to form a film for surface treatment. A 12 / 1.2 wt % cyclopentanone solution of PVCI (polyvinyl cinnamate, manufactured by Merck) / MC (methoxychalcone, manufactured by Tokyo Chemical Industry Co., Ltd.) was then spin-coated (MS-A150, manufactured by Mikasa Co., Ltd.) at 2000 rpm, followed by drying at 80°C for 20 minutes. The film was irradiated with 624 mJ / cm 2 of UV light having a wavelength of 365 nm, developed with PGMEA (propylene glycol monomethyl ether acetate, manufactured by Tokyo Chemical Industry Co., Ltd.), and heated at 150° C. for 120 minutes to form a gate insulating layer.

[0085] Next, a 0.3 wt % solution of PiPrNBC-AEMA in cyclopentanone was applied at 1000 rpm using a spin coater (MS-A150, manufactured by Mikasa Co., Ltd.) and heated at 100° C. for 20 minutes to form a photosensitive polymer layer.

[0086] Next, the substrate on which the photosensitive polymer layer was formed on the entire surface was irradiated with light of 365 nm wavelength at 1000 mJ / cm ２ The photopolymer layer was exposed to light to form an amine-generating layer.

[0087] [Step of forming a copper plating layer] Next, the substrate was immersed in a catalyst solution for electroless plating (Melplate Activator 7331, manufactured by Meltex) at room temperature for 10 minutes to attach a catalyst (Pd) to the amine-generating portion. After rinsing the surface with water, the substrate was immersed in a catalyst activation solution (OPC-150 Crystal RW, manufactured by Okuno Pharmaceutical Industries) at room temperature for 1 minute to attach and activate the catalyst (Pd) to the amine-generating portion. Subsequently, the substrate was immersed in an electroless plating solution (OPC Copper HFS, manufactured by Okuno Pharmaceutical Industries) at 40°C for 3 minutes to deposit electroless copper on the catalyst, producing a copper plating layer.

[0088] [Photoresist Process] A photoresist (OFPR5000, manufactured by Tokyo Ohka Kogyo Co., Ltd.) was applied by spin coating (MS-A150, manufactured by Mikasa Co., Ltd.) at 1500 rpm and heated at 105°C for 5 minutes to form a photoresist layer. UV light having a wavelength of 365 nm was irradiated through a photomask at 27 mJ / cm. ２ After irradiation and post-baking at 105° C. for 5 minutes, the exposed photoresist was removed by immersion in a developer (NMD-3, 2.38% tetramethylammonium hydroxide, manufactured by Tokyo Ohka Kogyo Co., Ltd.) for 25 seconds.

[0089] [Step of forming a preliminary pattern] The copper plating layer was partially removed by heating at 105° C. for 5 minutes and immersing in a copper etching solution (acetic acid / hydrogen peroxide / water=1 / 1 / 20) at 30° C. for 40 seconds, thereby forming a preliminary pattern comprising a photoresist layer on the copper wiring layer.

[0090] [Step of Removing the First Catalyst Layer] Subsequently, the substrate was immersed in a catalyst remover (ICP Postdip RP-C, manufactured by Okuno Chemical Industries Co., Ltd.) at 50° C. for 15 minutes to remove the palladium of the first catalyst layer present in the openings of the photoresist.

[0091] [Step of Removing Photoresist Layer] The substrate was immersed in a resist remover (N-342, manufactured by Nagase ChemteX Corporation) at room temperature for 4 minutes to remove the photoresist, thereby forming a copper fine wiring layer.

[0092] [Step of forming copper wiring protective layer] The substrate was immersed in a catalyst solution for electroless plating (Melplate Activator 352, manufactured by Meltex) at 30°C for 40 seconds, then immersed in a catalyst remover (ICP Postdip RP-C, manufactured by Okuno Chemical Industries Co., Ltd.) at 25°C for 1 minute, and then immersed in an electroless plating solution (Melplate NI-867, manufactured by Meltex) at 73°C for 3 minutes, whereby nickel phosphorus was deposited on the copper plating to produce fine plated wiring with a copper wiring protective layer, and a laminate was obtained.

[0093] [Gold Plating Step] The substrate was then immersed in an electroless plating solution (Flash Gold NC, manufactured by Okuno Chemical Industries Co., Ltd.) at 55° C. for 4 minutes to deposit displacement gold plating, thereby producing fine plated wiring as source / drain electrodes.

[0094] The electrode surface was subjected to UV cleaning for 8 minutes, ultrasonic cleaning in IPA (45 kHz, 3 minutes), and then heated and dried for 60 minutes at 120° C. Next, the substrate was immersed in a 0.75 wt % ethanol solution of TFTFMBT (2,3,5,6-tetrafluoro-4-(trifluoromethyl)benzenethiol, manufactured by Tokyo Chemical Industry Co., Ltd.) at room temperature for 5 minutes, removed, rinsed with ethanol, and dried with a nitrogen spray to form a gold-thiol SAM film on the electrode surface.

[0095] Next, a 0.2 / 0.45 wt % xylene solution of polystyrene (manufactured by Merck) / organic semiconductor (Ph-BTBT-10, 2-decyl-7-phenyl[1]benzothieno[3,2-b][1]benzothiophene, manufactured by Tokyo Chemical Industry Co., Ltd.) was applied using a heated spin coater at 145°C and 3000 rpm, and dried at 120°C for 10 minutes and then at 100°C for 60 minutes to prepare an organic semiconductor layer.

[0096] The copper fine wiring processed on the film is shown in Figure 8. Even on the film, uniform and smooth copper plating was achieved, and good patterning was possible without peeling even after wiring processing.

[0097] The fabricated source / drain electrode structure is shown in Figure 9. It shows that the entire TFT integrated shape was patterned in detail, and that Au layer plating was selectively formed only in the Cu plated areas.

[0098] Figure 10 shows the results of evaluation of the transfer characteristics of the fabricated OTFT (channel length L = 20 μm, channel width W = 500 μm). It shows that the OTFT operates normally even on a film substrate.

Claims

1. A laminate comprising, in this order, a substrate, an amine generating layer, a copper wiring layer, and a copper wiring protection layer.

2. The laminate according to claim 1, further comprising a layer containing palladium between the copper wiring layer and the amine generating layer.

3. The laminate according to claim 1 or 2, further comprising a gold plating layer on the copper wiring protection layer.

4. A transistor comprising the laminate according to claim 1 or 2 and an organic semiconductor layer.

5. A method for manufacturing a laminate, comprising the steps of: applying a photosensitive surface treatment agent onto a substrate to form a photosensitive resin film, exposing the photosensitive resin film to light, and forming an amine generating layer having an amine generating region in an exposed portion; forming a first catalyst layer on the amine generating layer, and then performing electroless copper plating to form a copper plating layer; forming a photoresist layer on the copper plating layer, exposing the photoresist layer to a pattern to form an exposed portion corresponding to a copper wiring layer pattern, and removing the photoresist layer in an unexposed portion; removing a portion of the copper plating layer to form a copper wiring layer, forming a preliminary pattern having a photoresist layer on the copper wiring layer, contacting the preliminary pattern with a catalyst remover to remove the first catalyst layer present in openings in the photoresist; removing the photoresist layer on the copper wiring layer; and forming a second catalyst layer on the copper wiring layer, and then performing electroless plating to form a copper wiring protection layer.

6. A method for manufacturing a transistor, comprising the method for manufacturing a laminate according to claim 5.

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