Gate drive device

Abstract

A gate drive device (100a) performs on / off control of a plurality of serially connected first and second semiconductor switching elements (1Q1, Q2) in accordance with a common drive control signal (Sdr). First and second drive units (GDU(1), GDU(2)) start the turn-off of each of the first and second semiconductor switching elements (Q1, Q2) in accordance with a change in the preset signal level of first and second control signals (Sd(1), Sd(2)). On the occasion of a turn-off command by the drive control signal (Sdr), a timing adjustment circuit (120a) generates the first and second control signals (Sd(1), Sd(2)) so as to provide a variable time difference that depends on a current value (Ic*) before turn-off between the timing of the signal level change in each of the first and second control signals (Sd(1), Sd(2)).

Description

Gate Driver

[0001] The present disclosure relates to a gate driver for a semiconductor switching element.

[0002] In power conversion devices using semiconductor switching elements, configurations in which multiple semiconductor switching elements are connected in series have been considered to accommodate higher voltages. For example, Japanese Patent No. 3724255 (Patent Document 1) describes a gate drive circuit that is applied when each arm of a power conversion device is configured by connecting voltage-driven switching elements in series.

[0003] The gate drive circuit described in Patent Document 1 can prevent element destruction by suppressing overvoltage caused by voltage imbalance due to differences in the turn-off timing of each semiconductor switching element. Specifically, when turning off two semiconductor switching elements connected in series, if the gate drive circuit detects an overvoltage in the semiconductor switching element that turned off earlier, it turns on the semiconductor switching element in which the overvoltage occurred again, thereby preventing element destruction.

[0004] Patent No. 3724255

[0005] However, in the gate drive circuit of Patent Document 1, it is basically assumed that when an IGBT (Insulated Gate Bipolar Transistor) is turned on again in response to overvoltage detection, the IGBT is operated in a non-saturation region (active region).

[0006] Therefore, a current path is formed between the re-turned-on IGBT and the other IGBT whose turn-off is delayed, and there is a concern that the loss in the re-turned-on IGBT will increase.

[0007] Therefore, in the technology of Patent Document 1, if the order in which multiple semiconductor switching elements connected in series are actually turned off is fixed, it is assumed that a specific semiconductor switching element will be the target for re-on. As a result, while overvoltage can be suppressed, there is a concern that the temperature may increase due to the concentration of losses. There is also a concern that the efficiency of the power converter may decrease.

[0008] The present disclosure has been made to solve such problems, and an object of the present disclosure is to suppress overvoltage without increasing losses in the semiconductor switching elements when multiple semiconductor switching elements connected in series are turned off in common.

[0009] According to one aspect of the present invention, a gate drive device for a plurality of semiconductor switching elements connected in series includes a plurality of drive circuits arranged corresponding to the plurality of semiconductor switching elements, respectively. A plurality of control signals are input to the plurality of drive circuits, and each drive circuit is configured to initiate turn-off of a corresponding semiconductor switching element in response to a predetermined signal level change of each input control signal. The timing adjustment circuit is configured to, when the plurality of semiconductor switching elements are turned off by a common drive control signal, provide a variable time difference between the timings of the signal level changes of the plurality of control signals, the time difference depending on the current values ​​of the plurality of semiconductor switching elements before the turn-off.

[0010] According to the present disclosure, when multiple semiconductor switching elements connected in series are turned off in common, by providing a time difference that is variably set according to the current value before the turn-off of the multiple semiconductor switching elements by the multiple drive circuits, it is possible to suppress overvoltage without increasing losses in the semiconductor switching elements.

[0011] 10 is a schematic configuration diagram of a power conversion device to which a gate drive circuit according to a comparative example is applied. FIG. 11 is a conceptual waveform diagram illustrating an example of operation of the gate drive device according to the comparative example. FIG. 12 is a schematic configuration diagram of a gate drive device according to embodiment 1. FIG. 13 is a schematic diagram illustrating an example of the configuration of a test circuit for the gate drive device according to the present embodiment. FIG. 14 is a conceptual diagram illustrating the relationship between the turn-off timing difference between semiconductor switching elements connected in series and the applied voltage in the off state. FIG. 15 is a graph illustrating an example of test results in the test circuit shown in FIG. 4. FIG. 16 is a graph illustrating an example of setting characteristics of the time difference (delay amount) based on the test results of FIG. 6. FIG. 17 is a block diagram illustrating an example of the configuration of the timing adjustment circuit shown in FIG. 6. FIG. 18 is a schematic waveform diagram illustrating an example of operation of the timing adjustment circuit shown in FIG. 8. FIG. 19 is a schematic configuration diagram of a gate drive device according to a modified example of embodiment 1. FIG. 19 is a block diagram illustrating an example of the configuration of the timing adjustment circuit shown in FIG. 10. FIG. 19 is a schematic configuration diagram of a gate drive device according to embodiment 2. FIG. 20 is a block diagram illustrating an example of the configuration of the timing adjustment circuit shown in FIG. 12. FIG. 21 is a graph illustrating another example of setting characteristics of the time difference (delay amount). FIG. 21 is a schematic configuration diagram of a gate drive device according to embodiment 2. FIG. 22 is a block diagram illustrating an example of the configuration of the timing adjustment circuit shown in FIG. 10. FIG. 23 is a schematic configuration diagram of a gate drive device according to embodiment 3. Fig. 18 is a block diagram illustrating a configuration example of the timing adjustment circuit shown in Fig. 17. Fig. 19 is a block diagram illustrating a schematic configuration of a gate drive device according to a modification of embodiment 3. Fig. 20 is a block diagram illustrating a configuration example of the timing adjustment circuit shown in Fig. 19.

[0012] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the following, the same or corresponding parts in the drawings will be denoted by the same reference numerals, and their description will not be repeated in principle.

[0013] First Embodiment (Description of a Comparative Example) First, a comparative example will be described in detail with reference to FIGS. 1 and 2 to explain the problems with Patent Document 1. FIG.

[0014] FIG. 1 is a schematic diagram of a power conversion device 10 to which a gate drive device according to a comparative example is applied.

[0015] 1, the power conversion device 10 includes semiconductor switching elements Q1 to Q4 each composed of an IGBT, and gate drive units GDU1 to GDU4 and re-on control units RTU1 to RTU4, which are arranged corresponding to the semiconductor switching elements Q1 to Q4, respectively. Each of the semiconductor switching elements Q1 to Q4 has an RC snubber circuit arranged between the positive terminal (collector) and the negative terminal (emitter). In the comparative example, the gate drive units GDU1 to GDU4 and the re-on control units RTU1 to RTU4 form a gate drive device for the semiconductor switching elements Q1 to Q4.

[0016] The semiconductor switching elements Q1 and Q2 are connected in series between a positive-side power supply line PL connected to the positive electrode of the DC power supply 2 and an output node No. The gate drive units GDU1 and GDU2 control the gate voltages of the semiconductor switching elements Q1 and Q2 in response to a drive control signal Sdr1, thereby controlling the on / off of the semiconductor switching elements Q1 and Q2.

[0017] The semiconductor switching elements Q3 and Q4 are connected in series between a negative-side power supply line NL connected to the negative electrode of the DC power supply 2 and an output node No. The gate drive units GDU3 and GDU4 control the gate voltages of the semiconductor switching elements Q3 and Q4 in accordance with a drive control signal Sdr2, thereby controlling the on / off of the semiconductor switching elements Q3 and Q4.

[0018] In this way, the series-connected semiconductor switching elements Q1 and Q2 are turned on and off in response to a common drive control signal Sdr1. Similarly, the series-connected semiconductor switching elements Q3 and Q4 are turned on and off in response to a common drive control signal Sdr2.

[0019] The capacitors C1 and C2 are connected in series between the power supply wiring PL and NL via the diodes D1 and D2. A resistor R1 is connected between the power supply wiring PL and the capacitor C2 (positive electrode), and a resistor R2 is connected between the power supply wiring NL and the capacitor C1 (negative electrode). This allows each of the capacitors C1 and C2, which have the same capacitance, to hold a voltage equivalent to the output voltage E of the DC power supply 2.

[0020] As a result, the voltage applied to each of the semiconductor switching elements Q1 to Q4 when it is turned off is (E / 2), which is the voltage of the capacitors C1 and C2 shared by the two series-connected semiconductor switching elements. In this way, by commonly controlling the on / off of the multiple series-connected semiconductor switching elements, the voltage applied after turn-off is complete (off state) can be shared by the multiple semiconductor switching elements. This makes it possible to accommodate higher voltages, for example, in FIG. 1, to accommodate an increase in the output voltage E of the DC power supply 2, without increasing the withstand voltage of each semiconductor switching element.

[0021] However, Patent Document 1 points out that a difference in the actual turn-off timing in response to a common drive control signal occurs between multiple (two) semiconductor switching elements connected in series, which can cause an overvoltage to occur in the semiconductor switching element that is turned off earlier.

[0022] To address this problem, the gate driver according to the comparative example shown in FIG. 1 includes re-on control units RTU1 to RTU4 for re-oning the semiconductor switching elements Q1 to Q4 when an overvoltage occurs between the positive and negative terminals of the semiconductor switching elements Q1 to Q4 after the turn-off operation.

[0023] 2 is a conceptual waveform diagram illustrating an example of the operation of a gate drive device according to a comparative example, in which an operating waveform example is shown for a case in which semiconductor switching element Q1 turns off first when a common turn-off command is issued to semiconductor switching elements Q1 and Q2 in FIG.

[0024] As shown in FIG. 2 , before time t0, a predetermined on-voltage, which is a voltage higher than the voltage at the negative terminal, is supplied to the gates of the semiconductor switching elements Q1 and Q2. This causes the semiconductor switching elements Q1 and Q2 to be in the on state. In the on state, an on-current Ion (Ic=Ion) flows through the semiconductor switching elements Q1 and Q2. Furthermore, in each of the semiconductor switching elements Q1 and Q2 (in the on state), the voltage Vce between the positive terminal (collector) and the negative terminal (emitter) is zero (Vce(Q1)=Vce(Q2)=0).

[0025] At time t0, in response to a signal level change (e.g., a change from L level to H level) of the drive control signal Sdr common to the semiconductor switching elements Q1 and Q2 shown in FIG. 1, the gate drive units GDU1 and GDU2 start turning off the semiconductor switching elements Q1 and Q2.

[0026] After starting to turn off, the gate drive units GDU1 and GDU2 supply an off voltage, which is equal to or lower than the voltage at the negative terminal, to the gates of the semiconductor switching elements Q1 and Q2. As a result, when the gate voltage drops below the threshold voltage of the semiconductor switching element, the semiconductor switching element changes to the off state.

[0027] In the operation example of FIG. 2, it is assumed that a difference (Δt) occurs between the actual turn-off timings of the semiconductor switching elements Q1 and Q2 due to a difference in characteristics between the semiconductor switching elements Q1 and Q2 caused by manufacturing variations or the like, typically a difference in threshold voltage.

[0028] After the start of turn-off at time t0, semiconductor switching element Q1 quickly turns off, causing the voltage Vce(Q1) between the positive terminal (collector) and the negative terminal (emitter) to rise. In contrast, semiconductor switching element Q2, which is delayed in turning off, is still on, so the voltage Vce(Q2) remains at 0.

[0029] At time t1, when Vce(Q1) of the semiconductor switching element Q1 rises to a threshold voltage Vov for detecting an overvoltage, the re-on control unit RTU1 operates, causing the gate drive unit GDU1 to re-on the semiconductor switching element Q1. The threshold voltage Vov is set to be at least higher than the voltage (here, E / 2) that each of the semiconductor switching elements Q1 and Q2 should bear in the turned-off state.

[0030] At this time, in Patent Document 1, the semiconductor switching element Q1 (IGBT) is turned on again so as to operate in a non-saturation region (active region) rather than the saturation region used during normal on-state. In response to this turning on again, the voltage Vce (Q1) exhibits a behavior of gradually decreasing.

[0031] At time t2, which is Δt after time t0, semiconductor switching element Q2 actually starts to turn off, causing voltage Vce(Q2) to begin to rise. Then, at time t3, voltage Vce(Q1) of semiconductor switching element Q1, which has been turned on again, is turned off again. As both semiconductor switching elements Q1 and Q2 turn off, current Ic begins to decrease, and at time t4, the turn-off of both semiconductor switching elements Q1 and Q2 is completed, causing current Ic to become 0.

[0032] By this operation of turning semiconductor switching element Q1 on again and then off, after time t4 when the turn-off is completed, the voltages Vce(Q1) and Vce(Q2) between semiconductor switching elements Q1 and Q2, i.e., the applied voltages in the off state, are equal (approximately E / 2).

[0033] However, in the comparative example, during the re-on period of the semiconductor switching element Q1 (times t1 to t3), the loss of the semiconductor switching element Q1 operating in the non-saturation region (active region) becomes higher than the loss of the semiconductor switching element Q2 before it is turned off, which raises concerns that the loss will be concentrated in the semiconductor switching element Q1.

[0034] 13 (Embodiment 5) of Patent Document 1 describes a timing control in which, when an overvoltage is detected during turn-off and the semiconductor switching element is turned on again, the turn-off timing of the semiconductor switching element is delayed by a predetermined time at the time of the next turn-off command, due to the arrangement of a timing adjustment circuit. However, there is a concern that this timing control makes it difficult to optimize the turn-off timing delay time according to switching.

[0035] 3 is a schematic configuration diagram of a gate driver 100a according to embodiment 1. The gate driver 100a turns on and off two (plural) semiconductor switching elements Q1 and Q2 connected in series in accordance with a common drive control signal Sdr.

[0036] In this embodiment, the semiconductor switching elements Q1 and Q2 are configured as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). That is, the semiconductor switching elements Q1 and Q2 are turned on and off by controlling the gate voltages of the gate drive device 100a, thereby varying the voltage Vds and current Id between the positive terminal (drain: D) and the negative terminal (source: S). The positive terminal corresponds to the "current inflow terminal," and the negative terminal corresponds to the "current outflow terminal." Note that in this embodiment, the semiconductor switching elements are not limited to MOSFETs and may be configured as IGBTs, as in the comparative example (Patent Document 1). The gate drive device according to this embodiment can be applied to any number of semiconductor switching elements connected in series.

[0037] The gate drive device 100a includes drive units GDU(1) and GDU(2) corresponding to the semiconductor switching elements Q1 and Q2, interface (I / F) circuits 110(1) and 110(2), and a timing adjustment circuit 120a. The drive unit GDU(1) and the I / F circuit 110(1) constitute an example of a "drive circuit" for the semiconductor switching element Q1. Similarly, the drive unit GDU(2) and the I / F circuit 110(2) constitute an example of a "drive circuit" for the semiconductor switching element Q2.

[0038] Furthermore, the gate driver 100a may include gate voltage adjustment circuits GVC(1) and GVC(2) corresponding to the semiconductor switching elements Q1 and Q2, respectively, and a current detector 31 for detecting a current Id passing through the series-connected semiconductor switching elements Q1 and Q2.

[0039] The drive units GDU(1) and GDU(2) have the same configuration, and the gate voltage adjustment circuits GVC(1) and GVC(2) have the same configuration. Therefore, the configurations of the drive unit GDU(1) and gate voltage adjustment circuit GVC(1) provided corresponding to the semiconductor switching element Q1 will be representatively described.

[0040] The drive unit GDU(1) has a P-type transistor 11, an N-type transistor 12, and gate resistors 13 and 14. The P-type transistor 11 is connected in series with the gate resistor 13 between a power supply line PLon that supplies an on-voltage Eon and a node Ng that is connected to the gate of the semiconductor switching element Q1. The gate resistor 13 is connected between the drain of the P-type transistor 11 and the node Ng. A signal is input to the gate of the P-type transistor 11 from the I / F circuit 110(1).

[0041] N-type transistor 12 is connected in series with gate resistor 14 between node Ng and a power supply line PLoff that supplies an off-voltage Eoff. Gate resistor 14 is connected between the drain of N-type transistor 12 and node Ng. A signal from I / F circuit 110(1) is input to the gate of N-type transistor 12.

[0042] DC power supplies 15 and 16 are connected in series between power supply lines PLon and PLoff via a node Ns having the same potential as the negative terminal (source) of semiconductor switching element Q1. Power supply line PLon is connected to the positive terminal of DC power supply 15, thereby supplying an ON voltage Eon for turning on semiconductor switching element Q1. Meanwhile, power supply line PLoff is connected to the negative terminal of DC power supply 16, thereby supplying an OFF voltage Eoff for turning off semiconductor switching element Q1.

[0043] As described above, the drive control signal Sdr is set to L level during the ON period of the semiconductor switching elements Q1 and Q2, and is set to H level during the OFF period. That is, in this embodiment, a turn-off command for the semiconductor switching elements Q1 and Q2 is generated in response to a signal level change of the drive control signal Sdr from L level to H level. Therefore, the L level of the drive control signal Sdr corresponds to an example of a "first level," and the H level corresponds to an example of a "second level."

[0044] The I / F circuit 110(1) generates gate signals for the P-type transistor 11 and the N-type transistor 12 in accordance with the control signal Sd(1) from the timing adjustment circuit 120a. While the control signal Sd(1) is at the L level, the I / F circuit 110(1) turns on the P-type transistor 11, while setting the gate signals for the P-type transistor 11 and the N-type transistor 12 to the L level in order to turn off the N-type transistor 12.

[0045] On the other hand, during the H level period of the control signal Sd(1), the gate signals of the P-type transistor 11 and the N-type transistor 12 are set to H level to turn off the P-type transistor 11 and turn on the N-type transistor 12. For example, the I / F circuit 110(1) can be configured with a signal buffer that outputs signals of the same logic as the control signal Sd(1) as the gate signals. This allows the semiconductor switching element Q1 to be turned on and off in accordance with the control signal Sd(1).

[0046] The gate voltage adjustment circuit GVC(1) is configured to adjust the voltage of the node Ng (gate of the semiconductor switching element Q1) in accordance with the voltage Vds between the positive terminal (drain) and the negative terminal (emitter: E) of the semiconductor switching element Q1 so as to suppress an overvoltage. Specifically, in this embodiment, the gate voltage adjustment circuit GVC(1) is configured to include a voltage divider circuit 21, a voltage comparator 22, and a P-type transistor 23.

[0047] The voltage divider circuit 21 divides the voltage Vds of the semiconductor switching element Q1 and outputs a divided voltage Vdiv. Using the voltage division ratio Kv (0<Kv<1.0) of the voltage divider circuit 21, Vdiv is expressed as Vdiv=Kv·Vds. The voltage comparator 22 compares the divided voltage Vdiv from the voltage divider circuit 21 with a reference voltage Vref and outputs an overvoltage detection signal Sov. The reference voltage Vref is expressed as Vref=Kv·Vov, where Vov is the reference voltage in FIG. 2 (comparative example).

[0048] The voltage comparator 22 sets the overvoltage detection signal Sov to the L level when Vdiv>Vref, i.e., when an overvoltage of Vce>Vov occurs. On the other hand, when an overvoltage of Vce≦Vov does not occur, the overvoltage detection signal Sov is set to the H level. The P-type transistor 23 is connected between the power supply line PLon and the node Ng, and receives the overvoltage detection signal Sov from the voltage comparator 22 at its gate.

[0049] Therefore, if an overvoltage (Vds>Vov) occurs after drive unit GDU(1) supplies off-voltage Eoff in response to a turn-off command, P-type transistor 23 turns on, thereby supplying on-voltage Eon to node Ng. This makes it possible to re-on semiconductor switching element Q1 after the turn-off command is generated. That is, voltage divider circuit 21 and voltage comparator 22 constitute an embodiment of an "overvoltage detection circuit," and P-type transistor 23 constitutes an embodiment of a "re-on circuit." That is, overvoltage detection signal Sov from voltage comparator 22 corresponds to an embodiment of a "re-on request signal."

[0050] 3, the semiconductor switching element Q1 (MOSFET) is turned on again by the on-voltage Eon common to the drive unit GDU(1), and therefore it is understood that it operates in the saturation region (corresponding to the linear region in an IGBT). Note that the gate voltage adjustment circuit GVC(1) is not limited to the example configuration of FIG. 3 and can have any configuration as long as it is possible to adjust the gate voltage (voltage at node Ng) so as to suppress overvoltage of the semiconductor switching element Q1.

[0051] A drive unit GDU(2) similar to the drive unit GDU(1) and a gate voltage adjustment circuit GVC(2) similar to the gate voltage adjustment circuit GVC(1) are arranged for the semiconductor switching element Q2. The I / F circuit 110(2) controls the drive unit GDU(2) in accordance with a control signal Sd(2) from the timing adjustment circuit 120a. This turns the semiconductor switching element Q2 on and off in accordance with the control signal Sd(2).

[0052] The timing adjustment circuit 120a receives the current value Ic* and the drive control signal Sdr during the on-period before the turn-off command for the semiconductor switching elements Q1 and Q2. Based on the drive control signal Sdr, the timing adjustment circuit 120a generates control signals Sd(1) and Sd(2) with a time difference tdf (delay) corresponding to the current value Ic*. For example, the drive control signal Sdr is used as is for the control signal Sd(1) for the semiconductor switching element Q1, and the control signal Sd(2) for the semiconductor switching element Q2 can be generated by delaying the drive control signal Sdr.

[0053] This allows the control signal Sd(2) to be a signal obtained by delaying the control signal Sd(1) by the time difference tdf. As a result, when a turn-off command for the semiconductor switching elements Q1 and Q2 is generated, the start timing of the turn-off operation for the semiconductor switching element Q2 by the drive unit GDU(2) can be delayed by the time difference tdf relative to the start timing of the turn-off operation for the semiconductor switching element Q1 by the drive unit GDU(1).

[0054] The current value Ic* indicates the current value at which the semiconductor switching elements Q1 and Q2 are turned off, and can be set, for example, using the value of the current Id detected by the current detector 31 before the semiconductor switching elements Q1 and Q2 are turned off. Alternatively, in a configuration in which the current Id from the semiconductor switching elements Q1 and Q2 in the ON state is supplied to a load (not shown), the current detector 31 can be disposed in the load to determine the current value Ic*. Alternatively, the current value Ic* may be determined using a command value for the current supplied to the load.

[0055] This embodiment is characterized in that the time difference between the start timing of the turn-off operation provided between drive units GDU(1) and GDU(2) is set to be variable depending on the current value Ic*, thereby equalizing the voltage Vds applied to semiconductor switching elements Q1 and Q2 after turn-off is completed.

[0056] As described above, possible causes of the difference in turn-off timing in response to the turn-off command by the common drive control signal Sdr include differences in characteristics (threshold voltage, etc.) between the semiconductor switching elements Q1 and Q2, as well as differences in drive speed between the drive units GDU(1) and GDU(2) (for example, differences in propagation delay between the control signals Sd(1) and Sd(2), differences in drive force of the N-type transistor 12, or differences in resistance value of the gate resistor 13). Generally, semiconductor switch elements and corresponding drive units are often integrated into the same module. Therefore, in this embodiment, the above-mentioned time difference tdf is set based on the results of an actual test of the turn-off of pairs of semiconductor switch elements and drive units. It should be noted that this actual test can be carried out without being limited to a situation in which the pairs of semiconductor switch elements and drive units are actually integrated into the same module.

[0057] FIG. 4 is a schematic diagram illustrating an example of the configuration of a test circuit for the gate drive device according to this embodiment.

[0058] 4, the test circuit 50 can be configured as a power conversion device that supplies current to an inductive load RL connected to an output node No. The test circuit 50 includes semiconductor switching elements Q1 and Q2 connected in series, diodes Da and Db, gate drive circuits 111 and 112, and a timing adjustment circuit 120 for applying an adjustable time difference.

[0059] The semiconductor switching elements Q1 and Q2 are connected in series between the positive power supply line PL and the output node No. When the semiconductor switching elements Q1 and Q2 are in the off state, voltages Vds1 and Vds2 are generated between the positive terminals (drains) and negative terminals (sources), while the current Id is 0. When the semiconductor switching elements Q1 and Q2 are in the on state, the voltages Vds1 and Vds2 are 0, while the current Id is generated (Id > 0).

[0060] The diodes Da and Db are connected between the output node No and the power supply line NL. The diodes Da and Db may be arranged as diode elements, or may be formed when the semiconductor switching elements Qa and Qb connected in series are turned off.

[0061] The load RL is connected between the output node No and the negative power supply line NL. As described above, the current detector 31 may be arranged to detect the current IL of the load RL. The test circuit 50 operates under the condition that the drive control signal Sdr is generated so that the current IL is controlled in accordance with the current command value ILref.

[0062] The timing adjustment circuit 120 generates control signals Sd(1) and Sd(2) for the semiconductor switching elements Q1 and Q2 in accordance with the drive control signal Sdr. At this time, the timing adjustment circuit 120 is configured to provide a time difference tdf between the control signals Sd(1) and Sd(2) that is adjustable in accordance with the test input Tstin.

[0063] Gate drive circuit 111 corresponds to the combination of drive unit GDU(1) and I / F circuit 110(1) in Fig. 3 and turns on and off semiconductor switching element Q1 in accordance with control signal Sd(1). Similarly, gate drive circuit 112 corresponds to the combination of drive unit GDU(2) and I / F circuit 110(2) in Fig. 3 and turns on and off semiconductor switching element Q2 in accordance with control signal Sd(2). As a result, test circuit 50 can provide an arbitrary time difference tdf corresponding to test input Tstin between the start timings of the turn-off operations of semiconductor switching elements Q1 and Q2.

[0064] In the test circuit 50, when the drive control signal Sdr is at an L level (before a turn-off command is issued), a current Id passing through the on-state semiconductor switching elements Q1 and Q2 is supplied to the load RL. That is, IL = Id holds. When the drive control signal Sdr changes from an L level to an H level in this state, the semiconductor switching elements Q1 and Q2 execute a turn-off operation to cut off the current Id.

[0065] FIG. 5 is a conceptual diagram illustrating the relationship between the difference in turn-off timing between series-connected semiconductor switching elements and the applied voltage in the off state.

[0066] 5 shows the circuit operation when, from a state in which current Id is flowing through semiconductor switching elements Q1 and Q2, semiconductor switching element Q2 is turned off before semiconductor switching element Q1. That is, in the first embodiment, of the two series-connected semiconductor switching elements Q1 and Q2, the one that actually turns off later when turned off in response to a common drive control signal Sdr is defined as semiconductor switching element Q1.

[0067] In this state, the current Id flows through a path between the drain and source of the semiconductor switching element Q1, which is still on, and the parasitic capacitance (output capacitance) Cds(2) between the drain and source of the semiconductor switching element Q2, which is off. As a result, the output capacitance Cds(1) of the semiconductor switching element Q1 is not charged, but the output capacitance Cds(2) is charged.

[0068] As a result, at the timing when semiconductor switching element Q1 actually starts to turn off after semiconductor switching element Q2 (corresponding to time t2 when semiconductor switching element Q2 starts to turn off in FIG. 2), a voltage difference occurs between output capacitances Cds(1) and Cds(2). After this timing, current Id decreases to zero while flowing through the series circuit of output capacitances Cds(1) and Cds(2).

[0069] Therefore, at the timing when the turn-off of semiconductor switching elements Q1 and Q2 is completed (time t4 in FIG. 2 ), the above-mentioned voltage difference remains between output capacitances Cds(1) and Cds(2), and this voltage difference causes a voltage difference between voltage Vds1 of semiconductor switching element Q1 and voltage Vds2 of semiconductor switching element Q2. This voltage difference corresponds to the voltage difference between Vce(Q1) and Vce(Q2) after time t4 in FIG. 2 , i.e., the applied voltage difference after the turn-off of semiconductor switching elements Q1 and Q2 is completed (off state) (hereinafter also referred to as the “post-off voltage difference Vdf”).

[0070] Since the rate of voltage rise of the output capacitances Cds(1) and Cds(2) changes depending on the value of the current Id that is cut off by turning off, it can be understood that even if the time difference tdf between the control signals Sd(1) and Sd2(2) is the same, the post-turn-off voltage difference Vdf changes depending on the value of the current Id.

[0071] 6 is a graph showing an example of test results obtained by the test circuit 50. The horizontal axis of FIG. 6 represents the current Id (or current IL) of the semiconductor switching elements Q1 and Q2 before they are turned off, and the vertical axis represents the voltage difference Vdf after the semiconductor switching elements Q1 and Q2 are turned off.

[0072] 6 plots the relationship between the current value (currents Id, IL) and the post-off voltage difference Vdf when the time difference tdf applied by the timing adjustment circuit 120 is set to T1 to T5 (T1<T2<T3<T4<T5). In FIG. 6, plotted points under the same time difference tdf are connected by dotted lines.

[0073] The time difference tdf is represented by the delay time of the change in the control signal Sd(2) of the semiconductor switching element Q2 from L level to H level relative to the change in the control signal Sd(1) of the semiconductor switching element Q1, which is assumed to be turned off with a delay. The post-off voltage difference Vdf is defined as (Vds1 - Vds2) after the turn-off is completed.

[0074] By providing a time difference tdf, a bias in the direction of charging the output capacitance Cds(1) of the semiconductor switching element Q1, i.e., a bias that increases Vds1 after turn-off, can be applied, and therefore the post-turn-off voltage difference Vdf increases in Figure 6. Furthermore, the greater the turn-off current value, the greater the rate of voltage increase of the output capacitance Cds(1), and therefore the greater the effect of this bias.

[0075] Therefore, as shown in FIG. 6, in regions where the time difference tdf is small and where the current value is small, the bias effect due to the time difference tdf is small, and therefore, due to the difference in turn-off behavior between the semiconductor switching elements Q1 and Q2 described in FIG. 4, there is a tendency for Vce2>Vce1, i.e., Vdf<0, after turn-off is complete.

[0076] On the other hand, as the time difference tdf increases or the current value increases, the bias effect described above increases, causing the post-off voltage difference Vdf to increase. Therefore, at the same current value, the post-off voltage difference Vdf increases as the time difference tdf increases. Furthermore, at the same time difference tdf, the post-off voltage difference Vdf increases as the current value increases.

[0077] As a result, it is possible to determine the current value at which Vdf=0 at each level (T1 to T5) of the time difference tdf set by the test input Tstin shown in Fig. 6. In Fig. 6, the current value corresponds to the intersection of each dotted line when tdf=T1 to T5 and Vdf=0.

[0078] Fig. 7 is a graph illustrating an example of the setting characteristics of the time difference tdf (delay amount) based on the test results of Fig. 6. The horizontal axis of Fig. 7 represents the current value of the semiconductor switching elements Q1 and Q2 before turn-off, as in Fig. 6, and the vertical axis represents the appropriate value of the time difference tdf (delay amount).

[0079] 7, current values ​​at which Vdf=0 at time differences T1 to T5 are plotted, corresponding to the intersections of the dotted lines (tdf=T1 to T5) in FIG. 6 with Vdf=0. By performing function approximation on these plotted points, it is possible to determine the setting characteristic CHL1 of Id(IL)-tdf for constructing a table (hereinafter referred to as the delay amount table) for outputting the time difference tdf provided by the timing adjustment circuit 120a, using the current value Ic* in FIG. 3 as an input. As can be seen from FIG. 7, the larger the current value Ic*, the shorter the time difference tdf is set.

[0080] In the example of Fig. 7, the set characteristic CHL1 is determined so as to approximate a function equation (inversely proportional) in which the product of the current and the time difference is constant, corresponding to the charge amounts of the output capacitances Cds(1) and Cds(2). Alternatively, by increasing the number of levels of the time difference tdf in the experiment of Fig. 6 and increasing the number of plotted points in Fig. 7, the set characteristic CHL1 can be determined by simple linear interpolation or linear extrapolation between the plotted points.

[0081] Fig. 8 is a block diagram illustrating an example of the configuration of the timing adjustment circuit 120a shown in Fig. 6. As described above, the timing adjustment circuit 120a generates the control signal Sd(2) based on the drive control signal Sdr so as to provide an appropriate time difference tdf between the start timings of the turn-off operations of the semiconductor switching elements Q1 and Q2.

[0082] As shown in FIG. 8, the timing adjustment circuit 120 a includes a delay amount table 121 , a rate limiter 122 , a D / A (Digital to Analog) converter 123 , and a voltage comparator 125 .

[0083] The delay amount table 121 stores a predetermined set characteristic CHL1 (FIG. 7) and is configured to output a time difference (delay amount) tdf corresponding to the current value Ic* input to the timing adjustment circuit 120a in accordance with the stored set characteristic CHL1.

[0084] The following description will be given assuming that the delay table 121 receives a digitally converted value of the current value Ic* and outputs a digital value of the time difference (delay amount) tdf. The D / A converter 123 outputs a reference voltage Vtdf, which is an analog voltage proportional to the time difference tdf output from the delay table 121. The delay table 121 corresponds to one embodiment of a "characteristics storage unit."

[0085] The rate limiter 122 receives the drive control signal Sdr as an input, and outputs an input voltage Vin to the voltage comparator 125, with the rate of change from L level to H level limited.

[0086] The voltage comparator 125 outputs the control signal Sd(2) in accordance with the result of comparison between the input voltage Vin from the rate limiter 122 and the reference voltage Vtdf from the D / A converter 123. On the other hand, the control signal Sd(1) is generated using the drive control signal Sdr as is.

[0087] FIG. 9 is a schematic waveform diagram illustrating an example of the operation of the timing adjustment circuit 120a shown in FIG.

[0088] 9, at time t0, the drive control signal Sdr changes from L level to H level, thereby issuing a turn-off command to the semiconductor switching elements Q1 and Q2. The control signal Sd(1) for the semiconductor switching element Q1 changes from L level to H level at time t0 in accordance with the drive control signal Sdr. As a result, the turn-off of the semiconductor switching element Q1 begins at time t0. Time t0 corresponds to the "reference timing."

[0089] The input voltage Vin output from the rate limiter 122 increases from time t0 at a constant voltage rate Kvin [V / s], which corresponds to the upper rate limit set by the rate limiter 122. During the period (times t0 to tx) in which the input voltage Vin is lower than the reference voltage Vtdf, the control signal Sd(2) is set to L level. In contrast, during the period (after time tx) in which the input voltage Vin is higher than the reference voltage Vtdf, the control signal Sd(2) changes to H level. Therefore, the turn-off of the semiconductor switching element Q2 begins at time tx.

[0090] The proportionality coefficient in the D / A converter 123 for generating the reference voltage Vtdf is set equal to the voltage rate Kvin by the rate limiter 122 (Vtdf = tdf · Kvin). As a result, the elapsed time from time t0 to time tx, i.e., the delay amount of the turn-off start timing of the semiconductor switching element Q2 relative to the turn-off start timing (reference timing) of the semiconductor switching element Q1, becomes equal to the time difference tdf set in the delay amount table 121 corresponding to the current value Ic*. Note that the entire function of the timing adjustment circuit 120a can also be configured by calculation of digital values. That is, the function of each timing adjustment circuit, including those in the following embodiments, can be realized by at least one of analog elements and digital elements (including software processing).

[0091] In the timing adjustment circuit 120a shown in FIG. 8, when the time difference tdf from the delay amount table 121 is 0, it is also possible to configure the circuit 120a to bypass the rate limiter 122 and the voltage comparator 125 and output the drive control signal Sdr as is as the control signal Sd(2).

[0092] As a result, with the gate drive device 100a according to the first embodiment, when a plurality of series-connected semiconductor switching elements Q1 and Q2 are turned off by a common drive control signal, a time difference (delay amount) can be provided between the timings at which the semiconductor switching elements Q1 and Q2 start to turn off, the time difference being variably set depending on the current value before the semiconductor switching elements Q1 and Q2 are turned off. This allows the time difference tdf to be appropriately set so as to equalize the applied voltages after the semiconductor switching elements Q1 and Q2 have been turned off, even if the operating states (current values ​​to be cut off) of the semiconductor switching elements Q1 and Q2 are different. As a result, overvoltage can be suppressed without increasing losses when the semiconductor switching elements Q1 and Q2 are turned off.

[0093] Furthermore, by providing the gate voltage adjustment circuits GVC(1) and GVC(2), if the actual voltage difference Vdf becomes large and an overvoltage occurs in one of the semiconductor switching elements Q1 and Q2 under the time difference tdf (delay amount) set by the delay amount table 121, the semiconductor switching element can be turned on again. This makes it possible to suppress the occurrence of an overvoltage in the semiconductor switching elements Q1 and Q2 after the turn-off is completed.

[0094] As is clear from the above explanation, the gate driver 100a can basically suppress overvoltage when the series-connected semiconductor switching elements Q1 and Q2 are turned off by appropriately setting the time difference tdf (delay amount) corresponding to the current value based on experimental results, etc. In other words, the provision of the gate voltage adjustment circuits GVC(1) and GVC(2) is not essential.

[0095] However, by further arranging gate voltage adjustment circuits GVC(1) and GVC(2), it is possible to suppress overvoltage even when there is a setting error in the time difference tdf (delay amount) according to the delay amount table 121 (setting characteristic CHL1).

[0096] Modification of First Embodiment In the first embodiment, the gate driver 100a is described as including two semiconductor switching elements Q1 and Q2 connected in series, but it is also possible to extend the number of semiconductor switching elements connected in series to three or more.

[0097] Fig. 10 is a schematic configuration diagram of a gate driver 100b according to a modification of embodiment 1. As shown in Fig. 10, the gate driver 100b controls the on / off of three semiconductor switching elements Q1 to Q3 connected in series in accordance with a common drive control signal Sdr.

[0098] The gate driver 100b includes drive units GDU(1) to GDU(3) corresponding to the semiconductor switching elements Q1 to Q3, I / F circuits 110(1) to 110(3), and a timing adjustment circuit 120b. The gate driver 100b may further include gate voltage adjustment circuits GVC(1) to GVC(3) corresponding to the semiconductor switching elements Q1 to Q3, respectively.

[0099] The configurations and functions of drive unit GDU(3) and I / F circuit 110(3) are similar to those of drive units GDU(1) and GDU(2) and I / F circuits 110(1) and 110(2). In Fig. 10, drive unit GDU(1) and I / F circuit 110(1) correspond to an embodiment of a "drive circuit" for semiconductor switching element Q1, drive unit GDU(2) and I / F circuit 110(2) correspond to an embodiment of a "drive circuit" for semiconductor switching element Q2, and drive unit GDU(3) and I / F circuit 110(3) correspond to an embodiment of a "drive circuit" for semiconductor switching element Q3.

[0100] The timing adjustment circuit 120b receives the current value Ic* and the drive control signal Sdr during the on period before the turn-off command of the semiconductor switching elements Q1 to Q3. In the modification of the first embodiment, the drive control signal Sdr is also used as the control signal Sd(1) for the semiconductor switching element Q1. The timing adjustment circuit 120b generates the control signals Sd(2) and Sd(3) so that a time difference tdf (delay) corresponding to the current value Ic* is applied to the drive control signal Sdr.

[0101] In a modification of the first embodiment, a test using the test circuit 50 shown in Fig. 4 can be applied to the semiconductor switching elements Q1 to Q3 connected in series. Of the three semiconductor switching elements Q1 to Q3, the one that turns off the slowest when turned off in response to a common drive control signal Sdr is defined as the semiconductor switching element Q1.

[0102] Furthermore, by obtaining test results equivalent to those shown in FIG. 6 for semiconductor switching elements Q2 and Q3 that have the characteristic of turning off earlier than semiconductor switching element Q1, it is possible to determine appropriate time differences (delay amounts) tdf2 and tdf3 relative to the turn-off start timing of semiconductor switching element Q1.

[0103] 7 can be set for each of the semiconductor switching elements Q2 and Q3. That is, it is possible to preset a setting characteristic CHL1(Q2) for setting the time difference tdf2 (amount of delay) of the semiconductor switching element Q2 using the current value Ic* as an input, and a setting characteristic CHL1(Q3) for setting the time difference tdf3 (amount of delay) of the semiconductor switching element Q3 using the current value Ic* as an input.

[0104] 6 and 7 can be obtained by conducting tests between semiconductor switching elements Q1 and Q2 and between semiconductor switching elements Q1 and Q3 similar to those in embodiment 1. Alternatively, it is also possible to obtain the set characteristics of semiconductor switching elements Q2 and Q3 shown in FIG. 7 based on measurement results obtained when semiconductor switching elements Q1 to Q3 are connected in series.

[0105] 11 is a block diagram illustrating an example of the configuration of the timing adjustment circuit 120b. As shown in FIG. 11, the timing adjustment circuit 120b includes delay amount tables 121(Q1) and 121(Q3), a rate limiter 122, D / A converters 123(2) and 123(3), and voltage comparators 125 and 126.

[0106] The delay amount table 121(Q2) stores a predetermined set characteristic CHL1(Q2). The delay amount table 121(Q2) is configured to output a time difference (delay amount) tdf2 corresponding to the current value Ic* input to the timing adjustment circuit 120b in accordance with the stored set characteristic CHL1(Q2). The D / A converter 123(2) outputs a reference voltage Vtdf2, which is an analog voltage proportional to the time difference tdf2 output from the delay amount table 121(Q2).

[0107] Similarly, the delay amount table 121(Q3) stores a predetermined set characteristic CHL1(Q3). The delay amount table 121(Q3) is configured to output a time difference (delay amount) tdf3 corresponding to the current value Ic* input to the timing adjustment circuit 120b in accordance with the stored set characteristic CHL1(Q3). The D / A converter 123(3) outputs a reference voltage Vtdf3, which is an analog voltage proportional to the time difference tdf3 output from the delay amount table 121(Q3).

[0108] The voltage comparator 125 outputs a control signal Sd(2) in accordance with the result of comparison between the input voltage Vin from the rate limiter 122, which is the same as in the first embodiment, and the reference voltage Vtdf2 from the D / A converter 123(2).

[0109] The voltage comparator 126 outputs the control signal Sd(3) in accordance with the result of comparison between the input voltage Vin from the rate limiter 122 and the reference voltage Vtdf3 from the D / A converter 123(3). On the other hand, the control signal Sd(1) is generated using the drive control signal Sdr as is.

[0110] As a result, the control signal Sd(2) is a signal obtained by delaying the control signal Sd(1) by a time difference tdf2, and the control signal Sd(3) is a signal obtained by delaying the control signal Sd(1) by a time difference tdf3. Therefore, when a turn-off command for the semiconductor switching elements Q1 to Q3 is generated, the timing at which the drive unit GDU(2) starts to turn off the semiconductor switching element Q2 can be delayed by the time difference tdf2 relative to the timing (reference timing) at which the drive unit GDU(1) starts to turn off the semiconductor switching element Q1. Furthermore, the timing at which the drive unit GDU(3) starts to turn off the semiconductor switching element Q3 can be delayed by the time difference tdf3 relative to the reference timing.

[0111] The timing adjustment circuit 120b can also be configured to output the drive control signal Sdr as the control signal Sd(2) when the time difference tdf2 from the delay amount table 121(Q2) is 0. Similarly, the timing adjustment circuit 120b can be configured to output the drive control signal Sdr as the control signal Sd(3) when the time difference tdf3 from the delay amount table 121(Q2) is 0.

[0112] As a result, according to the gate drive device 100b of the modified example of the first embodiment, when three semiconductor switching elements Q1 to Q3 connected in series are turned off by a common drive control signal, a time difference (amount of delay) can be provided between the turn-off start timings of the semiconductor switching elements Q1 to Q3, which is variably set depending on the current value before turn-off. As a result, even if the number of semiconductor switching elements connected in series increases, the same effects as those of the first embodiment can be achieved.

[0113] In the modified example of the first embodiment, the arrangement of the gate voltage adjustment circuits GVC(1) to GVC(3) is not essential, but they can be additionally arranged as a precaution in order to suppress overvoltage even when there is a setting error in the time differences tdf2, tdf3 (delay amounts) according to the current value Ic*.

[0114] It will be understood that in the modification of the first embodiment, even if the number of semiconductor switching elements is four or more, the same effect can be obtained by preparing the set characteristic CHL1 in Fig. 7 in accordance with the increase in the number. That is, the gate drive device 100a according to the first embodiment can be applied to a configuration in which a plurality of (two or more) series-connected semiconductor switching elements are commonly turned on and off, without limiting the number of semiconductor switching elements.

[0115] In the first embodiment, a configuration was described in which, among a plurality of semiconductor switching elements connected in series, the on / off control is performed using the drive control signal Sdr as is, and the semiconductor switching element that starts to turn off first is fixed. In such a configuration, after the timing adjustment circuits (120a, 120b) are implemented in the circuit, it is not possible to switch the semiconductor switching element that is the target of the turn-off delay.

[0116] This raises concerns that the flexibility of circuit implementation may be reduced. For example, if the implementation order is fixed, measures to prevent mix-ups during assembly are required, which may result in problems such as increased costs. In the second embodiment, a configuration will be described in which the semiconductor switching elements that are the targets of turn-off delay can be interchanged.

[0117] 12 is a schematic configuration diagram of a gate driving device 100c according to embodiment 2. As shown in FIG. 12, gate driving device 100c differs from gate driving device 100a (FIG. 3) in that it includes a timing adjustment circuit 120c instead of timing adjustment circuit 120a. The configuration of other parts of gate driving device 100c is similar to that of gate driving device 100a, and therefore detailed description thereof will not be repeated.

[0118] 13 is a block diagram illustrating an example of the configuration of the timing adjustment circuit 120c. As shown in FIG. 13, the timing adjustment circuit 120c differs from the timing adjustment circuit 120a (FIG. 8) in that it further includes a multiplexer 127. The other configuration of the timing adjustment circuit 120c is similar to that of the timing adjustment circuit 120a, and therefore detailed description thereof will not be repeated.

[0119] The multiplexer 127 receives the drive control signal Sdr and the output signal Sdl of the voltage comparator 125, and outputs the control signals Sd(1) and Sd(2) in accordance with the correspondence specified by the selection instruction signal Ssl. For example, the selection instruction signal Ssl can be input to the timing adjustment circuit 120c from outside the gate driver 100c.

[0120] For example, when the selection instruction signal Ssl is at H level, the correspondence is specified so that the multiplexer 127 outputs the drive control signal Sdr as the control signal Sd(1) and outputs the output signal Sdl of the voltage comparator 125 as the control signal Sd(2). In this case, the control signals Sd(1) and Sd(2) are generated so that the turn-off of the semiconductor switching element Q1 starts first, and then the turn-off of the semiconductor switching element Q2 starts after the time difference tdf has elapsed, as in the first embodiment (timing adjustment circuit 120a).

[0121] On the other hand, when the selection instruction signal Ssl is at L level, the correspondence is specified so that the multiplexer 127 outputs the drive control signal Sdr as the control signal Sd(2) and outputs the output signal Sdl of the voltage comparator 125 as the control signal Sd(1). As a result, the control signals Sd(1) and Sd(2) are generated such that the turn-off of the semiconductor switching element Q2 starts first, and then the turn-off of the semiconductor switching element Q1 starts after a time difference tdf, contrary to the first embodiment (timing adjustment circuit 120a).

[0122] In the timing adjustment circuit 120c, an embodiment of a "signal delay circuit" can be configured by the rate limiter 122 and the voltage comparator 125. Furthermore, the multiplexer 127 corresponds to an embodiment of a "signal selection circuit," and the output signal Sdl of the voltage comparator 125 corresponds to an embodiment of a "delay signal."

[0123] As described above, the gate drive device according to the second embodiment can change the order in which the series-connected semiconductor switching elements Q1 and Q2 start to turn off in response to the selection instruction signal Ssl. This allows the semiconductor switching elements that are subject to the turn-off delay to be switched after the gate drive device 100c is mounted in a circuit. Therefore, even if a measurement test using the test circuit 50 shown in FIG. 4 is performed after mounting the circuit and the characteristics shown in FIGS. 6 and 7 are obtained, an appropriate time difference (delay amount) can be provided between the turn-off start timings of the semiconductor switching elements Q1 and Q2.

[0124] 7 illustrates a case where the setting characteristic of the time difference tdf is only in the region of tdf > 0, i.e., an example where the semiconductor switching element that is to start turning off first is fixed. However, due to a fixed signal delay difference or the like caused by the wiring pattern between the semiconductor switching elements Q1 and Q2, an offset difference that is not dependent on the current value may occur between the turn-off timings of the semiconductor switching elements Q1 and Q2.

[0125] In this case, the set characteristic CHL1 in Fig. 7 is shifted upward or downward. As a result, when the after-off voltage difference Vdf that depends on the current value due to the characteristic difference between the semiconductor switching elements and the offset after-off voltage difference Vdf that does not depend on the current value occur with opposite polarities, the set characteristic CHL2 exemplified in Fig. 14 may be obtained from the experimental results.

[0126] 14 indicates that in the region where the current value is small, it is necessary to set tdf>0 to compensate for the post-off voltage difference Vdf caused by the difference in turn-off characteristics between the semiconductor switching elements. On the other hand, in the region where the current value is large, it is necessary to set tdf<0 to compensate for the post-off voltage difference Vdf caused by the offset.

[0127] In order to provide the time difference tdf according to the set characteristic CHL2 between the control signals Sd(1) and Sd(2), it is necessary to switch the semiconductor switching element whose turn-off start timing is delayed according to the current value.

[0128] 13, within the timing adjustment circuit 120c, the delay amount table 121 can be configured to output the absolute value of the time difference tdf to the D / A converter 123 in accordance with the current value Ic* in accordance with the set characteristic CHL2, and to output the sign of the time difference tdf as a selection instruction signal Ssl to the multiplexer 127. In this way, an appropriate time difference (delay amount) can be set between the turn-off start timings of the semiconductor switching elements Q1 and Q2 in accordance with the set characteristic CHL2 in which the polarity of the time difference tdf changes in accordance with changes in the current value Ic*.

[0129] As described above, the gate drive device according to embodiment 2 not only achieves the effects of the gate drive device according to embodiment 1, but also improves the flexibility in setting the time difference tdf applied between the turn-off start timings of semiconductor switching elements Q1 and Q2. This increases the degree of freedom in test timing for setting an appropriate time difference tdf and increases the number of factors that can be addressed for the after-off voltage difference Vdf.

[0130] Note that the provision of the gate voltage adjustment circuits GVC(1) and GVC(2) is not essential in the second embodiment either. That is, the gate voltage adjustment circuits GVC(1) and GVC(2) can be provided as a backup configuration for suppressing overvoltage occurrence even when there is a setting error in the time difference tdf according to the delay amount table 121.

[0131] Modification of Second Embodiment In a modification of the second embodiment, a configuration example for expanding the application of the gate drive device according to the second embodiment to a case where the number of semiconductor switching elements connected in series is increased will be described.

[0132] Fig. 15 is a schematic configuration diagram of a gate drive device 100d according to a modification of embodiment 2. As shown in Fig. 15, gate drive device 100d differs from gate drive device 100b (Fig. 10) in that it includes a timing adjustment circuit 120d instead of timing adjustment circuit 120b. The configuration of other parts of gate drive device 100d is similar to that of gate drive device 100b, and therefore detailed description thereof will not be repeated.

[0133] 16 is a block diagram illustrating an example configuration of a timing adjustment circuit 120d. As shown in FIG. 16, the timing adjustment circuit 120d differs from the timing adjustment circuit 120b (FIG. 11) in that it further includes a multiplexer 128. The other configuration of the timing adjustment circuit 120d is similar to that of the timing adjustment circuit 120b, and therefore detailed description thereof will not be repeated.

[0134] The multiplexer 128 receives the drive control signal Sdr and the output signals Sdl1 and Sdl2 of the voltage comparators 125 and 126, and outputs control signals Sd(1) to Sd(3) in accordance with the selection instruction signal Ssl (multiple bits).

[0135] The multiplexer 127 outputs each of the three signals, the drive control signal Sdr and the output signals Sdl1 and Sdl2, as control signals Sd(1) to Sd(3) in accordance with the correspondence specified by the selection instruction signal Ssl. Therefore, the selection instruction signal Ssl is set to select one of the combinations (six in total) of correspondences between the three signals, the drive control signal Sdr and the output signals Sdl1 and Sdl2, and the control signals Sd(1) to Sd(3). For example, by making the selection instruction signal Ssl a three-bit signal, it is possible to select one of the six combinations.

[0136] This allows the order in which the three semiconductor switching elements Q1 to Q3 start to turn off to be arbitrarily switched in response to the selection instruction signal Ssl among the three semiconductor switching elements Q1 to Q3 that are connected in series and turned on and off by a common drive control signal Sdr. As a result, even if the turn-off characteristics (FIGS. 6 and 7) of the semiconductor switching elements Q1 to Q3 are measured using the test circuit 50 shown in FIG. 4 after the gate driver 100d is mounted on a circuit, the order in which the semiconductor switching elements Q1 to Q3 start to turn off can be appropriately set to match the actual turn-off characteristics.

[0137] In timing adjustment circuit 120d, an embodiment of a "signal delay circuit" can be configured by rate limiter 122 and voltage comparators 125 and 126. Furthermore, multiplexer 128 corresponds to an embodiment of a "signal selection circuit," and output signals Sdl1 and Sdl2 of voltage comparators 125 and 126 correspond to an embodiment of a "delay signal."

[0138] In the modification of the second embodiment, the delay amount tables 121 (Q2) and 121 (Q3) do not necessarily store the set characteristic CHL1 ( FIG. 7 ) for the semiconductor switching elements Q2 and Q3. That is, the delay amount tables 121 (Q2) and 121 (Q3) are configured to store set characteristics of time differences tdf with respect to the current value Ic* that should be imparted to the turn-off start timings of the remaining two semiconductor switching elements relative to a reference timing that is the turn-off start timing of the semiconductor switching element that should be turned off earliest in accordance with the drive control signal Sdr.

[0139] As a result, according to the gate drive device 100d of the modified example of the second embodiment, the order of the turn-off start timings of the series-connected semiconductor switching elements Q1 to Q3, which are turned on and off by a common drive control signal, can be arbitrarily changed in accordance with the selection instruction signal Ssl (multiple bits). As a result, even if the number of series-connected semiconductor switching elements increases, the same effects as those of the second embodiment can be achieved.

[0140] In the modified example of the second embodiment, the arrangement of the gate voltage adjustment circuits GVC(1) to GVC(3) is not essential, but they can be additionally arranged as a precaution in order to suppress overvoltage even when there is a setting error in the time differences tdf2 and tdf3 (delay amounts) according to the current value Ic*.

[0141] Furthermore, it will be understood that in the modification of the second embodiment, even if the number of semiconductor switching elements is four or more, the same effect can be obtained by preparing the set characteristic CHL1 in accordance with the increase in the number. That is, the gate drive device 100c according to the second embodiment can be applied to a configuration in which a plurality of (two or more) series-connected semiconductor switching elements are commonly turned on and off, without limiting the number of semiconductor switching elements.

[0142] In addition, the timing adjustment circuits 120c and 120d according to the second embodiment and its modified example can also be configured so that when the time difference (tdf, tdf2, tdf3) is 0, the drive control signal Sdr is used as the input signal (Sdl, Sdl1, Sdl2) to the multiplexers 127 and 128, as appropriate.

[0143] Third Embodiment In a third embodiment, a configuration of a gate driver having a function for compensating for an error in the time difference tdf set by the delay amount table 121 in the first and second embodiments will be described.

[0144] 17 is a schematic diagram of a gate driving device 100e according to embodiment 3. Referring to FIG. 17, gate driving device 100e can be obtained by replacing timing adjustment circuit 120a or 120c in gate driving device 100a (FIG. 3) or gate driving device 100c (FIG. 12) with timing adjustment circuit 120e. Semiconductor switching elements Q1 and Q2 are turned on and off in accordance with control signals Sd(1) and Sd(2) from timing adjustment circuit 120e.

[0145] Furthermore, voltage detectors 30(1) and 30(2) are provided corresponding to semiconductor switching elements Q1 and Q2, respectively, for detecting voltages Vds1 and Vds2. The detected values ​​of voltages Vds1 and Vds2 by voltage detectors 30(1) and 30(2) are input to timing adjustment circuit 120e. The remaining configuration of gate driver 100e is the same as that of gate driver 100a (FIG. 3) or gate driver 100c (FIG. 12), and therefore detailed description thereof will not be repeated.

[0146] FIG. 18 is a block diagram illustrating an example configuration of a timing adjustment circuit 120e. Referring to FIG. 18, the timing adjustment circuit 120e further includes a delay adjustment circuit 200 between the delay table 121 and the D / A converter 123 in the configuration of the timing adjustment circuit 120a (FIG. 8) or the timing adjustment circuit 120c (FIG. 13). The delay adjustment circuit 200 outputs a time difference (delay) tdf at each turn-off. The time difference tdf(n) in FIG. 18 refers to the time difference tdf set at the nth (n: natural number) turn-off command. The following description will be given assuming that the delay adjustment circuit 200 receives digitally converted values ​​of the voltage and current values ​​and outputs the time difference (delay) tdf as a digital value.

[0147] Delay adjustment circuit 200 includes subtraction units 201 and 203, a gain multiplication unit 202, and an arithmetic unit 204. Delay adjustment circuit 200 corresponds to an embodiment of a "time difference adjustment circuit," and delay table 121 corresponds to an embodiment of a "characteristics storage unit."

[0148] The delay amount table 121 outputs the reference time difference (delay amount) tidf(n) corresponding to the current value Ic(*) before the turn-off at the time of the nth turn-off command, as in the first and second embodiments. As described in the first and second embodiments, the time difference (delay amount) tidf(n) can be set in accordance with the set characteristics CHL1 and CHL2 determined in advance by measurement experiments.

[0149] The subtraction unit 203 calculates a change amount Δtidf in the time difference tidf set by the delay amount table 121. Specifically, the subtraction unit 203 subtracts the time difference tidf(n−1), which is the output value from the delay amount table 121 at the previous turn-off, i.e., the (n−1)th turn-off, from the above-mentioned time difference tidf(n), and outputs Δtidf.

[0150] The subtraction unit 201 calculates the post-off voltage deviation ΔVdfc using the detection values ​​of the voltage detectors 30(1) and 30(2) at each turn-off. Specifically, the post-off voltage deviation ΔVdfc can be calculated by subtracting the post-off voltage Vdsc2 of the semiconductor switching element Q2 from the post-off voltage Vdsc1 of the semiconductor switching element Q1. Alternatively, the post-off voltage deviation ΔVdfc may be calculated by subtracting the post-off voltage Vdsc2 of the semiconductor switching element Q2 from the average value of the post-off voltages Vdsc1 and Vdsc2 of the semiconductor switching elements Q1 and Q2. The post-off voltages Vdsc1 and Vdsc2 correspond to the detection values ​​of the voltages Vds1 and Vds2 detected by the voltage detectors 30(1) and 30(2) after the turn-off is completed (corresponding to time t4 and thereafter in FIG. 2 ). The post-off voltage deviation ΔVdfc indicates the difference in post-off voltage between the semiconductor switching element Q2, which has a time difference tdf in the turn-off start timing, and the other semiconductor switching element Q1.

[0151] Therefore, it can be understood that if the time difference tdf(n-1) applied at the time of the previous (previous) turn-off is appropriate, the post-turn-off voltage deviation ΔVdfc = 0. The gain multiplication unit 202 multiplies the post-turn-off voltage deviation ΔVdfc from the subtraction unit 201 by a predetermined control gain K to calculate the compensation amount tvd.

[0152] In the example of Figure 18, the compensation amount tvd is calculated from the after-off voltage deviation ΔVdfc using proportional control (P), but it is also possible to calculate the compensation amount tvd using any other control calculation (for example, PI control, etc.).

[0153] The calculation unit 204 subtracts the compensation amount tvd from the gain multiplication unit 202 from the time difference tdf(n-1) at the time of the previous turn-off and adds the change amount Δtidf from the subtraction unit 203 to calculate the time difference tdf(n) to be imparted at the nth turn-off.

[0154] This makes it possible to set the time difference (delay amount) tdf(n) to be applied at the nth turn-off in a manner that reflects the change amount Δtid corresponding to the change in current value (the change from Ic*(n-1) to Ic*(n)) relative to the time difference tdf(n-1) applied at the previous turn-off, and the compensation amount tvd for compensating for the post-off voltage deviation ΔVdfc that actually occurred at the time difference tdf(n-1).

[0155] The time difference tdf(n) calculated by the calculation unit 204 is input to the D / A converter 123 that generates the reference voltage Vtdf. The generation of the control signals Sd(1) and Sd(2) using the reference voltage Vtdf is similar to that in the timing adjustment circuit 120a (FIG. 8) or the timing adjustment circuit 120c (FIG. 13), and therefore detailed description thereof will not be repeated.

[0156] In this way, in the timing adjustment circuit 120e of the third embodiment, the post-turn-off voltage difference ΔVdfc that occurs under the actually applied time difference is calculated using the voltage detection values ​​from the voltage detectors 30(1) and 30(2). Then, the time difference (delay amount) tidf, which is set according to the current value Ic* using the delay amount table 121, can be corrected to set the time difference (delay amount) tdf(n) at each turn-off so as to compensate for the calculated post-turn-off voltage difference ΔVdfc.

[0157] Therefore, in addition to the effects of the gate drive devices according to the first and second embodiments, the gate drive device according to the third embodiment can correct the setting value in the delay amount table 121 in accordance with the post-off voltage difference Vdf that actually occurred during previous turn-offs, thereby enabling the time difference tdf to be set more appropriately.

[0158] That is, even if the time difference tidf (delay amount) according to the delay amount table 121 (setting characteristic CHL1) includes an error, the overvoltage can be suppressed by adjusting the time difference (delay amount) tdf based on the actually occurring after-turn-off voltage difference. As a result, the timing adjustment circuit 120e (delay amount adjustment circuit 200) can provide the same effect as that achieved by additionally disposing the gate voltage adjustment circuits GVC(1) and GVC(2) described in the first and second embodiments.

[0159] Modification of Embodiment 3 In the third embodiment, the gate driver 100e of two semiconductor switching elements Q1 and Q2 connected in series has been described, but it is also possible to expand the number of semiconductor switching elements connected in series to three or more.

[0160] FIG. 19 is a schematic diagram of a gate driver 100f according to a modification of the third embodiment. As shown in FIG. 19, the gate driver 100f controls the on / off of three series-connected semiconductor switching elements Q1 to Q3 in accordance with a common drive control signal Sdr. The gate driver 100f can be obtained by replacing the timing adjustment circuit 120b or 120d in the gate driver 100b (FIG. 10) or the gate driver 100d (FIG. 15) with a timing adjustment circuit 120f. The semiconductor switching elements Q1 to Q3 are turned on and off in accordance with control signals Sd(1) to Sd(3) from the timing adjustment circuit 120f.

[0161] Furthermore, voltage detectors 30(1) to 30(3) are provided corresponding to semiconductor switching elements Q1 to Q3, respectively, for detecting voltages Vds1 to Vds2. The detected values ​​of voltages Vds1 to Vds3 by voltage detectors 30(1) to 30(3) are input to timing adjustment circuit 120f. The configuration of other parts of gate driver 100f is the same as that of gate driver 100b (FIG. 10) or gate driver 100d (FIG. 15), and therefore detailed description thereof will not be repeated.

[0162] 20 is a block diagram for explaining an example of the configuration of a timing adjustment circuit 120f. Referring to FIG. 20, the timing adjustment circuit 120f further includes a delay adjustment circuit 200a between the delay amount table 121(Q2) and the D / A converter 123(2) in the configuration of the timing adjustment circuit 120b (FIG. 11) or the timing adjustment circuit 120d (FIG. 16), and further includes a delay adjustment circuit 200b between the delay amount table 121(Q3) and the D / A converter 123(3). The delay adjustment circuits 200a and 200b correspond to an example of a "time difference adjustment circuit."

[0163] The delay adjustment circuit 200a includes subtraction units 201a and 203a, a gain multiplication unit 202a, and a calculation unit 204a, which are similar to the subtraction units 201 and 203, the gain multiplication unit 202, and the calculation unit 204 of the delay adjustment circuit 200. In the delay adjustment circuit 200a, the subtraction unit 201a calculates a post-off voltage deviation ΔVdfc2 by subtracting the post-off voltage Vdsc2 of the semiconductor switching element Q2 from the average value of the post-off voltages Vdsc1 to Vdsc3 of the semiconductor switching elements Q1 to Q3, using the values ​​detected by the voltage detectors 30(1) to 30(3), at each turn-off. As a result, the post-off voltage deviation ΔVdfc2 can indicate the difference in the post-off voltage between the semiconductor switching element Q2, which has a turn-off timing with a time difference tdf2, and the other semiconductor switching elements Q1 and Q3. It is understood that if the time difference tdf2 is appropriate, ΔVdfc2=0.

[0164] The gain multiplication unit 202a, the subtraction unit 203a, and the calculation unit 204a operate in the same manner as the gain multiplication unit 202, the subtraction unit 203, and the calculation unit 204 in FIG. 18, so that the delay adjustment circuit 200a can set the time difference (delay amount) tdf2(n) to be applied when the semiconductor switching element Q2 is turned off for the nth time.

[0165] The time difference tdf2(n) is calculated in a manner that reflects the change amount Δtid2 corresponding to the change in current value (the change from Ic*(n-1) to Ic*(n)) relative to the time difference tdf2(n-1) imparted at the time of the previous turn-off, and the compensation amount tvd2 for compensating for the post-off voltage deviation ΔVdfc2 that actually occurred at the time difference tdf2(n-1).

[0166] Similarly, delay adjustment circuit 200b includes subtraction units 201b and 203b, a gain multiplication unit 202b, and a calculation unit 204b. In delay adjustment circuit 200b, subtraction unit 201b calculates a post-off voltage deviation ΔVdfc3 by subtracting the post-off voltage Vdsc3 of semiconductor switching element Q3 from the average value of the post-off voltages Vdsc1 to Vdsc3 of semiconductor switching elements Q1 to Q3 using the values ​​detected by voltage detectors 30(1) to 30(3) at each turn-off. As a result, post-off voltage deviation ΔVdfc3 can indicate the difference in post-off voltage between semiconductor switching element Q3, whose turn-off start timing is delayed by time tdf3, and the other semiconductor switching elements Q1 and Q2. It can be understood that if the time delay tdf3 is appropriate, ΔVdfc3 = 0.

[0167] The gain multiplication unit 202b, the subtraction unit 203b, and the calculation unit 204b operate in the same manner as the gain multiplication unit 202, the subtraction unit 203, and the calculation unit 204 in FIG. 18, so that the delay adjustment circuit 200b can set the time difference (delay amount) tdf3(n) to be applied when the semiconductor switching element Q3 is turned off for the nth time.

[0168] The time difference tdf3(n) is calculated in a manner that reflects a change amount Δtid3 corresponding to the change in current value relative to the time difference tdf3(n-1) imparted at the time of the previous turn-off, and a compensation amount tvd3 for compensating for the post-off voltage deviation ΔVdfc3 that actually occurred at the time difference tdf3(n-1).

[0169] The time difference tdf2(n) calculated by the delay adjustment circuit 200a is input to a D / A converter 123(2) that generates a reference voltage Vtdf2. Similarly, the time difference tdf3(n) calculated by the delay adjustment circuit 200b is input to a D / A converter 123(3) that generates a reference voltage Vtdf3.

[0170] The generation of control signals Sd(1) to Sd(3) using reference voltages Vtdf2 and Vtdf3 is similar to that in timing adjustment circuit 120b (FIG. 11) or timing adjustment circuit 120d (FIG. 16), and therefore detailed description thereof will not be repeated.

[0171] In this way, in the timing adjustment circuit 120f according to the modification of the third embodiment, the post-turn-off voltage differences ΔVdfc2 and ΔVdfc3 that occur under the actually applied time difference are calculated using the voltage detection values ​​from the voltage detectors 30(1) to 30(3). Then, the time differences (delay amounts) tidf2 and tidf3, which are set according to the current value Ic* using the delay amount tables 121(2) and 121(3), are corrected so as to compensate for the calculated post-turn-off voltage difference, thereby setting the time differences (delay amounts) tdf2(n) and tdf3(n) at each turn-off.

[0172] Therefore, according to the gate drive device of the modified example of the third embodiment, in a configuration in which the semiconductor switching elements Q1 to Q3 connected in series are turned on and off by a common drive control signal, it is possible to obtain the same effects as those of the third embodiment.

[0173] Furthermore, in the modification of the third embodiment, even if the number of semiconductor switching elements is four or more, it will be understood that the same effect can be obtained by preparing delay amount table 121 and delay amount adjustment circuit 200 in Fig. 18 in accordance with the increase in the number. That is, the gate driving device 100e according to the third embodiment can be applied to a configuration in which a plurality of (two or more) series-connected semiconductor switching elements are commonly turned on and off, without limiting the number of semiconductor switching elements.

[0174] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The scope of the present disclosure is defined by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims.

[0175] 2, 15, 16 DC power supply, 10 Power conversion device, 11, 23 P-type transistor, 12 N-type transistor, 13, 14 Gate resistor, 21 Voltage divider circuit, 22, 125, 126 Voltage comparator, 30 Voltage detector, 31 Current detector, 50 Test circuit, 100a to 100f Gate driver, 110, 110 (1), 110 (2) I / F circuit, 111, 112 Gate driver circuit, 120, 120a to 120f Timing adjustment circuit, 121, 121 (Q2), 121 (Q3) Delay amount table, 122 Rate limiter, 123, 123 (1), 123 (2) D / A converter, 127, 128 Multiplexer, 200, 200a, 200b Delay amount adjustment circuit, 201, 201a, 201b, 203, 203a, 203b Subtraction unit, 202, 202a, 202b Gain multiplication unit, 204, 204a, 204b Calculation unit, CHL1, CHL2 Setting characteristic, Cds(1), Cds(2) Output capacitance (semiconductor switching element), D1, D2, Da, Db Diode, Eoff Off voltage, Eon On voltage, GDU(1) to GDU(3) Drive unit, GDU1 to GDU4 Gate drive unit (comparison example), GVC(1) to GVC(3) Gate voltage adjustment circuit, ILref Current command value (load current), Ic* Current value, NL, PL Power supply wiring, No Output node, PLoff, PLon Power supply line, Q1 to Q4, Qa, Qb Semiconductor switching element, RL Load, RTU1 to RTU4 re-on control units (comparison example), Sd(1) to Sd(3) control signals, Sdr, Sdr1, Sdr2 drive control signals, Sov overvoltage detection signal, Ssl selection instruction signal, tdf, tdf2, tdf3, tidf, tidf2, tidf3 time difference, Vdf post-turn-off voltage difference, Vdf voltage difference, Vdsc1 to Vdsc3 post-turn-off voltage, Vdv divided voltage, Vov, Vref judgment voltage, Vtdf, Vtdf2, Vtdf3 reference voltage, tvd, tvd2, tvd3 compensation amount.

Claims

1. A gate drive device for a plurality of semiconductor switching elements connected in series, comprising a plurality of drive circuits arranged corresponding to each of the plurality of semiconductor switching elements and each of which receives a plurality of control signals, each of the drive circuits being configured to initiate turn-off of a corresponding one of the semiconductor switching elements in response to a predetermined signal level change of each of the input control signals, and further comprising a timing adjustment circuit for providing a variable time difference depending on the current value of the plurality of semiconductor switching elements prior to the turn-off between the timing of the signal level changes of the plurality of control signals when the plurality of semiconductor switching elements are turned off by a common drive control signal.

2. The gate driver of claim 1, wherein the plurality of semiconductor switching elements are composed of N semiconductor switching elements, N being a natural number equal to or greater than 2, the drive control signal is generated to change from a first level to a second level when the N semiconductor switching elements are turned off, and the timing adjustment circuit sets the timing of the signal level change of the control signal of one semiconductor switching element of the plurality of semiconductor switching elements in accordance with a reference timing at which the drive control signal changes from the first level to the second level, and includes a signal delay circuit for generating the control signals of (N-1) semiconductor switching elements other than the one semiconductor switching element of the plurality of semiconductor switching elements based on the drive control signal, and the signal delay circuit is configured to delay the timing of the signal level change of the control signal of the (N-1) semiconductor switching elements from the reference timing in accordance with the time difference.

3. The gate driver of claim 1, wherein the plurality of semiconductor switching elements are composed of N semiconductor switching elements, N being a natural number equal to or greater than 2, the drive control signal is generated so as to change from a first level to a second level when turning off the plurality of semiconductor switching elements, and the timing adjustment circuit includes: a signal delay circuit that generates (N-1) delayed signals by delaying the drive control signal in accordance with the time difference, and a signal selection circuit that receives the drive control signal, the (N-1) delayed signals, and a selection instruction signal, and outputs each of the drive control signal and the (N-1) delayed signals as the control signal for each of the N semiconductor switching elements in accordance with the correspondence specified by the selection instruction signal.

4. A gate driver as claimed in any one of claims 1 to 3, further comprising a gate voltage adjustment circuit provided corresponding to each of said plurality of semiconductor switching elements, said gate voltage adjustment circuit being configured to vary the gate voltage of a corresponding semiconductor switching element among said plurality of semiconductor switching elements in accordance with the voltage between the current inflow terminal and the current outflow terminal of the corresponding semiconductor switching element so as to suppress an overvoltage.

5. The gate drive device according to claim 4, wherein the gate voltage adjustment circuit includes an overvoltage detection circuit and a re-on circuit, the overvoltage detection circuit is configured to output a re-on request signal upon detecting an overvoltage between the current inflow terminal and the current outflow terminal of a corresponding semiconductor switching element when the corresponding semiconductor switching element is turned off, and the re-on circuit operates to supply, when the overvoltage detection circuit outputs the re-on request signal after a corresponding one of the plurality of drive circuits has started to turn off the corresponding semiconductor switching element, a voltage equivalent to that applied when each of the drive circuits turns on the corresponding semiconductor switching element, to the gate of the corresponding semiconductor switching element.

6. A gate drive device as claimed in any one of claims 1 to 3, further comprising a voltage detector provided in each of the plurality of semiconductor switching elements for detecting a voltage between a current inflow terminal and a current outflow terminal of the corresponding semiconductor switching element, wherein the timing adjustment circuit includes: a characteristic memory section for storing a predetermined set characteristic of the time difference with respect to the current value before the turn-off; and a time difference adjustment circuit for setting the time difference applied between the timing of the signal level change of each of the plurality of control signals by correcting, when a turn-off is commanded by the drive control signal, the time difference set by the characteristic memory section based on the current value before the turn-off, using a voltage detection value by the voltage detector at the time after completion of turn-off of the plurality of semiconductor switching elements at the time of the previous turn-off.

7. The gate driver according to any one of claims 1 to 6, wherein the time difference is set to be shorter as the current value is larger.

8. A gate drive device as claimed in any one of claims 1 to 7, further comprising a current detector for detecting a current flowing through said plurality of semiconductor switching elements, or a current flowing through a load to which current is supplied from said plurality of semiconductor switching elements in an on-state, wherein said timing adjustment circuit sets said time difference using a value detected by said current detector as said current value.

9. A gate drive device according to any one of claims 1 to 7, wherein the timing adjustment circuit sets the time difference using a current command value of a load to which current is supplied from the plurality of semiconductor switching elements in an on-state as the current value.

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