Method for manufacturing semiconductor device

Abstract

The present invention reduces the number of processes involving mounting and solder reflow during the manufacture of a semiconductor device 1 that has a plurality of semiconductor chips 3 joined on a substrate 2 and that also has a lead frame 4 which straddle over and are joined on the semiconductor chips 3.　An on-substrate jig 10 which has a partition 10B disposed in a gap between the mutually adjacent semiconductor chips 3 (a first semiconductor chip 3A and a second semiconductor chip 3B) for the purpose of positioning the chips and the lead frame 4 which enables a corner of the semiconductor chips 3 to be visible and which has a cutout 4D in a shape that allows the partition 10B to penetrate therethrough are used. The lead frame 4 is positioned using the on-substrate jig 10 before joining the semiconductor chips 3 to the substrate 2, and then, under-chip solder and on-chip solder are caused to reflow to join the substrate 2, the semiconductor chips 3, and the lead frame 4.

Description

Semiconductor device manufacturing method

[0001] The present invention relates to a method for manufacturing a semiconductor device.

[0002] A semiconductor module, which is a type of semiconductor device, is disclosed in, for example, Japanese Patent Application Laid-Open No. 2003-222299.

[0003] Japanese Patent Application Laid-Open No. 2003-124999 describes a semiconductor module having a substrate on which a plurality of semiconductor chips are bonded, and a lead frame bonded across the plurality of semiconductor chips.

[0004] Japanese Patent Application Laid-Open No. 2023-3573

[0005] Patent Document 1 does not describe the details of the manufacturing method.

[0006] In a conventional method for manufacturing a semiconductor device, when a semiconductor chip is bonded to a substrate via solder and a lead frame is bonded to the semiconductor chip via solder, a manufacturing method has been used in which the mounting and solder reflow processes are performed three times, as shown in, for example, FIGS. 10 to 12 .

[0007] FIG. 10 is a perspective view illustrating a step of pre-soldering to a lead frame in a conventional method for manufacturing a semiconductor device.

[0008] 10, an upper jig 12 for pre-soldering a lead frame and a lower jig 13 for pre-soldering a lead frame are used to position and mount solder 5A on the chip as solder 5 on the lead frame 4. Then, the solder 5 is reflowed to pre-solder the solder 5A on the chip to the lead frame 4.

[0009] FIG. 11 is a perspective view illustrating a step of positioning a semiconductor chip using an on-substrate jig in a conventional method for manufacturing a semiconductor device.

[0010] 11, first upper-substrate jig 14 and first lower-substrate jig 15 are used to position and mount solder 5 under the chip 5B and solder under the feet 5C as solder 5 on the substrate 2, and then the semiconductor chip 3 is positioned and mounted on the under-chip solder 5B. Thereafter, the solder 5 is reflowed to bond the semiconductor chip 3 onto the substrate 2 via the under-chip solder 5B, and pre-soldering of the under-foot solder 5C is performed on the substrate 2.

[0011] FIG. 12 is a perspective view illustrating a step of positioning a lead frame using an on-substrate jig in a conventional method for manufacturing a semiconductor device.

[0012] 12, a second upper-substrate jig 16 and a second lower-substrate jig 17 are used to position and mount the lead frame 4, on which the chip solder 5A has been pre-soldered, on the substrate 2, on which the semiconductor chip 3 has already been bonded and the foot-under solder 5C has been pre-soldered. Thereafter, the solder 5 is reflowed to bond the lead frame 4 onto the semiconductor chip 3 via the chip-under solder 5A, and also to bond the lead frame 4 onto the substrate 2 via the foot-under solder 5C.

[0013] However, the conventional method for manufacturing a semiconductor device shown in FIGS. 10 to 12 has the problem that it requires a large number of mounting and solder reflow steps, and therefore takes a long time to manufacture.

[0014] The problem that the present invention aims to solve is to provide a manufacturing method that reduces the number of mounting and solder reflow steps when manufacturing a semiconductor device in which multiple semiconductor chips 3 are bonded onto a substrate 2 and a lead frame 4 is bonded across the multiple semiconductor chips 3.

[0015] In order to solve the above-mentioned problems, a manufacturing method of a semiconductor device of the present invention is a manufacturing method of a semiconductor device having a substrate, a first semiconductor chip bonded to an upper surface of the substrate, a second semiconductor chip disposed adjacent to the first semiconductor chip and bonded to the upper surface of the substrate, and a lead frame bonded to the upper surfaces of the first semiconductor chip and the second semiconductor chip and having inter-chip connecting portions overlapping a gap between the first semiconductor chip and the second semiconductor chip, wherein the first semiconductor chip and the second semiconductor chip are positioned using an on-substrate jig having a partition for chip positioning in the gap between the first semiconductor chip and the second semiconductor chip, and the lead frame is The system is characterized in that a lead frame is used that has a notch through which the partition penetrates and through which corners of the first semiconductor chip and the second semiconductor chip are visible, and before bonding the first semiconductor chip and the second semiconductor chip to the substrate, the lead frame is positioned using the substrate jig, and chip under-solder provided between the first semiconductor chip and the substrate and between the second semiconductor chip and the substrate, and chip over-solder provided between the first semiconductor chip and the lead frame and between the second semiconductor chip and the lead frame is reflowed to bond the substrate, the first semiconductor chip, the second semiconductor chip, and the lead frame.

[0016] According to the present invention, when manufacturing a semiconductor device having a plurality of semiconductor chips 3 bonded onto a substrate 2 and a lead frame 4 bonded across the plurality of semiconductor chips 3, a manufacturing method can be realized that reduces the number of mounting and solder reflow steps.

[0017] 7 is a top view illustrating a step of positioning a semiconductor chip and a lead frame using an on-substrate jig in a manufacturing method for a semiconductor device according to an embodiment. It is a top view showing an enlarged view of part A in FIG. 1. It is a cross-sectional view taken along line B-B in FIG. 2. It is a top view illustrating the shape of a lead frame according to an embodiment. It is a perspective view illustrating a step of pre-soldering to a lead frame in a manufacturing method for a semiconductor device according to an embodiment. It is a perspective view illustrating a step of positioning a semiconductor chip and a lead frame using an on-substrate jig in a manufacturing method for a semiconductor device according to an embodiment. It is a top view illustrating a positional relationship between the outline of a lead frame and a semiconductor chip in an embodiment, and an enlarged view of parts C1 to C4. It is a top view illustrating the shape of a lead frame according to an embodiment, and cross-sectional views taken along lines E-E and F-F. It is a cross-sectional view taken along line D-D in FIG. 7. It is a perspective view illustrating a step of pre-soldering to a lead frame in a conventional manufacturing method for a semiconductor device. It is a perspective view illustrating a step of positioning a semiconductor chip using an on-substrate jig in a conventional manufacturing method for a semiconductor device. It is a perspective view illustrating a step of positioning a lead frame ...

[0018] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In each drawing, the same or similar components are designated by the same reference numerals, and redundant explanations will be omitted.

[0019] In conventional semiconductor device manufacturing methods, as shown in Figures 11 and 12, the process of bonding a semiconductor chip 3 to the top surface of a substrate 2 and the process of bonding a lead frame 4 to the top surfaces of the substrate 2 and the semiconductor chip 3 were carried out separately.

[0020] In contrast, in the manufacturing method of the semiconductor device of the embodiment, as shown in FIG. 6 described later, the processes of joining the substrate 2, the semiconductor chip 3, and the lead frame 4 are carried out all at once, thereby reducing the number of mounting and solder reflow processes.

[0021] Specifically, the manufacturing method of the semiconductor device of this embodiment uses an on-substrate jig 10 having a divider 10B for chip positioning in the gap between adjacent semiconductor chips 3 (first semiconductor chip 3A and second semiconductor chip 3B), and a lead frame 4 having a notch 4D that allows the corners of the semiconductor chip 3 to be seen and is shaped so that the divider 10B passes through; before bonding the semiconductor chip 3 to the substrate 2, the lead frame 4 is positioned using the on-substrate jig 10, and the under-chip solder 5B and the over-chip solder 5A are reflowed to bond the substrate 2, semiconductor chip 3, and lead frame 4.

[0022] The details of this embodiment will be described below.

[0023] FIG. 1 is a top view illustrating a step of positioning a semiconductor chip and a lead frame using an on-substrate jig in a manufacturing method for a semiconductor device according to an embodiment. FIG. 2 is a top view showing an enlarged view of portion A in FIG. 1. FIG. 3 is a cross-sectional view taken along line B-B in FIG. 2. FIG. 4 is a top view illustrating the shape of a lead frame according to an embodiment. Note that in FIG. 3, on-chip electrodes 3C (see FIG. 2) and solder 5 (see FIGS. 5 and 6 described below) are omitted.

[0024] The semiconductor device 1 of the embodiment has a substrate 2 on which a plurality of semiconductor chips 3 are bonded, and a lead frame 4 bonded across the plurality of semiconductor chips 3 .

[0025] More specifically, the semiconductor device 1 of the embodiment has a substrate 2, a first semiconductor chip 3A bonded to the upper surface of the substrate 2, a second semiconductor chip 3B arranged adjacent to the first semiconductor chip 3A and bonded to the upper surface of the substrate 2, and a lead frame 4 bonded to the upper surfaces of the first semiconductor chip 3A and the second semiconductor chip 3B and having an inter-chip connection portion 4B overlapping the gap 20 between the first semiconductor chip 3A and the second semiconductor chip 3B.

[0026] In the stage shown in FIG. 1, the positioning has been completed but the solder reflow has not yet been carried out, so strictly speaking, the components have not yet been joined.

[0027] 3, the substrate 2 has an insulating layer 2A, a wiring layer 2B provided on the upper surface side of the insulating layer 2A, and a backside metal layer 2C provided on the lower surface side of the insulating layer 2A. The wiring layer 2B is bonded to the wiring layer 2B that forms the circuit pattern.

[0028] The multiple semiconductor chips 3 include a first semiconductor chip 3A and a second semiconductor chip 3B arranged adjacent to each other. Each semiconductor chip 3 has at least a chip upper electrode 3C (see FIG. 2, not shown in FIG. 3) on its upper surface and a chip lower electrode (not shown) on its lower surface. The semiconductor chip 3 is bonded to the wiring layer 2B of the substrate 2 via chip lower solder 5B (not shown in FIG. 3, see FIG. 6 described below). While this embodiment illustrates an example in which a diode is used as the first semiconductor chip 3A and an IGBT (Insulated Gate Bipolar Transistor) is used as the second semiconductor chip 3B, this is not intended to be limiting. Furthermore, while this embodiment illustrates an example in which two first semiconductor chips 3A, two second semiconductor chips 3B, and two lead frames 4 are provided on one substrate 2 as shown in FIG. 1, this is not intended to be limiting. Furthermore, while this embodiment illustrates an example in which one lead frame 4 is bonded across two semiconductor chips 3, this is not intended to be limiting and the lead frame 4 may be bonded across three or more semiconductor chips 3.

[0029] The lead frame 4 has a chip connection portion 4A, an inter-chip connection portion 4B, a foot portion 4C, a notch 4D, and a through hole 4E. The chip connection portion 4A is recessed from its surroundings (see FIG. 9 described later) and is joined to an on-chip electrode 3C on the top surface of the semiconductor chip 3 via on-chip solder 5A (not shown in FIG. 3 , see FIG. 5 described later). The inter-chip connection portion 4B connects two chip connection portions 4A, and as shown in FIGS. 2 and 3 , at least a portion of the inter-chip connection portion 4B overlaps the gap 20 between the first semiconductor chip 3A and the second semiconductor chip 3B. The inter-chip connection portion 4B is provided with a notch 4D. The inter-chip connection portion 4B is also preferably provided with a through hole 4E. The notch 4D and the through hole 4E will be described in detail later. The foot portion 4C connects the chip connection portion 4A to the substrate 2. The legs 4C are joined to the wiring layer 2B on the upper surface of the substrate 2 via lower leg solder 5C (see FIG. 5 described later). The lead frame 4 serves to provide electrical connection and to dissipate heat through thermal conduction.

[0030] The upper-substrate jig 10 (see FIG. 1) and the lower-substrate jig 11 (see FIG. 3) are jigs used in the manufacturing stage of the semiconductor device 1, and are used to position and mount each component on the substrate 2. The upper-substrate jig 10 is disposed on the upper surface side of the substrate 2, and the lower-substrate jig 11 is disposed on the lower surface side of the substrate 2.

[0031] The on-substrate jig 10 has an opening 10A and a partition 10B. The opening 10A and the partition 10B have shapes for positioning each component, and each component can be positioned and mounted by inserting it into the opening 10A. The partition 10B is provided in the gap 20 between the first semiconductor chip 3A and the second semiconductor chip 3B, and is used for chip positioning.

[0032] Specifically, the first semiconductor chip 3A and the second semiconductor chip 3B are positioned using an on-substrate jig 10 having a divider 10B for chip positioning in the gap 20 between the first semiconductor chip 3A and the second semiconductor chip 3B. The divider 10B allows the first semiconductor chip 3A and the second semiconductor chip 3B, which are adjacent to each other, to be accurately positioned while maintaining the gap 20.

[0033] Furthermore, as the lead frame 4, as shown in Figures 1 and 2, a lead frame 4 is used in which the corners of the first semiconductor chip 3A and the corners of the second semiconductor chip 3B are visible, and as shown in Figure 3, a lead frame 4 having a notch 4D shaped to allow a partition 10B to pass through is used, and before the first semiconductor chip 3A and the second semiconductor chip 3B are joined to the substrate 2, the lead frame 4 is positioned using an on-substrate jig 10.

[0034] In this embodiment, in order to reduce the number of mounting and solder reflow processes, the lead frame 4 is positioned before the semiconductor chip 3 is bonded to the substrate 2, so it is necessary to position the lead frame 4 while checking whether the position of the semiconductor chip 3 is misaligned. Therefore, if the notch 4D were not present, the corners of the semiconductor chip 3 would be invisible or difficult to see, making it difficult to check whether the position of the semiconductor chip 3 is misaligned. In this embodiment, the notch 4D makes it possible to check the positions of the corners of the semiconductor chip 3, and the lead frame 4 can be positioned while checking whether the position of the semiconductor chip 3 is misaligned.

[0035] Furthermore, the notch 4D is shaped so that the partition 10B for maintaining the gap 20 passes through it, so that the two adjacent semiconductor chips 3 can be accurately positioned while avoiding interference with the partition 10B.

[0036] It is also possible to narrow the overall width of the lead frame 4 without providing the notches 4D, but in that case, the width of the portion including the chip connection portion 4A would be narrowed, which would reduce the effectiveness of electrical connection and heat dissipation by thermal conduction. Therefore, the configuration in this embodiment in which the width of the portion including the chip connection portion 4A is wide enough to cover almost the entire semiconductor chip 3 and the notches 4D are provided in the chip-to-chip connection portion 4B provides better electrical connection and heat dissipation by thermal conduction.

[0037] Although not explained here, the solder 5 is also mounted separately at an appropriate timing. After each component is mounted, the under-chip solder 5B provided between the first semiconductor chip 3A and the substrate 2 and between the second semiconductor chip 3B and the substrate 2, and the over-chip solder 5A provided between the first semiconductor chip 3A and the lead frame 4 and between the second semiconductor chip 3B and the lead frame 4 are reflowed to bond the substrate 2, the first semiconductor chip 3A, the second semiconductor chip 3B, and the lead frame 4. At the same time, the under-foot solder 5C provided between the substrate 2 and the lead frame 4 is also reflowed to bond the substrate 2 and the lead frame 4.

[0038] According to this embodiment, when manufacturing a semiconductor device 1 in which multiple semiconductor chips 3 are bonded onto a substrate 2 and a lead frame 4 is bonded across the multiple semiconductor chips 3, the number of mounting and solder reflow processes can be reduced.

[0039] Next, further details of this embodiment and modifications will be described.

[0040] 1, the lead frame 4 is desirably shaped so that at least two diagonal corners of the first semiconductor chip 3A and two diagonal corners of the second semiconductor chip 3B are visible. By making the two diagonal corners of the semiconductor chip 3 visible, misalignment of the semiconductor chip 3 can be more accurately confirmed. While FIG. 1 shows an example in which three corners are visible, excluding the corners corresponding to the feet 4C, this is not limiting.

[0041] In this embodiment, it is assumed that when positioning the lead frame 4, the lead frame 4 is pre-soldered with solder 5A on the chip. Hereinafter, a description will be given with reference to FIGS.

[0042] FIG. 5 is a perspective view illustrating a step of pre-soldering to a lead frame in the method for manufacturing a semiconductor device according to the embodiment.

[0043] As shown in Fig. 5, an upper jig 12 for pre-soldering a lead frame and a lower jig 13 for pre-soldering a lead frame are used to position and mount solder 5A on the chip and solder 5C under the foot on the lead frame 4 as solder 5. Then, the solder 5 is reflowed to pre-solder the solder 5A on the chip and solder 5C under the foot on the lead frame 4. Note that this differs from the conventional method shown in Fig. 10 in that pre-soldering of solder 5C under the foot is also performed.

[0044] FIG. 6 is a perspective view illustrating a step of positioning the semiconductor chip and the lead frame using an on-substrate jig in the method for manufacturing a semiconductor device according to the embodiment.

[0045] As shown in Figure 6, the upper-substrate jig 10 and lower-substrate jig 11 of this embodiment are used to position and mount under-chip solder 5B as solder 5 on the substrate 2. Then, the semiconductor chip 3 is positioned and mounted on the under-chip solder 5B. Then, the pre-soldered lead frame 4 shown in Figure 5 is positioned and mounted on the substrate 2 and semiconductor chip 3. Thereafter, the solder 5 is reflowed to bond the substrate 2, semiconductor chip 3, and lead frame 4 together. According to this embodiment, the conventional steps shown in Figures 11 and 12 can be combined into one step shown in Figure 6, reducing the number of mounting and solder reflow steps.

[0046] When a pre-soldered lead frame 4 is used, the number of mounting and solder reflow steps is two, as shown in Figures 5 and 6. However, this is not limited to this; when positioning the lead frame 4, the lead frame 4 may not have pre-soldered on-chip solder 5A. That is, Figures 5 and 6 may be combined to reduce the number of mounting and solder reflow steps to one. However, in this case, the upper jig 12 for pre-soldering the lead frame, which has openings for positioning the under-foot solder 5C shown in Figure 5, cannot be used, and the positioning of the under-foot solder 5C becomes more difficult. Therefore, the manufacturing method to be adopted can be selected depending on whether it is more important to reduce the number of mounting and solder reflow steps or to reliably position the under-foot solder 5C.

[0047] FIG. 7 is a top view illustrating the positional relationship between the outer shape of the lead frame and the semiconductor chip in the embodiment, and an enlarged view of portions C1 to C4.

[0048] 7 shows a state in which the joining is completed and the upper substrate jig 10 and the lower substrate jig 11 are removed. Therefore, the insulating layer 2A and the wiring layer 2B of the substrate 2 are also shown.

[0049] As shown in FIG. 7 , the lead frame 4 of this embodiment preferably has an outer shape such that at least the portion outside the notch 4D, the periphery of the notch 4D, is recessed by 0.1 mm or more from the first semiconductor chip 3A or the second semiconductor chip 3B, as shown in FIG. 7 . This shape takes into consideration the processing accuracy of the lead frame 4 and its expansion at the solder melting temperature. Furthermore, while the on-substrate jig 10 is made of, for example, carbon, the shape of this embodiment prevents interference with the on-substrate jig 10 and suppresses the generation of carbon debris around the semiconductor chip 3. By using the lead frame 4 of this embodiment, the semiconductor chip 3 and the lead frame 4 can be positioned and mounted using the same on-substrate jig 10.

[0050] FIG. 8 is a top view illustrating the shape of the lead frame of the embodiment, and cross-sectional views taken along lines EE and FF.

[0051] As shown in FIG. 8 , the lead frame 4 of this embodiment has foot portions 4C bonded to the upper surface of the substrate 2, and it is desirable that the cross-sectional area of ​​the inter-chip connection portion 4B (cross-sectional area at E-E) is greater than or equal to the cross-sectional area of ​​the foot portions 4C (cross-sectional area at F-F). The lead frame 4 serves to dissipate heat through thermal conduction. The rate of heat dissipation through thermal conduction is determined by the cross-sectional area, and the larger the cross-sectional area, the greater the heat dissipation effect through thermal conduction. For example, assuming that the heat generated by the second semiconductor chip 3B is greater than the heat generated by the first semiconductor chip 3A, by making the cross-sectional area of ​​the inter-chip connection portion 4B greater than or equal to the cross-sectional area of ​​the foot portions 4C, heat generated by the second semiconductor chip 3B can be easily dissipated through thermal conduction not only via the foot portion 4C at the bottom right of FIG. 8 , but also via the inter-chip connection portion 4B and the foot portion 4C at the top left of FIG. 8 .

[0052] FIG. 9 is a cross-sectional view taken along line DD in FIG.

[0053] 4 and 9, the lead frame 4 of this embodiment preferably has through holes 4E in the inter-chip connection portions 4B at positions different from the notches 4D. The manufacturing method of this embodiment preferably includes a step of sealing the substrate 2, the first semiconductor chip 3A, the second semiconductor chip 3B, and the lead frame 4 with a sealing resin (not shown) after bonding the substrate 2, the first semiconductor chip 3A, the second semiconductor chip 3B, and the lead frame 4. At this time, the sealing resin can infiltrate through the through holes 4E as shown by the sealing resin infiltration path 21. Therefore, the through holes 4E can improve the permeability of the sealing resin into the area around the semiconductor chip 3 below the lead frame 4 and improve adhesion.

[0054] Although the embodiments of the present invention have been described above, the present invention is not limited to the configurations described in the embodiments, and various modifications are possible within the scope of the technical concept of the present invention. In addition, some or all of the configurations described in the embodiments may be combined and applied.

[0055] REFERENCE SIGNS LIST 1...semiconductor device, 2...substrate, 2A...insulating layer, 2B...wiring layer, 2C...rear-side metal layer, 3...semiconductor chip, 3A...first semiconductor chip, 3B...second semiconductor chip, 3C...electrode on chip, 4...lead frame, 4A...chip connection portion, 4B...inter-chip connection portion, 4C...foot portion, 4D...notch, 4E...through hole, 4F...setback portion, 5...solder, 5A...solder on chip, 5B...solder under chip, 5C...solder under foot portion, 10...substrate upper jig, 10A...opening, 10B...partition, 11...substrate lower jig, 12...upper jig for lead frame spare soldering, 13...lower jig for lead frame spare soldering, 14...first substrate upper jig, 15...first substrate lower jig, 16...second substrate upper jig, 17...second substrate lower jig, 20...gap, 21...sealing resin intrusion path

Claims

1. A method for manufacturing a semiconductor device comprising: a substrate; a first semiconductor chip bonded to an upper surface of the substrate; a second semiconductor chip disposed adjacent to the first semiconductor chip and bonded to the upper surface of the substrate; and a lead frame bonded to the upper surfaces of the first semiconductor chip and the second semiconductor chip and having inter-chip connections overlapping a gap between the first semiconductor chip and the second semiconductor chip, the method comprising: positioning the first semiconductor chip and the second semiconductor chip using an on-substrate jig having a partition for chip positioning in the gap between the first semiconductor chip and the second semiconductor chip; using a lead frame as the lead frame having a notch through which the partition passes and through which a corner of the first semiconductor chip and a corner of the second semiconductor chip are visible; and positioning the lead frame using the on-substrate jig before bonding the first semiconductor chip and the second semiconductor chip to the substrate; A method for manufacturing a semiconductor device, comprising the steps of: reflowing under-chip solder provided between the first semiconductor chip and the substrate and between the second semiconductor chip and the substrate, and over-chip solder provided between the first semiconductor chip and the lead frame, and between the second semiconductor chip and the lead frame, to join the substrate, the first semiconductor chip, the second semiconductor chip, and the lead frame.

2. A method for manufacturing a semiconductor device according to claim 1, characterized in that the lead frame is shaped so that at least two diagonal corners of the first semiconductor chip and two diagonal corners of the second semiconductor chip are visible.

3. A method for manufacturing a semiconductor device according to claim 1, wherein the lead frame has an outer shape such that at least the peripheral portion of the notch outside the notch is recessed by 0.1 mm or more from the first semiconductor chip or the second semiconductor chip.

4. The method for manufacturing a semiconductor device according to claim 1, wherein the lead frame has a foot portion joined to the upper surface of the substrate, and the cross-sectional area of ​​the inter-chip connection portion is greater than or equal to the cross-sectional area of ​​the foot portion.

5. A method for manufacturing a semiconductor device according to claim 1, wherein the lead frame has a through hole in the inter-chip connection portion at a position different from the notch.

6. A method for manufacturing a semiconductor device according to claim 5, further comprising a step of sealing the substrate, the first semiconductor chip, the second semiconductor chip, and the lead frame with a sealing resin after bonding the substrate, the first semiconductor chip, the second semiconductor chip, and the lead frame.

7. A method of manufacturing a semiconductor device as claimed in claim 1, characterized in that when the lead frame is positioned, the chip is pre-soldered on the lead frame.

8. The method of manufacturing a semiconductor device according to claim 1, wherein when the lead frame is positioned, the chip solder is not pre-soldered on the lead frame.

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