Digital cascode amplifier

Abstract

The present invention relates to a digital cascode amplifier. The present invention further relates to a digital Doherty amplifier that comprises such a digital cascode amplifier, and to a digital transmitter in which the digital cascode amplifier or digital Doherty amplifier is used. The present invention particularly relates to a digital cascode amplifier, digital Doherty amplifier, and / or digital transmitter that are configured to operate in the radiofrequency, RF, frequency range, e.g. between 0.1 and 12 GHz. The proposed digital cascode amplifier comprises a cascode arrangement that includes a common-source or common-emitter stage and a common-gate or common-base stage, wherein the common-source or common-emitter stage comprises a plurality of first transistors, and wherein the common-gate or common-base stage comprises a second transistor. The proposed digital cascode amplifier further comprises a driver configured for providing a respective control signal to a gate or base of each first transistor in dependence of a digital input signal.

Description

[0001] DIGITAL CASCODE AMPLIFIER

[0002] The present invention relates to a digital cascode amplifier. The present invention further relates to a digital Doherty amplifier that comprises such a digital cascode amplifier, and to a digital transmitter in which the digital cascode amplifier or digital Doherty amplifier is used. The present invention particularly relates to a digital cascode amplifier, digital Doherty amplifier, and / or digital transmitter that is / are configured to operate in a radiofrequency, RF, frequency range, e.g. between 0.1 and 12 GHz, and that output powers in a range between 0.1 and 100 Watt.

[0003] A digital transmitter uses a digital input signal to create an analog output signal. An example of such a digital transmitter is disclosed in WO2021162545A1. This known digital transmitter includes a digital amplifier that comprises a driver and a common-source RF amplifier that is segmented into individually switchable parallel segments. All these segments are connected to a single common-drain output.

[0004] The segments are individually driven by the driver. To this end, the driver includes a plurality of driver stages. More in particular, the gate(s) corresponding to a particular segment of the common-source RF amplifier is / are driven by a respective driver stage.

[0005] The number of segments necessarily defines the total resolution of the digital amplifier. To achieve a high digital resolution and hence linear signal operation, many segments are necessary. For common mobile communication signals and a reasonable bandwidth, a resolution of at least 9 bits is required to meet adjacent channel power ratio, ACPR, requirements. Such a high number of segments can be easily realized by segmentation in complementary metal-oxide-semiconductor, CMOS, technology. However, CMOS is limited in its maximum output power level due to combining losses. The usage of various technologies with flip-chip interconnects may help to allow a combination of high resolution and reasonable output power levels. In the known digital transmitter, this is achieved using a CMOS driver that drives a segmented laterally diffused metal- oxide-semiconductor, LDMOS, power transistor.

[0006] For future applications, efficiency demands can be met by using Gallium Nitride, GaN, based field-effect transistors, FETs, in the final stage of power amplifiers. As the power density of GaN is significantly higher (~x7 times) compared to Si-based reference technologies, the segmentation cannot be done as fine as for LDMOS. For example, scaling down the gate periphery of a GaN FET to increase the digital resolution would necessarily mean a waste of space on the costly GaN semiconductor material. Moreover, GaN requires a wide voltage range as input drive power. Voltage swings of 15V are commonly observed at the input to drive the GaN FETs into deep compression. Additionally, the majority of GaN FETs are depletion mode transistors that require a negative voltage to switch off. The Applicant has found that a driver technology that provides these high AC voltage swings paired with high digital integration capabilities and negative supply voltages is not or not readily available.

[0007] According to the present invention, this problem is solved or at least alleviated using a digital cascode amplifier as defined in claim 1. This amplifier comprises one or more inputs configured for receiving a digital input signal, an output configured for outputting an analog output signal, and a cascode arrangement. The cascode arrangement comprises a common-source or common-emitter stage and a common-gate or common-base stage, wherein the common-source or common-emitter stage comprises a plurality of first transistors, and wherein the common-gate or common-base stage comprises a second transistor.

[0008] The digital cascode amplifier according to the present invention further comprises a driver configured for providing a respective control signal to a gate or base of each first transistor in dependence of the digital input signal. A gate or base of the second transistor is configured to be biased during operation using a first DC reference voltage. A source or emitter of the first transistors is configured to be set to a second reference voltage during operation. Furthermore, a drain or collector of the second transistor is connected to and / or forms the output of the digital cascode amplifier. The second reference voltage may correspond to a ground reference voltage, e.g. 0V.

[0009] Compared to the abovementioned known digital transmitter, the present invention proposes to not modulate the gate of the final stage, i.e. the second transistor, but rather its source using a cascode configuration. The resolution is then determined by the number of first transistors, whereas the efficiency is mostly determined by the second transistor. This is particularly advantageous if the first and second transistors correspond to different semiconductor processes and / or materials. In this respect, it should be noted that although the present invention is not limited to a particular semiconductor technology, the first transistors could comprise laterally diffused metal-oxide-semiconductor, LDMOS, transistors, and the second transistor could comprise a Gallium Nitride based field-effect transistor. However, the present invention could be implemented using other semiconductor material systems and / or transistor types such as bipolar transistors.

[0010] Each first transistor may further comprise a drain or collector, wherein the sources or emitters of the first transistors are electrically connected to each other. In this case, the drains or collectors of the first transistors are electrically connected to a source or emitter of the second transistor.

[0011] The second transistor may have an output capacitance between its drain or collector and its source or emitter. This output capacitance acts as feedback in the common-gate configuration. The Applicant has found that by adding a series connection of an inductor and a capacitor arranged in between the drain or collector of the second transistor and the source or emitter of the second transistor, the problem can be alleviated. This particularly holds true when a series resonance frequency of the series connection of the inductor and the capacitor is much smaller than an operating frequency of the digital cascode amplifier, and when a parallel resonance frequency of the inductor and the output capacitance is at or close to the operating frequency. In this way, the negative effect of the output capacitance on the high-frequency performance of the digital cascode amplifier can be mitigated.

[0012] A breakdown voltage between the drain or collector and the source or emitter of the first transistors can be much smaller than a breakdown voltage between the drain or collector and the source or emitter of the second transistor. For example, the breakdown voltage of the first transistors may lie in a range between 2.5 and 70 Volt, whereas the breakdown voltage of the second transistor may lie in a range between 70 and 500 Volt. The first transistors may be identical apart from the individual gate peripheries of the first transistors. Using different individual gate peripheries allows for an improved resolution to be reached when controlling the output power of the digital cascode amplifier when compared to first transistors having the same individual gate periphery. For example, having 4 first transistors each having a gate periphery of P and associated maximum current Imax allows for the current through the common-source or common-emitter stage to reach the values n x Imax, wherein n is an integer from 0 to 4. Accordingly, the smallest step in current equals Imax. Using 4 first transistors having gate peripheries of 4 / 9xP, 4 / 9xP, 8 / 9xP, and 20 / 9xP and associated maximum currents 4 / 9xImax, 4 / 9xImax, 8 / 9xImax, and 20 / 9xImax allows for the current through the common-source or common-emitter stage to reach the values n x 4 / 9 x Imax, wherein n is an integer from 0 to 9. The smallest step in current in this case equals 4 / 9 Imax. This example therefore demonstrates that by using different individual gate peripheries an improved resolution can be obtained for the same total gate periphery.

[0013] The first transistors and the second transistor can be manufactured from different semiconductor material systems. Additionally, or alternatively, the driver can be manufactured from a different semiconductor material system as the second transistor. For example, the driver is implemented in CMOS technology.

[0014] The first transistors can be implemented on one or more semiconductor dies of a first type, and the second transistor can be implemented on a semiconductor die of a second type. Furthermore, the digital cascode amplifier may comprise a carrier on which the one or more semiconductor dies of a first type are mounted and on which the semiconductor die of a second type is mounted adjacent the one or more semiconductor dies of a first type. Alternatively, the one or more semiconductor dies of the first type are mounted on the carrier, and the semiconductor die of the second type is mounted on one of said one or more semiconductor dies of a first type. In both cases, the carrier can be in the form of a laminate such as a printed circuit board. The driver can be implemented on a semiconductor die of a third type. This semiconductor die of a third type can be mounted on the carrier or on one of said one or more semiconductor dies of a first type.

[0015] The semiconductor die of a second type can be flip-chipped onto the carrier or onto one of said one or more semiconductor dies of a first type. Additionally, or alternatively, the semiconductor die of a third type can be flip-chipped onto the carrier or onto one of said one or more semiconductor dies of a first type.

[0016] Instead of being flip-chipped, the semiconductor die of a second type can be wire-bonded onto the carrier or onto one of said one or more semiconductors of a first type. Additionally, or alternatively, the semiconductor die of a third type can be wire-bonded onto the carrier or onto one of said one or more semiconductors of a first type.

[0017] The one or more inputs may comprise a first input for receiving an in-phase component of a digital input signal and a second input for receiving a quadrature component of that digital input signal. In this case, the driver may comprise a converter for converting the in-phase component and the quadrature component to an envelope component and a phase component. The envelope component is fed to a digital word creating unit that generates a digital word based on the envelope component. The driver may further comprise an oscillator configured to generate a carrier signal of which the phase depends on the phase component, and a combining unit for generating said respective control signal for the gate or base of each first transistor in dependence of the digital word and the generated carrier signal. The combining unit may comprise a plurality of AND gates, each AND gate having a first terminal and a second terminal. The digital word creating unit can in this case be configured to provide the first terminal of each AND gate of the plurality of AND gates with a respective bit of the generated digital word. The oscillator can be configured to provide the generated carrier signal to the second terminal of each AND gate of the plurality of AND gates.

[0018] In the manner described above, a polar modulation scheme can be implemented. Here, it should be noted that the present invention is not limited to the manner in which the digital signal to be provided to the first transistors is generated. Furthermore, the present invention, although being particular advantageous for polar modulation, is not limited to this modulation technique.

[0019] According to a second aspect, the present invention provides a digital Doherty amplifier that comprises a main amplifier, a peak amplifier, and a Doherty combiner for combining signals from the main amplifier and the peak amplifier. Here, both the main amplifier and the peak amplifier comprise a digital cascode amplifier as described above.

[0020] The digital Doherty amplifier may comprise one or more main inputs configured for receiving a digital main input signal, one or more peak inputs configured for receiving a digital peak input signal, and an output configured for outputting an analog output signal. The one or more inputs of the digital cascode amplifier of the main amplifier can be respectively connected to the one or more main inputs. Similarly, the one or more inputs of the digital cascode amplifier of the peak amplifier can be respectively connected to the one or more peak inputs.

[0021] The Doherty combiner can be configured for combining, at a combining node, the analog output signal outputted at the output of the digital cascode amplifier of the main amplifier and the analog output signal outputted at the output of the digital cascode amplifier of the peak amplifier, wherein the combining node is connected to the output of the digital Doherty amplifier.

[0022] As mentioned above, the digital cascode amplifier may comprise a carrier. In this case, the Doherty combiner may be at least partially arranged on the carrier. For example, the Doherty combiner may comprise a quarter wavelength transformer.

[0023] The Doherty combiner may comprise a first capacitor at least partially formed by an output capacitance of the second transistor of the digital cascode amplifier of the main amplifier, a second capacitor at least partially formed by an output capacitance of the second transistor of the digital cascode amplifier of the peak amplifier, and a second inductor arranged in between the drain or collector of the second transistor of the digital cascode amplifier of the main amplifier and the drain or collector of the second transistor of the digital cascode amplifier of the peak amplifier. In this case, the second inductor, the first capacitor, and the second capacitor may jointly form an equivalent of a quarter wavelength transformer at or near an operating frequency of the digital Doherty amplifier.

[0024] Furthermore, the digital cascode amplifier of the main amplifier and the digital cascode of the peak amplifier may use the same carrier. Moreover, in case the digital cascode amplifiers of the main amplifier and peak amplifier use semiconductor dies of the first and / or second type, these dies may be shared in the sense that a semiconductor die of the first type may comprise a first transistor and / or second transistor for both the main and peak amplifier. Similar considerations hold for the semiconductor die(s) of the second type.

[0025] According to a third aspect, the present invention provides a digital transmitter that comprises a digital amplifier, and an antenna connected to the digital amplifier. The digital amplifier comprises the digital cascode amplifier or the digital Doherty amplifier described above.

[0026] Next, the present invention will be described in more detail referring to the appended drawings, wherein identical or similar components will be referred to using the same reference signs, and wherein:

[0027] Figure 1 illustrates an embodiment of a digital cascode amplifier in accordance with the present invention;

[0028] Figure 2 illustrates the driver used in the digital cascode amplifier of figure 1 in more detail; Figure 3 illustrates an embodiment of a digital Doherty amplifier in accordance with the present invention;

[0029] Figure 4 illustrates a cross-section of an embodiment of a digital cascode amplifier in accordance with the present invention;

[0030] Figure 5 illustrates a cross-section of a further embodiment of a digital cascode amplifier in accordance with the present invention;

[0031] Figure 6 illustrates more details on a possible implementation of the digital cascode amplifier of figure 5; and

[0032] Figure 7 illustrates an embodiment of a digital transmitter in accordance with the present invention.

[0033] Figure 1 illustrates an embodiment of a digital cascode amplifier 1 in accordance with the present invention. It comprises a common-source stage 10 that includes four Si LDMOS transistors 11. In this embodiment, sources si of transistors 11 are grounded, and drains dl are connected to a source s2 of a GaN FET 21, which is included in a common-gate stage 20. Gates gl of transistors 11 are each provided with a respective control signal generated by driver 30.

[0034] Gate g2 is connected via an RF choke inductor L3 to a bias supply providing a DC reference voltage Vref 1. At the point where this bias supply is connected, an RF short to ground is created using capacitor C3. Application of DC reference voltage Vrefl ensures that GaN FET 21 can be driven between a fully off and fully open condition. For example, Vrefl equals around 2 V.

[0035] Drain d2 of GaN FET 21 is connected via an RF choke inductor L4 to a bias supply providing a DC reference voltage Vsup. At the point where this bias supply is connected, an RF short to ground is connected using capacitor C4.

[0036] GaN FET 21 has an output capacitance Cds, modelled in figure 1 using capacitor Cds, in between drain d2 and source s2. To mitigate the influence of Cds, a series connection of an inductor LI and capacitor Cl is arranged parallel to Cds. Inductor LI and capacitor Cl display a series resonance at a frequency that is much lower than an operating frequency of digital cascode amplifier 1. For example, the operating frequency may lie in a range between 0.1 and 12 GHz, preferably between 1 and 6 GHZ. A ratio between the operating frequency and the series resonance frequency may at least be 2, more preferably at least 4. Alternatively, or additionally, the capacitance of Cl is at least 5 times the output capacitance Cds, more preferably at least 10 times Cds, and even more preferably at least 20 times Cds.

[0037] As the series resonance of LI and Cl occurs at a frequency that is significantly lower than the operating frequency, the series connection of LI and Cl acts inductively at or close to the operating frequency. The effective inductance of this series connection is such that a parallel resonance occurs between Cds and the series connection at or close to the operating frequency thereby cancelling or mitigating the impact Cds has on RF performance. The load to which digital cascode amplifier 1 should output its power can be connected to output RF_out of digital cascode amplifier 1. At the input, digital cascode amplifier 1 comprises a pair of inputs I, Q for receiving digital input signals I, Q, respectively. Next, the operation of driver 30 will be described referring to figure 2.

[0038] As shown in figure 2, driver 30 comprises two inputs for receiving an in-phase component I and a quadrature component Q that jointly form a digital input signal. For example, the I and Q components could be the well known I and Q signals used in quadrature amplitude modulation schemes.

[0039] Driver 30 comprises a converter 31 that converts the I and Q components into phase and envelope data. This approach is known from WO2021162545 Al. The phase data is used for controlling a local oscillator 33 that outputs a carrier signal having a frequency corresponding to the operating frequency. The envelope data is provided to a digital word creation unit that creates a digital word based on the envelope data.

[0040] Bits of the digital word are provided to respective first terminals of AND gates 35 of combining unit 34. The second terminals of AND gates 35 receive the output of local oscillator 33. The output of AND gates 35 is provided to gates gl of transistors 11.

[0041] Figure 3 illustrates an embodiment of a digital Doherty amplifier 100 in accordance with the present invention. It comprises a main amplifier 110 and a peak amplifier 120 of which the analog outputs are combined by a Doherty combiner 130. In the embodiment in figure 3, Doherty combiner 130 comprises a quarter wavelength transformer 131. However, the present invention is not limited to this type of combiner. The skilled person is well aware of other combiner topologies, such as combiners for inverted or parallel Doherty amplifiers. Such topologies may equally be used in the digital Doherty amplifier of the present invention.

[0042] Due to digital nature of the way the first transistors of the digital cascode amplifier of the present invention are controlled, it becomes less difficult to accurately control both amplitude and phase of the input signals that are fed to the main amplifier and peak amplifier. This allows the present invention to be efficiently used in n-way Doherty amplifiers, wherein n > 2. In analog n- way Doherty amplifiers it is difficult to design the Doherty splitter such that phase and amplitude of the signals fed to the main and peak amplifiers are properly controlled. In a digital Doherty amplifier in accordance with the present invention, the Doherty splitter is implemented digitally thereby allowing better control over phase and amplitude. Similar considerations hold when the digital cascode amplifier of the present invention is used as an amplifying unit in a load-modulated balanced amplifier.

[0043] In figure 3, main amplifier 110 and peak amplifier 120 are both realized using digital Doherty amplifier 1 of figure 1. Main amplifier 110 is provided with digital signals I,m and Q,m similar to signals I and Q in figure 1. Main amplifier 110 is also provided with a separate reference voltage Vrefl,m and Vsup,m, similar to reference voltages Vrefl and Vsup in figure 1. Similar considerations hold for peak amplifier 120.

[0044] The outputs of main amplifier 110 and peak amplifier 120, corresponding to RF_out in figure 1, are fed to Doherty combiner 130.

[0045] Instead of transmission lines, lumped equivalent circuits can be used. An example thereof is shown on the bottom right in figure 3. This is a particular example in which the output capacitance of GaN FET 21 of digital cascode amplifier 1 of main amplifier 110, referred to as Cds,m, and the output capacitance of GaN FET 21 of digital cascode amplifier 1 of peak amplifier 120, referred to as Cds,p, are used as parts of a C-L-C lumped network 131 A that behaves like a 90 degrees transmission line with particular characteristic impedance at or close to the operating frequency. In some embodiment, GaN FETs 21 for the main amplifier 110 and the peak amplifier 120 are identical. Furthermore, in case Cds, m and Cds,p are insufficient for realizing the required capacitance, additional lumped capacitors can be arranged in parallel.

[0046] Figure 7 illustrates a digital transmitter 200 that comprises an amplifier 201 connected to an antenna 202. According to the invention, amplifier 201 comprises digital cascode amplifier 1 or digital Doherty amplifier 100.

[0047] Figures 4-6 illustrate cross-sections and a top view of embodiments of a digital cascode amplifier in accordance with the present invention.

[0048] Figures 4 and 5 illustrate a digital cascode amplifier in the form of a module 1A, IB, respectively. In these figures, similar or identical components will be referred to using the same reference signs.

[0049] As shown in figures 4 and 5, modules 1A and IB each comprise a carrier 40, which can be in the form of a single-layer or multi-layer laminate. As shown in figure 4, on a top surface of carrier 40, die pads 41, 42 are provided on which a Si semiconductor die 11A and a GaN semiconductor die 21 A are arranged, respectively. First transistors 11 are realized as LDMOS transistors on semiconductor die 11 A and second transistor 21 is realized as a GaN FET on semiconductor die 21 A.

[0050] On a backside surface of carrier 40, several package terminals are provided. An example of a package terminal is ground pad 43 that provides a grounding for Si semiconductor die 11 A through vias 44. It is noted that Si semiconductor die 11 A is conductive.

[0051] Further package terminals 45 are provided that act as signal pads for receiving a digital input signal (left), and for outputting an analog RF signal (right). Signal pads 45 are connected to corresponding pads 46 arranged on the opposite side of carrier 40.

[0052] For thermal management, carrier 40 is provided with a coin 47 arranged underneath GaN semiconductor die 21A. Bondwires 48 are used for connecting pads 46 to pads arranged on semiconductor dies 11 A, 21 A. In figure 4, driver 30 is realized using a CMOS semiconductor die 30A that is flip-chipped onto Si semiconductor die 11A using e.g. solder balls 30B. Transport of signals between semiconductor die 11 A on semiconductor die 30A is realized using bondwires 48.

[0053] As shown, capacitor Cl in figure 1 is realized, in figure 4, on GaN semiconductor die 21 A. One terminal of capacitor Cl is connected to drain d2 of GaN FET 21. Inductor LI can be realized on semiconductor die 21A or on carrier 40 using one or more bondwires. Similarly, capacitor Cl could be arranged on carrier 40 and even on semiconductor die 11 A.

[0054] The series combination of Cl and LI resonates at a frequency that is much lower than an operating frequency of digital cascode amplifier 1A. Consequently, at sufficiently high temperatures, the series combination of Cl and LI acts as an inductor of which the inductance is substantially equal to the inductance of LI. This latter inductance is chosen such that LI and the output capacitance of GaN FET 21 on semiconductor die 21 A resonate at or close to the operating frequency of the digital cascode amplifier 1A.

[0055] Although a single semiconductor die 11 A is shown in figure 4, the present invention does not exclude embodiments in which multiple of these dies are used.

[0056] The module shown in figure 4 also comprises a solidified molding compound 49 that protects semiconductor dies 11 A, 21 A from environmental conditions.

[0057] Figure 5 illustrates a cross-section of a further embodiment of a digital cascode amplifier IB in accordance with the present invention. Digital cascode amplifier IB differs from digital cascode amplifier 1A in that semiconductor die 21A has been flip-chipped using e.g. solder balls 2 IB onto semiconductor die 11 A. In addition, a heat sink 50 is fixedly attached to an exposed portion of semiconductor die 21 A. This can for example be achieved by etching away molding compound 49 until a surface of semiconductor die 21 A becomes exposed.

[0058] Figure 6 illustrates more details on a possible implementation of digital cascode amplifier IB. As shown in figure 6, semiconductor die 21 A is flip-chipped onto semiconductor die 11A using e.g. solder balls 21B. GaN FET 21 is connected to various conductive traces 51 on semiconductor die 11A. Source s2 is connected to drain d2 via two conductive traces 51 that are mutually connected using one or more bondwires 48. Together, these traces and bondwire 48 form inductor LI. As indicated, capacitor Cl is integrated on semiconductor die 21 A, although it is also possible to integrate this capacitor on semiconductor die 11 A.

[0059] Various pads 45 are formed on a surface of carrier 40 opposite to the surface on which semiconductor die 11 A is arranged. In figure 6, these pads correspond to the package terminals Vrefl, Vsup, GND, and RF_out. Connection between pads 46 and corresponding pads 45 on the opposite surface of carrier 40 is realized using vias 44. It is noted that in figure 6, only pads 46 are shown. Drain d2 and gate g2 are connected to respective bondpads 52 on semiconductor die 11 A. Bondpads 52 are connected to pads on carrier 40 using one or more bondwires 48. On carrier 40, transmission lines are formed for realizing L3 and L4 of the biasing networks for supplying Vrefl and Vsup, respectively. As an example, these transmission lines could be formed using quarter wavelength transformers that transform the RF short generated by SMD capacitors C3 and C4 to an RF open. In this manner, the biasing networks do not provide an RF loading at gate g2 and at RF_out, respectively.

[0060] In the above, the present invention was explained using detailed embodiments. However, the present invention is not limited to these embodiments. Various modifications are possible without departing from the scope of the present invention, which is defined by the appended claims and their equivalents.

Claims

CLAIMS1. A digital cascode amplifier (1; 1A; IB), comprising: one or more inputs (I, Q) configured for receiving a digital input signal (I, Q); an output (RF_out) configured for outputting an analog output signal; a cascode arrangement comprising a common-source stage (10) and a common-gate stage (20), wherein the common-source stage(lO) comprises a plurality of first transistors (11), and wherein the common-gate stage (20) comprises a second transistor (21); a driver configured (30) for providing a respective control signal to a gate (gl) of each first transistor (11) in dependence of the digital input signal (I, Q); wherein a gate (g2) of the second transistor (21) is configured to be biased during operation using a first DC reference voltage (Vrefl); wherein a source (si) of the first transistors (11) is configured to be set to a second reference voltage during operation; wherein a drain (d2) of the second transistor (21) is connected to and / or forms the output (RF_out) of the digital cascode amplifier (1; 1A; IB); wherein the second transistor (21) has an output capacitance (Cds) between the drain (d2) of the second transistor (21) and a source (s2) of the second transistor (21), the digital cascode amplifier (1; 1A; IB) further comprising a series connection of an inductor (LI) and a capacitor (Cl) arranged in between the drain (d2) of the second transistor (21) and the source (s2) of the second transistor (21); wherein a series resonance frequency of the series connection of the inductor (LI) and the capacitor (Cl) is much smaller than an operating frequency of the digital cascode amplifier (1; 1A; IB), and wherein a parallel resonance frequency of the inductor (LI) and the output capacitance (Cds) is at or close to the operating frequency.

2. The digital cascode amplifier (1; 1A; IB) according to claim 1, wherein each first transistor (11) further comprises a drain (dl), wherein the sources (si) of the first transistors (11) are electrically connected to each other; wherein the drains (dl) of the first transistors (11) are electrically connected to the source (s2) of the second transistor (21).

3. The digital cascode amplifier (1; 1A; IB) according to claim 1 or 2, wherein a breakdown voltage between the drain (dl) and the source (si) of the first transistors (11) is much smaller than a breakdown voltage between the drain (d2) and the source (s2) of the second transistor (21).

4. The digital cascode amplifier (1; 1A; IB) according to any of the previous claims, wherein the first transistors (11) are substantially identical apart from individual gate peripheries of the first transistors (11) being different among the first transistors (11).

5. The digital cascode amplifier (1; 1A; IB) according to claim 3 or claim 4, wherein the first transistors (11) and the second transistor (21) are manufactured from different semiconductor material systems; wherein the first transistors (11) comprise laterally diffused metal-oxide-semiconductor, LDMOS, transistors, and wherein the second transistor (21) comprises a Gallium Nitride based field-effect transistor; wherein the driver (30) is preferably implemented in complementary metal-oxide- semiconductor, CMOS, technology.

6. The digital cascode amplifier (1; 1A; IB) according to claim 5, wherein the first transistors (11) are implemented on a semiconductor die (11 A) of a first type, and wherein the second transistor (21) is implemented on a semiconductor die (21 A) of a second type.

7. The digital cascode amplifier (1; 1A) according to claim 6, comprising a carrier (40) on which the semiconductor die (11 A) of the first type is mounted and on which the semiconductor die (21 A) of the second type is mounted adjacent to the semiconductor die (11 A) of the first type, and wherein the carrier (40) is a laminate; wherein the digital cascode amplifier (1; 1A) comprises a plurality of pads (45) formed on a surface of the carrier (40) opposite to the surface on which the semiconductor die (11 A) of the first type is arranged, the pads (45) corresponding to package terminals; wherein the semiconductor die (21 A) of the second type is wire-bonded onto the carrier (40); wherein the capacitor (Cl) is realized on the semiconductor die (21 A) of the second type; wherein a terminal of the capacitor (Cl) is connected to the source (s2) of the second transistor (21) through one or more bondwires (48) that form the inductor (LI), and wherein another terminal of the capacitor (Cl) is connected to the drain (d2) of the second transistor (21); wherein the drain (d2) of the second transistor (21) is connected to a pad (45) among the plurality of pads (45) forming an RF output package terminal (RF_out).

8. The digital cascode amplifier (1; IB) according to claim 6, comprising a carrier (40) on which the semiconductor die (11 A) of the first type is mounted, wherein the semiconductordie (21 A) of the second type is mounted on said semiconductor die (11 A) of the first type, wherein the carrier (40) is a laminate; wherein the semiconductor die (21 A) of the second type is flip-chipped onto the semiconductor die (11 A) of the first type, wherein the capacitor (Cl) is integrated on the semiconductor die (21 A) of the second type; wherein the source (s2) of the second transistor (21) is connected to the drain (d2) of the second transistor (21) via a pair of conductive traces (51) arranged on the semiconductor die (11A) of the first type, which traces are mutually connected using one or more bondwires (48) that form, together with these traces, the inductor (LI).

9. The digital cascode amplifier (1; 1A; IB) according to any of the claims 6-8, wherein the driver (30) is implemented on a semiconductor die (30A) of a third type.

10. The digital cascode amplifier (1; 1A; IB) according to claim 9, wherein the semiconductor die (30A) of the third type is mounted on said semiconductor die (11 A) of the first type-11. The digital cascode amplifier (1; 1A; IB) according to any of the previous claims, wherein the one or more inputs (I, Q) comprise a first input (I) for receiving an in-phase component of a digital input signal and a second input (Q) for receiving a quadrature component of that digital input signal.

12. The digital cascode amplifier (1; 1A; IB) according to claim 11, wherein the driver (30) comprises: a converter (31) for converting the in-phase component and the quadrature component to an envelope and phase component, respectively; a digital word creating unit (32) configured to generate a digital word based on the envelope component; an oscillator (33) configured to generate a carrier signal of which the phase depends on the phase component; a combining unit (34) for generating said respective control signal for the gate or base of each first transistor in dependence of the digital word and the generated carrier signal.

13. The digital cascode amplifier (1; 1A; IB) according to claim 12, wherein the combining unit (34) comprises a plurality of AND gates (35), each AND gate (35) having a first terminal and a second terminal, wherein the digital word creating unit (32) is configured to providethe first terminal of each AND gate (35) of the plurality of AND gates (35) with a respective bit of the generated digital word, and wherein the oscillator (33) is configured to provide the generated carrier signal to the second terminal of each AND gate (35) of the plurality of AND gates (35).

14. A digital Doherty amplifier (100), comprising: a main amplifier (110), a peak amplifier (120), and a Doherty combiner (130) for combining signals from the main amplifier (110) and the peak amplifier (120), wherein both the main amplifier (110) and the peak amplifier (120) comprise a digital cascode amplifier (1; 1A; IB) as defined in any of the previous claims.

15. The digital Doherty amplifier (100) according to claim 14, comprising: one or more main inputs (I,m, Q,m) configured for receiving a digital main input signal; one or more peak inputs (I,p, Q,p) configured for receiving a digital peak input signal; an output (Out) configured for outputting an analog output signal; wherein the one or more inputs (I, Q) of the digital cascode amplifier (1; 1A; IB) of the main amplifier (110) are respectively connected to the one or more main inputs (I,m, Q,m); wherein the one or more inputs (I, Q) of the digital cascode amplifier (1; 1A; IB) of the peak amplifier (120) are respectively connected to the one or more peak inputs (I,m, Q,m); wherein the Doherty combiner (130) is configured for combining, at a combining node (C), the analog output signal outputted at the output (RF_out) of the digital cascode amplifier (1; 1A; IB) of the main amplifier (110) and the analog output signal outputted at the output (RF_out) of the digital cascode amplifier (1; 1A; IB) of the peak amplifier (120), wherein the combining node (C) is connected to the output (Out) of the digital Doherty amplifier (100).

16. The digital Doherty amplifier (100) to any of the claims 14-15, in so far as depending on claim 7 or claim 8, wherein the Doherty combiner (130) is at least partially arranged on the carrier (40).

17. The digital Doherty amplifier (100) to any of the claims 14-16, wherein the Doherty combiner (130) comprises a first capacitor at least partially formed by the output capacitance (Cds,m) of the second transistor (21) of the digital cascode amplifier (1; 1A; IB) of the main amplifier (110), a second capacitor at least partially formed by the output capacitance (Cds,p) of the second transistor (21) of the digital cascode amplifier (1; 1A; IB) of the peak amplifier (120), and a second inductor (L2) arranged in between the drain (d2) of the second transistor (21) of the digital cascode amplifier (1; 1A; IB) of the main amplifier (110) and the drain (d2) of the second transistor (21) of the digital cascode amplifier (1; 1A; IB) of the peak amplifier (120),wherein the second inductor, the first capacitor, and the second capacitor jointly form an equivalent of a quarter wavelength transformer (131) at or near an operating frequency of the digital Doherty amplifier (100).

18. A digital transmitter (200), comprising: a digital amplifier (201); and an antenna (202) connected to the digital amplifier (201); wherein the digital amplifier (201) comprises the digital cascode amplifier (1; 1A; IB) defined in any of the claims 1-13 or the digital Doherty amplifier (100) defined in any of the claims

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