Floating termination cell and arrangement for handling tap termination

Abstract

A chip includes a tap column including tap cells (810) arranged in a column, and a termination tap cell terminating an end of the tap column. The termination tap cell includes a first N-well (815) extending across the termination tap cell in a first direction (112), a first n-tap (820) coupling the first N-well to a first supply rail, a first p-tap (830) coupling a p-substrate or a P-well to a ground rail, and a second p-tap (835) coupling the p-substrate or the P-well to the ground rail, wherein a first portion of the first N-well is disposed between the first p-tap and the second p-tap in a second direction (114) perpendicular to the first direction.

Description

Qualcomm Ref. No.2308574WO 1 FLOATING TERMINATION CELL AND ARRANGEMENT FOR HANDLING TAP TERMINATION CROSS-REFERENCE TO RELATED APPLICATION(S)

[0001] This application claims priority to and the benefit of application serial number 202341065654 filed in the Indian Patent Office on September 29, 2023, the entire content of which is incorporated herein as if fully set forth below in its entirety and for all applicable purposes. BACKGROUND Field

[0002] Aspects of the present disclosure relate generally to chip layout, and, more particularly, to tap cells. Background

[0003] A chip (i.e., silicon die) may include tap cells to prevent latch-up in circuit designs (e.g., complementary metal oxide semiconductor (CMOS) designs). A tap cell may couple an N-well to a voltage supply rail and / or couple a p-substrate or a P-well to a ground rail to prevent latch-up. SUMMARY

[0004] The following presents a simplified summary of one or more implementations in order to provide a basic understanding of such implementations. This summary is not an extensive overview of all contemplated implementations and is intended to neither identify key or critical elements of all implementations nor delineate the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the more detailed description that is presented later.

[0005] A first aspect relates to a chip. The chip includes a tap column including tap cells arranged in a column, and a floating termination cell terminating an end of the tap column. The floating termination cell includes an n-tap or a p-tap, and floating devices.

[0006] A second aspect relates to a chip. The chip includes a tap column including tap cells arranged in a column, and a termination tap cell terminating an end of the tap column. The termination tap cell includes a first N-well extending across the termination tap cellQualcomm Ref. No.2308574WO 2 in a first direction, a first n-tap coupling the first N-well to a first supply rail, a first p-tap coupling a p-substrate or a P-well to a ground rail, and a second p-tap coupling the p- substrate or the P-well to the ground rail, wherein a first portion of the first N-well is disposed between the first p-tap and the second p-tap in a second direction perpendicular to the first direction.

[0007] A third aspect relates to a chip. The chip includes a tap column including tap cells arranged in a column, and a termination tap cell terminating an end of the tap column. The termination tap cell includes a p-substrate or P-well extending across the termination tap cell in a first direction, a first p-tap coupling the p-substrate or the P-well to a first ground rail, a first N-well, a first n-tap coupling the first N-well to a supply rail, a second N-well, wherein the first N-well and the second N-well are separated by a portion of the p-substrate or the P-well in a second direction perpendicular to the first direction, and a second n-tap coupling the second N-well to the supply rail. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] FIG.1A shows an exemplary arrangement of tap columns and one or more cells colliding with one of the tap columns according to certain aspects of the present disclosure.

[0009] FIG. 1B shows an example in which the one or more cells are moved to avoid collision with the one of the tap columns according to certain aspects of the present disclosure.

[0010] FIGS. 2A and 2B show an exemplary arrangement of tap cells illustrating examples of collisions between tap columns and cells on a chip according to certain aspects of the present disclosure.

[0011] FIG. 3A shows an example of a floating termination cell including an n-tap and floating devices according to certain aspects of the present disclosure.

[0012] FIG. 3B shows an example of the n-tap of FIG. 3A coupled to a supply rail according to certain aspects of the present disclosure.

[0013] FIG. 4A shows an example of the floating termination cell of FIG. 3A terminating a tap column according to certain aspects of the present disclosure.

[0014] FIG. 4B shows an example of the floating termination cell of FIG. 3A terminating a tap column in which the orientation of the floating termination cell is flipped with respect to FIG. 4A according to certain aspects of the present disclosure.

[0015] FIG. 5A shows an example of a floating termination cell including a p-tap and floating devices according to certain aspects of the present disclosure.Qualcomm Ref. No.2308574WO 3

[0016] FIG. 5B shows an example of the p-tap of FIG. 5A coupled to a ground rail according to certain aspects of the present disclosure.

[0017] FIG. 6A shows an example of the floating termination cell of FIG. 5A terminating a tap column according to certain aspects of the present disclosure.

[0018] FIG. 6B shows an example of the floating termination cell of FIG. 5A terminating a tap column in which the orientation of the floating termination cell is flipped with respect to FIG. 6A according to certain aspects of the present disclosure.

[0019] FIGS. 7A and 7B show an exemplary arrangement of tap cells and floating termination cells according to certain aspects of the present disclosure.

[0020] FIG. 8A shows an example of a tap cell with a continuous N-well according to certain aspects of the present disclosure.

[0021] FIG.8B shows an example of supply rails and a ground rail extending over the tap cell of FIG. 8A according to certain aspects of the present disclosure.

[0022] FIG. 9A shows an example of the tap cell of FIG. 8A disposed between a tap cell and a standard cell according to certain aspects of the present disclosure.

[0023] FIG. 9B shows another example of the tap cell of FIG. 8A disposed between a tap cell and a standard cell according to certain aspects of the present disclosure.

[0024] FIG. 10A shows an example of a tap cell with a continuous p-substrate or P-well according to certain aspects of the present disclosure.

[0025] FIG. 10B shows an example of supply rails and a ground rail extending over the tap cell of FIG. 10A according to certain aspects of the present disclosure.

[0026] FIG. 11A shows an example of the tap cell of FIG. 10A disposed between a tap cell and a standard cell according to certain aspects of the present disclosure.

[0027] FIG. 11B shows another example of the tap cell of FIG. 10A disposed between a tap cell and a standard cell according to certain aspects of the present disclosure.

[0028] FIGS.12A and 12B show an exemplary arrangement of tap cells, switch cells, and corner endcap cells according to certain aspects of the present disclosure.

[0029] FIG. 13A shows an exemplary layout of the tap cell of FIG. 8A according to certain aspects of the present disclosure.

[0030] FIG. 13B shows an example of supply rails and a ground rail extending over the tap cell of FIG. 13A according to certain aspects of the present disclosure.

[0031] FIG. 14A shows another exemplary layout of the tap cell of FIG.8A according to certain aspects of the present disclosure.Qualcomm Ref. No.2308574WO 4

[0032] FIG. 14B shows an example of metal routing for coupling n-taps of the tap cell to supply rails according to certain aspects of the present disclosure.

[0033] FIG. 15A shows an exemplary layout of the tap cell of FIG. 10A according to certain aspects of the present disclosure.

[0034] FIG. 15B shows an example of ground rails and a supply rail extending over the tap cell of FIG. 15A according to certain aspects of the present disclosure.

[0035] FIG. 16 is a block diagram illustrating a computer system according to certain aspects of the present disclosure. DETAILED DESCRIPTION

[0036] The detailed description set forth below, in connection with the appended drawings, is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.

[0037] A chip (i.e., silicon die) may include tap cells to prevent latch-up in circuit designs (e.g., complementary metal oxide semiconductor (CMOS) designs). A tap cell may couple an N-well to a voltage supply rail (also referred to as a vdd rail) and / or couple a p-substrate or a P-well to a ground rail (also referred to as a vss rail) to prevent latch-up. The maximum distance between tap cells in a row may be specified by a design rule check (DRC) for a particular process technology. Latch-up may also be referred to as LUP.

[0038] In prior process technologies, tap cells may be arranged in a checkerboard pattern, in which each tap cell may cover latch-up over two rows. In newer process technologies, tap cells may be arranged in columns (e.g., vertical direction), in which each column of tap cells is referred to as a tap column. The tap columns are spaced apart from one another (e.g., at regular intervals in the horizontal direction). The top and the bottom of a tap column may be terminated with termination cells (e.g., to satisfy a termination cell requirement). The termination cells may be adjacent to rows of endcap cells. Endcap cells may be placed along a boundary of a block including cells, where each endcap cell may be configured to terminate a column of cells and / or terminate a row of cells in the block. An endcap cell configured to be placed at a corner of the block may be referred to as a corner endcap cell. As used herein, a first cell is adjacent to a second cell when theQualcomm Ref. No.2308574WO 5 layout does not include another cell placed between and separating the first cell and the second cell. Adjacent cells may also be referred to as neighboring cells, abutting cells, or another term, and adjacent may also be referred to as abut. It is to be appreciated that the layout may include a diffusion break (e.g., a single diffusion break or a double diffusion break) between adjacent cells to isolate diffusion regions of the adjacent cells.

[0039] FIG.1A shows a top view of an exemplary arrangement of tap columns 120-1, 120-2, and 120-3 on a chip according to certain aspects. Each of the tap columns 120-1, 120-2, 120- 3 includes tap cells arranged in direction 112 (e.g., vertical direction). In the example in FIG. 1A, the pitch (i.e., spacing) between tap columns 120-1, 120-2, and 120-3 in direction 114 (e.g., horizontal direction) may be fixed, where the direction 114 is perpendicular to the direction 112.

[0040] FIG. 1A also shows an example of one or more cells 130 (e.g., one or more switch cells, corner endcap cells, and / or other types of cells) colliding with the tap column 120-3 on the chip. The collision may break the termination cell requirement for the tap column 120-3. Note that the chip includes other cells that do not collide with the tap columns 120-1, 120-2, and 120-3, which are not explicitly shown in FIG. 1A.

[0041] One approach to avoid collision is to move the one or more cells 130 to avoid the collision. In this regard, FIG. 1B shows an example in which the one or more cells 130 are moved to avoid the collision with the tap column 120-3. However, moving the one or more cells 130 to avoid the collision may impact core area utilization and can increase the design size. For example, in the example illustrated in FIG.1B, the design width is increased by “X”. Also, changing the placement and / or shape of the one or more cells 130 to avoid the collision can negatively impact design cycle turn around time (TAT).

[0042] Another approach to avoid collision is to vary the pitch (i.e., spacing) between tap columns in the direction 114 to avoid the collision. However, using a fixed pitch for the tap columns is more desirable than using a variable pitch for the tap columns. This is because a predicable pitch between tap columns is desirable to avoid latch-up violations, help control area / design size change, and help with the arrangement of other fixed cells in a core area (e.g., power switch cells, large repeaters, macros, and the like).

[0043] FIGS.2A and 2B shows an example of a layout 205 of cells in a block illustrating various scenarios in which a tap column collides with one or more cells. FIG. 2A shows a left half of the layout 205 and FIG. 2B shows a right half of the layout 205. In the example in FIGS. 2A and 2B, endcap cells are placed along the boundary of the block (e.g., to terminate rows and columns in the block). The area within the block may be referred toQualcomm Ref. No.2308574WO 6 as the core area or core region. In this example, the layout 205 includes tap columns 210, 212, 214, 216, 218, 220, 222, 224, 226, and 228. The layout 205 also includes switch cells 230-1 and 230-2, vss corner cells 240-1 to 240-5, vss corner neighbor cells 245-1 to 245-5, vdd corner cells 250-1 to 250-5, and vdd corner neighbor cells 255-1 to 255-5. It is to be appreciated that the layout 205 may include additional cells (e.g., standard cells) within the block. Note that tap column 210 is shown in both FIGS.2A and 2B to indicate the relationship between the first half of the layout 205 shown in FIG. 2A and the right half of the layout 205 shown in FIG. 2B.

[0044] In the example shown in FIGS. 2A and 2B, the tap columns 210 and 212 have no collisions. Each of these tap columns 210 and 212 is terminated at the top and the bottom with termination cells adjacent to rows of endcap cells on the boundary of the block. FIGS.2A and 2B also show various examples of collisions between tap columns and one or more cells. For example, FIGS. 2A and 2B show examples of collisions 232-1 and 232-2 between tap columns 214 and 216 and switch cells 230-1 and 230-2, respectively, which causes breaks in the tap columns 214 and 216. FIGS. 2A and 2B also show examples of corner collisions 260-1 to 260-7 in which tap columns 218, 220, 222, 224, and 226 collide with corner endcap cells. In these example, the termination requirement for each of the tap columns 218, 220, 222, 224, and 226 is not meet because each of these tap columns has at least one end that does not terminate at a row of endcap cells with a termination cell.

[0045] FIGS.2A and 2B also show an example of a narrow channel area 236, which has a narrow width in the direction 114 that allows the endcap cells on the left and right boundaries of the narrow channel area 236 to provide latch-up coverage for the cells in the narrow channel area 236 without the need for tap cells. Since tap cells are not needed in the narrow channel area 236, it is desirable to end the tap column 228 before the narrow channel area 236 to increase area efficiency. However, ending the tap column 228 within the core region does meet the termination requirement because the bottom 235 of the tap column 228 does not terminate at a row of endcap cells with a termination cell.

[0046] To address the above, aspects of the present disclosure provide floating termination cells that allow a tap column to be terminated within a core region (e.g., to avoid collision with one or more cells (e.g., switch cells, a corner endcap cells, a macro, and the like) and / or to terminate a tap column in a narrow channel area). This avoids the need for moving one or more cells to avoid the collision with a tap column, which can lead to area inefficiency due to redesign of the floorplan shape, change in the placement of the cells, and so on.Qualcomm Ref. No.2308574WO 7 This also avoids the need for having to move (i.e., shift) an entire tap column to avoid the collision. Exemplary features of the floating termination cells and exemplary tap cell placement arrangements are discussed further below.

[0047] FIG. 3A shows an example of a floating termination cell 310 including an n-tap 320 and floating devices 330 according to certain aspects of the present disclosure. As discussed further below, the floating termination cell 310 may be used to terminate a tap column within a core area. It is to be appreciated that the orientation of the floating termination cell 310 shown in the example in FIG.3A may be flipped in the direction 112, as discussed further below.

[0048] In this example, the floating termination cell 310 includes an N-well 315 that may extend across the cell 310 in the direction 114 (e.g., horizontal direction). The N-well 315 may extend to other cells (not shown) adjacent to the cell 310 in the direction 114. The n-tap 320 couples the N-well 315 to a supply rail 380 (shown in FIG.3B), which is configured to provide a supply voltage vdd. The supply rail 380 may also be referred to as a power rail, a voltage supply rail, the vdd rail, or another term, and the n-tap 320 may also be referred to as an N-well tap, or another term.

[0049] In the example in FIG. 3A, the n-tap 320 includes an active region 325 over the N-well 315. The active region 325 may also be referred to as an RX region, an oxide diffusion (OD) region, or another term. In certain aspects, the active region 325 is an n-type active region with n-type dopants (labeled NPLUS in FIG. 3A). The n-tap 320 also includes one or more contacts (e.g., metal contacts) formed on the active region 325 (e.g., using a lithographic and etching process), and one or more vias coupling the one or more contacts to the supply rail 380 (shown in FIG. 3B). Thus, in this example, the n-tap 320 couples the N-well 315 to the supply rail 380 through the active region 325, the one or more contacts, and the one or more vias of the n-tap 320. The supply rail 380 (shown in FIG. 3B) may be formed from metal layer M0 or another metal layer (e.g., using a lithographic and etching process).

[0050] In the example in FIG. 3A, the floating devices 330 include one or more active regions 332, 334, 336, and 338 extending in direction 114 (e.g., horizontal direction). For a FinFET process, the one or more active regions 332, 334, 336, and 338 may each include fins extending in the direction 114. Each of the one or more active regions 332, 334, 336, and 338 may be an n-type active region with n-type dopants (labeled NPLUS in FIG.3A). In this example, the one or more active regions 332, 334, 336, and 338 are spaced apart in the direction 114 (e.g., using a cut layer during processing).Qualcomm Ref. No.2308574WO 8

[0051] The floating devices 330 also include a plurality of gates formed over the one or more active regions 332, 334, 336, and 338, in which the gates are spaced apart in the direction 114. Each of the gates is elongated and extends in the direction 112 (e.g., vertical direction), which is perpendicular to the direction 114. In certain aspects, each of the gates may include polysilicon. In these aspects, the gates may also be referred to as poly gates. However, it is to be appreciated that the gates are not limited to the example of poly gates. In this example, the floating devices 330 also include contacts formed on the one or more active regions 332, 334, 336, and 338 and disposed between the gates. The contacts may be formed from a contact layer (referred to as contact active (CA) layer, metal-diffusion (MD) layer, or another term) using a lithographic and etching process. In certain aspects, the gates and the contacts are electrically floating (i.e., not coupled to any one of a supply rail, a ground rail, and a signal path).

[0052] As discussed above, the floating termination cell 310 may be used to terminate a tap column within a core area. In this regard, FIG.4A shows an example in which the floating termination cell 310 is used to terminate the bottom of a tap column within the core area. In this example, a first side 412 of the floating termination cell 310 adjacent to the n-tap 320 is adjacent to a tap cell 410 of the tap column to terminate the tap column. In the example in FIG. 4A, the tap cell 410 includes an n-tap 415 adjacent to the n-tap 320 of the floating termination cell 310. The n-tap 415 may have a structure similar to the structure of the n-tap 320. The n-tap 415 couples an N-well (not shown) in the tap cell 410 to the supply rail 380 shown in FIG.3B or another supply rail. The N-well in the tap cell 410 may be contiguous with the N-well 315 in the floating termination cell 310 or separate.

[0053] In this example, a second side 414 of the floating termination cell 310 adjacent to the floating devices 330 is adjacent to a standard cell 420. For example, the standard cell 420 may be a power switch cell including one or more switches (e.g., for power gating), a corner endcap cell, or another type of cell. The first side 412 and the second side 414 of the floating termination cell 310 are opposite sides (i.e., opposing sides) of the floating termination cell 310.

[0054] It is to be appreciated that the structure of the floating termination cell 310 may be flipped in the direction 112 to terminate the top of a tap column. In this regard, FIG. 4B shows an example in which the floating termination cell 310 is flipped in the direction 112 to terminate the top of the tap column. In this example, the first side 412 of the floatingQualcomm Ref. No.2308574WO 9 termination cell 310 is adjacent to a top side of the tap cell 410, and the second side 414 of the floating termination cell 310 is adjacent to a bottom side of the standard cell 420.

[0055] It is to be appreciated that a chip may include multiple instances of the floating termination cell 310 to terminate tap columns within a core area. One or more of the instances of the floating termination cell 310 may each have the exemplary orientation shown in FIG. 4A to terminate the bottom of one or more tap columns, and one or more other instances of the floating termination cell 310 may each have the exemplary orientation shown in FIG. 4B to terminate the top of one or more tap columns.

[0056] FIG. 5A shows an example of a floating termination cell 510 including an p-tap 520 and floating devices 530 according to certain aspects of the present disclosure. As discussed further below, the floating termination cell 510 may be used to terminate a tap column within a core area. It is to be appreciated that the orientation of the floating termination cell 510 shown in the example in FIG.5A may be flipped in the direction 112, as discussed further below.

[0057] In this example, the p-tap 520 couples the p-substrate to a ground rail 580 (shown in FIG. 5B), which may be at a ground potential. The ground rail 580 may also be referred to as a vss rail, or another term. In the example in FIG. 5A, the p-tap 520 includes an active region 525 over the p-substrate. The active region 525 may also be referred to as an RX region, an oxide diffusion (OD) region, or another term. In certain aspects, the active region 525 is a p-type active region with p-type dopants (labeled PPLUS in FIG. 5A). The p-tap 520 also includes one or more contacts (e.g., metal contacts) formed on the active region 525 (e.g., using a lithographic and etching process), and one or more vias coupling the one or more contacts to the ground rail 580 (shown in FIG. 5B). Thus, in this example, the p-tap 520 couples the p-substrate to the ground rail 580 through the active region 525, the one or more contacts, and the one or more vias of the p-tap 520. The ground rail 580 (shown in FIG. 5B) may be formed from metal layer M0 or another metal layer (e.g., using a lithographic and etching process).

[0058] In the example in FIG. 5A, the floating devices 530 include one or more active regions 532, 534, 536, and 538 extending in direction 114 (e.g., horizontal direction). For a FinFET process, the one or more active regions 532, 534, 536, and 538 may each include fins extending in the direction 114. Each of the one or more active regions 532, 534, 536, and 538 may be an p-type active region with p-type dopants (labeled PPLUS in FIG.5A). In this example, the one or more active regions 532, 534, 536, and 538 are spaced apart in the direction 114 (e.g., using a cut layer during processing).Qualcomm Ref. No.2308574WO 10

[0059] The floating devices 530 also include a plurality of gates formed over the one or more active regions 532, 534, 536, and 538, in which the gates are spaced apart in the direction 114. Each of the gates is elongated and extends in the direction 112 (e.g., vertical direction), which is perpendicular to the direction 114. In certain aspects, each of the gates may include polysilicon. In these aspects, the gates may also be referred to as poly gates. However, it is to be appreciated that the gates are not limited to the example of poly gates. In this example, the floating devices 530 also include contacts formed on the one or more active regions 532, 534, 536, and 538 and disposed between the gates. The contacts may be formed from a contact layer (referred to as CA layer, MD layer, or another term) using a lithographic and etching process. In certain aspects, the gates and the contacts are electrically floating (i.e., not coupled to any one of a supply rail, a ground rail, and a signal path).

[0060] As discussed above, the floating termination cell 510 may be used to terminate a tap column within a core area. In this regard, FIG.6A shows an example in which the floating termination cell 510 is used to terminate the bottom of a tap column within the core area. In this example, a first side 612 of the floating termination cell 510 adjacent to the p-tap 520 is adjacent to a tap cell 610 of the tap column to terminate the tap column. In the example in FIG. 6A, the tap cell 610 includes a p-tap 615 adjacent to the p-tap 520 of the floating termination cell 510. The p-tap 615 may have a structure similar to the structure of the n-tap 320. The p-tap 615 couples the p-substrate to the ground rail 580 shown in FIG. 5B or another ground rail.

[0061] In this example, a second side 614 of the floating termination cell 510 adjacent to the floating devices 530 is adjacent to a standard cell 620. For example, the standard cell 620 may be a power switch cell including one or more switches (e.g., for power gating), a corner endcap cell, or another type of cell. The first side 612 and the second side 614 of the floating termination cell 510 are opposite sides (i.e., opposing sides) of the floating termination cell 510.

[0062] It is to be appreciated that the structure of the floating termination cell 510 may be flipped in the direction 112 to terminate the top of a tap column. In this regard, FIG. 6B shows an example in which the floating termination cell 510 is flipped in the direction 112 to terminate the top of the tap column. In this example, the first side 612 of the floating termination cell 510 is adjacent to a top side of the tap cell 610, and the second side 614 of the floating termination cell 510 is adjacent to a bottom side of the standard cell 620.Qualcomm Ref. No.2308574WO 11

[0063] It is to be appreciated that a chip may include multiple instances of the floating termination cell 510 to terminate tap columns within a core area. One or more of the instances of the floating termination cell 510 may each have the exemplary orientation shown in FIG. 6A to terminate the bottom of one or more tap columns, and one or more other instances of the floating termination cell 510 may each have the exemplary orientation shown in FIG. 6B to terminate the top of one or more tap columns. It is also to be appreciated that the chip may include both instances of the floating termination cell 310 and instances of the floating termination cell 510.

[0064] FIGS. 7A and 7B show an exemplary layout 710 including an arrangement of floating termination cells according to aspects of the present disclosure. FIG.7A shows a left half of the layout 710 and FIG. 7B shows a right half of the layout 710. In this example, the layout 710 includes the tap columns 210, 212, 218, 220, 222, 224, 226, and 228 discussed above. The layout 710 may also include the switch cells 230-1 and 230-2, vss corner cells 240-1 to 240-5, vss corner neighbor cells 245-1 to 245-5, vdd corner cells 250-1 to 250- 5, and vdd corner neighbor cells 255-1 to 255-5.

[0065] In the example shown in FIGS. 7A and 7B, the floating termination cells include n-tap floating termination cells and p-tap floating termination cells. Each of the n-tap floating termination cells may be a separate instance (i.e., copy) of the exemplary floating termination cell 310, and each of the p-tap floating termination cells may be a separate instance (i.e., copy) of the exemplary floating termination cell 510. As discussed above, the floating termination cells allow a tap column to be terminated within a core region (e.g., to avoid collision with one or more cells (e.g., switch cells, a corner endcap cells, a macro, and the like) and / or to terminate a tap column in a narrow channel area).

[0066] In this regard, FIGS.7A and 7B show various examples in which the floating termination cells according to aspects of the present disclosure are used to terminate tap columns within the core region. For example, FIGS. 7A and 7B show an example where the floating termination cells are arranged to terminate tap columns to avoid collisions with the switch cells 230-1 and 230-2 without the need to move the switch cells 230-1 and 230-2. In this example, the floating termination cell 734 terminates the bottom of the tap column 732 and the floating termination cell 738 terminates the top of column 736 to avoid collision with the switch cell 230-1. Also, in this example, the floating termination cell 744 terminates the bottom of the tap column 742 and the floating termination cell 748 terminates the top of column 746 to avoid collision with the switch cell 230-2. FIGS.7A and 7B also show an example where the floating termination cells are used to terminateQualcomm Ref. No.2308574WO 12 tap columns to avoid collisions with corner endcap cells including vss corner cells 240- 1, 240-2, 240-3, and 240-5 and vdd corner cells 250-3, 250-4, and 250-5.

[0067] FIGS. 7A and 7B also shows an example where the floating termination cell 754 terminates the bottom of the tap column 228 within the core region. This stops the tap column 228 from extending across the narrow channel area 236, which increases area efficiency by making more space within the narrow channel area 236 available for other cells.

[0068] When a tap column is terminated with a floating termination cell to avoid a collision with a cell (e.g., a switch cell, a corner endcap cell, or another cell), one or more tap cells may be placed next to the cell in the same row(s) as the cell to provide latch-up coverage for the row(s). Examples of this approach are illustrated in FIGS. 7A and 7B. For example, FIG. 7B shows an example of a tap column 770 including two tap cells adjacent to the left side of the switch cell 230-2 to provide latch-up coverage for the two rows including the switch cell 230-2. The top and the bottom of the tap column 770 are terminated by floating termination cells 772 and 774, respectively.

[0069] Aspects of the present disclosure provide tap cells with continuous N-well or continuous p-substrate or P-well. In certain aspects, a tap cell with a continuous N-well or a continuous p-substrate or P-well provides latch-up coverage for one or more cells located above and / or below the tap cell. This allows the tap cell to terminate a tap column (e.g., the tap column 770) to avoid collision with a cell (e.g., the switch cell 230-2 or a corner endcap cell) while avoiding the need for placing one or more tap cells (e.g., tap column 770) next to the cell in the same row(s) as the cell to provide latch-up coverage for the row(s). Avoiding the need for placing the one or more tap cells next to the cell (e.g., the switch cell 230-2) improves area efficiency and reduces placement disturbance in the layout (e.g., layout 705). The above features and other features of the present disclosure are discussed further below.

[0070] FIG. 8A shows a top view of an exemplary tap cell 810 with a continuous N-well 815 according to certain aspects. The N-well 815 may be formed in a p-substrate using a N- well process (e.g., diffusion, ion implantation, etc.). In certain aspects, the tap cell 810 may extend across two rows in the direction 112 (e.g., the vertical direction) where each row includes two rows of active regions. In the example in FIG. 8A, the tap cell 810 includes the N-well 815, a first n-tap 820, a second n-tap 825, a first p-tap 830, and a second p-tap 835. As discussed further below, the tap cell 810 may be used to terminateQualcomm Ref. No.2308574WO 13 a tap column. For examples where the tap cell 810 is used to terminate a tap column, the tap cell 810 may also be referred to as a termination tap cell.

[0071] In this example, the N-well 815 has an I shape in which a first portion 818 of the N-well 815 extends continuously across the tap cell 810 in the direction 112 (e.g., the vertical direction). The first n-tap 820 and the second n-tap 825 are disposed on the N-well 815. The first n-tap 820 couples the N-well 815 to a first supply rail 840 (shown in FIG. 8B) and the second n-tap 825 couples the N-well 815 to a second supply rail 845 to provide N-well latch-up coverage.

[0072] The first p-tap 830 and the second p-tap 835 are disposed on a p-substrate or a P-well, and are both located outside of the N-well 815. In the example in FIG. 8A, the first portion 818 of the N-well 815 is disposed between the first p-tap 830 and the second p- tap 835 with the first p-tap 830 located to the left of the first portion 818 and the second p-tap 835 located to the right of the first portion 818. The first p-tap 830 and the second p-tap 835 couple the p-substrate or the P-well to a ground rail 850 (shown in FIG. 8B) to provide p-substrate or P-well latch-up coverage for cells (not shown) located to the left and / or the right of the tap cell 810.

[0073] In this example, the I shape of the N-well 815 includes a second portion 822 extending from the first portion 818 in the direction 114 (e.g., horizontal direction) and a third portion 824 extending from the first portion 818 in the direction 114 (e.g., horizontal direction) with the first p-tap 830 between the second portion 822 and the third portion 824 in the direction 112 (e.g., the vertical direction). The I shape of the N-well 815 also includes a fourth portion 832 extending from the first portion 818 in the direction 114 (e.g., horizontal direction) and a fifth portion 834 extending from the first portion 818 in the direction 114 (e.g., horizontal direction) with the second p-tap 835 between the fourth portion 832 and the fifth portion 834 in the direction 112 (e.g., the vertical direction). The I shape of the N-well 815 allows the first portion 818 of the N-well 815 to extend continuously in the direction 112 (e.g., the vertical direction) while providing a space to the left of the first portion 818 for the first p-tap 830 and a space to the right of the first portion 818 for the second p-tap 835.

[0074] As shown in FIG.8B, the ground rail 1050 and the supply rails 840 and 845 extend in the direction 114 (e.g., horizontal direction) with the ground rail 850 disposed between the first supply rail 840 and the second supply rail 845 in the direction 112 (e.g., the vertical direction). The ground rail 850 and the supply rails 840 and 845 may each be formedQualcomm Ref. No.2308574WO 14 from metal layer M0 or another metal layer (e.g., using a lithographic and etching process).

[0075] FIG. 9A shows an example in which the tap cell 810 terminates the bottom of a tap column. In this example, a first side 912 of the tap cell 810 is adjacent to a tap cell 910, in which the tap cell 910 is arranged vertically with other tap cells (not shown in FIG. 9A) in the tap column. A second side 914 of the tap cell 810 is adjacent to a standard cell 920. For example, the standard cell 920 may be a power switch cell including one or more switches (e.g., for power gating), a corner endcap cell, or another type of cell. The first side 912 and the second side 914 of the tap cell 810 are opposite sides (i.e., opposing sides) of the tap cell 810. It is to be appreciated that the tap cell 910 may have a different length than the tap cell 810 in the direction 114 (e.g., horizontal direction) and that the standard cell 920 may have a different length than the tap cell 810 in the direction 114 (e.g., horizontal direction).

[0076] In this example, the standard cell 920 includes an N-well 930. In certain aspects, the N- well 930 is contiguous with the N-well 815 of the tap cell 810. Because the N-well 930 is contiguous with the N-well 815 of the tap cell 810, the n-taps 825 and 820 of the tap cell 810 provide latch-up coverage for the standard cell 920. This may avoid the need for placing one or more additional tap cells on the left side and / or the right side of the standard cell to provide the latch-up coverage. It is to be appreciated that the N-well 930 may extend in the direction 114 (e.g., horizontal direction) across other cells in the same row(s) to provide latch-up coverage for the other cells.

[0077] As shown in FIG. 9A, the standard cell 920 may include a p-type field effect transistor (PFET) 940 disposed on the N-well 930. For the example where the standard cell 920 is a switch cell, the PFET 940 may implement a power switch, which may be coupled between the second supply rail 845 (shown in FIG.8B) and another supply rail to provide power gating between the supply rails. In the example shown in FIG. 9A, the PFET 940 includes a p-type active region (labeled PPLUS in FIG. 9A) disposed on the N-well 930, gates formed over the p-type active region, and contacts formed on the p-type active region and disposed between the gates. In this example, the p-type active region extends in the direction 114 (e.g., horizontal direction) and the gates and the contacts extend in the direction 112 (e.g., vertical direction). The gates may include polysilicon and / or another gate material and the contacts may be formed from a contact layer (referred to as contact active (CA) layer, metal-diffusion (MD) layer, or another term) using a lithographic and etching process. The layout of the standard cell 920 may be specified inQualcomm Ref. No.2308574WO 15 a standard cell library, as discussed further below. It is to be appreciated that the standard cell 920 may include multiple PFETs including the PFET 940. In its also to be appreciated that the standard cell 920 may also include one or more n-type field effect transistors (NFETs).

[0078] FIG. 9B shows an example in which the tap cell 910 is adjacent to the second side 914 of the tap cell 810 and the standard cell 920 is adjacent to the first side 912 of the tap cell 810. In this example, the tap cell 810 terminates the top of a tap column, in which the tap cell 910 is arranged vertically with other tap cells (not shown in FIG. 9B) in the tap column.

[0079] FIG. 10A shows a top view of an exemplary tap cell 1010 with a continuous p-substrate or P-well according to certain aspects. As used herein a continuous p-substrate is a continuous area of the p-substrate within which no N-well is formed. A P-well may be formed in a p-substrate and have a different p doping level than the p-substrate. In certain aspects, the tap cell 1010 may extend across two rows in the direction 112 (e.g., the vertical direction) where each row includes two rows of active regions. In the example in FIG. 10A, the tap cell 1010 includes a first p-tap 1020, a second p-tap 1025, a first n- tap 1030, a second n-tap 1035, a first N-well 1040, and a second N-well 1045. As discussed further below, the tap cell 1010 may be used to terminate a tap column. For examples where the tap cell 1010 is used to terminate a tap column, the tap cell 810 may also be referred to as a termination tap cell.

[0080] In the example shown in FIG.10A, the first N-well 1040 is located in a left half of the tap cell 1010 and the second N-well 1045 is located in a right half of the tap cell 1010. The continuous p-substrate or P-well extends continuously across the tap cell 1010 in the direction 112 (e.g., the vertical direction) between the first N-well 1040 and the second N-well 1045. The first p-tap 1020 and the second p-tap 1025 are disposed on the p- substrate or the P well. The first p-tap 1020 couples the p-substrate or P-well to a first ground rail 1050 (shown in FIG. 10B) and the second p-tap 1025 couples the p-substrate or P-well to a second ground rail 1055 to provide p-substrate or P-well latch-up coverage.

[0081] The first n-tap 1030 is disposed on the first N-well 1040 and the second n-tap 1035 is disposed on the second N-well 1045. The first n-tap 1030 couples the first N-well 1040 to a supply rail 1060 (shown in FIG. 10B) to provide N-well latch-up coverage to cells located to the left of the tap cell 1010. It is to be appreciated that the first N-well 1040 may be contiguous with an N-well (not shown) extending from the left of the tap cell 1010 in the direction 114 (e.g., horizontal direction). The second n-tap 1035 couples theQualcomm Ref. No.2308574WO 16 second N-well 1045 to the supply rail 1060 (shown in FIG.10B) to provide N-well latch- up coverage to cells located to the right of the tap cell 1010. It is to be appreciated that the second N-well 1045 may be contiguous with an N-well (not shown) extending from the right of the tap cell 1010 in the direction 114 (e.g., horizontal direction).

[0082] As shown in FIG. 10B, the supply rail 1060 and the ground rails 1050 and 1055 extend in the direction 114 (e.g., horizontal direction) with the supply rail 1060 disposed between the first ground rail 1050 and the ground rail 1055 in the direction 112 (e.g., the vertical direction). The supply rail 1060 and the ground rails 1050 and 1055 may each be formed from metal layer M0 or another metal layer (e.g., using a lithographic and etching process).

[0083] FIG. 11A shows an example in which the tap cell 1010 terminates the bottom of a tap column. In this example, a first side 1112 of the tap cell 1010 is adjacent to a tap cell 1110, in which the tap cell 1110 is arranged vertically with other tap cells (not shown in FIG. 11A) in the tap column. A second side 1114 of the tap cell 1010 is adjacent to a standard cell 1120, For example, the standard cell 1120 may be a corner endcap cell, a power switch cell, or another type of cell. The first side 1112 and the second side 1114 of the tap cell 1010 are opposite sides (i.e., opposing sides) of the tap cell 1010. It is to be appreciated that the tap cell 1110 may have a different length than the tap cell 1010 in the direction 114 (e.g., horizontal direction) and that the standard cell 1120 may have a different length than the tap cell 1010 in the direction 114 (e.g., horizontal direction). In this example, the p-taps 1020 and 1025 in the tap cell 1010 provide p-substrate or P-well latch-up coverage for the standard cell 1120, which is formed on the p-substrate or on a P-well that is contiguous with the P-well in the tap cell 1010.

[0084] FIG.11B shows an example in which the tap cell 1110 is adjacent to the second side 1114 of the tap cell 1010 and the standard cell 1120 is adjacent to the first side 1112 of the tap cell 1010. In this example, the tap cell 1010 terminates the top of a tap column, in which the tap cell 1110 is arranged vertically with other tap cells (not shown in FIG.11B) in the tap column.

[0085] FIGS.12A and 12B show an exemplary layout 1210 including an arrangement of tap cells with continuous N-well and tap cells with continuous p-substrate or P-well according to aspects of the present disclosure. FIG. 12A shows a left half of the layout 1210 and FIG. 12B shows a right half of the layout 1210. In this example, the layout 1210 includes the tap columns 210, 212, 218, 220, 222, 224, 226, and 228 discussed above. The layout 1210 may also include the switch cells 230-1 and 230-2, vss corner cells 240-1 to 240-5,Qualcomm Ref. No.2308574WO 17 vss corner neighbor cells 245-1 to 245-5, vdd corner cells 250-1 to 250-5, and vdd corner neighbor cells 255-1 to 255-5.

[0086] In the example shown in FIGS. 12A and 12B, each of the tap cells with continuous N- well may be a separate instance (i.e., copy) of the exemplary tap cell 810, and each of the tap cells with continuous p-substrate or P-well may be a separate instance (i.e., copy) of the exemplary tap cell 1010. In this regard, FIGS. 12A and 12B show various examples in which the tap cells with continuous N-well and the tap cells with continuous p-substrate or P-well according to aspects of the present disclosure are used to terminate tap columns within the core region. For example, FIG. 12A shows an example where a first tap cell with continuous N-well 1234 terminates the bottom of the tap column 1232 and a second tap cell with continuous N-well 1238 terminates the top of column 1236 to avoid collision with the switch cell 230-1. In this example, the first tap cell with continuous N-well 1234 and the second tap cell with continuous N-well 1238 provide latch-up coverage for the switch cell 230-1 and cells in the same rows as the switch cell 230-1. This avoids the need of having to place taps cells next to the left side or next to the right side of switch cell 230-1 to provide the latch-up coverage for the rows. FIG. 12B shows another example where a first tap cell with continuous N-well 1244 terminates the bottom of the tap column 1242 and a second tap cell with continuous N-well 1448 terminates the top of column 1446 to avoid collision with the switch cell 230-2. In this example, the first tap cell with continuous N-well 1244 and the second tap cell with continuous N-well 1248 provide latch-up coverage for the switch cell 230-2 and cells in the same rows as the switch cell 230-2.

[0087] FIG. 13A shows an example layout of the tap cell 810 according to certain aspects of the present disclosure. In this example, the first n-tap 820 includes one or more active regions 1310 disposed on the N-well 815. The one or more active regions 1310 extend in the direction 114 (e.g., horizontal direction) and are n-type active regions with n-type dopants (labeled NPLUS in FIG. 13A). The first n-tap 820 also includes one or more contacts (e.g., metal contacts) formed on the one or more active regions 1310 (e.g., using a lithographic and etching process), and one or more vias 1315 coupling the one or more contacts to the first supply rail 840 (shown in FIG. 13B). Thus, in this example, the first n-tap 820 couples the N-well 815 to the first supply rail 840 through the one or more active regions 1310, the one or more contacts, and the one or more vias 1315 of the first n-tap 820.Qualcomm Ref. No.2308574WO 18

[0088] The second n-tap 825 includes one or more active regions 1320 disposed on the N-well 815. The one or more active regions 1320 extend in the direction 114 (e.g., horizontal direction) and are n-type active regions with n-type dopants (labeled NPLUS in FIG. 13A). The second n-tap 825 also includes one or more contacts (e.g., metal contacts) formed on the one or more active regions 1320 (e.g., using a lithographic and etching process), and one or more vias 1325 coupling the one or more contacts to the second supply rail 845 (shown in FIG.13B). Thus, in this example, the second n-tap 825 couples the N-well 815 to the second supply rail 845 through the one or more active regions 1320, the one or more contacts, and the one or more vias 1325 of the second n-tap 825.

[0089] The first p-tap 830 includes one or more active regions 1330 disposed on the p-substrate or P-well. The one or more active regions 1330 extend in the direction 114 (e.g., horizontal direction) and are p-type active regions with p-type dopants (labeled PPLUS in FIG.13A). The first p-tap 830 also includes one or more contacts (e.g., metal contacts) formed on the one or more active regions 1330 (e.g., using a lithographic and etching process), and one or more vias 1335 coupling the one or more contacts to the ground rail 850 (shown in FIG. 13B). Thus, in this example, the first p-tap 830 couples the p- substrate or the P-well to the ground rail 850 through the one or more active regions 1330, the one or more contacts, and the one or more vias 1335 of the first p-tap 830.

[0090] The second p-tap 835 includes one or more active regions 1340 disposed on the p- substrate or P-well. The one or more active regions 1340 extend in the direction 114 (e.g., horizontal direction) and are p-type active regions with p-type dopants (labeled PPLUS in FIG. 13A). The second p-tap 835 also includes one or more contacts (e.g., metal contacts) formed on the one or more active regions 1340 (e.g., using a lithographic and etching process), and one or more vias 1345 coupling the one or more contacts to the ground rail 850 (shown in FIG.13B). Thus, in this example, the second p-tap 835 couples the p-substrate or the P-well to the ground rail 850 through the one or more active regions 1340, the one or more contacts, and the one or more vias 1345 of the second p-tap 835.

[0091] The tap cell 810 may also include gates formed over the one or more active regions 1310, 1320, 1330, and 1340, in which the gates are spaced apart in the direction 114, as shown in FIG.13A. Each of the gates is elongated and extends in the direction 112 (e.g., vertical direction), which is perpendicular to the direction 114. In certain aspects, each of the gates may include polysilicon.

[0092] In certain aspects, the one or more vias 1315 of the first n-tap 820 may not be aligned with the first supply rail 840 in the direction 112 (e.g., vertical direction) due to DRCQualcomm Ref. No.2308574WO 19 constraints or other constraints. In this regard, FIGS. 14A and 14B show an example in which the one or more vias 1315 of the first n-tap 820 are coupled to the first supply rail 840 through metal routing 1450 (shown in FIG.14B) extending in the direction 114. The metal routing 1450 may be formed from the same metal layer (e.g., metal layer M0) as the first supply rail 840. In this example, the tap cell 810 includes via 1410 align with one or more vias 1315 of the first n-tap 820 in the direction 112 (e.g., vertical direction) and one or more vias 1420 aligned with the first supply rail 840 in the direction 112. The via 1410 is coupled to the one or more vias 1420 through one or more contact layers, as shown in FIG. 14A. In this example, the metal routing 1450 is coupled between the one or more vias 1315 of the first n-tap 820 and the via 1410, and the via 1410 is coupled to the first supply rail 840 through the one or more contacts and the one or more vias 1420. Thus, in this example, the one or more vias 1315 of the first n-tap 820 are coupled to the first supply rail 840 through the metal routing 1450.

[0093] Similarly, the one or more vias 1325 of the second n-tap 825 may not be aligned with the second supply rail 845 in the direction 112 (e.g., vertical direction) due to DRC constraints or other constraints. In this regard, FIGS. 14A and 14B show an example in which the one or more vias 1325 of the second n-tap 825 are coupled to the second supply rail 845 through metal routing 1460 (shown in FIG. 14B) extending in the direction 114. The metal routing 1460 may be formed from the same metal layer (e.g., metal layer M0) as the second supply rail 845. In this example, the tap cell 810 includes via 1430 align with one or more vias 1325 of the first n-tap 820 in the direction 112 (e.g., vertical direction) and one or more vias 1440 aligned with the second supply rail 845 in the direction 112. The via 1430 is coupled to the one or more vias 1440 through one or more contact layers, as shown in FIG. 14A. In this example, the metal routing 1460 is coupled between the one or more vias 1325 of the second n-tap 825 and the via 1430, and the via 1430 is coupled to the second supply rail 845 through the one or more contacts and the one or more vias 1440. Thus, in this example, the one or more vias 1325 of the second n-tap 825 are coupled to the second supply rail 845 through the metal routing 1460.

[0094] FIG. 15A shows an example layout of the tap cell 1010 according to certain aspects of the present disclosure. In this example, the first p-tap 1020 includes one or more active regions 1510 disposed on the p-substrate or P-well. The one or more active regions 1510 extend in the direction 114 (e.g., horizontal direction) and are p-type active regions with p-type dopants (labeled PPLUS in FIG. 15A). The first p-tap 1020 also includes one or more contacts (e.g., metal contacts) formed on the one or more active regions 1510 (e.g.,Qualcomm Ref. No.2308574WO 20 using a lithographic and etching process), and one or more vias 1515 coupling the one or more contacts to the first ground rail 1050 (shown in FIG. 15B). Thus, in this example, the first p-tap 1020 couples the p-substrate or P-well to the first ground rail 1050 through the one or more active regions 1510, the one or more contacts, and the one or more vias 1515.

[0095] The second p-tap 1025 includes one or more active regions 1520 disposed on the p- substrate or P-well. The one or more active regions 1520 extend in the direction 114 (e.g., horizontal direction) and are p-type active regions with p-type dopants (labeled PPLUS in FIG. 15A). The second p-tap 1025 also includes one or more contacts (e.g., metal contacts) formed on the one or more active regions 1520 (e.g., using a lithographic and etching process), and one or more vias 1525 coupling the one or more contacts to the second ground rail 1055 (shown in FIG. 15B). Thus, in this example, the second p-tap 1025 couples the p-substrate or P-well to the second ground rail 1055 through the one or more active regions 1520, the one or more contacts, and the one or more vias 1525.

[0096] The first n-tap 1030 includes one or more active regions 1530 disposed on the first N- well 1040. The one or more active regions 1530 extend in the direction 114 (e.g., horizontal direction) and are n-type active regions with n-type dopants (labeled NPLUS in FIG. 15A). The first n-tap 1030 also includes one or more contacts (e.g., metal contacts) formed on the one or more active regions 1530 (e.g., using a lithographic and etching process), and one or more vias 1535 coupling the one or more contacts to the supply rail 1060 (shown in FIG.15B). Thus, in this example, the first n-tap 1030 couples the first N-well 1040 to the supply rail 1060 through the one or more active regions 1530, the one or more contacts, and the one or more vias 1535.

[0097] The second n-tap 1035 includes one or more active regions 1540 disposed on the second N-well 1045. The one or more active regions 1540 extend in the direction 114 (e.g., horizontal direction) and are n-type active regions with n-type dopants (labeled NPLUS in FIG. 15A). The second n-tap 1035 also includes one or more contacts (e.g., metal contacts) formed on the one or more active regions 1540 (e.g., using a lithographic and etching process), and one or more vias 1545 coupling the one or more contacts to the supply rail 1060 (shown in FIG. 15B). Thus, in this example, the second n-tap 1035 couples the second N-well 1045 to the supply rail 1060 through the one or more active regions 1540, the one or more contacts, and the one or more vias 1545.

[0098] The tap cell 1010 may also include gates formed over the one or more active regions 1510, 1520, 1530, and 1540, in which the gates are spaced apart in the direction 114, asQualcomm Ref. No.2308574WO 21 shown in FIG. 15A. Each of the gates is elongated and extends in the direction 112 (e.g., vertical direction), which is perpendicular to the direction 114. In certain aspects, each of the gates may include polysilicon.

[0099] In certain aspects, the exemplary layouts discussed above may be determined using a computer system. In this regard, FIG. 16 illustrates a computer system 1600 that may be used to determine a layout (e.g., layout 710 and / or layout 1210) for a chip according to certain aspects. The computer system 1600 may include a processor 1620, a memory 1610, a network interface 1630, and a user interface 1640. These components may be in electronic communication via one or more buses 1645.

[0100] The memory 1610 may store instructions 1615 that are executable by the processor 1620 to cause the computer system 1600 to perform one or more of the operations described herein. The processor 1620 may include a general-purpose processor, a digital signal processor (DSP), a central processing unit (CPU), a microcontroller, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a programmable logic device, a discrete gate or transistor logic component, a discrete hardware component, or any combination thereof. The memory 1610 may include, by way of example, random access memory (RAM), flash memory, read only memory (ROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), registers, magnetic disks, optical disks, hard drives, or any other suitable storage medium, or any combination thereof. The memory 1610 may also store a standard cell library in which the standard cell library includes one or more files specifying layouts for various cells (e.g., standard cell 920 and / or standard cell 1120) that may be placed on the chip including the layouts of the tap cells, termination cells, switch cells, corner endcap cells, floating termination cells (e.g., floating termination cells 310 and 510), tap cells with continuous N-well (e.g., tap cell 810), and / or tap cells with continuous p-substrate or P- well (e.g., tap cell 1010).

[0101] The network interface 1630 is configured to interface the computer system 1600 with one or more other devices. The user interface 1640 may be configured to receive data from a user (e.g., via keypad, mouse, etc.) and provide the data to the processor 1620. The user interface 1640 may also be configured to output data from the processor 1620 to the user (e.g., via a display, a speaker, etc.).

[0102] In certain aspects, the processor 1620 is configured to generate a layout for at least a portion of a chip (i.e., chip layout), which may include retrieving cells from the standardQualcomm Ref. No.2308574WO 22 cell library in the memory 1610, specifying the placement (i.e., layout) of the retrieved cells on the chip based on a desired circuit design (e.g., specified in a netlist or another format in a file) and / or design rule checks (DRCs), and / or specifying metal routing in one or more of the metal layers (e.g., M0, M1, etc.) for providing signal routing and / or supply routing for the cells. The processor 1620 may be configured to store the layout in a file which may be stored in the memory 1610. In certain aspects, specifying the placement of the cells may include placing (i.e., laying out) the floating termination cells, the tap cells with continuous N-well, and / or the tap cells with continuous p-substrate or P-well on the chip to avoid collisions between tap columns and switch cells, corner endcap cells, and / or other types of cells.

[0103] Implementation examples are described in the following numbered clauses:

[0104] 1. A chip, comprising:

[0105] a tap column including tap cells arranged in a column; and

[0106] a floating termination cell terminating an end of the tap column, wherein the floating termination cell comprises:

[0107] an n-tap or a p-tap; and

[0108] floating devices.

[0109] 2. The chip of clause 1, wherein the floating devices include:

[0110] one or more active regions; and

[0111] gates formed on the one or more active regions, wherein the gates are floating.

[0112] 3. The chip of clause 2, wherein the floating devices further include contacts formed on the one or more active regions, wherein the contacts are disposed between the gates, and the contacts are floating.

[0113] 4. The chip of any one of clauses 1 to 3, wherein the n-tap is configured to couple an N-well to a voltage supply rail.

[0114] 5. The chip of any one of clauses 1 to 4, wherein the p-tap is configured to couple a p-substrate to a ground rail.

[0115] 6. The chip of any one of clauses 1 to 5, wherein the floating termination cell is adjacent to a switch cell or a corner endcap cell.

[0116] 7. The chip of any one of clauses 1 to 6, wherein a first side of the floating termination cell is adjacent to one of the tap cells in the tap column, a second side of the floating termination cell is adjacent to a switch cell or a corner endcap cell, and the first side and the second side are opposite sides of the floating termination cell.Qualcomm Ref. No.2308574WO 23

[0117] 8. The chip of clause 7, wherein the n-tap or the p-tap is between the first side of the floating termination cell and the floating devices.

[0118] 9. A chip, comprising:

[0119] a tap column including tap cells arranged in a column; and

[0120] a termination tap cell terminating an end of the tap column, wherein the termination tap cell comprises:

[0121] a first N-well extending across the termination tap cell in a first direction;

[0122] a first n-tap coupling the first N-well to a first supply rail;

[0123] a first p-tap coupling a p-substrate or a P-well to a ground rail; and

[0124] a second p-tap coupling the p-substrate or the P-well to the ground rail, wherein a first portion of the first N-well is disposed between the first p-tap and the second p-tap in a second direction perpendicular to the first direction.

[0125] 10. The chip of clause 9, wherein the termination tap cell further comprises:

[0126] a second n-tap coupling the first N-well to a second supply rail, wherein the ground rail is disposed between the first supply rail and the second supply rail in the first direction.

[0127] 11. The chip of clause 9 or 10, wherein the first n-tap comprises:

[0128] one or more n-type active regions disposed on the first N-well;

[0129] one or more contacts disposed on the one or more n-type active regions; and

[0130] one or more vias disposed on the one or more contacts, the one or more vias coupling the one or more contacts to the first supply rail.

[0131] 12. The chip of any one of clauses 9 to 11, further comprising a switch cell, wherein a first side of the termination tap cell is adjacent to one of the tap cells in the tap column, a second side of the termination tap cell is adjacent to the switch cell, and the first side and the second side are opposite sides of the termination tap cell.

[0132] 13. The chip of clause 12, wherein second switch comprises:

[0133] a second N-well that is contiguous with the first N-well; and

[0134] a p-type field effect transistor (PFET) disposed on the second N-well.

[0135] 14. The chip of any of clauses 9 to 11, further comprising a corner endcap cell, wherein a first side of the termination tap cell is adjacent to one of the tap cells in the tap column, a second side of the termination tap cell is adjacent to the corner endcap cell, and the first side and the second side are opposite sides of the termination tap cell.

[0136] 15. The chip of any one of clauses 9 to 14, wherein the first p-tap is between a second portion of the first N-well and a third portion of the first N-well in the first direction, theQualcomm Ref. No.2308574WO 24 second portion of the first N-well extends in the second direction, and the third portion of the first N-well extends in the second direction.

[0137] 16. The chip of clause 15, wherein the second p-tap is between a fourth portion of the first N-well and a fifth portion of the first N-well in the first direction, the fourth portion of the first N-well extends in the second direction, and the fifth portion of the first N-well extends in the second direction.

[0138] 17. A chip, comprising:

[0139] a tap column including tap cells arranged in a column; and

[0140] a termination tap cell terminating an end of the tap column, wherein the termination tap cell comprises:

[0141] a p-substrate or P-well extending across the termination tap cell in a first direction;

[0142] a first p-tap coupling the p-substrate or the P-well to a first ground rail;

[0143] a first N-well;

[0144] a first n-tap coupling the first N-well to a supply rail;

[0145] a second N-well, wherein the first N-well and the second N-well are separated by a portion of the p-substrate or the P-well in a second direction perpendicular to the first direction; and

[0146] a second n-tap coupling the second N-well to the supply rail.

[0147] 18. The chip of clause 17, wherein the termination tap cell further comprises:

[0148] a second p-tap coupling the p-substrate or the P-well to a second ground rail, wherein the supply rail is disposed between the first ground rail and the second ground rail in the first direction.

[0149] 19. The chip of clause 17 to 18, wherein the first p-tap comprises:

[0150] one or more p-type active regions disposed on the p-substrate or the P-well;

[0151] one or more contacts disposed on the one or more p-type active regions; and

[0152] one or more vias disposed on the one or more contacts, the one or more vias coupling the one or more contacts to the first ground rail.

[0153] 20. The chip of any one of clauses 17 to 19, further comprising a corner endcap cell, wherein a first side of the termination tap cell is adjacent to one of the tap cells in the tap column, a second side of the termination tap cell is adjacent to the corner endcap cell, and the first side and the second side are opposite sides of the termination tap cell.

[0154] Within the present disclosure, the word “exemplary” is used to mean “serving as an example, instance, or illustration.” Any implementation or aspect described herein asQualcomm Ref. No.2308574WO 25 “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term “aspects” does not require that all aspects of the disclosure include the discussed feature, advantage or mode of operation. The term “coupled” is used herein to refer to the direct or indirect electrical coupling between two structures.

[0155] Any reference to an element herein using a designation such as “first,” “second,” and so forth does not generally limit the quantity or order of those elements. Rather, these designations are used herein as a convenient way of distinguishing between two or more elements or instances of an element. Thus, a reference to first and second elements does not mean that only two elements can be employed, or that the first element must precede the second element.

[0156] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

Qualcomm Ref. No.2308574WO 26 CLAIMS 1. A chip, comprising: a tap column including tap cells arranged in a column; and a floating termination cell terminating an end of the tap column, wherein the floating termination cell comprises: an n-tap or a p-tap; and floating devices.

2. The chip of claim 1, wherein the floating devices include: one or more active regions; and gates formed on the one or more active regions, wherein the gates are floating.

3. The chip of claim 2, wherein the floating devices further include contacts formed on the one or more active regions, wherein the contacts are disposed between the gates, and the contacts are floating.

4. The chip of claim 1, wherein the n-tap is configured to couple an N-well to a voltage supply rail.

5. The chip of claim 1, wherein the p-tap is configured to couple a p-substrate to a ground rail.

6. The chip of claim 1, wherein the floating termination cell is adjacent to a switch cell or a corner endcap cell.

7. The chip of claim 1, wherein a first side of the floating termination cell is adjacent to one of the tap cells in the tap column, a second side of the floating termination cell is adjacent to a switch cell or a corner endcap cell, and the first side and the second side are opposite sides of the floating termination cell.

8. The chip of claim 7, wherein the n-tap or the p-tap is between the first side of the floating termination cell and the floating devices.Qualcomm Ref. No.2308574WO 27 9. A chip, comprising: a tap column including tap cells arranged in a column; and a termination tap cell terminating an end of the tap column, wherein the termination tap cell comprises: a first N-well extending across the termination tap cell in a first direction; a first n-tap coupling the first N-well to a first supply rail; a first p-tap coupling a p-substrate or a P-well to a ground rail; and a second p-tap coupling the p-substrate or the P-well to the ground rail, wherein a first portion of the first N-well is disposed between the first p-tap and the second p-tap in a second direction perpendicular to the first direction.

10. The chip of claim 9, wherein the termination tap cell further comprises: a second n-tap coupling the first N-well to a second supply rail, wherein the ground rail is disposed between the first supply rail and the second supply rail in the first direction.

11. The chip of claim 9, wherein the first n-tap comprises: one or more n-type active regions disposed on the first N-well; one or more contacts disposed on the one or more n-type active regions; and one or more vias disposed on the one or more contacts, the one or more vias coupling the one or more contacts to the first supply rail.

12. The chip of claim 9, further comprising a switch cell, wherein a first side of the termination tap cell is adjacent to one of the tap cells in the tap column, a second side of the termination tap cell is adjacent to the switch cell, and the first side and the second side are opposite sides of the termination tap cell.

13. The chip of claim 12, wherein second switch comprises: a second N-well that is contiguous with the first N-well; and a p-type field effect transistor (PFET) disposed on the second N-well.

14. The chip of claim 9, further comprising a corner endcap cell, wherein a first side of the termination tap cell is adjacent to one of the tap cells in the tap column, a secondQualcomm Ref. No.2308574WO 28 side of the termination tap cell is adjacent to the corner endcap cell, and the first side and the second side are opposite sides of the termination tap cell.

15. The chip of claim 9, wherein the first p-tap is between a second portion of the first N-well and a third portion of the first N-well in the first direction, the second portion of the first N-well extends in the second direction, and the third portion of the first N-well extends in the second direction.

16. The chip of claim 15, wherein the second p-tap is between a fourth portion of the first N-well and a fifth portion of the first N-well in the first direction, the fourth portion of the first N-well extends in the second direction, and the fifth portion of the first N-well extends in the second direction.

17. A chip, comprising: a tap column including tap cells arranged in a column; and a termination tap cell terminating an end of the tap column, wherein the termination tap cell comprises: a p-substrate or P-well extending across the termination tap cell in a first direction; a first p-tap coupling the p-substrate or the P-well to a first ground rail; a first N-well; a first n-tap coupling the first N-well to a supply rail; a second N-well, wherein the first N-well and the second N-well are separated by a portion of the p-substrate or the P-well in a second direction perpendicular to the first direction; and a second n-tap coupling the second N-well to the supply rail.

18. The chip of claim 17, wherein the termination tap cell further comprises: a second p-tap coupling the p-substrate or the P-well to a second ground rail, wherein the supply rail is disposed between the first ground rail and the second ground rail in the first direction.

19. The chip of claim 17, wherein the first p-tap comprises: one or more p-type active regions disposed on the p-substrate or the P-well;Qualcomm Ref. No.2308574WO 29 one or more contacts disposed on the one or more p-type active regions; and one or more vias disposed on the one or more contacts, the one or more vias coupling the one or more contacts to the first ground rail.

20. The chip of claim 17, further comprising a corner endcap cell, wherein a first side of the termination tap cell is adjacent to one of the tap cells in the tap column, a second side of the termination tap cell is adjacent to the corner endcap cell, and the first side and the second side are opposite sides of the termination tap cell.

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