Multilayer ceramic capacitor

Abstract

The objective of the present invention is to provide a multilayer ceramic capacitor that enables the specifications, etc., of the multilayer ceramic capacitor to be determined on the basis of a view in the stacking direction.　A multilayer ceramic capacitor 10 according to the present invention comprises: a multilayer body having a first main surface and a second main surface facing one other in the stacking direction, a first side surface and a second side surface facing one other in a first direction orthogonal to the stacking direction, and a third side surface and a fourth side surface facing one other in a second direction orthogonal to the stacking direction and the first direction; a first external electrode disposed on the first side surface, the third side surface, and the first main surface and / or the second main surface; a second external electrode disposed on the second side surface, the third side surface, and the first main surface and / or the second main surface; a third external electrode disposed on the first side surface, the fourth side surface, and the first main surface and / or the second main surface; and a fourth external electrode disposed on the second side surface, the fourth side surface, and the first main surface and / or the second main surface. The multilayer ceramic capacitor 10 is characterized in that, in the first external electrode to the fourth external electrode disposed on the first main surface and / or the second main surface, when viewed in the stacking direction, if straight lines parallel to the first direction and the second direction are drawn from points of intersection where the first external electrode to the fourth external electrode intersect the multilayer body, at least one recessed portion is disposed so as to project inward from an edge portion positioned on the central side of the multilayer body and inward from an outer edge of the range of a region surrounded by the straight lines in at least one of the first external electrode to the fourth external electrode.

Description

Multilayer ceramic capacitors

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] In recent years, as electronic devices incorporating multilayer ceramic capacitors become smaller in size, there has been a demand for multilayer ceramic capacitors with a lower height.

[0003] For example, Patent Document 1 discloses a multilayer ceramic capacitor having a dimension of less than 0.3 mm in the lamination direction. In the multilayer ceramic capacitor described in Patent Document 1, external electrodes formed on the laminate are composed of a base film made of a sintered metal film and a plating film disposed thereon.

[0004] Furthermore, Patent Document 2 discloses a multilayer ceramic capacitor in which, when two adjacent sides are defined as a first side and a second side, the ratio of the length of the first side to the length of the second side is 0.9 or more and 1.1 or less.

[0005] JP 2020-136363 A JP 2021-103730 A

[0006] However, because the shapes of the external electrodes are the same when viewed in the stacking direction of the multilayer ceramic capacitors, there is a risk that products with different capacitances may be mixed in. Furthermore, if marks are applied to each capacitance, depending on the material and shape, there is a risk that the external electrodes may become electrically connected to each other, and because the dimensions of the multilayer ceramic capacitor in the stacking direction are small, there is a risk that the multilayer ceramic capacitor may crack during the marking process.

[0007] SUMMARY OF THE INVENTION Therefore, a primary object of the present invention is to provide a multilayer ceramic capacitor that allows the specifications of the multilayer ceramic capacitor to be determined based on the view in the stacking direction.

[0008] A multilayer ceramic capacitor according to the present invention includes a laminate having a first main surface and a second main surface that face each other in a stacking direction, a first side surface and a second side surface that face each other in a first direction that is perpendicular to the stacking direction, and a third side surface and a fourth side surface that face each other in a second direction that is perpendicular to the stacking direction and the first direction; first external electrodes arranged on the first side surface, the third side surface, the first main surface, and / or the second main surface; second external electrodes arranged on the second side surface, the third side surface, the first main surface, and / or the second main surface; a third external electrode arranged on the first side surface, the fourth side surface, the first main surface, and / or the second main surface; and a fourth external electrode arranged on the top, fourth side surface, first main surface and / or second main surface, wherein, in the first to fourth external electrodes arranged on the first main surface and / or second main surface, when viewed in the stacking direction, when straight lines parallel to the first and second directions are drawn from the points of intersection where the first to fourth external electrodes intersect with the laminate, at least one external electrode of the first to fourth external electrodes has one or more recesses arranged inward from the outer edge of a range surrounded by the straight lines and protruding inward from an edge portion located toward the center of the laminate.

[0009] According to the multilayer ceramic capacitor of the present invention, in the first to fourth external electrodes arranged on the first main surface and / or the second main surface, when viewed in the stacking direction, when straight lines parallel to the first and second directions are drawn from the intersections where the first to fourth external electrodes intersect with the laminate, at least one of the first to fourth external electrodes has one or more recesses arranged inward from the outer edge of the range surrounded by the straight lines and protruding inward from an edge portion located toward the center of the laminate. Therefore, it is possible to provide a multilayer ceramic capacitor whose specifications, etc., can be determined by checking the presence or absence and size of the recesses with an image sensor or the like.

[0010] According to the present invention, a multilayer ceramic capacitor is provided that allows the specifications of the multilayer ceramic capacitor to be determined based on the view in the stacking direction.

[0011] The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments of the present invention, which proceeds with reference to the accompanying drawings.

[0012] 1 is a perspective view showing an example of a multilayer ceramic capacitor according to a first embodiment of the present invention; FIG. 2 is a front view showing an example of a multilayer ceramic capacitor according to the first embodiment of the present invention; FIG. 3 is a side view showing an example of a multilayer ceramic capacitor according to the first embodiment of the present invention; FIG. 4 is a plan view showing an example of a multilayer ceramic capacitor according to the first embodiment of the present invention; FIG. 5 is a plan view showing a state in which a thin film layer is disposed on a first main surface of a laminate; and FIG. 6 is a plan view showing a state in which an underlayer plating layer is disposed on the first main surface of the laminate.

[0033] FIG. 6 shows external electrodes of the multilayer ceramic capacitor according to the first embodiment of the present invention, where FIG. 6 is another example of the arrangement of recesses disposed in the external electrodes, FIG. 6 is yet another example of the arrangement of recesses disposed in the external electrodes, and FIG. 6 is yet another example of the arrangement of recesses disposed in the external electrodes.

[0034] FIG. 7 is a schematic cross-sectional view taken along line V-V in FIG. 1; FIG. 8 is a schematic cross-sectional view taken along line VI-VI in FIG. 1; FIG. 9 is a schematic cross-sectional view taken along line VII-VII in FIG. 1; FIG. 10 is a schematic cross-sectional view taken along line VIII-VIII in FIG. 1; and FIG. 11 is a schematic cross-sectional view taken along line IX-IX in FIG. 1. 1. An exploded perspective view of the laminate shown in FIG. 1. A cross-sectional view schematically illustrating an example of a multilayer ceramic capacitor according to a first modified example of the first embodiment of the present invention. A cross-sectional view schematically illustrating an example of a multilayer ceramic capacitor according to a second modified example of the first embodiment of the present invention. A cross-sectional view schematically illustrating an example of a multilayer ceramic capacitor according to a third modified example of the first embodiment of the present invention. An external perspective view from one side of an example of a multilayer ceramic capacitor according to a second embodiment of the present invention. An external perspective view from the other side of an example of a multilayer ceramic capacitor according to a second embodiment of the present invention. A plan view of an example of a multilayer ceramic capacitor according to a second embodiment of the present invention. A cross-sectional view schematic diagram along line XVII-XVII in FIG. 14, which is a cross-sectional view schematic diagram for explaining the structure of an example of a multilayer ceramic capacitor according to a second embodiment of the present invention. A cross-sectional view schematic diagram along line XVIII-XVIII in FIG. 14. A cross-sectional view schematic diagram along line XIX-XIX in FIG. 14. A cross-sectional view schematic diagram along line XX-XX in FIG. 14.

[0013] A. First Embodiment 1. Multilayer Ceramic Capacitor Next, an example of a multilayer ceramic capacitor 10 according to an embodiment of the present invention will be described.

[0014] FIG. 1 is an external perspective view showing an example of a multilayer ceramic capacitor according to a first embodiment of the present invention. FIG. 2 is a front view showing an example of a multilayer ceramic capacitor according to the first embodiment of the present invention. FIG. 3 is a side view showing an example of a multilayer ceramic capacitor according to the first embodiment of the present invention. FIG. 4A is a plan view showing an example of a multilayer ceramic capacitor according to the first embodiment of the present invention. FIG. 4B(a) is a plan view showing a state in which a thin film layer is disposed on a first main surface of a laminate, and FIG. 4B(b) is a plan view showing a state in which an underlayer plating layer is disposed on the first main surface of the laminate. FIG. 4C shows external electrodes of a multilayer ceramic capacitor according to the first embodiment of the present invention, where FIG. 4C(a) is another example of the arrangement of recesses disposed in the external electrodes, FIG. 4C(b) is yet another example of the arrangement of recesses disposed in the external electrodes, and FIG. 4C(c) is yet another example of the arrangement of recesses disposed in the external electrodes. FIG. 5 is a schematic cross-sectional view taken along line V-V in FIG. 1. FIG. 6 is a schematic cross-sectional view taken along line VI-VI in FIG. 1. Fig. 7 is a cross-sectional view taken along line VII-VII in Fig. 1. Fig. 8 is a cross-sectional view taken along line VIII-VIII in Fig. 1. Fig. 9 is a cross-sectional view taken along line IX-IX in Fig. 1. Fig. 10 is an exploded perspective view of the laminate shown in Fig. 1.

[0015] The multilayer ceramic capacitor 10 includes a laminate 12 and a plurality of external electrodes 30 .

[0016] The laminate 12 has a first main surface 12a and a second main surface 12b facing in a stacking direction x, a first side surface 12c and a second side surface 12d facing in a first direction y perpendicular to the stacking direction x, and a third side surface 12e and a fourth side surface 12f facing in a second direction z perpendicular to the stacking direction x and the first direction y. The direction connecting the first main surface 12a and the second main surface 12b of the laminate 12 is the stacking direction x.

[0017] It is also preferable that the corners and ridges of the laminate 12 are rounded. Note that a corner refers to a portion where three adjacent faces of the laminate 12 intersect, and a ridge refers to a portion where two adjacent faces of the laminate 12 intersect. Furthermore, unevenness or the like may be formed on part or all of the first main surface 12a and the second main surface 12b, the first side surface 12c and the second side surface 12d, and the third side surface 12e and the fourth side surface 12f.

[0018] The laminate 12 includes a plurality of dielectric layers 14 and a plurality of internal electrodes 16. The dielectric layers 14 include an inner dielectric layer 14a and an outer dielectric layer 14b. The internal electrodes 16 include a first internal electrode 16a and a second internal electrode 16b.

[0019] The laminate 12 also has an inner layer portion 18, a first outer layer portion 20a located on the first main surface 12a side, and a second outer layer portion 20b located on the second main surface 12b side.

[0020] The first outer layer portion 20a is located on the first main surface 12a side of the laminate 12 and is an aggregate of multiple outer dielectric layers 14b located between the first main surface 12a and the internal electrode 16 closest to the first main surface 12a.

[0021] The second outer layer portion 20b is located on the second main surface 12b side of the laminate 12 and is an aggregate of multiple outer dielectric layers 14b located between the second main surface 12b and the internal electrode 16 closest to the second main surface 12b.

[0022] The region sandwiched between the first outer layer portion 20a and the second outer layer portion 20b is the inner layer portion 18.

[0023] The inner layer portion 18 has a first inner electrode 16a having one end exposed to the first side surface 12c and the third side surface 12e and the other end exposed to the second side surface 12d and the fourth side surface 12f, a second inner electrode 16b having one end exposed to the first side surface 12c and the fourth side surface 12f and the other end exposed to the second side surface 12d and the third side surface 12e, and an inner layer dielectric layer 14a.

[0024] The dielectric layer 14 may be formed from, for example, a dielectric material. Examples of the dielectric material include dielectric ceramics primarily composed of BaTiO3, CaTiO3, SrTiO3, or CaZrO3. Substituents such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds may also be added to these primary components. The inner dielectric layer 14a and the outer dielectric layer 14b may be made of the same dielectric material, or may be made of different dielectric materials to separate the functions of the inner layer 18 and the outer layer 20a, 20b. At least one of Si, Mg, Ba, and Mn may also be added as an additive. The additive is present between the ceramic particles.

[0025] For example, if the inner dielectric layer 14a contains a large amount of CaTiO3 or CaZrO3 as a dielectric component, it can make it difficult for insulation breakdown to occur between the first inner electrode 16a and the second inner electrode 16b. Furthermore, without being limited to this, the inner dielectric layer 14a can also be mainly composed of SrTiO3 or the like. Separately, in order to increase the capacitance of the multilayer ceramic capacitor 10, it is preferable that the inner dielectric layer 14a be made of a material with a high dielectric constant, such as BaTiO3.

[0026] The dielectric layer 14 may have a plurality of crystal grains containing a perovskite-type compound having a basic structure of BaTiO3.

[0027] The thinner the dielectric layer 14, the greater the capacitance of the capacitor, so the crystal grain size is preferably 1 μm or less.

[0028] The number of dielectric layers 14 to be laminated is not particularly limited, but is preferably 3 to 700, including the first outer layer portion 20a and the second outer layer portion 20b. The thickness of the inner dielectric layer 14a is preferably 0.4 μm to 2.0 μm, and the thickness of the outer dielectric layer 14b is preferably 2.0 μm to 100.0 μm.

[0029] (Internal Electrode) The internal electrode 16 includes a plurality of first internal electrodes 16a and a plurality of second internal electrodes 16b. The first internal electrodes 16a and the second internal electrodes 16b are alternately stacked with the dielectric layer 14 interposed therebetween.

[0030] The first internal electrode 16a is disposed on the surface of the dielectric layer 14. The first internal electrode 16a faces the first main surface 12a and the second main surface 12b, has a first opposing electrode portion 22a facing the second internal electrode 16b, and is laminated in the direction connecting the first main surface 12a and the second main surface 12b.

[0031] The first internal electrode 16a is extended by a first extension electrode portion 24a to the first side surface 12c and the third side surface 12e of the laminate 12, and is extended by a second extension electrode portion 24b to the second side surface 12d and the fourth side surface 12f of the laminate 12. The width of the first extension electrode portion 24a extended to the first side surface 12c may be approximately equal to the width of the first extension electrode portion 24a extended to the third side surface 12e, and the width of the second extension electrode portion 24b extended to the second side surface 12d may be approximately equal to the width of the second extension electrode portion 24b extended to the fourth side surface 12f.

[0032] Furthermore, the first internal electrode 16a is continuously extended to the first side surface 12c and the third side surface 12e of the laminate 12 by the first extension electrode portion 24a, and continuously extended to the second side surface 12d and the fourth side surface 12f of the laminate 12 by the second extension electrode portion 24b, but this is not limitative and the first internal electrode 16a may be discontinuously extended. Furthermore, the first internal electrode 16a may be arranged so that only one of the first side surface 12c to the fourth side surface 12f is exposed.

[0033] The second internal electrode 16b is disposed on a surface of the inner dielectric layer 14a different from the surface of the inner dielectric layer 14a on which the first internal electrode 16a is disposed. The second internal electrode 16b faces the first principal surface 12a and the second principal surface 12b, has a second opposing electrode portion 22b facing the first internal electrode 16a, and is laminated in a direction connecting the first principal surface 12a and the second principal surface 12b.

[0034] The second internal electrode 16b is extended to the first side surface 12c and the fourth side surface 12f of the laminate 12 by the third extension electrode portion 24c, and is extended to the second side surface 12d and the third side surface 12e of the laminate 12 by the fourth extension electrode portion 24d. The width of the third extension electrode portion 24c extended to the first side surface 12c may be approximately equal to the width of the third extension electrode portion 24c extended to the fourth side surface 12f, and the width of the fourth extension electrode portion 24d extended to the second side surface 12d may be approximately equal to the width of the fourth extension electrode portion 24d extended to the third side surface 12e.

[0035] The second internal electrode 16b is continuously extended to the first side surface 12c and the fourth side surface 12f of the laminate 12 by the third extension electrode portion 24c, and continuously extended to the second side surface 12d and the third side surface 12e of the laminate 12 by the fourth extension electrode portion 24d, but this is not limitative and the second internal electrode 16b may be extended discontinuously. The second internal electrode 16b may be arranged so that only one of the first side surface 12c to the fourth side surface 12f is exposed.

[0036] Furthermore, when the multilayer ceramic capacitor 10 is viewed from the stacking direction, it is preferable that a straight line connecting the first extraction electrode portion 24a and the second extraction electrode portion 24b of the first internal electrode 16a intersects with a straight line connecting the third extraction electrode portion 24c and the fourth extraction electrode portion 24d of the second internal electrode 16b.

[0037] As shown in FIG. 7 , the laminate 12 also includes a side portion (W gap) 26 a of the laminate 12 located between one end in the first direction y of the second opposing electrode portion 22 b of the second internal electrode 16 b and the first side surface 12 c, and a side portion (W gap) 26 b of the laminate 12 located between the other end in the first direction y of the first opposing electrode portion 22 a of the first internal electrode 16 a and the second side surface 12 d.

[0038] Furthermore, as shown in FIG. 8 , the laminate 12 includes an end portion (L gap) 28a of the laminate 12 located between one end in the second direction z of the second opposing electrode portion 22b of the second internal electrode 16b and the third side surface 12e, and a side portion (L gap) 28b of the laminate 12 located between the other end in the second direction z of the first opposing electrode portion 22a of the first internal electrode 16a and the fourth side surface 12f.

[0039] The first internal electrode 16a and the second internal electrode 16b can be made of an appropriate conductive material, such as, for example, metals such as Ni, Cu, Ag, Pd, and Au, or alloys containing at least one of these metals, such as Ni-Cu alloys and Ag-Pd alloys, but are not limited thereto. Furthermore, the first internal electrode 16a and the second internal electrode 16b may be made of the same conductive material or different conductive materials.

[0040] Furthermore, by including Sn in the first internal electrode 16a and the second internal electrode 16b, the height of the potential barrier at the interface between the internal electrode 16 and the dielectric layer 14 is increased, and electric field concentration at the interface between the internal electrode 16 and the dielectric layer 14 can be alleviated, leading to improved high-temperature load reliability. In this case, Sn can be sufficiently effective even if it is included in only one of the internal electrodes 16, either the first internal electrode 16a or the second internal electrode 16b.

[0041] The total number of the first internal electrodes 16a and the second internal electrodes 16b is preferably 3 to 700. The thickness of the first internal electrodes 16a and the second internal electrodes 16b is not particularly limited, but is preferably 0.2 μm to 2.0 μm, for example.

[0042] 1 to 9, external electrodes 30 are arranged on the laminate 12. The external electrodes 30 include a plurality of external electrodes 30 connected to the first internal electrodes 16a and the second internal electrodes 16b. The external electrodes 30 include a first external electrode 30a, a second external electrode 30b, a third external electrode 30c, and a fourth external electrode 30d.

[0043] The first external electrode 30a is disposed on the first side surface 12c and the third side surface 12e so as to cover the first lead electrode portion 24a of the first internal electrode 16a, and further so as to cover a part of the first principal surface 12a and a part of the second principal surface 12b. The first external electrode 30a is electrically connected to the first lead electrode portion 24a of the first internal electrode 16a.

[0044] The second external electrode 30b is disposed on the second side surface 12d and the fourth side surface 12f so as to cover the second lead electrode portion 24b of the first internal electrode 16a, and further so as to cover a part of the first main surface 12a and a part of the second main surface 12b. The second external electrode 30b is electrically connected to the second lead electrode portion 24b of the first internal electrode 16a.

[0045] The third external electrode 30c is disposed on the first side surface 12c and the fourth side surface 12f so as to cover the third lead electrode portion 24c of the second internal electrode 16b, and further so as to cover a part of the first principal surface 12a and a part of the second principal surface 12b. The third external electrode 30c is electrically connected to the third lead electrode portion 24c of the second internal electrode 16b.

[0046] The fourth external electrode 30d is disposed on the second side surface 12d and the third side surface 12e so as to cover the fourth lead electrode portion 24d of the second internal electrode 16b, and further so as to cover a part of the first principal surface 12a and a part of the second principal surface 12b. The fourth external electrode 30d is electrically connected to the fourth lead electrode portion 24d of the second internal electrode 16b.

[0047] In the laminate 12, the first opposing electrode portion 22a of the first internal electrode 16a and the second opposing electrode portion 22b of the second internal electrode 16b face each other via the inner dielectric layer 14a, thereby forming a capacitance. Therefore, a capacitance can be obtained between the first external electrode 30a and the second external electrode 30b to which the first internal electrode 16a is connected, and the third external electrode 30c and the fourth external electrode 30d to which the second internal electrode 16b is connected, thereby realizing the characteristics of a capacitor.

[0048] Each of the first external electrode 30a, the second external electrode 30b, the third external electrode 30c, and the fourth external electrode 30d preferably has a thin film layer 32, an underlayer plating layer 34, and a surface plating layer 36.

[0049] In other words, the first external electrode 30a preferably has a first thin film layer 32a, a first underlayer plating layer 34a, and a first surface plating layer 36a. The second external electrode 30b preferably has a second thin film layer 32b, a second underlayer plating layer 34b, and a second surface plating layer 36b. The third external electrode 30c preferably has a third thin film layer 32c, a third underlayer plating layer 34c, and a third surface plating layer 36c. The fourth external electrode 30d preferably has a fourth thin film layer 32d, a fourth underlayer plating layer 34d, and a fourth surface plating layer 36d.

[0050] (Thin Film Layers) The thin film layers 32 include a first thin film layer 32a, a second thin film layer 32b, a third thin film layer 32c, and a fourth thin film layer 32d.

[0051] The first thin film layer 32a is arranged so as to cover a portion of the first main surface 12a and the second main surface 12b of the laminate 12 on the first side surface 12c side and the third side surface 12e side, and not to cover the first side surface 12c and the third side surface 12e of the laminate 12.

[0052] The second thin film layer 32b is arranged so as to cover a portion of the first main surface 12a and the second main surface 12b of the laminate 12 on the second side surface 12d side and the fourth side surface 12f side, and not to cover the second side surface 12d and the fourth side surface 12f.

[0053] The third thin film layer 32c is arranged so as to cover a portion of the first main surface 12a and the second main surface 12b of the laminate 12 on the first side surface 12c side and the fourth side surface 12f side, and not to cover the first side surface 12c and the fourth side surface 12f.

[0054] The fourth thin film layer 32d is arranged so as to cover a portion of the first main surface 12a and the second main surface 12b of the laminate 12 on the third side surface 12e side and the second side surface 12d side, and not to cover the third side surface 12e and the second side surface 12d.

[0055] Each of the first to fourth thin film layers 32 a to 32 d is preferably formed by depositing metal particles by sputtering, vapor deposition, etc. This allows the thickness of the first to fourth thin film layers 32 a to 32 d in the direction connecting the first main surface 12 a and the second main surface 12 b of the laminate 12 to be 1 μm or less, and the dimension of the multilayer ceramic capacitor 10 in the stacking direction x can be sufficiently reduced, thereby making it possible to reduce the height of the multilayer ceramic capacitor 10.

[0056] The dimensions of the first to fourth thin film layers 32 a to 32 d in the stacking direction x can be measured as follows. That is, when the thin film layers are formed by depositing metal particles, a fluorescent X-ray device can be used to convert the concentration of a predetermined element into a thickness using a calibration curve method for the corresponding metal species. Alternatively, a cross section of a component can be observed using an FIB with a scanning microscope, and the thickness can be measured from the actual observation image.

[0057] Furthermore, when the first to fourth thin film layers 32a to 32d are formed by a thin film forming method, these thin film layers are preferably made of a metal such as Cu or Ni.

[0058] The thin film layers 32 of the multilayer ceramic capacitor 10 shown in Fig. 1 are formed by depositing metal particles by sputtering. In this case, if the thickness of the thin film layers 32 is 1 µm or less, the dimension in the stacking direction x can be made sufficiently small.

[0059] The first to fourth thin film layers 32a to 32d can be configured taking into consideration their respective functions. For example, it is preferable that the main component be NiCr or NiCu in consideration of adhesion to the laminate 12. The first to fourth thin film layers 32a to 32d may be multiple layers or may have a two-layer structure of NiCr and NiCu.

[0060] The thin film layer 32 may be formed by screen printing or the like and contain a dielectric material and a metal component. This allows the thin film layer 32 to adhere to the ceramic of the laminate 12, thereby improving the adhesion between the laminate 12 and the external electrode 30. In this case, the thin film layer 32 may contain a ceramic component having the same main component as the inner dielectric layer 14a in addition to the metal component. The inclusion of a ceramic component in the thin film layer 32 reduces the difference in thermal expansion coefficient between the laminate 12 and the thin film layer 32, thereby alleviating stress on the thin film layer 32. However, the metal component may be other metal components besides Cu and Ni, or a glass component may be included in addition to the ceramic component. Examples of the glass component include oxides of Ba (barium), Sr (strontium), Si (silicon), Ca (calcium), Zn, Al, or B (boron). Other metal components may include Mg, Cr, Sr, Al, Na, Fe, etc. The thin film layer 32 may also have a discontinuous shape. The term "discontinuous" means that the film is formed discontinuously when viewed in a direction perpendicular to the longitudinal direction.

[0061] For example, when the thin film layer 32 is formed using a material containing ceramic, one method is to polish the cross section, then take a cross section photograph using a digital microscope (Keyence Corporation: VHX-5000), and use the cross section photograph to calculate the thickness, etc. Another method is to measure the thickness, etc. from the actual observation image of the cross section of the part taken by FIB using a scanning microscope.

[0062] (Underlayer Plating Layer) The underlayer plating layer 34 includes a first underlayer plating layer 34a, a second underlayer plating layer 34b, a third underlayer plating layer 34c, and a fourth underlayer plating layer 34d.

[0063] The first lower-layer plating layer 34a is disposed so as to cover the first thin film layer 32a and the first and third side surfaces 12c, 12e of the laminate 12. The second lower-layer plating layer 34b is disposed so as to cover the second thin film layer 32b and the second and fourth side surfaces 12d, 12f of the laminate 12. The third lower-layer plating layer 34c is disposed so as to cover the third thin film layer 32c and the first and fourth side surfaces 12c, 12f of the laminate 12. The fourth lower-layer plating layer 34d is disposed so as to cover the fourth thin film layer 32d and the second and third side surfaces 12d, 12e of the laminate 12.

[0064] The lower plating layer 34 contains at least one selected from, for example, Cu, Ni, Sn, Ag, Pd, an Ag-Pd alloy, Au, etc. The lower plating layer 34 is preferably Cu plating. In this case, the lower plating layer 34 may be directly connected to the internal electrode 16. In addition to this, another Cu plating layer with a different particle size may be provided.

[0065] The thickness of the lower plating layer 34 is preferably, for example, 1 μm or more and 10 μm or less.

[0066] (Surface Plating Layer) The surface plating layer 36 includes a first surface plating layer 36a, a second surface plating layer 36b, a third surface plating layer 36c, and a fourth surface plating layer 36d.

[0067] The first surface plating layer 36a is disposed so as to cover the first underlayer plating layer 34a. The second surface plating layer 36b is disposed so as to cover the second underlayer plating layer 34b. The third surface plating layer 36c is disposed so as to cover the third underlayer plating layer 34c. The fourth surface plating layer 36d is disposed so as to cover the fourth underlayer plating layer 34d.

[0068] The surface plating layer 36 may be, for example, only Sn plating, or may have a two-layer structure of Ni plating, Sn plating, or Ni plating and Cu plating.

[0069] The thickness of the surface plating layer 36 is preferably, for example, 1 μm or more and 10 μm or less.

[0070] The plating layer may be composed of only the lower plating layer 34. In this case, the first lower plating layer 34a is disposed so as to cover the first thin film layer 32a, and the second lower plating layer 34b is disposed so as to cover the second thin film layer 32b. Similarly, the third lower plating layer 34c is disposed so as to cover the third thin film layer 32c, and the fourth lower plating layer 34d is disposed so as to cover the fourth thin film layer 32d.

[0071] The plating layer preferably contains at least one metal selected from Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, Zn, etc., or an alloy containing such a metal. The plating layer preferably does not contain glass.

[0072] The metal content per unit volume of the plating layer is preferably 99% by volume or more.

[0073] The thickness of each plating layer is preferably 0.5 μm or more and 10.0 μm or less.

[0074] (Recess) In the external electrodes 30 arranged on the first main surface 12 a, when viewed from the stacking direction x, a straight line parallel to the first direction y and the second direction z is drawn from the intersection point where the external electrode 30 and the laminate 12 intersect, and a first region R 10 One or more recesses 40 are arranged inward from the outer edge of the range and protrude inward from an edge portion located toward the center of the laminate 12. The recesses 40 include a first recess 40a, a second recess 40b, a third recess 40c, and a fourth recess 40d.

[0075] The first recess 40a is positioned relative to the first external electrode 30a disposed on the first main surface 12a. The second recess 40b is positioned relative to the second external electrode 30b disposed on the first main surface 12a. The third recess 40c is positioned relative to the third external electrode 30c disposed on the first main surface 12a. The fourth recess 40d is positioned relative to the fourth external electrode 30d disposed on the first main surface 12a.

[0076] Specifically, the first recess 40a disposed on the first external electrode 30a will be described as an example. That is, as shown in FIG. 4A , when viewed in the stacking direction x, the intersection of the first external electrode 30a disposed on the first main surface 12a with the laminate 12 located closest to the first side face 12c and closest to the fourth side face 12f is referred to as a first intersection P 11 The intersection of the first external electrode 30a arranged on the first main surface 12a with the laminate 12 located closest to the third side surface 12e and closest to the second side surface 12d is defined as a second intersection P 12 The first intersection point P 11 A straight line l is drawn parallel to the first direction y from 11 and the first intersection point P 11 A straight line l is drawn parallel to the second direction z from 12 and the second intersection point P 12 A straight line l is drawn parallel to the first direction y from 13 and the second intersection point P 12 A straight line l is drawn parallel to the second direction z from 14 When drawn, the line l 11 , l 12 , l 13 , l 14 A first region R surrounded by 10 At that time, the first region R 10 One or more first recesses 40a are arranged so as to protrude inward from at least one of the edge portions located on the center side of the laminate 12, which is located inside the outer edge of the range of R. Specifically, the first recesses 40a in the first external electrode 30a of the multilayer ceramic capacitor 10 shown in FIG. 10 The outer periphery of the first external electrode 30a is located inside the outer edge of the range and is positioned toward the center of the laminate 12, and is arranged so as to protrude inward from the edge on the fourth side surface 12f side of the first external electrode 30a arranged on the first main surface 12a.

[0077] The base of the first recess 40a at the edge of the first external electrode 30a on the fourth side face 12f side may be wavy. Furthermore, in the first recess 40a disposed on the first external electrode 30a, the length in the first direction y of the boundary between the first recess 40a and the edge of the first external electrode 30a on the fourth side face 12f side is defined as W1, and the length in the second direction z of the boundary between the first recess 40a and the edge of the first external electrode 30a on the fourth side face 12f side is defined as L1. The lengths W1 and L1 can be set arbitrarily. Furthermore, the length L1 is preferably 10 μm or more. This allows the first recess 40a to be more clearly distinguished.

[0078] (Thin film layer recess) In addition, in the thin film layers 32 arranged on the first main surface 12 a, when viewed from the stacking direction x, a straight line parallel to the first direction y and the second direction z is drawn from a contact point where the thin film layer 32 constituting the external electrode 30 and the laminate 12 come into contact, and a second region R 20 One or more thin film layer recesses 40 1 may be arranged so as to protrude inward from an edge portion located on the central side of the laminate 12, inside the outer edge of the range.

[0079] Specifically, the first thin film layer 32a disposed on the first main surface 12a will be described as an example. That is, as shown in FIG. 4B(a), when viewed from the stacking direction x, the first thin film layer 32a disposed on the first main surface 12a is in contact with the laminate 12 at a point closest to the first side surface 12c and closest to the fourth side surface 12f, and the point is referred to as a first contact point P. 21 The point of contact between the first thin film layer 32a disposed on the first main surface 12a and the laminate 12 on the side closest to the third side surface 12e and the side closest to the second side surface 12d is defined as a second contact point P 22 The first contact point P 21 A straight line l is drawn parallel to the first direction y from 21 Pull the first contact P 21 A straight line l is drawn parallel to the second direction z from 22 Pull the second contact P 22 A straight line l is drawn parallel to the first direction y from 23 Pull the second contact P22 A straight line l is drawn parallel to the second direction z from 24 When drawn, the line l 21 , l 22 , l 23 , l 24 A second region R surrounded by 20 At that time, the second region R 20 One or more first thin film layer recesses 40 a are arranged so as to protrude inward from at least one of the edge portions located on the center side of the laminate 12, inside the outer edge of the range of the second region R. Specifically, the first thin film layer recesses 40 a in the first thin film layer 32 a of the multilayer ceramic capacitor 10 shown in FIG. 20 The first thin film layer 32a is arranged inside the outer edge of the range and among the edge portions located toward the center of the laminate 12, so as to protrude inward from the edge portion on the fourth side surface 12f side of the first thin film layer 32a arranged on the first main surface 12a.

[0080] Moreover, the above description of the first thin film layer 32a may also be applied to the second thin film layer 32b to the fourth thin film layer 32d in the same manner.

[0081] (Underlayer plating layer recess) In addition, in the underlayer plating layer 34 disposed on the first main surface 12 a, when viewed in the stacking direction x, a straight line parallel to the first direction y and the second direction z is drawn from the intersection of the underlayer plating layer 34 constituting the external electrode 30 and the laminate 12, and a third region R surrounded by the straight line in any one of the underlayer plating layers 34 is formed. 30 One or more lower plating layer recesses 402 may be arranged inward from the outer edge of the range and protruding inward from an edge portion located toward the center of the laminate 12.

[0082] Specifically, the case of the first underlayer plating layer 34a disposed on the first main surface 12a will be described as an example. That is, as shown in FIG. 4B(b), when viewed in the stacking direction x, the intersection point of the first underlayer plating layer 34a disposed on the first main surface 12a with the stack body 12 located closest to the first side surface 12c and closest to the fourth side surface 12f is defined as a third intersection point P 31The intersection of the first lower plating layer 34a disposed on the first main surface 12a with the laminate 12 located closest to the third side surface 12e and closest to the second side surface 12d is defined as a fourth intersection P 32 The third intersection point P 31 A straight line l is drawn parallel to the first direction y from 31 and the third intersection point P 31 A straight line l is drawn parallel to the second direction z from 32 Draw the fourth intersection point P 32 A straight line l is drawn parallel to the first direction y from 33 Draw the fourth intersection point P 32 A straight line l is drawn parallel to the second direction z from 34 When drawn, the line l 31 , l 32 , l 32 , l 34 A third region R bounded by 30 At that time, the third region R 30 One or more first lower-layer plating layer recesses 402a are arranged so as to protrude inward from at least one of the edge portions located on the center side of the laminate 12, inside the outer edge of the range of the third region R 30 The first lower layer plating layer 34a is disposed on the first main surface 12a, and is positioned so as to protrude inward from the edge portion located on the fourth side surface 12f side of the first lower layer plating layer 34a, which is located inside the outer edge of the range and is located toward the center of the laminate 12.

[0083] Furthermore, the above description of the first lower plating layer 34a may also be applied to the second lower plating layer 34b to the fourth lower plating layer 34d.

[0084] The above description of the first external electrode 30a may also be applied to the second external electrode 30b to the fourth external electrode 30d in a similar manner. That is, the second external electrode 30b has one or more second recesses 40b, the third external electrode 30c has one or more third recesses 40c, and the fourth external electrode 30d has one or more fourth recesses 40d.

[0085] Other examples of the arrangement of the recesses 40 relative to the external electrode 30 will be specifically described below.

[0086] As shown in FIG. 4C(a), the first recess 40a in the first external electrode 30a is located in the first region R 10 The first external electrode 30a is disposed so as to protrude inward from the edge portion on the second side face 12d side of the first external electrode 30a disposed on the first main surface 12a, among the edge portions located inward from the outer edge of the range and toward the center of the laminate 12. The description of the first external electrode 30a can also be applied to the second external electrode 30b to the fourth external electrode 30d in the same manner.

[0087] 4C(b), a plurality of first recesses 40a1, 40a2 may be arranged in the first external electrode 30a. In this case, the first recesses 40a1 are located in the first region R 10 The first recess 40a2 is disposed so as to protrude inward from an edge portion on the fourth side surface 12f side of the first external electrode 30a disposed on the first main surface 12a, among edge portions located on the center side of the laminate 12, which is inward from the outer edge of the range of 10 The first external electrode 30a is disposed so as to protrude inward from the edge portion on the second side face 12d side of the first external electrode 30a disposed on the first main surface 12a, among the edge portions located inward from the outer edge of the range and toward the center of the laminate 12. The description of the first external electrode 30a can also be applied to the second external electrode 30b to the fourth external electrode 30d in the same manner.

[0088] As shown in Fig. 4C(c), a plurality of first recesses 40a1, 40a2 may be arranged in the first external electrode 30a. In this case, the plurality of first recesses 40a, 40a2 are arranged in the first region R 10 The first recesses are arranged so as to protrude inward from the edge portion of the first external electrode 30a on the fourth side surface 12f side of the first external electrode 30a arranged on the first main surface 12a, among the edge portions located inward from the outer edge of the range of the first recesses, and toward the center of the laminate 12. 10The first recesses may be arranged so as to protrude inward from an edge portion located on the second side surface 12d side of the first external electrode 30a arranged on the first main surface 12a, among edge portions located inward from the outer edge of the range and toward the center of the laminate 12. 10 The first external electrode 30a may be disposed so as to protrude inward from the edge portion on the fourth side face 12f side and the edge portion on the second side face 12d side of the first external electrode 30a disposed on the first main surface 12a, among the edge portions located inside the outer edge of the range and toward the center of the laminate 12. The description of the first external electrode 30a can be similarly applied to the second external electrode 30b to the fourth external electrode 30d.

[0089] Note that the above description of the recesses 40 has been given with respect to the recesses 40 arranged in each of the first external electrode 30a to the fourth external electrode 30d arranged on the first main surface 12a, but this is not limited to this and can be similarly applied to the recesses 40 arranged in each of the first external electrode 30a to the fourth external electrode 30d arranged on the second main surface 12b.

[0090] The dimension of the multilayer ceramic capacitor 10 including the laminate 12 and the external electrodes 30 in the first direction y is defined as dimension L, the dimension of the multilayer ceramic capacitor 10 including the laminate 12 and the external electrodes 30 in the stacking direction x is defined as dimension T, and the dimension of the multilayer ceramic capacitor 10 including the laminate 12 and the external electrodes 30 in the second direction z is defined as dimension W. The dimensions of the multilayer ceramic capacitor 10 are preferably such that the L dimension in the first direction y is 0.2 mm or more and 3.2 mm or less, the T dimension in the stacking direction x is 0.04 mm or more and 0.22 mm or less, and the W dimension in the second direction z is 0.2 mm or more and 3.2 mm or less. The dimensions of the multilayer ceramic capacitor 10 preferably satisfy the relationship 7 / 10≦L / W≦10 / 7. This allows the laminate 12 to have a substantially tetragonal shape, thereby improving the flexibility of mounting.

[0091] In the multilayer ceramic capacitor 10 shown in FIG. 1, when a straight line parallel to the first direction y and the second direction z is drawn from the intersection point where the external electrode 30 and the laminate 12 intersect, a first region R 10One or more recesses 40 are arranged inside the outer edge of the range and protrude inward from an edge portion located on the center side of the laminate 12, so that by checking the presence or absence and size of the recesses 40 with an image sensor or the like, it is possible to provide a multilayer ceramic capacitor whose specifications, etc., can be determined.

[0092] 2. Modifications (1) First Modification Next, an example of a multilayer ceramic capacitor 10A according to a first modification of the first embodiment of the present invention will be described. Fig. 11 is a cross-sectional schematic diagram showing an example of a multilayer ceramic capacitor according to a first modification of the first embodiment of the present invention. However, the same reference numerals are used to designate the same or corresponding components as those in Figs. 1 to 10, and detailed descriptions thereof will be omitted.

[0093] As shown in FIG. 11, in the multilayer ceramic capacitor 10A according to the first modification, the thin film layers 32 are formed so as to extend around to each side surface of the laminate 12.

[0094] Specifically, the first thin film layer 32a of the first external electrode 30a covers parts of the first and second main surfaces 12a and 12b, and is formed around each main surface to cover the first and third side surfaces 12c and 12e. The second thin film layer 32b of the second external electrode 30b covers parts of the first and second main surfaces 12a and 12b, and is formed around each main surface to cover the second and fourth side surfaces 12d and 12f. Although not shown, the same applies to the third thin film layer 32c of the third external electrode 30c and the fourth thin film layer 32d of the fourth external electrode 30d.

[0095] The first thin film layer 32a is directly electrically connected to the first lead electrode portion 24a of the first internal electrode 16a exposed from the first side surface 12c and the third side surface 12e. The second thin film layer 32b is directly electrically connected to the second lead electrode portion 24b of the first internal electrode 16a exposed from the second side surface 12d and the fourth side surface 12f. Although not shown, the third thin film layer 32c is directly electrically connected to the third lead electrode portion 24c of the second internal electrode 16b, and the fourth thin film layer 32d is directly electrically connected to the fourth lead electrode portion 24d of the second internal electrode 16b.

[0096] In the first thin film layer 32a, the thin film layers formed on the first and second main surfaces 12a and 12b may be continuously or discontinuously connected to the thin film layers formed on the first and third side surfaces 12c and 12e. In the second thin film layer 32b, the thin film layers formed on the first and second main surfaces 12a and 12b may be continuously or discontinuously connected to the thin film layers formed on the second and fourth side surfaces 12d and 12f. The same applies to the third thin film layer 32c of the third external electrode 30c and the fourth thin film layer 32d of the fourth external electrode 30d.

[0097] The multilayer ceramic capacitor 10A according to the first embodiment shown in FIG. 11 has the same effects as the multilayer ceramic capacitor 10 described above.

[0098] (2) Second Modification Next, an example of a multilayer ceramic capacitor 10B according to a second modification of the first embodiment of the present invention will be described. Fig. 12 is a schematic cross-sectional view showing an example of a multilayer ceramic capacitor according to the second modification of the first embodiment of the present invention. However, the same reference numerals are used to designate the same or corresponding components as those in Figs. 1 to 10, and detailed descriptions thereof will be omitted.

[0099] As shown in FIG. 12, the external electrodes 30 of the multilayer ceramic capacitor 10B according to the second modified example of the first embodiment include a direct plating layer 33.

[0100] (Direct Plated Layer) The first external electrode 30a includes a first direct plated layer 33a, the second external electrode 30b includes a second direct plated layer 33b, and although not shown, the third external electrode 30c includes a third direct plated layer, and the fourth external electrode 30d includes a fourth direct plated layer.

[0101] The first direct plating layer 33a is arranged to cover a portion of each of the first side surface 12c and the third side surface 12e of the laminate 12, as well as the ridge portion sandwiched therebetween. The first direct plating layer 33a is electrically and directly connected to the first lead electrode portion 24a of the first internal electrode 16a. The second direct plating layer 33b is arranged to cover a portion of each of the second side surface 12d and the fourth side surface 12f of the laminate 12, as well as the ridge portion sandwiched therebetween. The second direct plating layer 33b is electrically and directly connected to the second lead electrode portion 24b of the first internal electrode 16a. Although not shown, the same applies to the third direct plating layer of the third external electrode 30c and the fourth direct plating layer of the fourth external electrode 30d.

[0102] The upper end of the first direct plating layer 33a of the first external electrode 30a is preferably arranged so as to overlap the underside of the first thin film layer 32a on the ridge formed by the first main surface 12a, the first side surface 12c, and the third side surface 12e of the laminate 12. The upper end of the second direct plating layer 33b of the second external electrode 30b is preferably arranged so as to overlap the underside of the second thin film layer 32b on the ridge formed by the first main surface 12a, the second side surface 12d, and the fourth side surface 12f of the laminate 12. Although not shown, the same applies to the third direct plating layer of the third external electrode 30c and the fourth direct plating layer of the fourth external electrode 30d.

[0103] Note that a portion of the first direct plating layer 33 a may be disposed so as to wrap around to the second main surface 12 b, and a portion of the second direct plating layer 33 b may be disposed so as to wrap around to the second main surface 12 b. Also, a portion of the third direct plating layer and a portion of the fourth direct plating layer may be disposed so as to wrap around to the second main surface 12 b.

[0104] The upper ends of the first and second direct plating layers 33 a and 33 b may be spaced apart from the first and second thin film layers 32 a and 32 b, respectively. The upper ends of the third and fourth direct plating layers may be spaced apart from the third and fourth thin film layers 32 c and 32 d, respectively.

[0105] The direct plating layer 33 is not particularly limited as long as it contains, as a main metal component, at least one metal selected from, for example, Cu, Ni, Ag, Pd, an Ag—Pd alloy, Au, etc. For example, when the first internal electrode 16 a and the second internal electrode 16 b are formed using Ni, it is preferable to adopt Cu plating as the direct plating layer 33, which has good bonding properties with Ni.

[0106] The direct plating layer 33 is formed by plating growing from the internal electrode 16 .

[0107] The thickness of each direct plating layer 33 is preferably 0.5 μm or more and 10.0 μm or less.

[0108] 12 according to the first embodiment, the multilayer ceramic capacitor 10B has the same effects as the above-described multilayer ceramic capacitor 10. That is, by forming the plating layer 33 directly on each side surface of the laminate 12, the thickness in the lamination direction of the external electrodes 30 formed on the first principal surface 12a and the second principal surface 12b can be further reduced, and therefore a multilayer ceramic capacitor with an even lower profile can be provided without impairing mountability during mounting.

[0109] (3) Third Modification Next, a multilayer ceramic capacitor 10C according to a third modification of the first embodiment of the present invention will be described. Fig. 13 is a cross-sectional view showing an example of a multilayer ceramic capacitor according to the third modification of the first embodiment of the present invention. However, the same reference numerals are used to designate the same or corresponding components as those in Figs. 1 to 10, and detailed descriptions thereof will be omitted.

[0110] The external electrodes 30 of the multilayer ceramic capacitor 10C according to the third modification do not include a plating layer and are composed of a plurality of thin film layers. In the multilayer ceramic capacitor 10C shown in Fig. 13, the first external electrode 30a does not include a plating layer and is composed of only four thin film layers 32a1 to 32a4, and the second external electrode 30b does not include a plating layer and is composed of only four thin film layers 32b1 to 32b4.

[0111] In the first external electrode 30a, the thin film layer 32a extends from the first principal surface 12a to cover the first side surface 12c and the third side surface 12e. Then, thin film layers 32a2, 32a3, and 32a4 are formed in this order on the surface of the thin film layer 32a1. In the second external electrode 30b, the thin film layer 32b1 extends from the first principal surface 12a to cover the second side surface 12d and the fourth side surface 12f. Then, thin film layers 32b2, 32b3, and 32b4 are formed in this order on the surface of the thin film layer 32b1. Although not shown, the same applies to the third thin film layer 32c of the third external electrode 30c and the fourth thin film layer 32d of the fourth external electrode 30d.

[0112] In the first external electrode 30a, the edge portions of the laminate 12 made up of the four thin film layers 32a1 to 32a4 near the center may or may not be formed to cover the corresponding edge portions of the lower layers. Similarly, in the second external electrode 30b, the edge portions of the laminate 12 made up of the four thin film layers 32b1 to 32b4 near the center may or may not be formed to cover the corresponding edge portions of the lower layers. Although not shown, the same applies to the third thin film layer 32c of the third external electrode 30c and the fourth thin film layer 32d of the fourth external electrode 30d.

[0113] 13 according to the first embodiment, the multilayer ceramic capacitor 10C has the same effects as the multilayer ceramic capacitor 10 described above, and also has the following effect: The multilayer ceramic capacitor 10C does not include a plating layer, and the first external electrode 30a is composed only of thin film layers 32a1 to 32a4, the second external electrode 30b is composed only of thin film layers 32b1 to 32b4, and the third external electrode 30c and the fourth external electrode 30d also have a similar configuration, which reduces the T dimension in the stacking direction x, the L dimension in the first direction y, and the W dimension in the second direction z, thereby making it possible to reduce the dimensions of the multilayer ceramic capacitor.

[0114] 3. Method for Manufacturing the Multilayer Ceramic Capacitor A method for manufacturing the multilayer ceramic capacitor, which is an example of the multilayer ceramic capacitor according to the first embodiment, will now be described.

[0115] (a) Manufacturing Method of Multilayer Ceramic Capacitor First, a conductive paste for the dielectric sheets and the internal electrodes is prepared. The conductive paste for the dielectric sheets and the internal electrodes contains a binder and a solvent. Known binders and solvents can be used.

[0116] Next, a conductive paste for the internal electrodes is printed in a predetermined pattern on the dielectric sheet by, for example, inkjet printing, screen printing, gravure printing, etc. This prepares a dielectric sheet on which the pattern of the first internal electrode is formed and a dielectric sheet on which the pattern of the second internal electrode is formed. Thereafter, the sheet on which the first internal electrode is printed and the sheet on which the second internal electrode is printed are laminated together to form a portion that becomes the inner layer portion 18.

[0117] Next, a predetermined number of dielectric sheets not printed with an internal electrode pattern are stacked to form the portion that will become the first outer layer portion 20a on the first main surface 12a. After that, the portion that will become the inner layer portion 18 prepared above is stacked, and a predetermined number of dielectric sheets not printed with an internal electrode pattern are stacked on top of this portion that will become the inner layer portion 18 to form the portion that will become the second outer layer portion 20b on the second main surface 12b. In this way, a laminated sheet is produced.

[0118] Next, the laminated sheet is pressed in the lamination direction by means of a hydrostatic press or the like to produce a laminated block.

[0119] The laminated block is then cut to a predetermined size to obtain laminated chips, the corners and ridges of which may be rounded by barrel polishing or the like.

[0120] Next, the laminated chip is fired to produce the laminate 12. The firing temperature depends on the ceramic and internal electrode materials, but is preferably 900° C. or higher and 1400° C. or lower.

[0121] Next, the obtained laminate 12 is aligned on a workbench, and thin film layers 32 are formed on the first principal surface 12a and the second principal surface 12b by sputtering. At this time, each thin film layer 32 is formed in a desired shape. That is, a mask is prepared so that the thin film layer 32 in the external electrode 30 of the present invention has one or more recesses 40 that protrude outward from an edge portion located toward the center of the laminate 12, and by using this mask, the thin film layer 32 can be formed into a desired shape.

[0122] Thereafter, an underlayer plating layer 34 is formed on the thin film layer 32 and the surface of the laminate 12, and a surface plating layer 36 is formed to cover the underlayer plating layer 34. More specifically, a Cu plating layer is formed on the thin film layer 32 as the underlayer plating layer 34. Then, a Ni plating layer and an Sn plating layer are formed on the surface of the underlayer plating layer 34 as the surface plating layer 36. Either electrolytic plating or electroless plating may be used for the plating process. However, electroless plating has the disadvantage of requiring pretreatment using a catalyst or the like to improve the plating deposition rate, which complicates the process. Therefore, it is usually preferable to use electrolytic plating.

[0123] In this manner, the multilayer ceramic capacitor 10 according to the embodiment shown in Fig. 1 can be manufactured. When manufacturing the multilayer ceramic capacitor 10A of the first modified example shown in Fig. 11, the multilayer ceramic capacitor 10B of the second modified example shown in Fig. 12, and the multilayer ceramic capacitor 10B of the third modified example shown in Fig. 13, the shapes of the corresponding portions are appropriately changed in each process.

[0124] B. Second Embodiment 1. Multilayer Ceramic Capacitor Next, an example of a multilayer ceramic capacitor 110 according to a second embodiment of the present invention will be described.

[0125] FIG. 14 is an external perspective view, from one side, showing an example of a multilayer ceramic capacitor according to the second embodiment of the present invention. FIG. 15 is an external perspective view, from the other side, showing an example of a multilayer ceramic capacitor according to the second embodiment of the present invention. FIG. 16 is a plan view showing an example of a multilayer ceramic capacitor according to the second embodiment of the present invention. FIG. 17 is a cross-sectional view taken along line XVII-XVII in FIG. 14, and is a cross-sectional view illustrating the structure of an example of a multilayer ceramic capacitor according to the second embodiment of the present invention. FIG. 18 is a cross-sectional view taken along line XVIII-XVIII in FIG. 14. FIG. 19 is a cross-sectional view taken along line XIX-XIX in FIG. 14. FIG. 20 is a cross-sectional view taken along line XX-XX in FIG. 14. Note that components that are the same as or equivalent to those in FIGS. 1 to 8 are designated by the same reference numerals, and detailed description thereof will be omitted.

[0126] In the multilayer ceramic capacitor 110 according to the second embodiment, the laminate 12 has a configuration similar to that of the laminate 12 according to the first embodiment of the present invention shown in Fig. 1. The first internal electrode 16a of the internal electrode 16 is extended to the first side surface 12c and the third side surface 12e of the laminate 12 by a first extension electrode portion 24a, and is extended to the second side surface 12d and the fourth side surface 12f of the laminate 12 by a second extension electrode portion 24b.

[0127] The second internal electrode 16b of the internal electrode 16 is extended to the first side surface 12c and the fourth side surface 12f of the laminate 12 by the third extension electrode portion 24c, and is extended to the second side surface 12d and the third side surface 12e of the laminate 12 by the fourth extension electrode portion 24d.

[0128] In the multilayer ceramic capacitor 110 according to the second embodiment, the external electrodes 130 are arranged so as to cover the first main surface 12a of the laminate 12 but not the second main surface 12b.

[0129] 14 to 20, external electrodes 130 are arranged on the laminate 12. The external electrodes 130 include a plurality of external electrodes 130 connected to the first internal electrodes 16a and the second internal electrodes 16b. The external electrodes 130 include a first external electrode 130a, a second external electrode 130b, a third external electrode 130c, and a fourth external electrode 130d.

[0130] The first external electrode 130a is disposed on the first side surface 12c and the third side surface 12e so as to cover the first lead electrode portion 24a of the first internal electrode 16a, and further so as to cover a portion of the first main surface 12a. The first external electrode 130a is electrically connected to the first lead electrode portion 24a of the first internal electrode 16a.

[0131] The second external electrode 130b is disposed on the second side surface 12d and the fourth side surface 12f so as to cover the second lead electrode portion 24b of the first internal electrode 16a, and further so as to cover a part of the first main surface 12a. The second external electrode 130b is electrically connected to the second lead electrode portion 24b of the first internal electrode 16a.

[0132] The third external electrode 130c is disposed on the first side surface 12c and the fourth side surface 12f so as to cover the third lead electrode portion 24c of the second internal electrode 16b, and further so as to cover a part of the first main surface 12a. The third external electrode 130c is electrically connected to the third lead electrode portion 24c of the second internal electrode 16b.

[0133] The fourth external electrode 130d is disposed on the second side surface 12d and the third side surface 12e so as to cover the fourth lead electrode portion 24d of the second internal electrode 16b, and further so as to cover a part of the first main surface 12a. The fourth external electrode 130d is electrically connected to the fourth lead electrode portion 24d of the second internal electrode 16b.

[0134] (Recess) In the external electrode 130 disposed on the first main surface 12 a, when a straight line parallel to the first direction y and the second direction z is drawn from the intersection point where the external electrode 130 and the laminate 12 intersect, a first region R 10 One or more recesses 40 are arranged inward from the outer edge of the range and protrude inward from an edge portion located toward the center of the laminate 12. The recesses 40 include a first recess 40a, a second recess 40b, a third recess 40c, and a fourth recess 40d.

[0135] The first recess 40a is positioned relative to the first external electrode 130a disposed on the first main surface 12a. The second recess 40b is positioned relative to the second external electrode 130b disposed on the first main surface 12a. The third recess 40c is positioned relative to the third external electrode 130c disposed on the first main surface 12a. The fourth recess 40d is positioned relative to the fourth external electrode 130d disposed on the first main surface 12a.

[0136] Specifically, the first recess 40a disposed on the first external electrode 130a will be described as an example. That is, as shown in FIG. 16 , when viewed in the stacking direction x, the intersection of the first external electrode 130a disposed on the first main surface 12a with the laminate 12 located closest to the first side face 12c and closest to the fourth side face 12f is referred to as a first intersection P 11 The intersection of the first external electrode 130a arranged on the first main surface 12a with the laminate 12 located closest to the third side surface 12e and closest to the second side surface 12d is defined as a second intersection P 12 The first intersection point P 11 A straight line l is drawn parallel to the first direction y from 11 and the first intersection point P 11 A straight line l is drawn parallel to the second direction z from 12 and the second intersection point P 12 A straight line l is drawn parallel to the first direction y from 13 and the second intersection point P 12 A straight line l is drawn parallel to the second direction z from 14 When drawn, the line l 11 , l 12 , l 13 , l 14A first region R surrounded by 10 At that time, the first region R 10 One or more first recesses 40a are arranged so as to protrude inward from at least one of the edge portions located on the center side of the laminate 12, which is located inside the outer edge of the range of R. Specifically, the first recesses 40a in the first external electrode 130a of the multilayer ceramic capacitor 10 shown in FIG. 10 The first external electrode 130a is arranged so as to protrude inward from the edge portion located on the fourth side surface 12f side of the first external electrode 130a arranged on the first main surface 12a, among the edge portions located inward from the outer edge of the range and toward the center of the laminate 12.

[0137] The above description of the first external electrode 130a may also be applied to the second external electrode 130b to the fourth external electrode 130d in a similar manner. That is, the second external electrode 130b has one or more second recesses 40b, the third external electrode 130c has one or more third recesses 40c, and the fourth external electrode 130d has one or more fourth recesses 40d.

[0138] Moreover, the examples of the arrangement of the recesses 40 relative to the external electrodes 30 explained in FIGS. 4C(a) to 4C(c) can also be applied to the external electrodes 130 of the multilayer ceramic capacitor 110 according to the second embodiment.

[0139] According to the multilayer ceramic capacitor 110 according to the second embodiment shown in FIGS. 14 to 20 , even in a multilayer ceramic capacitor in which the external electrodes 130 are disposed so as to cover only the first main surface 12 a of the laminate 12 and not cover the second main surface 12 b, it is possible to provide a multilayer ceramic capacitor having a reduced height without impairing mountability during mounting, similar to the multilayer ceramic capacitor 10 shown in FIG. 1 .

[0140] Furthermore, the multilayer ceramic capacitor 110 according to the second embodiment may be configured such that the external electrodes 130 cover a portion of the second main surface 12b and do not cover the first main surface 12a.

[0141] The multilayer ceramic capacitor 110 according to the second embodiment of the present invention may also be combined with all or part of the first to third modified examples described above. Furthermore, it may also be combined with all or part of the first to third modified examples of the multilayer ceramic capacitor 10 according to the first embodiment, and with other modified examples shown in the respective drawings.

[0142] 2. Method for Manufacturing a Multilayer Ceramic Capacitor A method for manufacturing a multilayer ceramic capacitor, which is an example of a multilayer ceramic capacitor according to the second embodiment, will now be described.

[0143] First, a conductive paste for the dielectric sheets and the internal electrodes is prepared. The conductive paste for the dielectric sheets and the internal electrodes contains a binder and a solvent. Known binders and solvents can be used.

[0144] Next, a conductive paste for the internal electrodes is printed in a predetermined pattern on the dielectric sheet by, for example, inkjet printing, screen printing, gravure printing, etc. This prepares a dielectric sheet on which the pattern of the first internal electrode is formed and a dielectric sheet on which the pattern of the second internal electrode is formed. Thereafter, the sheet on which the first internal electrode is printed and the sheet on which the second internal electrode is printed are laminated together to form a portion that becomes the inner layer portion 18.

[0145] Next, a predetermined number of dielectric sheets not printed with an internal electrode pattern are stacked to form the portion that will become the first outer layer portion 20a on the first main surface 12a. After that, the portion that will become the inner layer portion 18 prepared above is stacked, and a predetermined number of dielectric sheets not printed with an internal electrode pattern are stacked on top of this portion that will become the inner layer portion 18 to form the portion that will become the second outer layer portion 20b on the second main surface 12b. In this way, a laminated sheet is produced.

[0146] Next, the laminated sheet is pressed in the lamination direction by means of a hydrostatic press or the like to produce a laminated block.

[0147] The laminated block is then cut to a predetermined size to cut out laminated chips, the corners and ridges of which may be rounded by barrel polishing or the like.

[0148] Next, the laminated chip is fired to produce the laminate 12. The firing temperature depends on the ceramic and internal electrode materials, but is preferably 900° C. or higher and 1400° C. or lower.

[0149] Next, the obtained laminate 12 is aligned on a workbench, and the thin film layer 32 is formed on the first main surface 12a by sputtering. At this time, each thin film layer 32 is formed in a desired shape. That is, a mask is prepared so that the thin film layer 32 in the external electrode 130 of the present invention has one or more recesses 40 that protrude outward from an edge portion located toward the center of the laminate 12, and by using this mask, the thin film layer 32 can be formed into a desired shape.

[0150] Thereafter, an underlayer plating layer 34 is formed on the thin film layer 32 and the surface of the laminate 12, and a surface plating layer 36 is formed to cover the underlayer plating layer 34. More specifically, a Cu plating layer is formed on the thin film layer 32 as the underlayer plating layer 34. Then, a Ni plating layer and an Sn plating layer are formed on the surface of the underlayer plating layer 34 as the surface plating layer 36. Either electrolytic plating or electroless plating may be used for the plating process. However, electroless plating has the disadvantage of requiring pretreatment using a catalyst or the like to improve the plating deposition rate, which complicates the process. Therefore, it is usually preferable to use electrolytic plating.

[0151] In this manner, the multilayer ceramic capacitor 110 according to the second embodiment shown in FIG. 16 can be manufactured.

[0152] According to the method for manufacturing a multilayer ceramic capacitor according to this embodiment, it is possible to reduce the thickness of the external electrodes 130 formed on the first principal surface 12 a and the second principal surface 12 b in the lamination direction x, which is the dimension T, and therefore it is possible to provide a multilayer ceramic capacitor with a reduced height without impairing mountability during mounting.

[0153] Although the embodiments of the present invention have been disclosed above, the present invention is not limited thereto. In other words, various modifications can be made to the above-described embodiments in terms of mechanism, shape, material, quantity, position, arrangement, etc., without departing from the scope of the technical idea and purpose of the present invention, and such modifications are included in the present invention.

[0154] 10, 10A, 10B, 10C, 110 Multilayer ceramic capacitor 12 Laminate 12a First main surface 12b Second main surface 12c First side surface 12d Second side surface 12e Third side surface 12f Fourth side surface 14 Dielectric layer 14a Inner dielectric layer 14b Outer dielectric layer 16 Internal electrode 16a First internal electrode 16b Second internal electrode 18 Internal layer portion 20a First outer layer portion 20b Second outer layer portion 22a First opposing electrode portion 22b Second opposing electrode portion 24a First lead electrode portion 24b Second lead electrode portion 24c Third lead electrode portion 24d Fourth lead electrode portion 26a, 26b Side portions (W gaps) 28a, 28b of laminate End of laminate (L gap) 30, 130 External electrodes 30a, 130a First external electrode 30b, 130b Second external electrode 30c, 130c Third external electrode 30d, 130d Fourth external electrode 32 Thin film layer 32a First thin film layer 32b Second thin film layer 32c Third thin film layer 32d Fourth thin film layer 34 Underlayer plating layer 34a First underlayer plating layer 34b Second underlayer plating layer 34c Third underlayer plating layer 34d Fourth underlayer plating layer 36 Top layer plating layer 36a First surface plating layer 36b Second surface plating layer 36c Third surface plating layer 36d Fourth surface plating layer 40 Recess 40a First recess 40b Second recess 40c Third recess 40d Fourth recess 401 Thin film layer recess 401a First thin film layer recess 402 Underlayer plating layer recess 402a First underlayer plating layer recess 33 Direct plating layer 33a First direct plating layer 33b Second direct plating layer x Stacking direction y First direction z Second direction L Dimension of multilayer ceramic capacitor in first direction W Dimension of multilayer ceramic capacitor in second direction T Dimension of multilayer ceramic capacitor in stacking direction

Claims

1. A laminate having a first main surface and a second main surface that face each other in a stacking direction, a first side surface and a second side surface that face each other in a first direction perpendicular to the stacking direction, and a third side surface and a fourth side surface that face each other in a second direction perpendicular to the stacking direction and the first direction, a first external electrode arranged on the first side surface, the third side surface, the first main surface, and / or the second main surface, a second external electrode arranged on the second side surface, the third side surface, the first main surface, and / or the second main surface, a third external electrode arranged on the first side surface, the fourth side surface, the first main surface, and / or the second main surface, and a fourth external electrode arranged on the second side surface, the fourth side surface, the first main surface, and / or the second main surface, a multilayer ceramic capacitor in which, in the first external electrode to the fourth external electrode arranged on the first main surface and / or the second main surface, when viewed in the stacking direction, a straight line parallel to the first direction and the second direction is drawn from an intersection point where the first external electrode to the fourth external electrode and the laminate intersect, and one or more recesses are arranged inward from the outer edge of a range of an area surrounded by the straight line in at least one of the first external electrode to the fourth external electrode, and so as to protrude inward from an edge portion located toward the center of the laminate.

2. A laminate having a first main surface and a second main surface opposed to each other in a stacking direction, a first side surface and a second side surface opposed to each other in a first direction perpendicular to the stacking direction, and a third side surface and a fourth side surface opposed to each other in a second direction perpendicular to the stacking direction and the first direction; a first external electrode arranged on the first side surface, the third side surface, the first main surface and / or the second main surface; a second external electrode arranged on the second side surface, the third side surface, the first main surface and / or the second main surface; a third external electrode arranged on the first side surface, the fourth side surface, the first main surface and / or the second main surface; and a fourth external electrode arranged on the second side surface, the fourth side surface, the first main surface and / or the second main surface, wherein the first external electrode is the second external electrode comprises a second thin film layer disposed on the first main surface and / or the second main surface, a first underlayer plating layer disposed on the first side surface and the third side surface, and a first surface plating layer disposed on the first underlayer plating layer; the second external electrode comprises a second thin film layer disposed on the first main surface and / or the second main surface, a second underlayer plating layer disposed on the second side surface and the third side surface, and a second surface plating layer disposed on the second underlayer plating layer; the third external electrode comprises a third thin film layer disposed on the first main surface and / or the second main surface, a third underlayer plating layer disposed on the first side surface and the fourth side surface, and a third surface plating layer disposed on the third underlayer plating layer; the fourth external electrode comprises a fourth thin film layer disposed on the first main surface and / or the second main surface, a fourth underlayer plating layer disposed on the second side surface and the fourth side surface; and a fourth surface plating layer disposed on the fourth underlayer plating layer,a laminated ceramic capacitor, in which, in the first to fourth thin film layers arranged on the first main surface and / or the second main surface, when viewed in the stacking direction, a straight line parallel to the first direction and the second direction is drawn from a contact point where the first to fourth thin film layers and the laminate (12) contact, in at least one of the first to fourth thin film layers, the one or more recesses are arranged inside from an outer edge of a range surrounded by the straight line and protruding inward from an edge portion located toward the center of the laminate.

3. A laminate having a first main surface and a second main surface opposed to each other in a stacking direction, a first side surface and a second side surface opposed to each other in a first direction perpendicular to the stacking direction, and a third side surface and a fourth side surface opposed to each other in a second direction perpendicular to the stacking direction and the first direction; a first external electrode arranged on the first side surface, the third side surface, the first main surface and / or the second main surface; a second external electrode arranged on the second side surface, the third side surface, the first main surface and / or the second main surface; a third external electrode arranged on the first side surface, the fourth side surface, the first main surface and / or the second main surface; and a fourth external electrode arranged on the second side surface, the fourth side surface, the first main surface and / or the second main surface, wherein the first external electrode is the second external electrode comprises a second thin film layer disposed on the first main surface and / or the second main surface, a first underlayer plating layer disposed on the first side surface and the third side surface, and a first surface plating layer disposed on the first underlayer plating layer; the second external electrode comprises a second thin film layer disposed on the first main surface and / or the second main surface, a second underlayer plating layer disposed on the second side surface and the third side surface, and a second surface plating layer disposed on the second underlayer plating layer; the third external electrode comprises a third thin film layer disposed on the first main surface and / or the second main surface, a third underlayer plating layer disposed on the first side surface and the fourth side surface, and a third surface plating layer disposed on the third underlayer plating layer; the fourth external electrode comprises a fourth thin film layer disposed on the first main surface and / or the second main surface, a fourth underlayer plating layer disposed on the second side surface and the fourth side surface; and a fourth surface plating layer disposed on the fourth underlayer plating layer,a multilayer ceramic capacitor in which, in the first to fourth underlayer plating layers arranged on the first main surface and / or the second main surface, when viewed in the stacking direction, a straight line parallel to the first direction and the second direction is drawn from an intersection point where the first to fourth underlayer plating layers intersect with the laminate (12), and one or more recesses are arranged inside the outer edge of a range of an area surrounded by the straight line in at least one of the first to fourth underlayer plating layers, and protruding inward from an edge portion located toward the center of the laminate.

4. A multilayer ceramic capacitor as claimed in any one of claims 1 to 3, wherein, when the dimension of said multilayer ceramic capacitor in said first direction is dimension L and the dimension of said multilayer ceramic capacitor in said second direction is dimension W, the dimensions of said multilayer ceramic capacitor satisfy 7 / 10≦L dimension / W dimension≦10 / 7.

Images