Storage device and electronic apparatus

Abstract

Provided are: a storage device which enables highly reliable writing; and an electronic apparatus.　The storage device comprises: a plurality of magnets; and a plurality of magnetoresistive elements. In the storage device comprising the plurality of magnets and the plurality of magnetoresistive elements, the plurality of magnets are arranged in an array shape in first and second directions different from each other. Additionally, in the storage device comprising the plurality of magnets and the plurality of magnetoresistive elements, the plurality of magnetoresistive elements are arranged, together with the plurality of magnets, in a direction oblique to each of the first and second directions.

Description

Storage device and electronic device

[0001] The present disclosure relates to a storage device and an electronic device.

[0002] Magnetoresistive random access memory (MRAM), which uses magnetoresistive elements as memory elements, retains its state depending on the magnetization state of a ferromagnetic material, making it nonvolatile, meaning that recorded data is retained even when the power is turned off. The basic structure of a magnetoresistive element is a sandwich structure in which a nonmagnetic thin insulating film is sandwiched between two magnetic thin films made of magnetic material. This structure is called a magnetic tunnel junction (MTJ). Because the nonmagnetic thin films are very thin, on the order of a few nanometers, a tunnel current flows when a voltage is applied to both ends of the element. The magnitude of this tunnel current is characterized by its dependence on the relative angle of the magnetization of the two magnetic layers. This is called the tunnel magnetoresistance (TMR) effect.

[0003] In MRAM, the magnetization of one of the two magnetic layers (a fixed magnetization layer) is fixed, and the magnetization of the other magnetic layer (a storage layer) is controlled by an external field. The state in which the magnetizations of the fixed magnetization layer and the storage layer are parallel to each other is called state 0, and the state in which they are antiparallel is called state 1. In this way, the parallel / antiparallel state of magnetization is rewritten to store the state ("0" or "1") in a nonvolatile manner. Examples of external fields used to control the direction of magnetization include a current magnetic field generated by passing a current through external wiring, a method using the spin transfer torque (STT) effect by passing a current directly through the MTJ, and a method using voltage-controlled magnetic anisotropy (VCMA). The TMR effect is used to read the state.

[0004] The currently mainstream MRAM is STT-MRAM, which allows for more miniaturization and reduced power consumption than MRAMs using a current magnetic field. Meanwhile, voltage-controlled (VC) MRAMs using VCMA are attracting attention because of their high-speed writing and low power consumption. The VC-MRAM disclosed in Patent Document 1 includes a magnet disposed adjacent to the memory layer.

[0005] When no voltage is applied to the MTJ, the magnetization of the storage layer is oriented in the direction perpendicular to the film plane (z-direction) due to its perpendicular magnetic anisotropy (the tendency for magnetization to orient perpendicular to the film plane). Similarly, the magnetization of the fixed layer is oriented in the z-direction due to its perpendicular magnetic anisotropy. Assume now that the magnetizations of both the storage layer and the fixed layer are oriented in the +z direction, i.e., parallel, and state 0 is written. Also, assume that a magnetic field (hereinafter referred to as a bias magnetic field) generated by a magnet is applied in the +x direction of the film plane (the x and y directions). When a voltage is applied to the MTJ, the perpendicular magnetic anisotropy of the storage layer is eliminated by the electric field generated near the interface between the nonmagnetic layer and the storage layer, and the tendency for magnetization to orient perpendicular to the film plane is lost. As a result, the magnetization of the storage layer begins to move toward the x-direction, where magnetic energy is minimized by the bias magnetic field. At this time, the magnetization does not simply change linearly from the +z direction to the +x direction, but rather begins a so-called precession, gradually moving toward the +x direction while orbiting within the yz plane. The magnetization of the storage layer, which was initially oriented in the +z direction, experiences a moment of approximately oriented in the -z direction during precession in the yz plane. If the voltage applied to the MTJ is reduced to zero at this time, the perpendicular magnetic anisotropy of the storage layer returns to its original state, making it easier for the magnetization to orient perpendicular to the film surface, and the magnetization of the storage layer is fixed in the -z direction. In other words, applying a pulsed voltage writes from state 0 to state 1, where the magnetizations of the storage layer and fixed layer are antiparallel. The same thing happens even when the magnetization of the storage layer is initially oriented in the -z direction.

[0006] Japanese Patent Application Laid-Open No. 2016-225633

[0007] In the write operation described above, the precession caused by the bias magnetic field Bx is utilized, and the voltage application is stopped when the magnetization direction reverses due to the precession. The optimal timing is when half a period of the precession (hereinafter referred to as the half period) has elapsed. The half period is expressed as π(1 + α2) / γBx, where α is the diving constant of the storage layer. Here, γ is the gyromagnetic ratio. As can be seen from this equation, the half period is inversely proportional to the bias magnetic field Bx. The pulse width of the write voltage is generally the same for multiple MTJs in a memory cell array. Therefore, if the bias magnetic field differs among multiple MTJs, the half periods of each MTJ will differ, making it impossible to write with the optimal pulse width. Such fluctuations in the bias magnetic field occur, for example, when the relative positions of the magnet and the storage layer differ due to misalignment of the patterning.

[0008] Therefore, an object of the present disclosure is to provide a highly reliable writable storage device and electronic device.

[0009] The present technology has been made to solve the above-mentioned problems, and a first aspect thereof is a storage device including a plurality of magnets arranged in an array along first and second directions different from each other, and a plurality of magnetoresistive elements arranged together with the plurality of magnets along directions oblique to each of the first and second directions, thereby improving the reliability of writing.

[0010] In addition, in this first aspect, each of the magnetoresistive elements may be surrounded by four of the magnets on a plane parallel to the first and second directions, thereby improving the reliability of writing.

[0011] In addition, in this first aspect, two of the plurality of magnetoresistance elements may be arranged along the diagonal direction between two of the plurality of magnets that are arranged adjacent to each other along the diagonal direction, thereby providing the effect of reducing the area of ​​the memory cell.

[0012] In addition, in this first aspect, the shape of the magnets may be rectangular when viewed from a third direction perpendicular to the first and second directions, thereby improving the reliability of writing to a storage device in which rectangular magnets are arranged.

[0013] In addition, in this first aspect, the shape of the magnet may be circular when viewed from a third direction perpendicular to the first and second directions, thereby improving the reliability of writing to a storage device in which circular magnets are arranged.

[0014] In addition, in this first aspect, the plurality of magnets and the plurality of magnetoresistive elements may be arranged in the same layer, thereby improving the reliability of writing to a memory device in which the magnets and the magnetoresistive elements are arranged in the same layer.

[0015] In addition, in this first aspect, the plurality of magnets may be arranged in a first layer, and the plurality of magnetoresistive elements may be arranged in a second layer stacked on the first layer, thereby improving the reliability of writing to a storage device in which magnets and magnetoresistive elements are arranged in different layers.

[0016] In addition, in this first aspect, each of the plurality of magnetoresistive elements may have a structure in which a first ferromagnetic layer having fixed magnetization, a tunnel barrier layer, and a second ferromagnetic layer having a variable magnetization direction are stacked, thereby improving the reliability of writing to a storage device in which magnetoresistive elements, each of which is formed by stacking the first and second ferromagnetic layers and the tunnel barrier layer, are arranged.

[0017] In the first aspect, the first and second ferromagnetic layers may comprise a cobalt-iron-boron alloy layer, thereby improving the reliability of writing to a storage device including the cobalt-iron-boron alloy layer.

[0018] In the first aspect, the tunnel barrier layer may include a magnesium oxide layer, which improves the reliability of writing to a memory device including the magnesium oxide layer.

[0019] In this first aspect, each of the plurality of magnets may include a hard ferromagnetic layer or a soft ferromagnetic layer fixed by an antiferromagnetic material, thereby improving the reliability of writing to a storage device in which magnets including hard or soft ferromagnetic layers are arranged.

[0020] In this first aspect, the storage device may be a VC-MRAM, which has the effect of improving the reliability of writing to the VC-MRAM.

[0021] A second aspect of the present technology is an electronic device including a storage device including a plurality of magnets arranged in an array along first and second directions different from each other, and a plurality of magnetoresistive elements arranged together with the plurality of magnets along directions oblique to each of the first and second directions, and a host system that accesses the storage device, thereby improving the reliability of writing to the storage device in the electronic device.

[0022] FIG. 1 is a diagram illustrating a first exemplary configuration of a memory system according to an embodiment of the present disclosure. FIG. 2 is a diagram illustrating a second exemplary configuration of a memory system according to an embodiment of the present disclosure. FIG. 3 is a diagram illustrating a first exemplary configuration of a memory cell according to an embodiment of the present disclosure. FIG. 4 is a diagram illustrating a second exemplary configuration of a memory cell according to an embodiment of the present disclosure. FIG. 5 is a diagram illustrating a first exemplary configuration of a magnetoresistive element according to an embodiment of the present disclosure. FIG. 6 is a diagram illustrating a second exemplary configuration of a magnetoresistive element according to an embodiment of the present disclosure. FIG. 7 is a diagram illustrating a first exemplary configuration of a vertical arrangement of magnetoresistive elements and magnets according to an embodiment of the present disclosure. FIG. 8 is a diagram illustrating an exemplary configuration of a conventional in-plane arrangement of magnetoresistive elements and magnets. FIG. 9 is a diagram illustrating a bias magnetic field in an exemplary configuration of a conventional in-plane arrangement of magnetoresistive elements and magnets. FIG. 10 is a diagram illustrating a first exemplary configuration of an in-plane arrangement of magnetoresistive elements and magnets according to an embodiment of the present disclosure. FIG. 11 is a diagram illustrating a bias magnetic field in a first exemplary configuration of an in-plane arrangement of magnetoresistive elements and magnets according to an embodiment of the present disclosure. FIG. 12 is a diagram illustrating a second exemplary configuration of an in-plane arrangement of magnetoresistive elements and magnets according to an embodiment of the present disclosure. FIG. 13 is a diagram illustrating a bias magnetic field in a second exemplary configuration of an in-plane arrangement of magnetoresistive elements and magnets according to an embodiment of the present disclosure. FIG. 10 is a diagram illustrating a bias magnetic field in a third configuration example of an in-plane arrangement of magnetoresistive elements and magnets according to an embodiment of the present disclosure. FIG. 11 is a diagram illustrating a second configuration example of a vertical arrangement of magnetoresistive elements and magnets according to an embodiment of the present disclosure. FIG. 12 is a diagram illustrating a fourth configuration example of an in-plane arrangement of magnetoresistive elements and magnets according to an embodiment of the present disclosure. FIG. 13 is a diagram illustrating a bias magnetic field in a fourth configuration example of an in-plane arrangement of magnetoresistive elements and magnets according to an embodiment of the present disclosure. FIG. 14 is a diagram illustrating a manufacturing method for the first configuration example up to the formation of an insulating layer according to an embodiment of the present disclosure. FIG. 15 is a diagram illustrating a manufacturing method for the first configuration example up to the formation of a magnet according to an embodiment of the present disclosure. FIG. 16 is a diagram illustrating a manufacturing method for the first configuration example up to the formation of a memory cell according to an embodiment of the present disclosure. FIG. 17 is a diagram illustrating a manufacturing method for the second configuration example up to the formation of an insulating layer according to an embodiment of the present disclosure. FIG. 18 is a diagram illustrating a manufacturing method for the second configuration example up to the embedding of a magnet according to an embodiment of the present disclosure.10A to 10C are diagrams for explaining a manufacturing method of the second configuration example up to the formation of a memory cell according to an embodiment of the present disclosure.

[0023] The present disclosure will be described in the following order: 1. Embodiment 1-1. Configuration example of memory system 1-2. Configuration example of memory cell 1-3. Configuration example of magnetoresistive element 1-4. Configuration example of magnet 1-5. Arrangement example of magnetoresistive element and magnet

[0024] <1. Embodiment> <1-1. Configuration Example of Memory System> A configuration example of a memory system 1 according to this embodiment will be described with reference to FIG. 1. FIG. 1 is a diagram showing the configuration example of the memory system 1 according to this embodiment. This memory system 1 is an example of a storage device that retains information by the magnetization direction of a magnetic material. The magnetization direction is controlled by voltage. Such a storage device is called a VC-MRAM.

[0025] As shown in FIG. 1, a memory system 1 according to this embodiment includes an interface unit 2, a memory control unit 3, and a memory array 4.

[0026] The interface unit 2 exchanges (for example, transmits and receives) signals with a host system or the like that uses the memory system 1. The memory system 1 and the host system are provided in various electronic devices.

[0027] The memory control unit 3 communicates with the host system or the like and controls the memory array 4. The memory control unit 3 receives commands from the host system or the like and controls the writing and reading of data based on the received commands. For example, the memory control unit 3 outputs write and read commands, addresses, and data to be written to the memory array 4. After outputting a read command, the memory control unit 3 receives read data from the memory array 4.

[0028] The memory array 4 stores data and includes a memory cell array 10, a word line address decoder 20, a word line control circuit 30, a bit line address decoder 40, a bit line control circuit 50, a sense amplifier 60, a write circuit 70, a read circuit 80, and a voltage generation circuit 90. The write circuit 70 functions as a write unit.

[0029] The memory cell array 10 is configured by arranging memory cells 100, each storing data, in a two-dimensional matrix. Each memory cell 100 includes a selection element 110 and a magnetoresistive element 120. The magnetoresistive element 120 may be, for example, a magnetoresistive element such as an MTJ. The selection element 110 is connected to one end of the magnetoresistive element 120 and controls the application of voltage to the magnetoresistive element 120. The selection element 110 may be, for example, an n-channel MOS (Metal-Oxide-Semiconductor) transistor.

[0030] Word lines 11 (WL) and bit lines 12 (BL) that transmit control signals are connected to the memory cells 100. Source lines 13 (SL) that transmit signals from the magnetoresistive elements 120 are also arranged in the memory cells 100. In the memory cell array 10, a plurality of word lines 11 are wired to extend in the row direction, and a plurality of bit lines 12 and source lines 13 are wired to extend in the column direction.

[0031] The word line address decoder 20 selects the word line 11 of the memory cell array 10 based on a control signal from the memory control unit 3 .

[0032] The word line control circuit 30 outputs a control signal to the word line 11 selected by the word line address decoder 20 .

[0033] The bit line address decoder 40 selects the bit lines 12 of the memory cell array 10 based on a control signal from the memory control unit 3 .

[0034] The bit line control circuit 50 outputs a control signal to the bit line 12 selected by the bit line address decoder 40 .

[0035] The sense amplifier 60 reads data by detecting the current flowing through the memory cell 100 during reading. The read data is output to the memory control unit 3.

[0036] The write circuit 70 is a circuit that writes data to the memory cell 100 at the intersection of the selected word line 11 and bit line 12. The write circuit 70 writes data to the magnetoresistive element 120 of the memory cell 100 via the selection element 110.

[0037] The read circuit 80 is a circuit that reads data from the memory cell 100 at the intersection of the selected word line 11 and bit line 12. The read circuit 80 reads data from the magnetoresistive element 120 of the memory cell 100 via the selection element 110.

[0038] The voltage generating circuit 90 is a circuit that generates a voltage to be applied when writing to and reading from the memory cell 100 .

[0039] Although details of writing to the memory cell 100 will be described later, reading can be performed by applying a predetermined read voltage to the magnetoresistive element 120 of the memory cell 100 and detecting the current flowing through the memory cell 100. It is preferable that the read voltage has a different polarity from the write voltage.

[0040] Next, another configuration example of the memory system 1 according to the embodiment will be described with reference to Fig. 2. Fig. 2 is a diagram showing another configuration example of the memory system 1 according to the embodiment of the present disclosure. This memory system 1 is also an example of a storage device that retains information based on the magnetization direction of a magnetic material.

[0041] 2, unlike in FIG. 1, bit line control circuits 51 and 52 are arranged above and below the memory cell array 10. This allows, for example, the bit line control circuit 52 arranged above to control the even-numbered bit lines 12, and the bit line control circuit 51 arranged below to control the odd-numbered bit lines 12. Other functions are the same as those of the memory system 1 shown in FIG. 1.

[0042] <1-2. Configuration Example of Memory Cell> A configuration example of the memory cell 100 according to this embodiment will be described with reference to FIGS. 3 and 4. FIGS. 3 and 4 are diagrams each showing a configuration example of the memory cell 100 according to this embodiment. Either the configuration shown in FIGS. 3 or 4 is used. Each diagram is a schematic diagram showing a configuration example of the memory cell 100. As described above, the memory cell 100 includes a selection element 110 and a magnetoresistive element 120. In the example shown in FIGS. 3 and 4, the selection element 110 and the magnetoresistive element 120 are connected in series, and the selection element 110 has a drain (drain terminal), a source (source terminal), and a gate (gate terminal). In addition, a magnet 130 for applying a bias magnetic field is disposed near the magnetoresistive element 120. A specific arrangement method will be described later.

[0043] 3, the magnetoresistive element 120 of the memory cell 100 is connected to the wiring 101 via the contact layer 103, and is connected to the selection element 110 via the contact layer 104. The selection element 110 has a drain connected to the contact layer 104 and a source connected to a source line 13 (SL). The gate of the selection element 110 is connected to a word line 11 (WL). The contact layer 103 is connected to the wiring 101 that constitutes the bit line 12 (BL). By applying an on-voltage to the word line 11 (WL), the selection element 110 becomes conductive, allowing a voltage to be applied to the magnetoresistive element 120.

[0044] 4, the magnetoresistive element 120 of the memory cell 100 is connected to the wiring 102 via the contact layer 104, and is connected to the selection element 110 via the contact layer 103. The selection element 110 has a drain connected to the bit line 12 (BL) and a source connected to the contact layer 103. The gate of the selection element 110 is connected to the word line 11 (WL). The contact layer 104 is connected to the wiring 102 that constitutes the source line 13 (SL). By applying an on-voltage to the word line 11 (WL), the selection element 110 becomes conductive, allowing a voltage to be applied to the magnetoresistive element 120.

[0045] As described above, the word line 11 (WL) is connected to the word line control circuit 30 (see FIGS. 1 and 2). The bit line 12 (BL) is connected to the bit line control circuit 50, 51, or 52 (see FIGS. 1 and 2). The source line 13 (SL) is connected to the sense amplifier 60 (see FIGS. 1 and 2). By applying a voltage between the bit line 12 (BL) and the source line 13 (SL) and also applying an on-voltage to the word line 11 (WL) that turns on the selection element 110, a voltage for writing or reading can be applied to the magnetoresistive element 120.

[0046] <1-3. Configuration Example of Magnetoresistive Element> A configuration example of the magnetoresistive element 120 according to this embodiment will be described with reference to Fig. 5 and Fig. 6. Fig. 5 and Fig. 6 are diagrams each showing a configuration example of the magnetoresistive element 120 according to this embodiment. Either the configuration shown in Fig. 5 or Fig. 6 is used. Each figure is a cross-sectional view showing a configuration example of the magnetoresistive element 120.

[0047] 5 and 6, the magnetoresistive element 120 includes an underlayer 121, a magnetization fixed layer 122, a tunnel barrier layer 123, a memory layer 124, and a cap layer 125. The magnetoresistive element 120 shown in Fig. 5 is configured by sequentially stacking the underlayer 121, the magnetization fixed layer 122, the tunnel barrier layer 123, the memory layer 124, and the cap layer 125. On the other hand, the magnetoresistive element 120 shown in Fig. 6 is configured by sequentially stacking the underlayer 121, the memory layer 124, the tunnel barrier layer 123, the magnetization fixed layer 122, and the cap layer 125.

[0048] The underlayer 121 can be a layer or a laminate structure of a precious metal or transition metal element, such as chromium (Cr), tantalum (Ta), ruthenium (Ru), gold (Au), silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), vanadium (V), molybdenum (Mo), zirconium (Zr), hafnium (Hf), rhenium (Re), tungsten (W), platinum (Pt), lead (Pd), iridium (Ir), or rhodium (Rh). The underlayer 121 can also be made of a conductive nitride, such as titanium nitride (TiN). For example, the underlayer 121 can be made of a film for controlling the crystal orientation of the pinned magnetization layer 122 or improving adhesion strength to the lower electrode.

[0049] The magnetization pinned layer 122 is a layer that has magnetic anisotropy and whose magnetization direction is invariable. This magnetization pinned layer 122 can be composed of, for example, cobalt-iron-boron (CoFeB), cobalt-iron-carbon (CoFeC) alloy, nickel-iron-boron (NiFeB) alloy, nickel-iron-carbon (NiFeC) alloy, etc. The magnetization pinned layer 122 can also have a laminated ferri-pinned structure in which multiple ferromagnetic layers are stacked with non-magnetic layers interposed between them. Ferromagnetic layers that constitute the magnetization pinned layer of this laminated ferri-pinned structure can be made of cobalt (Co), cobalt-iron (CoFe), cobalt-iron-boron (CoFeB), etc. The non-magnetic layers can be made of ruthenium (Ru), rhenium (Re), iridium (Ir), osmium (Os), etc.

[0050] The magnetization fixed layer 122 can have a fixed direction of magnetization by utilizing antiferromagnetic coupling between an antiferromagnetic layer and a ferromagnetic layer. Materials for the antiferromagnetic layer include iron-manganese (FeMn) alloy, platinum-manganese (PtMn) alloy, platinum-chromium-manganese (PtCrMn) alloy, nickel-manganese (NiMn) alloy, iridium-manganese (IrMn) alloy, nickel oxide (NiO), and iron trioxide (FeO). ２ O ３) and other magnetic materials. In addition, non-magnetic elements such as silver (Ag), copper (Cu), gold (Au), aluminum (Al), silicon (Si), bismuth (Bi), tantalum (Ta), boron (B), carbon (C), oxygen (O), nitrogen (N), lead (Pd), platinum (Pt), zirconium (Zr), hafnium (Hf), iridium (Ir), tungsten (W), molybdenum (Mo), and niobium (Nb) can also be added to these magnetic materials.

[0051] The tunnel barrier layer 123 is disposed adjacent to a storage layer 124 (described later) and applies an electric field to the storage layer 124 to impart a voltage-controlled magnetic anisotropy effect. The tunnel barrier layer 123 may be composed of an oxide of at least one element selected from the group consisting of magnesium (Mg), aluminum (Al), titanium (Ti), silicon (Si), zinc (Zn), zirconium (Zr), hafnium (Hf), tantalum (Ta), bismuth (Bi), chromium (Cr), gallium (Ga), lanthanum (La), gadolinium (Gd), bromine (Sr), and barium (Ba), or a nitride of at least one element selected from the group consisting of magnesium (Mg), aluminum (Al), titanium (Ti), silicon (Si), zinc (Zn), zirconium (Zr), hafnium (Hf), tantalum (Ta), bismuth (Bi), chromium (Cr), gallium (Ga), lanthanum (La), gadolinium (Gd), bromine (Sr), and barium (Ba). Alternatively, magnesium difluoride (MgF ２ ), calcium fluoride (CaF), strontium titanium dioxide (SrTiO ２ ), lanthanum aluminum trioxide (AlLaO ３ The tunnel barrier layer 123 may be formed using an insulator, a dielectric, or a semiconductor such as aluminum oxynitride (AlNO). A structure in which these layers are stacked may also be used. The thickness of the tunnel barrier layer 123 is preferably 0.6 nm (nanometers) or more.

[0052] The memory layer 124 is a layer that has magnetic anisotropy and a variable magnetization direction. The memory layer 124 is also a layer that has the VCMA effect. The states in which the magnetization direction of the memory layer 124 is the same as and different from the magnetization direction of the magnetization fixed layer 122 are called the parallel state and the antiparallel state, respectively. The magnetoresistive element 120 is in a low resistance state when in the parallel state, and in a high resistance state when in the antiparallel state. As described above, the magnetization direction of the memory layer 124 can be changed by applying a voltage to the magnetoresistive element 120.

[0053] The memory layer 124 can be composed of cobalt iron (CoFe), cobalt iron boron (CoFeB), Fe, iron boride (FeB), or the like. It can also be configured to include a transition metal. Examples of transition metals include hafnium (Hf), tantalum (Ta), tungsten (W), rhenium (Re), iridium (Ir), platinum (Pt), gold (Au), zirconium (Zr), niobium (Nb), molybdenum (Mo), ruthenium (Ru), rhodium (Rh), lead (Pd), silver (Ag), titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), nickel (Ni), and copper (Cu). It can also include nitrides or oxides. Iridium (Ir) and osmium (Os) can be used as materials that induce a proximity magnetic moment in a magnetic material. It is also possible to improve the voltage-controlled magnetic anisotropy effect by adding a heavy metal to the memory layer 124. The thickness of the memory layer 124 is preferably set to 3.0 nm (nanometers) or less.

[0054] The memory layer 124 may also have a stacked structure in which multiple ferromagnetic layers are stacked with a non-magnetic layer interposed therebetween. In this case, two adjacent ferromagnetic layers may be exchange-coupled via the non-magnetic layer. The non-magnetic layer may be composed of magnesium (Mg), aluminum (Al), titanium (Ti), silicon (Si), zinc (Zn), zirconium (Zr), hafnium (Hf), tantalum (Ta), bismuth (Bi), chromium (Cr), gallium (Ga), lanthanum (La), gadolinium (Gd), bromine (Sr), barium (Ba), tungsten (W), rhenium (Re), iridium (Ir), platinum (Pt), gold (Au), niobium (Nb), molybdenum (Mo), ruthenium (Ru), rhodium (Rh), lead (Pd), silver (Ag), vanadium (V), manganese (Mn), nickel (Ni), copper (Cu), or the like.

[0055] The cap layer 125 is a layer that prevents metal diffusion from the wiring member. This cap layer 125 can be composed of metals such as chromium (Cr), tantalum (Ta), ruthenium (Ru), gold (Au), silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), vanadium (V), molybdenum (Mo), zirconium (Zr), hafnium (Hf), rhenium (Re), tungsten (W), platinum (Pt), lead (Pd), iridium (Ir), and rhodium (Rh). The cap layer 125 can also be composed of an alloy containing these metals or a layer made of a transition metal element. The cap layer 125 can also be composed of a stack of these metals. The cap layer 125 can also be composed of a conductive nitride such as titanium nitride (TiN).

[0056] The various layers described above can be fabricated by, for example, a physical vapor deposition (PVD) method, such as sputtering, ion beam deposition, or vacuum evaporation, or a chemical vapor deposition (CVD) method, such as atomic layer deposition (ALD). These layers can be patterned by reactive ion etching (RIE) or ion milling. It is preferable to form the various layers consecutively in a vacuum chamber, followed by patterning.

[0057] <1-4. Configuration Examples of Magnets> Configuration examples of the magnet 130 according to this embodiment will be described.

[0058] The magnet can be made of a hard magnetic material such as cobalt platinum (CoPt), or a soft magnetic material such as NiFe fixed by an antiferromagnetic material. The magnet 130 can be fabricated by the same fabrication and patterning methods as those for the magnetoresistive element described above.

[0059] 1-5. Examples of Arrangements of Magnetoresistive Elements and Magnets Examples of arrangements of the magnetoresistive elements 120 and magnets 130 according to this embodiment will be described with reference to FIGS. 7 to 18. FIG.

[0060] 7 is a diagram showing a first example of the vertical arrangement of the magnetoresistive element 120 and the magnet 130 according to this embodiment. The magnetoresistive element 120 and the magnet 130 are arranged on the same plane.

[0061] FIG. 8 is a diagram showing an example of the in-plane arrangement of conventional magnetoresistance elements 120 and magnets 130. The vertical arrangement is the same as FIG. 7. Here, the cross-sectional shape of the magnet 130 is square, and the cross-sectional shape of the magnetoresistance element 120 is circular. The magnetization of the magnet 130 is oriented in the +x direction. A bias magnetic field is generated from the magnet, and FIG. 8 shows its magnetic field lines. The magnetoresistance elements 120 and magnets 130 are arranged in a lattice pattern, alternating in the X direction. The saturation magnetization of the magnet 130 is 1 T (tesla), the side length is 50 nm (nanometers), and the film thickness is 15 nm (nanometers). The magnetoresistance elements 120 and magnets 130 are arranged with a center-to-center distance of 100 nm (nanometers). The magnets 130 are arranged in an array along the X and Y directions, which are orthogonal to each other. The direction perpendicular to these X and Y directions is the Z direction. FIG. 8 is a plan view viewed from the Z direction. The X direction, Y direction, and Z direction are examples of the first direction, second direction, and third direction set forth in the claims.

[0062] FIG. 9 is a diagram showing the bias magnetic field in an example configuration of a conventional magnetoresistive element 120 and magnet 130 arranged in the in-plane direction. The bias magnetic field Bx in the X direction is shown, with the center of the magnetoresistive element 120 taken as the origin. The solid line indicates the X direction, and the dotted line indicates the Y direction. Looking at the solid line, it is clear that it is parabolic with respect to the X direction position. It can be seen that when the magnetoresistive element is displaced in the X direction due to misalignment of the patterning, etc., the bias magnetic field fluctuates. This causes the aforementioned half-period shift, which reduces the reliability of the write operation.

[0063] Figure 10 is a diagram showing a first configuration example of the in-plane arrangement of the magnetoresistance elements 120 and magnets 130 according to this embodiment. Compared to the conventional example of Figure 8, the magnetoresistance elements 120 are arranged with a shift of 50 nm in the Y direction. In other words, the number of magnets 130 nearest to one magnetoresistance element 120 is four. In other words, if the diagonal directions with respect to both the X direction and the Y direction are defined as S directions, then the magnets 130 and magnetoresistance elements 120 are arranged alternately one by one in the S direction.

[0064] 11 is a diagram showing the bias magnetic field in a first configuration example of the in-plane arrangement of the magnetoresistive element 120 and magnet 130 according to this embodiment. Compared to the conventional example of FIG. 9, the X-direction dependency of the bias magnetic field Bx is almost eliminated. Therefore, even if the magnetoresistive element is displaced in the X-direction due to misalignment of the patterning, the bias magnetic field hardly fluctuates, and no half-period shift occurs. This prevents a decrease in the reliability of the write operation.

[0065] FIG. 12 is a diagram showing a second configuration example of the in-plane arrangement of the magnetoresistive elements 120 and the magnets 130 according to this embodiment. Compared to the configuration example shown in FIG. 10 , the number of rows of the magnetoresistive elements 120 is two. In other words, two magnetoresistive elements 120 are arranged along a diagonal direction (i.e., the S direction) between two magnets 130 arranged adjacent to each other along the diagonal direction. This allows the number of magnets 130 per magnetoresistive element 120 to be reduced, thereby reducing the memory cell area. For ease of explanation, for example, the area of ​​the magnetoresistive element 120 and the area of ​​the magnet 130 are both represented as "s," and attention is focused only on these areas. In this case, in the first configuration example, the area of ​​one memory cell including one magnetoresistive element 120 and one magnet 130 is "2×s." On the other hand, in the second configuration example, the area of ​​each of two memory cells including two magnetoresistive elements and one shared magnet 130 is reduced to "1.5×s."

[0066] 13 is a diagram showing the bias magnetic field in a second configuration example of the in-plane arrangement of the magnetoresistive element 120 and the magnet 130 according to this embodiment. Although the bias magnetic field fluctuates more than in FIG. 11, since it is not parabolic like the conventional example shown in FIG. 9, the fluctuation of the bias magnetic field can be suppressed compared to the conventional example.

[0067] 14 is a diagram showing a third configuration example of the in-plane arrangement of the magnetoresistive element 120 and the magnet 130 according to this embodiment. Compared to the configuration example of FIG. 10, the cross-sectional shape of the magnet 130 is circular when viewed from the Z direction.

[0068] 15 is a diagram showing the bias magnetic field in a third configuration example of the in-plane arrangement of the magnetoresistance element 120 and the magnet 130 according to this embodiment. As in FIG. 11, there is almost no fluctuation in the bias magnetic field.

[0069] Fig. 16 is a diagram showing a second configuration example of the vertical arrangement of the magnetoresistance element 120 and the magnet 130 according to this embodiment. The vertical positions are different from those in Fig. 7. Note that the relative vertical positional relationship between the magnetoresistance element 120 and the magnet 130 may be reversed from that in Fig. 16.

[0070] Fig. 17 is a diagram showing a fourth configuration example of the in-plane arrangement of the magnetoresistive element 120 and the magnet 130 according to this embodiment. The in-plane arrangement is the same as Fig. 10. The vertical arrangement is as shown in Fig. 16, and the vertical center distance between the magnetoresistive element 120 and the magnet 130 is 10 nm (nanometers).

[0071] 18 is a diagram showing the bias magnetic field in a fourth configuration example of the in-plane arrangement of the magnetoresistance element 120 and the magnet 130 according to this embodiment. As in FIG. 11, there is almost no fluctuation in the bias magnetic field.

[0072] Next, a method for manufacturing the first configuration example illustrated in FIG. 7 will be described with reference to FIGS.

[0073] First, the manufacturing system forms peripheral circuits, such as write drivers and sense amplifiers, necessary for memory operation on a semiconductor substrate such as a silicon substrate, and also forms bottom electrodes for connection to each magnetoresistive element.

[0074] As a result, a base substrate 141 including a peripheral circuit is fabricated, as illustrated in Fig. 19a. The element formation surface of the semiconductor substrate on which the lower electrode is formed may be buried with an insulating layer except for the connection portion with the magnetoresistive element to be formed later.

[0075] Then, as illustrated in b in the figure, a first layer to be processed into an underlayer 121 is stacked on the entire surface of the base substrate, then a second layer to be processed into a magnetization fixed layer 122 is stacked, and a third layer to be processed into a tunnel barrier layer 123 is stacked. Furthermore, a fourth layer to be processed into a memory layer 124 is stacked, and a fifth layer to be processed into a cap layer 125 is stacked. In this way, a stacked film 120-1 consisting of these five layers is formed. Various film formation techniques suitable for each layer, such as a CVD method or a sputtering method, may be used to form the first to fifth layers.

[0076] Then, as illustrated in FIG. 1C, the manufacturing system forms a hard mask 142 on the stacked film 120-1 by using photolithography or the like. Furthermore, the manufacturing system forms a mesa-shaped magnetoresistive element 120 by digging out the stacked film 120-1 exposed from the hard mask 142 using an etching technique such as IBE (Ion Beam Etching) or RIE (Reactive Ion Etching). By forming the hard mask 142 from a conductive metal, the hard mask 142 can be used for electrical connection between the magnetoresistive element 120 and the upper electrode.

[0077] Then, as illustrated in d in the figure, the manufacturing system uses a CVD method or a sputtering method to form an insulating layer 143 so as to bury the structure made up of the magnetoresistive element 120 and the hard mask 142. The upper surface of the insulating layer 143 may be planarized by CMP (Chemical Mechanical Polishing) or the like.

[0078] 20A, the manufacturing system uses photolithography and etching techniques to form trenches in the insulating layer 143 for forming the magnets 130. The upper surface of the insulating layer 143 may be planarized by CMP or the like.

[0079] Then, as illustrated in b in the figure, the manufacturing system forms a magnet film 130-1 on the base substrate 141 exposed from the trench and on the insulating layer 143. The magnet film 130-1 formed on the insulating layer 143 may be removed by a lift-off method, CMP, or the like. Various film formation techniques suitable for the magnet film 130-1, such as a CVD method or a sputtering method, may be used to form the magnet film 130-1.

[0080] Then, as illustrated in c in the figure, the manufacturing system forms a hard mask 144 on the magnet film 130-1 by using photolithography or the like. Then, the manufacturing system forms the mesa-shaped magnet 130 by digging into the magnet film 130-1 exposed from the hard mask 144 using an etching technique such as IBE or RIE.

[0081] 21 a, the manufacturing system uses CVD or sputtering to fill the trenches in the insulating layer 143. This forms the insulating layer 143 that covers the structure made up of the magnetoresistive element 120 and the hard mask 142 and the structure made up of the magnet 130 and the hard mask 144. The top surface of the insulating layer 143 may be planarized by CMP or the like.

[0082] Then, as illustrated in FIG. 1B, the manufacturing system uses photolithography and etching techniques to form an opening that exposes a portion of the top surface of the hard mask 142 on the magnetoresistive element 120 .

[0083] Then, as illustrated in c in the figure, wiring 145 connected to the hard mask 142 is buried in the opening. After that, wiring (not shown) that connects the wiring to peripheral circuits is formed on the insulating layer 143, thereby fabricating the memory cell 100 according to this embodiment.

[0084] Next, a method for manufacturing the second configuration example shown in FIG. 16 will be described with reference to FIGS.

[0085] As illustrated in FIGS. 22a, 22b, 22c, and 22d, a structure made up of the magnetoresistive element 120 and the hard mask 142 is embedded in the insulating layer 143 by the same manufacturing method as in the first configuration example.

[0086] 23a, the manufacturing system forms a magnet film 130-1 over the entire surface of the insulating layer 143. The magnet film 130-1 may be formed using various film formation techniques suitable for the magnet film, such as a CVD method or a sputtering method.

[0087] Then, as illustrated in b in the figure, the manufacturing system forms a hard mask 144 on the magnet film 130-1 by using photolithography or the like. Then, the manufacturing system forms a mesa-shaped magnet 130 by digging into the magnet film 130-1 exposed from the hard mask 144 using an etching technique such as IBE.

[0088] Then, as illustrated in c in the figure, the manufacturing system uses a CVD method or a sputtering method to form an insulating layer 143 so as to embed the structure made up of the magnet 130 and the hard mask 144. The upper surface of the insulating layer 143 may be planarized by CMP or the like.

[0089] Next, as illustrated in FIG. 24A, the manufacturing system uses photolithography and etching techniques to form an opening that exposes a portion of the top surface of the hard mask 142 on the magnetoresistive element 120 .

[0090] Then, as illustrated in b in the figure, wiring 145 connected to the hard mask 142 is buried in the opening. After that, wiring (not shown) that connects the wiring 145 to the peripheral circuit is formed on the insulating layer, thereby fabricating the memory cell 100 according to this embodiment.

[0091] Note that the above-described embodiment shows an example for realizing the present technology, and the matters in the embodiment and the matters specifying the invention in the claims correspond to each other. Similarly, the matters specifying the invention in the claims and the matters in the embodiment of the present technology having the same name correspond to each other. However, the present technology is not limited to the embodiment, and can be realized by applying various modifications to the embodiment within the scope of the gist thereof.

[0092] The effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0093] The present technology may also be configured as follows: (1) A storage device comprising: a plurality of magnets arranged in an array along first and second directions different from each other; and a plurality of magnetoresistive elements arranged together with the plurality of magnets along a direction oblique to each of the first and second directions. (2) The storage device according to (1), wherein each of the magnetoresistive elements is surrounded by four of the magnets on a plane parallel to the first and second directions. (3) The storage device according to (1), wherein two of the plurality of magnetoresistive elements are arranged along the oblique direction between two of the plurality of magnets arranged adjacent to each other along the oblique direction. (4) The storage device according to any of (1) to (3), wherein the shape of the magnet is rectangular when viewed from a third direction perpendicular to the first and second directions. (5) The storage device according to any of (1) to (3), wherein the shape of the magnet is circular when viewed from a third direction perpendicular to the first and second directions. (6) The storage device according to any one of (1) to (5), wherein the plurality of magnets and the plurality of magnetoresistive elements are arranged in the same layer. (7) The storage device according to any one of (1) to (5), wherein the plurality of magnets are arranged in a first layer, and the plurality of magnetoresistive elements are arranged in a second layer stacked on the first layer. (8) The storage device according to (1), wherein each of the plurality of magnetoresistive elements has a stacked structure of a first ferromagnetic layer having fixed magnetization, a tunnel barrier layer, and a second ferromagnetic layer whose magnetization direction is variable. (9) The storage device according to (8), wherein the first and second ferromagnetic layers comprise cobalt-iron-boron alloy layers. (10) The storage device according to (8) or (9), wherein the tunnel barrier layer comprises a magnesium oxide layer. (11) The storage device according to any one of (1) to (10), wherein each of the plurality of magnets comprises a hard ferromagnetic layer or a soft ferromagnetic layer fixed by an antiferromagnetic material. (12) The storage device according to any one of (1) to (11), wherein the storage device is a VC-MRAM.(13) An electronic device comprising: a storage device having a plurality of magnets arranged in an array along first and second directions different from each other; and a plurality of magnetic resistance elements arranged together with the plurality of magnets along directions oblique to each of the first and second directions; and a host system that accesses the storage device.

[0094] 1 Memory system 2 Interface unit 3 Memory control unit 4 Memory array 10 Memory cell array 11 Word line 12 Bit line 13 Source line 20 Word line address decoder 30 Word line control circuit 40 Bit line address decoder 50, 51, 52 Bit line control circuit 60 Sense amplifier 70 Write circuit 80 Read circuit 90 Voltage generation circuit 100 Memory cell 101 Wiring 102 Wiring 103 Contact layer 104 Contact layer 110 Selection element 120 Magnetoresistance element 120-1 Stacked film 121 Underlayer 122 Magnetization fixed layer 123 Tunnel barrier layer 124 Memory layer 125 Cap layer 130 Magnet 130-1 Magnet film 141 Base substrate 142, 144 Hard mask 143 Insulating layer 145 Wiring

Claims

1. A memory device comprising: a plurality of magnets arranged in an array along first and second directions that are different from each other; and a plurality of magnetic resistance elements arranged together with the plurality of magnets along directions oblique to each of the first and second directions.

2. The storage device according to claim 1, wherein each of said magnetoresistance elements is surrounded by four of said magnets on a plane parallel to said first and second directions.

3. The storage device according to claim 1, wherein two of said plurality of magnetoresistance elements are arranged along said diagonal direction between two magnets among said plurality of magnets that are arranged adjacent to each other along said diagonal direction.

4. The storage device according to claim 1, wherein the magnet has a rectangular shape when viewed in a third direction perpendicular to the first and second directions.

5. The storage device according to claim 1, wherein the magnet has a circular shape when viewed in a third direction perpendicular to the first and second directions.

6. The storage device according to claim 1, wherein the plurality of magnets and the plurality of magnetoresistance elements are arranged in the same layer.

7. The storage device according to claim 1, wherein the plurality of magnets are arranged in a first layer, and the plurality of magnetoresistance elements are arranged in a second layer laminated on the first layer.

8. The memory device according to claim 1, wherein each of the plurality of magnetoresistance elements has a laminated structure including a first ferromagnetic layer having fixed magnetization, a tunnel barrier layer, and a second ferromagnetic layer whose magnetization direction is variable.

9. The memory device of claim 8, wherein the first ferromagnetic layer and the second ferromagnetic layer comprise a cobalt iron boron alloy layer.

10. The memory device of claim 8, wherein the tunnel barrier layer comprises a magnesium oxide layer.

11. The storage device of claim 1, wherein each of the plurality of magnets comprises a hard ferromagnetic layer or a soft ferromagnetic layer fixed by an antiferromagnetic material.

12. The storage device according to claim 1, wherein the storage device is a VC-MRAM (Voltage-controlled Magnetoresistive Random Access Memory).

13. An electronic device comprising: a storage device having a plurality of magnets arranged in an array along first and second directions different from each other, and a plurality of magnetoresistance elements arranged together with the plurality of magnets along directions oblique to each of the first and second directions; and a host system that accesses the storage device.

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