Optical detection device and electronic equipment

Abstract

Provided is an optical detection device that is capable of suppressing reduction in a quantum efficiency Qe while suppressing generation of a dark current. Specifically, the optical detection device comprises: a semiconductor substrate; a plurality of photoelectric conversion parts formed in a two-dimensional array on the semiconductor substrate; a trench part which is formed in a region between the photoelectric conversion parts of the semiconductor substrate and has an opening on at least the rear surface side thereof; and a conductive film which is disposed inside the trench part and to which a negative bias voltage is applied. A first portion, which is a portion on the rear surface side of the conductive film, includes a first conductive film that covers one inner wall surface of a pair of inner wall surfaces facing each other in the trench portion, and a second conductor film that is separated from the first conductor film and covers the other inner wall surface of the pair of inner wall surfaces. The second portion, which is a portion on the front surface side, has a blocking portion that blocks the inside of the trench portion.

Description

Photodetector and electronic equipment

[0001] The present technology (technology according to the present disclosure) relates to a light detection device and an electronic device.

[0002] Conventionally, for example, a photodetector has been proposed that includes a semiconductor substrate having a plurality of photoelectric conversion units, a trench portion formed in a region of the semiconductor substrate between the photoelectric conversion units, and a conductor that is filled in the trench portion and to which a negative bias voltage is applied (see, for example, Patent Document 1). In the photodetector described in Patent Document 1, a negative bias voltage is applied to the conductor to create a high hole concentration around the trench portion, thereby suppressing the generation of dark current.

[0003] Patent No. 7279014

[0004] However, in the photodetector described in Patent Document 1, the conductor in the trench portion absorbs light, which reduces the amount of incident light that is photoelectrically converted in the photoelectric conversion portion, potentially resulting in a decrease in quantum efficiency.

[0005] An object of the present disclosure is to provide a photodetector and electronic equipment that can suppress the occurrence of dark current and also suppress a decrease in quantum efficiency Qe.

[0006] The photodetector disclosed herein comprises: (a) a semiconductor substrate having a first surface that is a light-receiving surface and a second surface opposite the first surface; (b) a plurality of photoelectric conversion units formed in a two-dimensional array on the semiconductor substrate; (c) a trench portion formed in a region of the semiconductor substrate between the photoelectric conversion units and having an opening at least on the first surface side; and (d) a conductor film disposed inside the trench portion and to which a negative bias voltage is applied; (e) a first portion of the conductor film that is on the first surface side has a first conductor film that covers one of a pair of opposing inner wall surfaces of the trench portion and a second conductor film that is spaced from the first conductor film and covers the other inner wall surface of the pair of inner wall surfaces; and the second portion that is on the second surface side has a blocking portion that blocks the inside of the trench portion.

[0007] The electronic device of the present disclosure comprises: (a) a semiconductor substrate having a first surface that is a light receiving surface and a second surface opposite to the first surface; (b) a plurality of photoelectric conversion units formed in a two-dimensional array on the semiconductor substrate; (c) a trench portion formed in a region of the semiconductor substrate between the photoelectric conversion units and having an opening at least on the first surface side; (d) and a conductor film disposed inside the trench portion and to which a negative bias voltage is applied; (e) a photodetector device in which the first portion of the conductor film, which is the portion on the first surface side, has a first conductor film covering one of a pair of opposing inner wall surfaces of the trench portion, and a second conductor film spaced from the first conductor film and covering the other of the pair of inner wall surfaces; and the second portion, which is the portion on the second surface side, has a blocking portion that blocks the inside of the trench portion.

[0008] 20 is a diagram showing the overall configuration of a solid-state imaging device according to a first embodiment; FIG. 21 is a diagram showing a cross-sectional configuration of a solid-state imaging device when the semiconductor substrate of FIG. 1 is broken along the row direction; FIG. 22 is a diagram showing the overall configuration of a solid-state imaging device according to a modified example; FIG. 23 is a diagram showing the overall configuration of a solid-state imaging device according to a modified example; FIG. 24 is a diagram showing a method for forming a trench isolation structure; FIG. 25 is a diagram showing a method for forming a trench isolation structure; FIG. 26 is a diagram showing a method for forming a trench isolation structure; FIG. 27 is a diagram showing a method for forming a trench isolation structure; FIG. 28 is a diagram showing a cross-sectional configuration of a voltage application structure; FIG. 29 is a diagram showing an enlarged view of a negative bias region; FIG. 30 is a diagram showing an enlarged view of a negative bias region according to a modified example; FIG. 31 is a diagram showing a cross-sectional configuration of a solid-state imaging device according to a modified example; FIG. 32 is a diagram showing a cross-sectional configuration of a solid-state imaging device according to a modified example; FIG. 33 is a diagram showing a cross-sectional configuration of a solid-state imaging device according to a modified example; FIG. 34 is a diagram showing a cross-sectional configuration of a solid-state imaging device according to a modified example; FIG. 35 is a diagram showing a cross-sectional configuration of a solid-state imaging device according to a modified example; FIG. 36 is a diagram showing a cross-sectional configuration of a solid-state imaging device according to a modified example; FIG. 37 is a diagram showing a cross-sectional configuration of a solid-state imaging device according to a modified example; FIG. 38 is a diagram showing a cross-sectional configuration of a solid-state imaging device according to a modified example;

[0009] Examples of a photodetector and electronic device according to an embodiment of the present disclosure will be described below with reference to FIGS. 1 to 23. The embodiments of the present disclosure will be described in the following order. Note that the present disclosure is not limited to the following examples. Furthermore, the effects described in this specification are merely examples and are not limiting, and other effects may also be present. 1. First embodiment: solid-state imaging device 1-1 Overall configuration of solid-state imaging device 1-2 Configuration of main parts 1-3 Method for forming trench isolation structure 1-4 Voltage application structure 1-5 Modifications 2. Second embodiment: Example of application to electronic device

[0010] 1. First Embodiment 1-1 Overall Configuration of Solid-State Imaging Device A solid-state imaging device 1 (or, more broadly, a "photodetector") according to a first embodiment of the present disclosure will be described. FIG. 1 is a diagram illustrating the overall configuration of the solid-state imaging device 1 according to the first embodiment. The solid-state imaging device 1 of FIG. 1 is a back-illuminated CMOS (Complementary Metal Oxide Semiconductor) image sensor. As shown in FIG. 23, the solid-state imaging device 1 (1002) captures image light (incident light) from a subject via a lens group 1001, converts the amount of incident light focused on the imaging surface into an electrical signal on a pixel-by-pixel basis, and outputs the electrical signal as a pixel signal. As shown in FIG. 1, the solid-state imaging device 1 includes a pixel region 2, a vertical drive circuit 3, a column signal processing circuit 4, a horizontal drive circuit 5, an output circuit 6, and a control circuit 7.

[0011] The pixel region 2 has a plurality of pixels 8 arranged in a two-dimensional array. Each pixel 8 has a plurality of photoelectric conversion units PD (see FIG. 2 ) and a plurality of pixel transistors Tr (e.g., transfer transistors, reset transistors, amplification transistors, and selection transistors). The vertical drive circuit 3 is configured, for example, by a shift register, and sequentially selects each pixel 8 in the pixel region 2 row by row by, for example, sequentially outputting selection pulses to pixel drive wiring 9, and outputs pixel signals of the selected pixels 8 to the column signal processing circuit 4 through vertical signal lines 10. The pixel signals are signals obtained from charges (e.g., electrons) generated in the photoelectric conversion units PD.

[0012] The column signal processing circuits 4 are arranged, for example, for each column of pixels 8, and perform signal processing such as noise removal on signals output from one row of pixels 8 for each pixel column. Examples of signal processing that can be used include correlated double sampling and AD (Analog-Digital) conversion to remove fixed pattern noise specific to pixels. The horizontal drive circuit 5 is configured, for example, with a shift register, and sequentially outputs horizontal scanning pulses to the column signal processing circuits 4, selects the column signal processing circuits 4 in order, and causes the selected column signal processing circuit 4 to output the processed pixel signals to the horizontal signal line 11.

[0013] The output circuit 6 performs various signal processing operations on each pixel signal sequentially output from the column signal processing circuit 4 through the horizontal signal line 11. Examples of signal processing that can be used include various types of digital signal processing such as buffering, black level adjustment, and column variation correction. The control circuit 7 generates clock signals and control signals that serve as references for the operations of the vertical drive circuit 3, the column signal processing circuit 4, the horizontal drive circuit 5, etc., based on a vertical synchronization signal, a horizontal synchronization signal, and a master clock signal (not shown). The control circuit 7 then outputs the generated clock signals and control signals to the vertical drive circuit 3, the column signal processing circuit 4, the horizontal drive circuit 5, etc.

[0014] [1-2 Configuration of Main Parts] Next, the detailed structure of the solid-state imaging device 1 will be described. FIG. 2 is a diagram showing a cross-sectional configuration of the solid-state imaging device 1 when the semiconductor substrate 12 in FIG. 1 is cut along the row direction. As shown in FIG. 2, the solid-state imaging device 1 has a semiconductor substrate 12, and a fixed charge film 13, an insulating film 14, a color filter 15, and an on-chip lens 16 are stacked in this order on the light-receiving surface (hereinafter also referred to as the "back surface S1"; in a broad sense, the "first surface") of the semiconductor substrate 12. In addition, a wiring layer 17 is arranged on the surface (hereinafter also referred to as the "front surface S2"; in a broad sense, the "second surface") of the semiconductor substrate 12 opposite the back surface S1.

[0015] The semiconductor substrate 12 is a substrate made of, for example, silicon (Si). The semiconductor substrate 12 has a photoelectric conversion unit PD formed in each region corresponding to each pixel 8. That is, multiple photoelectric conversion units PD are arranged in a two-dimensional array on the semiconductor substrate 12. The photoelectric conversion unit PD has a p-type semiconductor region and an n-type semiconductor region. The pn junction of these semiconductor regions forms a photodiode, generating charge according to the amount of light received. The photoelectric conversion unit PD accumulates charge (e.g., electrons) generated by photoelectric conversion in the capacitance generated by the pn junction. A p-well region pwell is formed in a region on the surface S2 side of the semiconductor substrate 12. A pixel transistor Tr is formed in the p-well region pwell. The gate electrode 18 of the pixel transistor Tr is disposed on the surface S2 via an insulating film 22.

[0016] Furthermore, trench isolation structures 20 are formed in the semiconductor substrate 12 in all regions between adjacent photoelectric conversion units PD. That is, the trench isolation structures 20 are formed in a lattice pattern in the semiconductor substrate 12 so as to surround each of the multiple photoelectric conversion units PD. The trench isolation structures 20 are formed so as to penetrate the semiconductor substrate 12 from the back surface S1 to the front surface S2 of the semiconductor substrate 12. The trench isolation structures 20 include trench portions 21, as well as an insulating film 22 and a conductor film 23 disposed within the trench portions 21. The trench portions 21 penetrate the semiconductor substrate 12 from the back surface S1 to the front surface S2 of the semiconductor substrate 12, and their inner wall surfaces form the outer shape of the trench isolation structure 20. That is, the trench portions 21 are formed in regions between the photoelectric conversion units PD of the semiconductor substrate 12 and have an opening at least on the back surface S1 side. Furthermore, an insulating film 24 is disposed within the end of the trench portions 21 on the front surface S2 side so as to close the interior of the trench portions 21.

[0017] The insulating film 22 is formed by stacking the fixed charge film 13 and an insulating film 25 other than the fixed charge film 13. That is, the fixed charge film 13 and the insulating film 25 are arranged in this order between the inner wall surface of the trench portion 21 and the conductor film 23, starting from the inner wall surface. The fixed charge film 13 continuously covers the inner wall surface of the trench portion 21, the surface of the insulating film 24 on the back surface S1 side (hereinafter also referred to as the "back surface S3"), and the back surface S1 of the semiconductor substrate 12. The fixed charge film 13 induces holes (positive holes) on the trench isolation structure 20 side of the semiconductor substrate 12, forming a high hole concentration region, thereby realizing pinning of the inner wall surface of the trench portion 21 and suppressing the generation of dark current. The fixed charge film 13 can be made of, for example, a negatively charged high refractive index material film or a high dielectric constant film. Examples of the insulating film 25 include oxides or nitrides containing at least one element selected from the group consisting of hafnium (Hf), aluminum (Al), zirconium (Zr), tantalum (Ta), and titanium (Ti). The insulating film 25 continuously covers the inner wall surfaces of the trench portions 21 covered with the fixed charge film 13 and the back surface S3 of the insulating film 24. The insulating film 25 enables the trench isolation structure 20 to suppress charge transfer from one side to the other between adjacent photoelectric conversion units PD, thereby suppressing color mixing. Silicon oxide (SiO), for example, can be used as the material for the insulating film 25.

[0018] The conductor film 23 is disposed within a space covered by the insulating film 22 within the trench portion 21. The conductor film 23 covers the inner wall surfaces of the trench portion 21 via the insulating film 22 (the fixed charge film 13 and the insulating film 25). Specifically, a portion of the conductor film 23 located on the back surface S1 side (hereinafter also referred to as the "first portion 26") includes a first conductor film 27 covering one of a pair of opposing inner wall surfaces S4, S5 of the trench portion 21, the first conductor film 27 covering one of the pair of inner wall surfaces S4, S5, and a second conductor film 28 covering the other of the pair of opposing inner wall surfaces S4, S5 of the trench portion 21. The first conductor film 27 and the second conductor film 28 are spaced apart from each other in the width direction of the trench portion 21 (the left-right direction in FIG. 2). As a result, the conductor film 23 is not present in the widthwise center of a region (hereinafter also referred to as the "first region 29") on the back surface S1 side of the trench portion 21, forming a slit-shaped void 30 with a constant width extending in the thickness direction of the semiconductor substrate 12. The thickness t1 of the first conductor film 27 in the width direction of the trench portion 21 and the thickness t2 of the second conductor film 28 in the width direction of the trench portion 21 are formed to be the same. In addition, the ends (upper ends in FIG. 2 ) of the insulating film 25, the first conductor film 27, and the second conductor film 28 on the back surface S1 side are formed closer to the front surface S2 side (lower side in FIG. 2 ) than the surface of the fixed charge film 13 on the insulating film 14 side (hereinafter also referred to as the "back surface S6"). As a result, a slit-shaped void 31 extending in the width direction of the trench portion 21 is formed on the insulating film 14 side of the first region 29.

[0019] Furthermore, a portion of the conductor film 23 on the surface S2 side (hereinafter also referred to as the "second portion 32") has a blocking portion 33 that blocks the interior of the trench portion 21. The blocking portion 33 is a space in a region on the surface S2 side of the interior region of the trench portion 21 (hereinafter also referred to as the "second region 34"), and is arranged without any gaps via the insulating film 22 in a space surrounded by the inner wall surfaces S4 and S5 of the trench portion 21 and the back surface S3 of the insulating film 24. That is, the fixed charge film 13 and the insulating film 25 cover the end of the blocking portion 33 on the surface S2 side. The thickness t3 of the blocking portion 33 in the thickness direction of the semiconductor substrate 12 is, for example, 10 nm or more, preferably 20 nm or more, and more preferably 30 nm or more. Furthermore, for example, it is larger than the thickness t1 (= t2) of the first conductor film 27. Furthermore, the upper limit of the thickness t1 is, for example, 1 μm or less, preferably 900 nm or less, and more preferably 800 nm or less. Also, for example, it is set to be equal to or less than ¼ of the thickness of the semiconductor substrate 12. As the material of the conductor film 23, for example, amorphous silicon BDAS doped with boron (B) or polysilicon B-poly doped with boron (B) can be used.

[0020] Furthermore, the conductive film 23 located on the outer periphery of the pixel region 2 is electrically connected to a negative bias voltage supply source by a voltage application structure (see FIG. 11 ) described later, and a negative bias voltage is applied to the conductive film 23. The negative bias voltage is transmitted from the outside to the center of the pixel region 2 via the second portion 32 of the conductive film 23, and is applied to the conductive film 23 located in each part of the pixel region 2. Furthermore, the conductive film 23 to which the negative bias voltage is applied can make the periphery of the trench isolation structure 20 (i.e., the region in contact with the sidewall of the trench isolation structure 20) a high hole concentration state via the first conductive film 27 and the second conductive film 28, thereby suppressing the generation of dark current.

[0021] The insulating film 14 continuously covers the rear surface S6 of the fixed charge film 13. Examples of materials that can be used for the insulating film 14 include silicon oxide (SiO2) and silicon nitride (SiN). The color filters 15 are arranged in a two-dimensional array, with one color filter 15 corresponding to one photoelectric conversion unit PD. Each color filter 15 transmits light of a predetermined wavelength and allows the transmitted light to enter the photoelectric conversion unit PD. The color filters 15 may be arranged in a Bayer array, for example. Waveguide walls 47 and inter-pixel light-shielding films 48 may be disposed between the color filters 15. The on-chip lenses 16 are arranged in a two-dimensional array, with one on-chip lens 16 corresponding to one photoelectric conversion unit PD. The on-chip lenses 16 collect light from a subject and direct the collected light through the color filters 15 to the photoelectric conversion unit PD. The wiring layer 17 has an interlayer insulating film (not shown) and wiring (not shown) stacked in multiple layers with the interlayer insulating film interposed therebetween, and drives the pixel transistors of each pixel 8 via the multiple layers of wiring.

[0022] In the solid-state imaging device 1 having the above configuration, when light is incident from the back surface S1 side of the semiconductor substrate 12, the incident light passes through the on-chip lens 16 and undergoes photoelectric conversion in the photoelectric conversion unit PD, generating charges (e.g., electrons). The generated charges are then output as pixel signals from the vertical signal lines 10 (see FIG. 1 ) formed by the wiring of the wiring layer 17. For example, if the conductor film 23 is tightly arranged inside the trench portion 21 as shown in FIG. 3 , the conductor film 23 in the trench portion 21 may absorb light, reducing the amount of incident light photoelectrically converted by the photoelectric conversion unit PD and potentially reducing the quantum efficiency Qe. Consider a configuration in which the thickness of the conductor film 23 is reduced and the volume of the conductor film 23 is reduced to suppress light absorption by the conductor film 23, as shown in FIG. 4 . In this case, the reduction in the volume of the conductive film 23 increases the resistance of the transmission path for the negative bias voltage from the outside to the center of the pixel region 2, and the increase in resistance may cause an IR drop or an RC delay in the negative bias voltage. Therefore, the negative bias voltage applied to the center of the pixel region 2 may decrease, and the dark current may worsen in the center of the pixel region 2.

[0023] In contrast, in the solid-state imaging device 1 according to the first embodiment, as shown in FIG. 2 , the portion of the conductor film 23 on the back surface S1 side (first portion 26) includes a first conductor film 27 covering one of a pair of opposing inner wall surfaces S4, S5 of the trench portion 21, and a second conductor film 28 spaced apart from the first conductor film and covering the other inner wall surface S5 of the pair of inner wall surfaces. Furthermore, the portion of the conductor film 23 on the front surface S2 side (second portion 32) includes a blocking portion 33 that blocks the interior of the trench portion 21. This reduces the volume of the conductor film 23 on the back surface S1 side, thereby suppressing absorption of incident light by the conductor film 23 within the trench portion 21. This increases the amount of incident light photoelectrically converted by the photoelectric conversion unit PD, thereby suppressing a decrease in quantum efficiency Qe. Furthermore, it is possible to increase the volume of the conductor film 23 on the surface S2 side where incident light is absorbed by the photoelectric conversion unit PD and is difficult to reach, thereby suppressing an increase in the resistance value of the transmission path of the negative bias voltage from the outside to the center of the pixel region 2. This makes it possible to suppress the IR drop and RC delay of the negative bias voltage caused by the resistance component of the transmission path, and to suppress the generation of dark current in the center of the pixel region 2.

[0024] [1-3 Method for Forming Trench Isolation Structure] Next, a method for forming the trench isolation structure 20 shown in FIG. 2 will be described. First, as shown in FIG. 5, a trench portion 21 is formed in the front surface S2 of the semiconductor substrate 12. Next, polysilicon 35 and an insulating film 24 are embedded inside the trench portion 21. Next, as shown in FIG. 6, a wiring layer 17 is formed on the front surface S2 side of the semiconductor substrate 12. Next, a polishing process such as CMP (Chemical Mechanical Polishing) is performed on the rear surface S1 of the semiconductor substrate 12 to expose the polysilicon 35 and the trench portion 21 on the rear surface S1. Next, as shown in FIG. 7, after removing the polysilicon 35, a fixed charge film 13 is formed so as to continuously cover the inner wall surface of the trench portion 21, the rear surface S3 of the insulating film 24, and the rear surface S1 of the semiconductor substrate 12.

[0025] Next, as shown in FIG. 8 , an insulating film 25 is formed to continuously cover the inner wall surfaces of the trench portion 21 covered with the fixed charge film 13 and the back surface S3 of the insulating film 24. The insulating film 25 is formed using a low-temperature process such as atomic layer deposition (ALD). Next, as shown in FIG. 9 , a conductor film 23 is formed in the space inside the trench portion 21 covered with the insulating film 25. The conductor film 23 is formed so as to fill the second region 34 of the trench portion 21 without any gaps, cover each of the pair of opposing inner wall surfaces of the first region 29 of the trench portion 21, and leave a gap 30 in the center of the first region 29 in the width direction. The conductor film 23 is formed using, for example, chemical vapor deposition (CVD). The conductor film 23 is made of, for example, BDAS. Here, the BDAS is formed at a temperature of 400° C. By this procedure, the trench portion 21, the fixed charge film 13, the insulating film 25, and the conductor film 23 are formed in this order, thereby forming the trench isolation structure 20 shown in FIG.

[0026] For example, if the procedure shown in FIG. 5 were to be used to deposit and embed the conductor film 23 instead of the polysilicon 35, a heat treatment performed before the formation of the wiring layer 17 could potentially cause boron (B) to diffuse from the material of the conductor film 23 (e.g., BDAS, B-poly) into the photoelectric conversion unit PD. This could reduce the volume of the n-type semiconductor region of the photoelectric conversion unit PD and decrease the saturation charge Qs of the photoelectric conversion unit PD. Furthermore, for example, if the above procedure were used, the material of the conductor film 23 (e.g., BDAS, B-poly) could migrate due to heat, changing the shape of the void 30 from a slit shape to an elliptical shape (void structure), as shown in FIG. 10, resulting in areas of the inner wall surface of the trench portion 21 where the conductor film 23 is absent. This could prevent a negative bias voltage from being applied to the inner wall surface of the trench portion 21 where the conductor film 23 is absent, potentially worsening the dark current. Furthermore, for example, in the above-described procedure, if BDAS is used as the material for the conductor film 23, the heat of the heat treatment may cause the BDAS to change into polysilicon, which may increase the volume of the BDAS (conductor film 23) and increase the warpage of the wafer.

[0027] In contrast, in the method for forming the trench isolation structure 20 according to the first embodiment, after forming the wiring layer 17, the conductive film 23 is formed inside the trench portion 21 from the back surface S1 side of the semiconductor substrate 12. This prevents the heat from a heat treatment (e.g., a heat treatment for repairing damage caused by the formation of the trench portion 21) performed before the formation of the wiring layer 17 from acting on the conductive film 23, thereby preventing boron (B) diffusion from the material (BDAS, B-poly) of the conductive film 23 to the photoelectric conversion portion PD. This prevents a decrease in the saturated charge Qs of the photoelectric conversion portion PD. Furthermore, because the heat from the heat treatment does not act on the conductive film 23, migration of the material of the conductive film 23 is prevented, and deformation of the conductive film 23 is suppressed. This allows a negative bias voltage to be appropriately applied to the inner wall surface of the trench portion 21, thereby appropriately suppressing the generation of dark current. Furthermore, since the heat from the heat treatment does not act on the conductive film 23, it is possible to prevent the material of the conductive film 23 (BDAS) from being converted into polysilicon by the heat treatment, which prevents an increase in the volume of the BDAS (conductive film 23) and an increase in the warpage of the wafer.

[0028] [1-4 Voltage Application Structure] Next, a structure for applying a negative bias voltage to the conductor film 23 (hereinafter also referred to as a "voltage application structure") will be described. Fig. 11 is a diagram showing a cross-sectional configuration of the voltage application structure. Note that in Fig. 11, the configuration of the solid-state imaging device 1 is partially changed from the configuration shown in Fig. 2, but a similar voltage application structure can also be applied to the solid-state imaging device 1 shown in Fig. 2. Furthermore, a similar voltage application structure can also be used for the solid-state imaging device 1 according to a modified example described below.

[0029] FIG. 11 illustrates an example of a solid-state imaging device 1 having a first substrate 100, a second substrate 200, and a third substrate 300 stacked in this order from the light incident surface side of the solid-state imaging device 1. The first substrate 100 includes a semiconductor substrate 12 having a transfer transistor 36 that transfers charges photoelectrically converted by the photoelectric conversion unit PD and a floating diffusion FD (broadly speaking, a "charge storage unit") that accumulates the charges transferred by the transfer transistor 36. The second substrate 200 includes a pixel transistor 37 that reads out the charges accumulated in the floating diffusion FD. Examples of the pixel transistor 37 that reads out the charges include a reset transistor, an amplification transistor, and a selection transistor. The third substrate 300 includes a logic circuit that processes pixel signals obtained from the charges read out by the second substrate 200. Examples of the logic circuit include a vertical drive circuit 3, a column signal processing circuit 4, a horizontal drive circuit 5, an output circuit 6, and a control circuit 7 (see FIG. 1).

[0030] 11, the semiconductor substrate 12 has a p-type semiconductor region 38 formed between the trench portion 21 and the photoelectric conversion portion PD so as to cover the sidewall surface of the trench isolation structure 20. The p-type semiconductor region 38 is formed continuously from the back surface S1 to the front surface S2 of the semiconductor substrate 12. This increases the hole concentration around the trench isolation structure 20, thereby further suppressing the generation of dark current. The p-type semiconductor region 38 is formed, for example, by doping the inner wall surface of the trench portion 21 with boron (B) or the like after the trench portion 21 is formed. Also, in FIG. 11, the insulating film 25 and void 31 inside the trench portion 21 are omitted, and the conductor film 23 is formed up to the back surface S1 of the semiconductor substrate 12.

[0031] As shown in FIG. 11 , the pixel region 2 includes an effective pixel region 39, a light-shielding pixel region 40 located around the effective pixel region 39, and a negative bias region 41 located around the light-shielding pixel region 40. The on-chip lens 16 and the color filter 15 are omitted from the light-shielding pixel region 40. As shown in FIG. 12 , the negative bias region 41 omits not only the on-chip lens 16 and the color filter 15, but also various structures for acquiring pixel signals (e.g., the on-chip lens 16, the color filter 15, the insulating film 14, the fixed charge film 13, the photoelectric conversion unit PD, the transfer transistor 36, the floating diffusion FD, the pixel transistor Tr, 37, etc.). FIG. 12 is an enlarged view of the negative bias region 41. In the negative bias region 41, a side contact 42 is formed at the end of the trench portion 21 on the surface S2 side. That is, the inside of the trench portion 21 is configured such that, from the surface S2 side of the semiconductor substrate 12, the side contact 42, the insulating film 24, the insulating film 22, and the conductor film 23 are stacked in this order. The side contacts 42 are formed without gaps inside the trench portion 21 and are electrically connected to each of the p-type semiconductor regions 38 located on the inner wall surface of the trench portion 21. The side contacts 42 may be made of, for example, doped polysilicon doped with boron (B). The side contacts 42 also protrude from the inside of the trench portion 21 toward the second substrate 200. The end of the side contact 42 on the second substrate 200 side is electrically connected to a contact via 43. The contact via 43 extends from the second substrate 200 toward the first substrate 100 and is electrically connected to a negative bias voltage supply source (not shown). As a result, the side contacts 42 transmit a negative bias voltage in the order of the contact via 43, the side contact 42, and the p-type semiconductor region 38.

[0032] Furthermore, a light-shielding metal film 44 is disposed on the back surface S1 side of the semiconductor substrate 12 in the light-shielding pixel region 40 and the negative bias region 41. The light-shielding metal film 44 blocks light from entering the photoelectric conversion unit PD in the light-shielding pixel region 40, allowing the pixels 8 in the light-shielding pixel region 40 to function as OPB pixels (pixels used for black level adjustment). Here, the insulating film 14 is omitted from the back surface S1 side of the semiconductor substrate 12 in the negative bias region 41, and the back surface S1 side is further dug down by etching or the like, exposing the p-type semiconductor region 38 and the conductor film 23 on the back surface S1 of the semiconductor substrate 12. Therefore, in the negative bias region 41, the light-shielding metal film 44 is disposed on the back surface S1 of the semiconductor substrate 12 and is electrically connected to the p-type semiconductor region 38 and the conductor film 23 exposed on the back surface S1 of the semiconductor substrate 12. As a result, the light-shielding metal film 44 transmits a negative bias voltage in the order of the p-type semiconductor region 38 → the light-shielding metal film 44 → the conductor film 23. For example, tungsten (W), aluminum (Al), or copper (Cu) can be used as the material of the light-shielding metal film 44. With the above configuration, a voltage application structure for applying a negative bias voltage to the conductor film 23 is formed, and the negative bias voltage is transmitted in the following order: negative bias voltage supply source → contact via 43 → side contact 42 → p-type semiconductor region 38 → light-shielding metal film 44 → conductor film 23.

[0033] Here, when a method for forming the trench isolation structure 20 is adopted in which the conductor film 23 is formed inside the trench portion 21 from the back surface S1 side of the semiconductor substrate 12 as shown in FIGS. 5 to 9 , the contact 45 (see FIG. 13 ) cannot be disposed directly below the conductor film 23. For example, if the contact 45 is formed directly below the conductor film 23, the contact 45 (e.g., doped polysilicon) would be removed together with the polysilicon 35 in the process of removing the polysilicon 35 shown in FIG. 6 . Therefore, the contact 45 cannot be used as a voltage application structure for applying a negative bias voltage. In contrast, the voltage application structure according to the first embodiment is configured to apply a negative bias voltage to the conductor film 23 via the side contact 42, the p-type semiconductor region 38, and the light-shielding metal film 44. Furthermore, the side contact 42 has an insulating film 24 between it and the insulating film 22 and conductor film 23 inside the trench portion 21. Therefore, the side contact 42 is protected by the insulating film 24 and is not removed together with the polysilicon 35 in the process of removing the polysilicon 35 shown in FIG. 6 .

[0034] [1-5 Modifications] (1) In the first embodiment, an example was shown in which a BDAS film or a B-poly film was used as the conductor film 23. However, other configurations may also be employed. For example, as shown in FIG. 14 , a transparent electrode film may be used as the conductor film 23. For example, an ITO (indium tin oxide) film may be used as the transparent electrode film. Here, the light absorption rate of an ITO film is lower than that of a BDAS film or a B-poly film. Therefore, compared to when a BDAS film or the like is used, for example, absorption of incident light by the conductor film 23 can be suppressed, and a decrease in quantum efficiency Qe can be suppressed. Furthermore, for example, as shown in FIG. 15 , a metal film may be used as the conductor film 23. For example, tungsten (W), aluminum (Al), or copper (Cu) may be used as the metal film. Here, the resistivity of the metal film is lower than that of a BDAS film, a B-poly film, or an ITO film. Therefore, for example, compared to when a BDAS film or the like is used, the IR drop and RC delay of the negative bias voltage can be suppressed, and the generation of dark current in the center of the pixel region 2 can be suppressed.

[0035] (2) Although the first embodiment illustrates an example in which a single-layer film is used as the conductor film 23, other configurations may also be employed. For example, as shown in FIG. 16 , a multilayer film may be used in which a transparent conductor film 50 and a conductor film other than the transparent conductor film 50 (hereinafter, also referred to as a "second conductor film 51") are stacked. FIG. 16 illustrates an example in which the second conductor film 51 and the transparent conductor film 50 are stacked in this order from the inner wall surface side of the trench portion 21. For example, a BDAS film and a B-poly film may be used as the second conductor film 51. This allows the second conductor film 51 (BDAS film, B-poly film) to be made thinner by the thickness of the transparent conductor film 50. Therefore, for example, compared to using a single-layer BDAS film or a single-layer B-poly film as the conductor film 23, absorption of incident light by the second conductor film 51 (BDAS film, B-poly film) can be suppressed, thereby suppressing a decrease in quantum efficiency Qe. Furthermore, for example, by increasing the thickness of the transparent conductor film 50, it is possible to suppress the IR drop and RC delay of the negative bias voltage, and to suppress the generation of dark current in the center of the pixel region 2.

[0036] (3) In the first embodiment, the insulating film 22 is configured by stacking the fixed charge film 13 and the insulating film 25. However, other configurations may be employed. For example, as shown in FIG. 17 , the insulating film 22 may be configured by only the fixed charge film 13. That is, the insulating film 22 is configured such that only the fixed charge film 13 is disposed between the inner wall surface of the trench portion 21 and the conductive film 23. This allows the insulating film 22 to be made thinner, thereby reducing the distance between the conductive film 23 and the peripheral portion of the trench isolation structure 20 where a high hole concentration is desired (hereinafter also referred to as the "periphery"). This allows the hole concentration in the peripheral portion to be increased, thereby further suppressing the generation of dark current.

[0037] (4) In the first embodiment, the insulating film 25 has a constant thickness. However, other configurations may be employed. For example, as shown in FIG. 18 , the thickness t4 of the portion of the insulating film 25 covering the end 46 on the surface S2 side of the blocking portion 33 may be made larger than the thickness t5 of the portion of the insulating film 25 covering the inner wall surface of the trench portion 21. This increases the distance between the floating diffusion FD in the p-well region pwell and the conductor film 23, thereby reducing the effect of a negative bias voltage applied to the conductor film 23 on the floating diffusion FD.

[0038] (5) Although the first embodiment illustrates an example in which an on-chip lens 16 is formed for each photoelectric conversion unit PD, other configurations may also be employed. For example, as shown in FIG. 19 , a configuration may be employed in which multiple shared on-chip lenses 16 are formed for each block of m*n photoelectric conversion units PD arranged in an m×n array (one of m and n is an integer greater than or equal to 2, and the other is an integer greater than or equal to 1). FIG. 19 illustrates an example in which a block is formed of four photoelectric conversion units PD arranged in a 2×2 array. In this case, the color filters 15 are also formed as shared lenses for each block. By making the on-chip lenses 16 and the color filters 15 shared, a phase difference signal can be obtained from the pixel signals of the four photoelectric conversion units PD. In this configuration, the trench isolation structure 20 surrounding the block and the trench isolation structure 20 between each photoelectric conversion unit PD within the block each have the same structure (the structure of the fixed charge film 13, the insulating film 25, and the conductor film 23) as the trench isolation structure 20 of the first embodiment.

[0039] (6) Although the first embodiment illustrates an example in which each pixel 8 has one photoelectric conversion unit PD, other configurations may also be employed. For example, as shown in FIGS. 20 and 21 , each pixel 8 may have two photoelectric conversion units PD1 and PD2. This results in a configuration similar to the configuration shown in FIG. 19 , in which multiple shared on-chip lenses 16 are formed for each block of two photoelectric conversion units PD1 and PD2 arranged in a 1×2 array. This allows a phase difference signal to be obtained from the pixel signals of the two photoelectric conversion units PD1 and PD2. FIG. 21 is a cross-sectional view of the solid-state imaging device 1 taken along line A-A in FIG. 20 . 19 and 20 , when the configuration in which the m*n photoelectric conversion units PD have the shared on-chip lens 16 is adopted, as shown in FIG. 21 , the trench unit 21 may have a first trench unit 52 surrounding the peripheries of the m*n photoelectric conversion units PD1 and PD2 (two in FIG. 21 ), and a second trench unit 53 located between the photoelectric conversion units PD1 and PD2 in the region surrounded by the first trench unit 52, and the second trench unit 53 may be a protrusion 54 protruding from the first trench unit 52 into the region between the two adjacent photoelectric conversion units PD1 and PD2. In such a configuration, the trench isolation structure 20 (including the first trench unit 52) ​​surrounding the pixel 8 and the trench isolation structure 20 (including the second trench unit 53) between the photoelectric conversion units PD1 and PD2 in the pixel 8 each have a structure similar to that of the trench isolation structure 20 of the first embodiment.

[0040] (7) In the first embodiment, an example was shown in which the gap 30 (air) was provided between the first conductor film 27 and the second conductor film 28. However, other configurations may also be employed. For example, a configuration may be adopted in which a film other than the conductor film 23 is disposed in the space between the first conductor film 27 and the second conductor film 28. An example of the film other than the conductor film 23 is a film having a lower light absorption rate than the conductor film 23.

[0041] (8) In the first embodiment, the electrical connection between the conductor film 23 and the light-shielding metal film 44 in the negative bias region 41 is made only at the end of the conductor film 23 on the light-shielding metal film 44 side. However, other configurations may be adopted. For example, as shown in FIG. 22 , the negative bias region 41 may have a back electrode 55 that protrudes from the light-shielding metal film 44 into the space between the first conductor film 27 and the second conductor film 28 and blocks the interior of that space. The back electrode 55 is disposed without gaps in the space between the first conductor film 27 and the second conductor film 28. This allows for more appropriate electrical connection between the conductor film 23 and the light-shielding metal film 44, improving contact. The back electrode 55 is formed of the same material as the light-shielding metal film 44 and is integrated with the light-shielding metal film 44.

[0042] (9) Furthermore, the present technology can be applied to photodetection devices in general, including distance measurement sensors that measure distance, also known as time-of-flight (ToF) sensors, in addition to the solid-state imaging device 1 as the image sensor described above. A distance measurement sensor emits light toward an object, detects the light reflected from the surface of the object, and calculates the distance to the object based on the time of flight between when the light is emitted and when the reflected light is received. The light-receiving pixel structure of this distance measurement sensor can employ the structure of pixel 8 described above.

[0043] 2. Second Embodiment The technology according to the present disclosure (the present technology) may be applied to various electronic devices. Fig. 23 is a diagram showing an example of a schematic configuration of an imaging device (digital still camera, video camera, etc.) as an electronic device to which the present technology is applied. As shown in Fig. 23 , the imaging device 1000 includes a lens group 1001, a solid-state imaging device 1002 (solid-state imaging device 1 according to the first embodiment), a signal processing circuit 1003, a memory 1004, and a monitor 1005. The signal processing circuit 1003, the memory 1004, and the monitor 1005 are connected to each other via a bus line 1006.

[0044] The lens group 1001 guides incident light (image light) from a subject to the solid-state imaging device 1002, forming an image on the light-receiving surface (pixel region) of the solid-state imaging device 1002. The solid-state imaging device 1002 is composed of the CMOS image sensor of the first embodiment described above. The solid-state imaging device 1002 converts the amount of incident light imaged on the light-receiving surface by the lens group 1001 into an electrical signal on a pixel-by-pixel basis and supplies the pixel signal to the signal processing circuit 1003. The signal processing circuit 1003 then performs predetermined image processing on the pixel signal supplied from the solid-state imaging device 1002. The signal processing circuit 1003 then stores the processed image signal in a memory 1004 and displays an image of the subject on a monitor 1005 based on the image signal. The memory 1004 is composed of a flash memory or the like. The monitor 1005 is composed of a display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel.

[0045] Note that the electronic device to which the solid-state imaging device 1 can be applied is not limited to the imaging device 1000, but can also be applied to other electronic devices. Also, although the solid-state imaging device 1 according to the first embodiment is used as the solid-state imaging device 1002, other configurations may also be adopted. For example, a configuration may be adopted in which other photodetection devices to which the present technology is applied, such as the solid-state imaging device 1 according to the modifications (1) to (8) of the first embodiment, are used.

[0046] The present technology can also be configured as follows: (1) A photodetector including: a semiconductor substrate having a first surface that is a light-receiving surface and a second surface opposite to the first surface; a plurality of photoelectric conversion units formed in a two-dimensional array on the semiconductor substrate; trench portions formed in regions of the semiconductor substrate between the photoelectric conversion units and having openings at least on the first surface side; and a conductor film disposed inside the trench portion and to which a negative bias voltage is applied, wherein a first portion of the conductor film that is on the first surface side has a first conductor film that covers one of a pair of opposing inner wall surfaces of the trench portion and a second conductor film that is spaced from the first conductor film and covers the other of the pair of inner wall surfaces, and a second portion that is on the second surface side has a blocking portion that blocks the interior of the trench portion. (2) The photodetector according to (1), wherein the conductor film is a transparent electrode film. (3) The photodetector according to (1) or (2), wherein the conductor film is a metal film. (4) The photodetector according to (1), wherein the conductor film is a multilayer film formed by stacking a transparent conductor film and a conductor film other than the transparent conductor film. (5) The photodetector according to any one of (1) to (4), wherein a fixed charge film having a negative charge and an insulating film are arranged in this order from the inner wall surface side between the inner wall surface of the trench portion and the conductor film. (6) The photodetector according to (5), wherein the fixed charge film and the insulating film cover the end of the blocking portion on the second surface side, and the thickness of the portion of the insulating film covering the end of the blocking portion on the second surface side is greater than the thickness of the portion of the insulating film covering the inner wall surface of the trench portion. (7) The photodetector according to any one of (1) to (4), wherein only a fixed charge film having a negative charge is arranged between the inner wall surface of the trench portion and the conductor film. (8) The photodetector according to any one of (1) to (7), further comprising a plurality of shared on-chip lenses formed for each of m*n blocks of the photoelectric conversion units arranged in an m×n array (one of m and n is an integer of 2 or more, and the other is an integer of 1 or more).(9) The photodetector according to any one of (1) to (9), wherein the trench portion has a first trench portion surrounding the periphery of the m*n photoelectric conversion portions and a second trench portion located between the photoelectric conversion portions in the region surrounded by the first trench portion, and the second trench portion is a protrusion protruding from the first trench portion into a region between two adjacent photoelectric conversion portions. (10) The photodetector according to any one of (1) to (9), wherein the semiconductor substrate has a transfer transistor that transfers charges photoelectrically converted in the photoelectric conversion portions and a charge accumulation portion that accumulates the charges transferred by the transfer transistor, and the photodetector comprises: a first substrate having the semiconductor substrate; and a second substrate stacked on the first substrate, the second substrate having a pixel transistor that reads out charges accumulated in the charge accumulation portion of the semiconductor substrate. (11) The photodetector according to any one of (1) to (10), comprising: a p-type semiconductor region formed between the trench portion and the photoelectric conversion portion; and a light-shielding metal film disposed on the first surface side of the semiconductor substrate in a region located around an effective pixel region, the light-shielding metal film electrically connecting the p-type semiconductor region and the conductor film. (12) The photodetector according to (11), comprising: a side contact formed at an end of the trench portion on the second surface side in a region located around the effective pixel region, the side contact being electrically connected to the p-type semiconductor region. (13) The photodetector according to (11) or (12), comprising: a back electrode protruding from the light-shielding metal film into a space between the first conductor film and the second conductor film in a region located around the effective pixel region, the back electrode blocking the interior of the space.(14) An electronic device comprising: a semiconductor substrate having a first surface that is a light-receiving surface and a second surface opposite to the first surface; a plurality of photoelectric conversion units formed in a two-dimensional array on the semiconductor substrate; trench portions formed in regions of the semiconductor substrate between the photoelectric conversion units and having openings on at least the first surface side; and a conductor film disposed inside the trench portion and to which a negative bias voltage is applied, wherein the first portion of the conductor film that is on the first surface side has a first conductor film that covers one of a pair of opposing inner wall surfaces of the trench portion and a second conductor film that is spaced from the first conductor film and covers the other inner wall surface of the pair of inner wall surfaces, and the second portion that is on the second surface side has a blocking portion that blocks the inside of the trench portion.

[0047] 1...solid-state imaging device, 2...pixel region, 3...vertical drive circuit, 4...column signal processing circuit, 5...horizontal drive circuit, 6...output circuit, 7...control circuit, 8...pixel, 9...pixel drive wiring, 10...vertical signal line, 11...horizontal signal line, 12...semiconductor substrate, 13...fixed charge film, 14...insulating film, 15...color filter, 16...on-chip lens, 17...wiring layer, 18...gate electrode, 20...trench isolation structure, 21...trench portion, 22...insulating film, 23...conductor film, 24...insulating film, 25...insulating film, 26...first portion, 27...first conductor film, 28...second conductor film, 29...first Region, 30...gap, 31...gap, 32...second portion, 33...blocking portion, 34...second region 34, 35...polysilicon, 36...transfer transistor, 37...pixel transistor, 38...semiconductor region, 39...effective pixel region, 40...light-shielding pixel region, 41...negative bias region, 42...side contact, 43...contact via, 44...light-shielding metal film, 45...contact, 50...transparent conductor film, 51...second conductor film, 52...first trench portion, 53...second trench portion, 54...protrusion portion, 55...rear electrode, 100...first substrate, 200...second substrate, 300...third substrate

Claims

1. A photodetector comprising: a semiconductor substrate having a first surface which is a light receiving surface and a second surface opposite to the first surface; a plurality of photoelectric conversion units formed in a two-dimensional array on the semiconductor substrate; a trench portion formed in an area of ​​the semiconductor substrate between the photoelectric conversion units and having an opening on at least the first surface side; and a conductor film disposed inside the trench portion and to which a negative bias voltage is applied, wherein a first portion of the conductor film which is on the first surface side has a first conductor film covering one of a pair of opposing inner wall surfaces of the trench portion, and a second conductor film spaced from the first conductor film covering the other of the pair of inner wall surfaces, and a second portion which is on the second surface side has a blocking portion which blocks the inside of the trench portion.

2. The photodetector according to claim 1, wherein the conductive film is a transparent electrode film.

3. The photodetector according to claim 1, wherein the conductive film is a metal film.

4. The photodetector according to claim 1, wherein the conductive film is a multi-layer film in which a transparent conductive film and a conductive film other than the transparent conductive film are laminated.

5. The photodetector according to claim 1, wherein a fixed charge film having a negative charge and an insulating film are disposed in this order from the inner wall side between the inner wall surface of the trench portion and the conductive film.

6. The photodetector according to claim 5, wherein the fixed charge film and the insulating film cover the end of the blocking portion on the second surface side, and the thickness of the portion of the insulating film covering the end of the blocking portion on the second surface side is greater than the thickness of the portion of the insulating film covering the inner wall surface of the trench portion.

7. The photodetector according to claim 1, wherein only a fixed charge film having a negative charge is disposed between the inner wall surface of the trench portion and the conductive film.

8. The photodetector according to claim 1, comprising a plurality of shared on-chip lenses formed for each block of m*n photoelectric conversion units arranged in an m×n array (one of m and n is an integer of 2 or more, and the other is an integer of 1 or more).

9. The photodetector device of claim 8, wherein the trench portion has a first trench portion surrounding the m*n photoelectric conversion portions and a second trench portion located between the photoelectric conversion portions within the area surrounded by the first trench portion, and the second trench portion is a protrusion protruding from the first trench portion into a region between two adjacent photoelectric conversion portions.

10. The photodetection device according to claim 1, wherein the semiconductor substrate has a transfer transistor that transfers charges photoelectrically converted by the photoelectric conversion section and a charge accumulation section that accumulates the charges transferred by the transfer transistor, and the photodetection device further comprises: a first substrate having the semiconductor substrate; and a second substrate having pixel transistors that read out charges accumulated in the charge accumulation section of the semiconductor substrate and stacked on the first substrate.

11. The photodetector according to claim 1, comprising: a p-type semiconductor region formed between the trench portion and the photoelectric conversion portion; and a light-shielding metal film disposed on the first surface side of the semiconductor substrate in a region surrounding an effective pixel region, electrically connecting the p-type semiconductor region and the conductor film.

12. The photodetector according to claim 11, further comprising a side contact formed at an end of the trench portion on the second surface side in a region located around the effective pixel region and electrically connected to the p-type semiconductor region.

13. The photodetector according to claim 11, further comprising a back electrode that protrudes from the light-shielding metal film into the space between the first conductor film and the second conductor film in a region located around the effective pixel region and blocks the inside of the space.

14. An electronic device comprising a photodetector comprising: a semiconductor substrate having a first surface which is a light receiving surface and a second surface opposite to the first surface; a plurality of photoelectric conversion units formed in a two-dimensional array on the semiconductor substrate; a trench portion formed in a region of the semiconductor substrate between the photoelectric conversion units and having an opening on at least the first surface side; and a conductor film disposed inside the trench portion and to which a negative bias voltage is applied, wherein a first portion of the conductor film which is on the first surface side has a first conductor film covering one of a pair of opposing inner wall surfaces of the trench portion, and a second conductor film spaced from the first conductor film and covering the other of the pair of inner wall surfaces, and wherein a second portion which is on the second surface side has a blocking portion which blocks the inside of the trench portion.

Images