Power semiconductor device and method for manufacturing power semiconductor device

By forming an oxide film on copper wiring within power semiconductor devices and covering it with hard resin, the bonding strength between copper and resin is enhanced, addressing peeling issues and maintaining low contact resistance.

WO2025074931A1PCT designated stage expired Publication Date: 2025-04-10MINEBEA POWER SEMICON DEVICE INC
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Patent Information

Application Number
PCT/JP2024/034319
Authority / Receiving Office
WO · WO
Patent Type
Applications
Current Assignee / Owner
Priority Date
2023-10-04
Filing Date
2024-09-26
Publication Date
2025-04-10

AI Technical Summary

Technical Problem

Power semiconductor devices sealed with hard resins, such as epoxy resin, experience peeling from copper wiring due to thermal stress during temperature cycling, leading to excessive stress on semiconductor chips and potential cracking.

Method used

Forming an oxide film with a thickness of 15 to 100 nm on the surface of the copper wiring and covering it with hard resin, while ensuring no oxide film is formed on areas where solder bonding or ultrasonic welding occurs, to enhance bonding strength and prevent contact resistance issues.

Benefits of technology

The proposed solution significantly increases the bonding strength between the hard resin and copper, preventing peeling and excessive stress on semiconductor chips, while maintaining low contact resistance during busbar mounting.

✦ Generated by Eureka AI based on patent content.

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Abstract

The present invention increases adhesive strength between copper and a hard resin and prevents increase in contact resistance during attachment of a bus bar. For that purpose, a power semiconductor device (7) comprises: an insulating substrate (1); a case 3 that houses the insulating substrate (1); copper wiring (11) formed on the insulating substrate (1); a semiconductor chip (42) connected to the copper wiring (11); and copper terminals (31) that reach the upper end of the case (3). The copper wiring (11) and the copper terminals (31) are bonded. Nuts (32) provided to a constituent member of the case (3) are in contact with the copper terminals (31). An oxide film having a thickness of 15-100 nm is formed on the surface of the copper wiring (11).
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Description

Power semiconductor device and method for manufacturing the same

[0001] The present invention relates to a power semiconductor device and a method for manufacturing a power semiconductor device.

[0002] With the recent trend toward electromechanical integration, the demands for earthquake resistance and heat resistance in power semiconductor devices are becoming stricter. As a result, hard resins are being considered as the encapsulant for power semiconductor device packages, replacing the conventional gel.

[0003] JP 2017-010985 A

[0004] When a power semiconductor device encapsulated with hard resin undergoes a temperature cycle test, thermal stress causes the hard resin (epoxy resin) to peel off from the copper wiring on the insulating substrate. The peeling of the epoxy resin from the copper wiring progresses gradually with the number of temperature cycles. A semiconductor chip is mounted on the copper wiring, and when the peeling reaches the semiconductor chip, excessive stress is generated in the semiconductor chip, causing the chip to crack. One solution is to increase the adhesive strength between the copper and the epoxy resin. One method for increasing the adhesive strength between copper and the epoxy resin is to oxidize the copper surface. Patent Document 1 describes an invention for a semiconductor device and a method for manufacturing a semiconductor device that can improve the adhesion between the encapsulant and each component.

[0005] However, oxidation of the copper surface poses problems during the manufacture of power semiconductor devices, such as impairing solderability and ultrasonic welding of copper terminals, and the oxide film on the copper surface increases contact resistance when attaching a bus bar. Therefore, the present invention aims to increase the adhesive strength between hard resin and copper while preventing an increase in contact resistance when attaching a bus bar.

[0006] In order to solve the above-mentioned problems, the semiconductor device of the present invention comprises an insulating substrate, a case that houses the insulating substrate, copper wiring formed on the insulating substrate, a semiconductor chip connected to the copper wiring, and a copper terminal that extends to the upper end of the case, wherein the copper wiring and the copper terminal are bonded together, a heat capacity body provided in a component of the case is in contact with the copper terminal, and an oxide film having a thickness of 15 nm to 100 nm is formed on the surface of the copper wiring, and the copper wiring is further covered with a hard resin.

[0007] The present invention provides a semiconductor device manufacturing method, which includes a semiconductor device including an insulating substrate, a case for housing the insulating substrate, copper wiring formed on the insulating substrate, a semiconductor chip connected to the copper wiring, a heat capacity provided in a component of the case, and a copper terminal extending to the upper end of the case and contacting the heat capacity, and the method includes the steps of: joining the copper wiring to the copper terminal; heating the insulating substrate from below; and filling the case with a hard resin to cover the insulating substrate and the semiconductor chip with the hard resin. Other means will be described in the description of the preferred embodiment of the invention.

[0008] According to the present invention, it is possible to increase the adhesive strength between the hard resin and copper and prevent an increase in contact resistance when the bus bar is attached.

[0009] FIG. 1 is a cross-sectional view showing copper wiring on an insulating substrate; FIG. 2 is a cross-sectional view showing a semiconductor chip connected on copper wiring; FIG. 3 is a cross-sectional view showing a case in which copper terminals are connected to the copper wiring on an insulating substrate; FIG. 4 is a cross-sectional view showing a power semiconductor device the interior of which is sealed with epoxy resin; FIG. 5 is a flowchart of a power semiconductor device of a first embodiment; FIG. 6 is a graph showing the relationship between film thickness and oxidation treatment time; FIG. 7 is a graph showing the relationship between shear strength and oxidation treatment time; and FIG. 8 is a flowchart of a power semiconductor device of a second embodiment.

[0010] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. First Embodiment Figures 1 to 4 show cross-sectional views of a power semiconductor device 7 for each manufacturing step. Figure 5 is a flowchart showing a manufacturing method of the power semiconductor device 7 of the first embodiment. Each step of the flowchart in Figure 5 will be described, and the power semiconductor device 7 at that time will be described with reference to the cross-sectional views.

[0011] Fig. 1 shows an initial insulating substrate 1 used in manufacturing a power semiconductor device 7. As shown in Fig. 1, the insulating substrate 1 has copper wiring 11 formed on the surface of a ceramic substrate 12 and a copper layer 13 formed on the back surface. The copper layer 13 is solder-bonded to a base 20 via a solder layer 14 on the underside of the ceramic substrate 12. The base 20 is made of metal and is provided with cooling fins for cooling the power semiconductor device 7.

[0012] A method for manufacturing the power semiconductor device 7 of Fig. 1 will be described with reference to Fig. 5. A manufacturing device (not shown) connects a semiconductor chip 42 onto the copper wiring 11 of the insulating substrate 1 shown in Fig. 1 (step S10). The state of the power semiconductor device 7 after step S10 is performed is shown in Fig. 2.

[0013] 2, a semiconductor chip 42 is bonded to the copper wiring 11 of the insulating substrate 1 via an under-chip solder layer 43. The semiconductor chip 42 is electrically connected to the copper wiring 11 without an oxide film being formed on the copper wiring 11, so solder bonding is not impaired.

[0014] A lead frame 44 is bonded to the upper side of the semiconductor chip 42 via an on-chip solder layer 41. Furthermore, one of the semiconductor chips 42 and the copper wiring 11 are electrically connected by a wire 5. Since the copper wiring 11 and the semiconductor chip 42 are electrically connected by the wire 5 without an oxide film being formed on the copper wiring 11, the solder bonding between the wire 5 and the copper wiring 11 is not impaired.

[0015] Continuing the explanation, returning to Fig. 5, a manufacturing apparatus (not shown) electrically connects the copper terminal 31 of the case 3 to the copper wiring 11 of the insulating substrate 1 (step S11), thereby manufacturing the power semiconductor device 7. The copper wiring 11 of the insulating substrate 1 and the copper terminal 31 of the case 3 shown in Fig. 3 are connected by ultrasonic bonding. At this time, no oxide film is formed on the surface of the copper wiring 11, and no oxide film is formed on the surface of the copper terminal 31. Therefore, the ultrasonic welding of the copper wiring 11 and the copper terminal 31 is not hindered.

[0016] The case 3 is bonded to the outer periphery of the surface of the insulating substrate 1. A nut 32 is embedded in the case 3. The nut 32 is a heat capacity body having a predetermined mass, and is provided as a component of the case 3. The copper terminal 31 is in surface contact with the nut 32, which is a heat capacity body. The nut 32 extends to the upper end of the case 3. The nut 32 is made of metal, such as iron or steel, copper, brass, or stainless steel. The copper wiring 11 of the insulating substrate 1 and the copper terminal 31 of the case 3 may be connected by soldering, but this is not limited to this.

[0017] 5 , the manufacturing apparatus (not shown) heats the underside of the power semiconductor device 7 with a hot plate (not shown) (step S12). This heats the copper wiring 11 and the copper terminal 31 through the base 20, and makes it possible to form an oxide film with a thickness of 15 nm to 100 nm on the surfaces thereof.

[0018] FIG. 6 is a graph showing the relationship between film thickness and oxidation treatment time. The vertical axis of the graph represents the thickness of the oxide film formed on the surface of the copper wiring 11. The horizontal axis of the graph represents the time of heating on the hot plate, which is referred to here as oxidation treatment time. Heating for approximately one hour allows the formation of an oxide film of approximately 15 nm. Here, the manufacturing equipment performs the oxidation treatment for at least one hour. The manufacturing equipment uses a hot plate to heat at 150°C for one to four hours. The heating temperature of the hot plate is set lower than the melting point of the solder. This allows the formation of an oxide film on the surface of the copper wiring 11 without melting the solder that constitutes the solder layer 14, the chip-top solder layer 41, and the chip-bottom solder layer 43.

[0019] Heating the underside of the power semiconductor device 7 with a hot plate heats the copper wiring 11 on the insulating substrate 1, thereby allowing the oxide film on the surface of the copper wiring 11 to be sufficiently thick. Meanwhile, the temperature decreases with increasing distance from the hot plate, suppressing oxidation of the busbar mounting portion 33 of the copper terminal 31. Furthermore, the nut 32, which serves as a heat capacity, is in surface contact with the copper terminal 31, suppressing heating of the copper terminal 31 at the busbar mounting portion 33 and preventing oxidation at the surface-to-surface contact point. This allows the thickness of the oxide film on the copper terminal 31 at the busbar mounting portion 33 to be thinner than that on the surface of the copper wiring 11 on the insulating substrate 1, thereby reducing the resistance of the oxide film. These treatments suppress an increase in contact resistance at the busbar mounting portion 33, which is a negative effect of copper surface oxidation intended to increase the adhesive strength between the copper and the epoxy resin 6.

[0020] 7 is a graph showing the relationship between the shear strength of the epoxy resin 6 filled in the case 3 and the oxidation treatment time. The vertical axis of the graph shows the shear strength of the epoxy resin 6 filled in the case 3. The horizontal axis of the graph shows the time of heating on the hot plate, which is referred to here as the oxidation treatment time. By heating for about one hour, it is possible to approximately double the shear strength of the epoxy resin 6.

[0021] 5, a manufacturing apparatus (not shown) seals the epoxy resin 6 (step S13) to manufacture a power semiconductor device 7. Fig. 4 is a cross-sectional view showing the power semiconductor device 7 whose interior is sealed with the epoxy resin 6. An oxide film having a thickness of 15 nm to 100 nm is formed on the surface of the copper wiring 11, and therefore the shear strength of the epoxy resin 6 is improved.

[0022] The thickness of the copper oxide film can be measured using the continuous electrochemical reduction method (SERA method). The graph of oxide film thickness in Figure 6 was measured using the SERA method. Alternatively, it can be measured using X-ray photoelectron spectroscopy (XPS). It is desirable to measure the thickness of the oxide film before filling the package encapsulant (epoxy resin). This is because filling with epoxy resin requires the effort of removing it. However, even after filling with epoxy resin, the oxide film thickness can be measured by cross-sectional observation using a scanning electron microscope (SEM) or transmission electron microscope (TEM).

[0023] Second Embodiment Figure 8 is a flowchart showing a method for manufacturing a power semiconductor device 7 according to a second embodiment. In the power semiconductor device 7 according to the second embodiment, instead of forming an oxide film on the surface of the copper wiring 11 by heating the insulating substrate 1 from below with a hot plate, an adhesive is applied. This improves the shear strength of the epoxy resin 6. Below, each step of the flowchart in Figure 8 will be explained, and the power semiconductor device 7 at that time will also be explained with reference to cross-sectional views.

[0024] Fig. 1 shows an initial insulating substrate 1 when manufacturing a power semiconductor device 7. As shown in Fig. 1, the insulating substrate 1 has copper wiring 11 formed on the surface of a ceramic substrate 12 and a copper layer 13 formed on the back surface. The copper layer 13 is solder-bonded to a base 20 via a solder layer 14 on the underside of the ceramic substrate 12.

[0025] Returning to Fig. 8, the description will continue. A manufacturing device (not shown) connects a semiconductor chip 42 onto the copper wiring 11 of the insulating substrate 1 shown in Fig. 1 (step S20). The result after step S20 is performed is shown in Fig. 2.

[0026] 2 is connected to the insulating substrate 1 via an under-chip solder layer 43. A lead frame 44 is connected to the upper side of the semiconductor chip 42 via an over-chip solder layer 41. Furthermore, one of the semiconductor chips 42 and the copper wiring 11 are electrically connected by a wire 5.

[0027] Returning to Fig. 8 , a manufacturing apparatus (not shown) manufactures a power semiconductor device 7 by connecting copper terminals 31 of case 3 to copper wiring 11 of insulating substrate 1 (step S21). Copper wiring 11 of insulating substrate 1 and copper terminals 31 of case 3 shown in Fig. 3 are connected by ultrasonic bonding. Case 3 is bonded to the outer periphery of the surface of insulating substrate 1. Nut 32 is embedded in case 3. Nut 32 is a heat capacity body having a predetermined mass and is in surface contact with copper terminal 31.

[0028] Returning to FIG. 8, the manufacturing device (not shown) applies adhesive to the surface of the power semiconductor device 7 (step S22).

[0029] Then, a manufacturing device (not shown) seals the epoxy resin 6 (step S23) to manufacture the power semiconductor device 7. Fig. 4 is a cross-sectional view showing the power semiconductor device 7 whose interior is sealed with the epoxy resin 6. The adhesive is applied to the surface of the copper wiring 11, thereby improving the shear strength. By applying the adhesive, the shear strength can be improved by about four times.

[0030] The configuration and effects of the present invention are explained below. [1] A semiconductor device (7) comprising: an insulating substrate (1), a case (3) for accommodating the insulating substrate (1), copper wiring (11) formed on the insulating substrate (1), a semiconductor chip (42) connected to the copper wiring (11), and a copper terminal (31) extending to the upper end of the case (3), wherein the copper wiring (11) and the copper terminal (31) are joined together, a heat capacity body provided in a component of the case (3) is in contact with the copper terminal (31), and an oxide film having a thickness of 15 nm to 100 nm is formed on the surface of the copper wiring (11), and the copper terminal (31) is further covered with a hard resin (6).

[0031] This makes it possible to increase the adhesive strength between the copper and the hard resin and to prevent an increase in contact resistance when the bus bar is attached.

[0032] [2] The semiconductor device according to claim 1, wherein the heat capacity body is a nut (32) that extends to the upper end of the case.

[0033] This makes it possible.

[0034] [3] The semiconductor device according to claim 1, characterized in that the oxide film formed on the copper wiring (11) is thicker than the oxide film formed on the surface of the copper terminal (31) opposite to the contact portion of the heat capacity body.

[0035] This keeps the electrical resistance low when the bus bar is attached to the copper terminal.

[0036] [4] The semiconductor device according to claim 1, wherein the copper wiring (11) and the copper terminal (31) are ultrasonically bonded together.

[0037] This keeps the electrical resistance between the copper wiring and the copper terminal low.

[0038] [5] The semiconductor device according to claim 1, wherein the copper wiring (11) and the copper terminal (31) are solder-bonded.

[0039] The semiconductor device according to claim 1, wherein the copper wiring (11) is connected to the semiconductor chip (42) through a copper terminal, and the copper wiring (11) is connected to the semiconductor chip through a copper terminal.

[0040] This can prevent the solder joint from being impaired.

[0041] [7] A method for manufacturing a semiconductor device comprising: an insulating substrate (1); a case (3) for accommodating the insulating substrate (1); copper wiring (11) formed on the insulating substrate (1); a semiconductor chip (42) connected to the copper wiring (11); a heat capacity body provided in a component of the case (3); and a copper terminal (31) extending to the upper end of the case (3) and contacting the heat capacity body, the method comprising the steps of: joining the copper wiring (11) and the copper terminal (31); heating the insulating substrate (1) from below; and filling the case (3) with hard resin (6) to cover the insulating substrate (1) and the semiconductor chip (42) with the hard resin (6).

[0042] This increases the adhesive strength between the copper and hard resin, prevents an increase in contact resistance when attaching the bus bar, and prevents any interference with solder bonding or ultrasonic welding of the copper terminals.

[0043] [8] The method for manufacturing a semiconductor device according to claim 7, characterized in that the semiconductor device (7) is constructed by connecting the semiconductor chip (42) to the copper wiring (11) in a state where no oxide film is formed on the copper wiring (11).

[0044] This can prevent the solder joint from being impaired.

[0045] [9] The method for manufacturing a semiconductor device according to claim 7, characterized in that the semiconductor device (7) is constructed by electrically connecting the semiconductor chip (42) to the copper wiring (11) via a wire (5) in a state where no oxide film is formed on the copper wiring (11).

[0046] This can prevent the solder joint from being impaired.

[0047]

[10] The method for manufacturing a semiconductor device according to claim 7, further comprising ultrasonically bonding the copper wiring (11) and the copper terminal (31).

[0048] This keeps the electrical resistance between the copper wiring and the copper terminal low.

[0049]

[11] The method for manufacturing a semiconductor device according to claim 7, further comprising soldering the copper wiring (11) and the copper terminal (31).

[0050] This keeps the electrical resistance between the copper wiring and the copper terminal low.

[0051] (Modifications) The present invention is not limited to the above-described embodiments and includes various modifications. For example, the above-described embodiments have been described in detail to clearly explain the present invention, and are not necessarily limited to those including all of the described configurations. It is possible to replace part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment. Furthermore, it is also possible to add, delete, or replace part of the configuration of each embodiment with other configurations.

[0052] The above-described configurations, functions, processing units, processing means, etc. may be implemented in part or in whole by hardware such as an integrated circuit. The above-described configurations, functions, etc. may also be implemented by software, with a processor interpreting and executing a program that implements each function. Information such as the program, table, and file that implements each function can be stored in a recording device such as a memory, a hard disk, or an SSD (Solid State Drive), or on a recording medium such as a flash memory card or a DVD (Digital Versatile Disk).

[0053] In each embodiment, the control lines and information lines shown are those considered necessary for explanation, and not all control lines and information lines in the product are necessarily shown. In reality, it can be considered that almost all components are interconnected. Examples of modified examples of the present invention include the following (a) to (c).

[0054] (a) The copper wiring 11 of the insulating substrate 1 and the copper terminal 31 are not limited to ultrasonic bonding, but may be soldered. (b) The resin filled inside the case 3 is not limited to epoxy resin, but may be any hard resin. (c) The present invention is not limited to power semiconductor devices, but may be applied to any semiconductor device.

[0055] REFERENCE SIGNS LIST 1 insulating substrate 12 ceramic substrate 11 copper wiring 13 copper layer 14 solder layer 20 base 3 case 31 copper terminal 32 nut (heat capacity body) 33 bus bar mounting portion 42 semiconductor chip 43 solder layer under chip 41 solder layer over chip 44 lead frame 5 wire 6 epoxy resin 7 power semiconductor device (semiconductor device)

Claims

1. A semiconductor device comprising: an insulating substrate; a case for housing the insulating substrate; copper wiring formed on the insulating substrate; a semiconductor chip connected to the copper wiring; and a copper terminal extending to an upper end of the case; wherein the copper wiring and the copper terminal are joined; a heat capacity provided in a component of the case is in contact with the copper terminal; and an oxide film having a thickness of 15 nm to 100 nm is formed on the surface of the copper wiring, and the copper terminal is further covered with a hard resin.

2. The semiconductor device according to claim 1, wherein the heat capacity body is a nut that reaches the upper end of the case.

3. The semiconductor device according to claim 1, characterized in that the oxide film formed on the copper wiring is thicker than the oxide film formed on the surface of the copper terminal opposite the contact portion with the heat capacity body.

4. The semiconductor device according to claim 1, wherein the copper wiring and the copper terminal are ultrasonically bonded.

5. The semiconductor device according to claim 1, wherein the copper wiring and the copper terminal are soldered together.

6. The semiconductor device according to claim 1, wherein no oxide film is formed on the copper wiring where the semiconductor chip is connected.

7. A method for manufacturing a semiconductor device comprising: an insulating substrate; a case for housing the insulating substrate; copper wiring formed on the insulating substrate; a semiconductor chip connected to the copper wiring; a heat capacity provided in a component of the case; and a copper terminal extending to an upper end of the case and in contact with the heat capacity, the method comprising the steps of: joining the copper wiring and the copper terminal; performing a heat treatment from below the insulating substrate; and filling the case with a hard resin to cover the insulating substrate and the semiconductor chip with the hard resin.

8. The method for manufacturing a semiconductor device according to claim 7, characterized in that the semiconductor device is constructed by connecting the semiconductor chip to the copper wiring in a state where no oxide film is formed on the copper wiring.

9. The method for manufacturing a semiconductor device according to claim 7, characterized in that the semiconductor device is constructed by electrically connecting the semiconductor chip to the copper wiring via a wire in a state where no oxide film is formed on the copper wiring.

10. The method for manufacturing a semiconductor device according to claim 7, further comprising ultrasonically bonding the copper wiring and the copper terminal.

11. The method for manufacturing a semiconductor device according to claim 7, further comprising the step of soldering the copper wiring and the copper terminal.

Citation Information

Patent Citations

  • Semiconductor device

    JP1998041460A

  • Semiconductor device

    JP2010219385A

  • Semiconductor device and manufacturing method of the same

    JP2015149370A

  • Semiconductor device, manufacturing method for semiconductor device, and power conversion equipment

    WO2020136810A1