Dynamic logic style-based energy efficient logic of spin torque majority gate

Abstract

A dynamic logic style-based energy efficient logic of a spin torque majority gate is presented. A dynamic logic-based spin torque majority gate circuit proposed by the present invention dynamically adjusts a current flow for each STMG through a transistor which is turned on / off according to a clock signal, in order to solve cascading and fan-out problems.

Description

Energy-efficient logic based on dynamic logic style with multiple spin-torque gates

[0001] The present invention relates to an energy-efficient logic based on a dynamic logic style of spin torque multiple gates and an operating method thereof.

[0002] With the rapid advancement of devices, reducing the power consumption of semiconductor chips has become an essential requirement. Spin-based devices have attracted significant attention as next-generation semiconductor devices for implementing ultra-low-power circuits due to their promising characteristics, such as nonvolatility, near-zero leakage power, high integration density, and compatibility with CMOS processes. In particular, the Spin-Torque Majority Gate (STMG) can simultaneously perform logic and non-volatile memory functions in a single device, enabling the design of highly efficient systems that store and directly operate data without flip-flops. Furthermore, STMG can implement non-inverting logic functions such as AND and OR gates. Furthermore, by integrating an inverting layer, the output can be inverted without additional inverter gates, enabling the implementation of NAND and NOR gates in a single device.

[0003]

[0004] Fig. 1 is a drawing for explaining an STMG-based circuit according to the prior art.

[0005] Conventional STMG-based circuits suffer from cascading and fan-out problems that make complex and large-scale integrated circuit and system designs impossible.

[0006] Figure 1(a) shows a 1-bit FA (Full-Adder) circuit designed using a conventional STMG. In the inverting layer, the output of the STMG is inverted.

[0007] Figure 1(b) shows the current flow when a 1-bit STMG FA is driven by passing current I through each STMG for normal operation. This is a simple configuration consisting of three STMGs connected in two stages. Even this simple circuit clearly reveals the biggest problem with conventional STMGs.

[0008] In order to drive a 1-bit STMG FA as shown in Fig. 1(b), a large current of 9×I, which is 9 times the operating current I of each STMG, is required.

[0009]

[0010] FIG. 2 is a drawing for explaining an STMG-based circuit having multiple stages according to the prior art.

[0011] For example, for a 3-stage circuit of 27×I and a 4-stage circuit of 81×I (27×I×3) to operate, the required current increases significantly as the number of stages increases, as shown in Fig. 2(a). Even with only 5 stages, a current 100 times greater is required, making cascading operation impossible.

[0012] Figure 2(b) shows the current flowing through an STMG with N fanouts. When the output is used as multiple inputs, the fanout increases, and the current flowing from the STMG also increases. This causes an imbalance in the current flowing through each STMG, making the normal operation of the STMG uncertain. If too much current flows through the STMG, reliability issues such as circuit breakdown may occur. On the other hand, if too little current flows, propagation may not occur accurately at the domain walls. If a very large current is required compared to the operating current of the STMG, it is disadvantageous in terms of power consumption, making it virtually impossible to increase the number of stages or implement complex circuits with multiple inputs and multiple outputs.

[0013] The technical challenge of the present invention is to provide a dynamic logic-based spin-torque majority gate (D-STMG) that solves the cascading and fan-out problems of a spin-torque majority gate (STMG) and enables the implementation of multiple logic stages for large-scale integration. In addition, a 32-bit full-adder (FA) circuit using a D-STMG is proposed.

[0014] In one aspect, the dynamic logic-based spin torque multi-gate circuit proposed in the present invention dynamically controls the current flow of each STMG through transistors that are turned on / off according to a clock signal to solve cascading and fan out problems.

[0015] When the above dynamic logic-based spin torque multiple gate circuit includes multiple stages, the current flowing in each stage is dynamically controlled through a transistor that is turned on / off according to a clock signal, and when the corresponding transistor that controls the current flow in the first stage is turned on, current flows in the first stage, and when the corresponding transistor that controls the current flow in the second stage is turned on, current flows in the second stage. The transistor that controls the current flow for each STMG is turned on / off according to the clock signal.

[0016] As the number of stages of the above dynamic logic-based spin torque multi-gate circuit increases, the amount of current does not increase, and the amount of current can be dynamically controlled according to the corresponding transistor that controls the current flow of each stage.

[0017] When the above dynamic logic-based spin torque multi-gate circuit includes multiple fan outs, a uniform amount of current is controlled to flow through all STMGs and all domain walls through transistors that are turned on / off according to a clock signal.

[0018] A dynamic logic-based spin torque multi-gate circuit according to an embodiment of the present invention operates independently with a uniform amount of current in each stage by turning on / off a transistor that controls the current flow of each STMG according to a clock signal in an operation for logic operations.

[0019] In another aspect, the full adder using the dynamic logic-based spin torque multi-gate circuit proposed in the present invention dynamically controls the current flow of each STMG through a transistor that is turned on / off according to a clock signal to solve the cascading and fan out problems, and in the operation for the logic operation of the full adder, the transistor that controls the current flow of each STMG is turned on / off according to the clock signal, so that each stage operates independently with a uniform amount of current.

[0020] A full adder using a dynamic logic-based spin torque multiple gate circuit according to an embodiment of the present invention adds a circuit to the second stage that generates the same carry as the first stage so that the carry generated in the first stage is used only for the carry input of the second stage and is not used for the sum operation of the third stage in the operation for the logic operation of the ripple carry full adder.

[0021] According to embodiments of the present invention, the cascading and fan-out problems of the existing spin-torque majority gate (STMG) can be solved through the dynamic logic style of spin-torque majority gate (D-STMG), thereby enabling the implementation of multiple logic stages for large-scale integration. In addition, a 32-bit full-adder (FA) circuit using D-STMG is proposed, and when compared with a complementary metal-oxide-semiconductor (CMOS) FA under the same conditions, the proposed 32-bit D-STMG FA circuit achieved 84% lower average power consumption and 22% lower power-delay product (PDP) under the condition of 3% activity ratio compared to the 32-bit CMOS FA circuit. Therefore, the proposed D-STMG-based circuit is suitable for energy-efficient system design because it can store data using non-volatility and operate directly without flip-flops.

[0022] Fig. 1 is a drawing for explaining an STMG-based circuit according to the prior art.

[0023] FIG. 2 is a drawing for explaining an STMG-based circuit having multiple stages according to the prior art.

[0024] FIG. 3 is a diagram illustrating a dynamic logic-based spin torque multi-gate circuit according to one embodiment of the present invention.

[0025] FIG. 4 is a diagram illustrating a D-STMG circuit implemented with multiple cascading and fan-outs according to one embodiment of the present invention.

[0026] FIG. 5 is a diagram showing a full adder using a D-STMG circuit according to one embodiment of the present invention.

[0027] FIG. 6 is a diagram illustrating a 2-bit D-STMG FA according to one embodiment of the present invention.

[0028] FIG. 7 is a diagram illustrating a 32-bit D-STMG FA according to an embodiment of the present invention.

[0029] FIG. 8 is a diagram illustrating a 32-bit D-STMG FA operating with 3 clocks according to one embodiment of the present invention.

[0030] Figure 9 is a micromagnetic simulation result using mumax3 according to one embodiment of the present invention.

[0031] FIG. 10 is a diagram illustrating a 32-bit CMOS FA according to one embodiment of the present invention.

[0032] The present invention proposes a dynamic logic-based spin-torque majority gate (D-STMG) that solves the cascading and fan-out problems of existing spin-torque majority gates (STMGs) and enables the implementation of multiple logic stages for large-scale integration. The D-STMG circuit according to an embodiment of the present invention is composed of PMOS and NMOS transistors and can control the current of each STMG according to a clock signal, thereby enabling fine pipelining. As the system block size increases, the advantages of using D-STMG also increase. To demonstrate the effectiveness of the proposed architecture, a 1-bit full-adder (FA) logic circuit was designed using D-STMG, followed by a 32-bit D-STMG FA circuit. In addition, for a fair comparison, the FA circuit was compared with a CMOS-based 32-bit adder under the same conditions. The performance comparison results show that the proposed 32-bit D-STMG FA circuit achieves 77% lower average power consumption and 3% lower power-delay product (PDP) at 10% operation rate compared to a 32-bit CMOS FA. It also achieves 84% ​​lower average power consumption and 22% lower PDP at 3% operation rate. The D-STMG circuit design and performance verification results confirm the feasibility of implementing an energy-efficient system design using spin elements. Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0033]

[0034] FIG. 3 is a diagram illustrating a dynamic logic-based spin torque multi-gate circuit according to one embodiment of the present invention.

[0035] The present invention proposes a D-STMG to address the fanout and cascading issues of conventional STMGs. The D-STMG comprises PMOS and NMOS transistors, allowing for control of the current flow within each STMG and using a clock to operate in a desired order.

[0036] FIG. 3 (a) is a diagram showing a 1-bit FA implemented with a dynamic logic style of spin-torque majority gate (D-STMG) according to one embodiment of the present invention.

[0037] Referring to Fig. 3 (a), the D-STMG is composed of PMOS and NMOS transistors, so that the current flow of each STMG can be controlled and a clock is used to operate in a desired order.

[0038] Stage 1 is based on CLK1 NMOS (311, 312, 314, 315, 316, 318) that turns on / off according to CLK1 Depending on the PMOS (321, 322) and CLK2 that are turned on / off It includes an NMOS (313, 317) that turns on / off, and stage 2 is controlled by CLK2. NMOS (331) that turns on / off according to CLK2 It includes a PMOS (341) that turns on / off.

[0039] Figure 3 (b) is a diagram showing the current flow when a 1-bit D-STMG FA is driven by flowing current I through each D-STMG for normal operation.

[0040] Referring to Fig. 3 (b), when CLK1 (351) is high and CLK2 (352) is low (310), the stage 1 transistor is turned on, and current flows only for the stage 1 domain wall devices. In other words, when CLK1 (351) is high, current flows only for the corresponding STMG connected to the stage 1 NMOS (311, 312, 314, 315, 316, 318) and PMOS (321, 322).

[0041] On the other hand, when CLK1 (351) is low and CLK2 (352) is high (320), the stage 1 transistor is turned off, the stage 2 transistor is turned on, and current flows to the stage 2 STMG element. In other words, when CLK2 (352) is high, current flows only to the corresponding STMG connected to the stage 1 NMOS (313, 317), stage 2 NMOS (331), and stage 2 PMOS (341).

[0042] When the transistor corresponding to each stage is turned on, current flows through that stage, turning on the transistor corresponding to the next stage to operate the next stage. The transistors of each stage can be turned on / off using a clock signal, so that each stage can operate independently with the same amount of current for logic operations.

[0043]

[0044] FIG. 4 is a diagram illustrating a D-STMG circuit implemented with multiple cascading and fan-outs according to one embodiment of the present invention.

[0045] FIG. 4(a) is a diagram illustrating a D-STMG circuit implemented in four stages according to one embodiment of the present invention. The D-STMG circuit implemented in four stages is merely an example and is not limited thereto, and the D-STMG circuit may be implemented with more or fewer stages.

[0046] The 4-stage circuit based on STMG according to the prior art requires a large current of 81×I as shown in Fig. 2(a) for normal operation.

[0047] On the other hand, the D-STMG-based 4-stage circuit according to the embodiment of the present invention only needs to apply 3×I of current to each stage by controlling the current flow for each STMG through a transistor that turns on / off according to a clock signal.

[0048] When the stage 1 transistor is turned on (410), current flows only through the stage 1 domain wall element.

[0049] When the stage 2 transistor is turned on (420), current flows only through the stage 2 domain wall element.

[0050] When the stage 3 transistor is turned on (430), current flows only through the stage 3 domain wall element.

[0051] When the stage 4 transistor is turned on (440), current flows only through the stage 4 domain wall element.

[0052] Unlike conventional STMG-based circuits, where current increases significantly with increasing number of stages, the current flowing in a D-STMG circuit can be adjusted by modifying the transistors in each stage. Furthermore, D-STMG circuits can be designed to allow different current levels at each stage, depending on desired requirements.

[0053] Fig. 4 (b) is a diagram showing the current flow in a D-STMG having N fan-outs. It is compared with the current flow in a conventional STMG having N fan-outs as shown in Fig. 2 (b).

[0054] In a conventional STMG, a large current of NxI flows through the output of the first STMG, and this current is divided between the domain walls, so that a current of N / 3xI flows through each domain wall.

[0055] On the other hand, in the D-STMG according to the embodiment of the present invention, by adjusting the values ​​of the transistors according to the fan-in (450) and the fan-out (460), the current flows uniformly as 3xI at the output of all STMGs, and the current flows uniformly as I at the domain walls of all STMGs.

[0056] The requirement that the current flowing through each STMG must remain within specific upper and lower limits for proper operation has limited the performance of prior art STMG-based circuits. This constraint has made it difficult to implement and cascade complex, large-scale integrated circuits.

[0057] However, using the D-STMG according to an embodiment of the present invention allows for control of the current flowing through the STMG, enabling circuit design that fully leverages the advantages of STMG technology. Furthermore, the non-volatility of the STMG allows for power supply only to the operating stages, reducing leakage power consumption. Furthermore, the proposed approach also benefits from increased throughput due to fine pipelining.

[0058]

[0059] FIG. 5 is a diagram showing a full adder using a D-STMG circuit according to one embodiment of the present invention.

[0060] FIG. 5(a) is a D-STMG symbolization diagram for improving visibility in the design process of a D-STMG full-adder (FA) according to one embodiment of the present invention, and FIG. 5(b) is a diagram showing a 1-bit D-STMG FA using a symbolized diagram according to one embodiment of the present invention.

[0061] The D-STMG according to the embodiment of the present invention can significantly improve performance as the system block size increases because it can pipeline in very small units. Therefore, to investigate the performance advantages of the proposed circuit, the design of a 1-bit FA was extended to a larger integrated circuit. Specifically, the 1-bit FA was extended to a 32-bit FA and compared with a conventional 32-bit CMOS FA under the same conditions.

[0062] In order to improve visibility in the 32-bit D-STMG FA design process according to an embodiment of the present invention, the 1-bit D-STMG circuit (310) illustrated in FIG. 3(a) was symbolized (520).

[0063] The transistors (511, 512, 513, 514) illustrated in the D-STMG FA circuit (310) correspond to the transistors (521, 522, 523, 524) of the symbolized drawing (520), respectively.

[0064] Referring to Fig. 5(b), a 1-bit D-STMG FA is represented using a symbolized drawing (520). The inversion layer is represented by an inverter symbol.

[0065]

[0066] FIG. 6 is a diagram illustrating a 2-bit D-STMG FA according to one embodiment of the present invention.

[0067] Referring to Fig. 5, a 2-bit D-STMG FA is represented using a symbolized D-STMG. The 2-bit D-STMG FA is a ripple carry adder that connects two stages of a 1-bit FA.

[0068] Referring to Fig. 6, the carry generated in the first stage (Cout0=Cin1) is used not only for the carry input of the second stage but also for the input for the sum operation of the third stage, so that the second and third stages cannot operate independently. To solve this, a circuit that generates the same carry as the first stage was added to the second stage, and the circuit was modified so that the carry generated in the second stage is used for the sum operation in the third stage, as shown in Fig. 6.

[0069]

[0070] FIG. 7 is a diagram illustrating a 32-bit D-STMG FA according to one embodiment of the present invention.

[0071] According to one embodiment of the present invention, after confirming the normal operation of a 2-bit D-STMG FA modified for cascade operation, the number of bits can be expanded up to 32 bits, and an outline of a 32-bit FA based on D-STMG is as shown in Fig. 7. Like a ripple carry adder, 32 1-bit D-STMG FAs are connected in a row, and three clocks (CLK1, CLK2, CLK3) are used.

[0072]

[0073] FIG. 8 is a diagram illustrating a 32-bit D-STMG FA operating with 3 clocks according to one embodiment of the present invention.

[0074] According to one embodiment of the present invention, the current flow is shown in Fig. 8 to help understand the operation of a 32-bit FA designed by D-STMG with 3 clocks.

[0075] Figure 8(a) is a diagram showing the current flow in stages 1, 4, and 7 when CLK1 is high, and Figure 8(b) is a diagram showing the current flow in stages 2 and 5 when CLK2 is high.

[0076] Figure 8(c) is a diagram showing the current flow in stages 3 and 6 when CLK3 is high.

[0077] Referring to Fig. 8, in a 32-bit D-STMG FA operating with 3 clocks according to an embodiment of the present invention, stages 1, 4, 7, 10, ... and 31 operate at CLK1, stages 2, 5, 8, 11, ... and 32 operate at CLK2, and stages 3, 6, 9, 12, ... and 30 operate at CLK3. The time of 1 clock according to an embodiment of the present invention was set by confirming the switching time of the STMG through mumax3 simulation and conducting an experiment.

[0078]

[0079] In order to simulate the D-STMG circuit according to an embodiment of the present invention, SPICE modeling of the STMG is required. In the present invention, the STMG was designed and simulated using mumax3, a GPU-accelerated micromagnetic simulation program, and the device dimensions, simulation parameters, and measured values ​​are listed in Table 1.

[0080] Table 1

[0081]

[0082]

[0083] Figure 9 is a micromagnetic simulation result using mumax3 according to one embodiment of the present invention.

[0084] Using the width, length, and thickness values ​​of HM, STMG was drawn as shown in Fig. 9, and material property values ​​such as HM resistivity, KuFM, and AexFM were applied. Next, the initial value (1) and the opposite value (-1) of STMG were input, and it was confirmed that the resulting output moved from 1 to -1. Fig. 9(a) shows STMG immediately after -1 was input, and Fig. 9(b) shows STMG after multiple operations were completed.

[0085] Propagation time refers to the time it takes for an STMG input to reach the multi-operation part where three inputs converge, and switching time refers to the time it takes for the multi-operation to complete and consequently change the data. To ensure proper operation of the D-STMG circuit, it is important to consider this switching time during SPICE modeling. Therefore, in the present invention, the D-STMG circuit was designed using a SPICE model of the STMG that reflects the results of the mumax3 micromagnetic simulation and a commercial 28nm process.

[0086]

[0087] FIG. 10 is a diagram illustrating a 32-bit CMOS FA according to one embodiment of the present invention.

[0088] According to one embodiment of the present invention, a basic 32-bit ripple carry full adder was designed and used as a comparison circuit of a 32-bit D-STMG FA, and a 1-bit FA and a D flip-flop based on a 3-state inverter were designed first, and a 32-bit CMOS FA was implemented by connecting 32 FAs and applying 66 D-FFs to each input / output as shown in FIG. 10, and this 32-bit CMOS FA was designed under the same conditions and process as the 32-bit D-STMG FA for accurate comparison.

[0089] The performance of 32-bit CMOS FA and 32-bit D-STMG is compared and summarized in Table 2.

[0090] Table 2

[0091]

[0092] In the 32-bit CMOS FA, the delay of the return path before FF application was determined as the worst-case delay and used as the total delay. In contrast, the 32-bit D-STMG FA considered a switching time of 1.1 nanoseconds based on the mumax3 simulation results. The final delay of the 32-bit D-STMG FA was calculated considering a 3-clock style and 25 picosecond rise and fall times, resulting in a total delay of 3,375 nanoseconds.

[0093] In the case of delays, 32-bit CMOS FAs are highly advantageous because STMGs must consider each STMG's switch timing for normal operation. Even if the STMG itself is very slow and cannot improve its base speed, performance can be improved by simultaneously increasing output through fine-tuned pipelining using non-volatile memory.

[0094] Dynamic power consumption is lower in the 32-bit D-STMG FA than in the 32-bit CMOS FA, which uses the power of all stages of the FA and D-FF simultaneously. The 32-bit D-STMG FA can sequentially turn on / off each stage by dividing it by a clock, which reduces dynamic power consumption. In addition, the 32-bit CMOS FA cannot turn the power on / off due to data volatility, so a leakage current of 41.5 uW continuously occurs even when not in operation, but the 32-bit D-STMG FA has a leakage power of 0. Therefore, it can be judged that the 32-bit D-STMG FA is superior overall in terms of power consumption.

[0095]

[0096] Finally, 32-bit CMOS FAs use significantly more devices than 32-bit D-STMG FAs. While D-STMGs can configure gates like NAND and NOR into a single device, CMOS uses numerous PMOS and NMOS gates to configure the gates. Furthermore, CMOS requires flip-flops for data storage to match the data processing order, making D-STMGs more efficient in terms of device count.

[0097]

[0098] Although the embodiments described above have been described by way of limited examples and drawings, those skilled in the art will appreciate that various modifications and variations can be made based on the above teachings. For example, appropriate results can still be achieved even if the described techniques are performed in a different order than described, and / or components of the described systems, structures, devices, circuits, etc. are combined or combined in a different manner than described, or are replaced or substituted with other components or equivalents.

[0099] Therefore, other implementations, other embodiments, and equivalents to the claims also fall within the scope of the claims described below.

Claims

1. In a spin-torque majority gate circuit, To solve the cascading and fan out problems, the current flow of each STMG is dynamically controlled through transistors that are turned on / off according to the clock signal. Spin torque multiple gate circuit.

2. In paragraph 1, When the above spin torque multiple gate circuit includes multiple stages, the current flowing in each stage is dynamically controlled through a transistor that is turned on / off according to a clock signal, When the corresponding transistor that controls the current flow of the first stage is turned on, current flows in the first stage, and when the corresponding transistor that controls the current flow of the second stage is turned on, current flows in the second stage. The transistor that controls the current flow of each STMG is turned on / off according to the clock signal. Spin torque multiple gate circuit.

3. In paragraph 2, As the number of stages of the above spin torque multiple gate circuit increases, the amount of current does not increase, The amount of current can be dynamically controlled according to the corresponding transistor that controls the current flow of each stage. Spin torque multiple gate circuit.

4. In paragraph 1, When the above spin torque multiple gate circuit includes multiple fan outs, it is controlled so that a uniform amount of current flows through all STMGs and all domain walls through transistors that are turned on / off according to a clock signal. Spin torque multiple gate circuit.

5. In paragraph 1, In the operation for logic operations, each stage operates independently with a uniform amount of current by turning on / off the transistor that controls the current flow of each STMG according to the clock signal. Spin torque multiple gate circuit.

6. In a full adder using a spin-torque majority gate circuit, To solve the cascading and fan out problems, the current flow of each STMG is dynamically controlled through transistors that are turned on / off according to the clock signal. In the operation for the logic operation of the full adder, each stage operates independently with a uniform amount of current by turning on / off the transistor that controls the current flow of each STMG according to the clock signal. A full adder using a spin-torque multi-gate circuit.

7. In paragraph 6, In the operation for the logic operation of the ripple carry full adder, the carry generated in the first stage is used only for the carry input of the second stage, and a circuit that generates the same carry as the first stage is added to the second stage so that it is not used for the sum operation of the third stage. A full adder using a spin-torque multi-gate circuit.

Images