Pixel driver configured for fast switching

Abstract

Displaying an image as a sequence of bit planes can include storing the sequence of bit planes in a buffer. Reducing the storage space of the buffer can decrease its physical size and power consumption, which is desirable for some mobile applications. The amount of storage space required depends on the compressibility and the brightness of the image, so is difficult to predict. The disclosed display can adjust how the bit planes are stored based on the compressibility and brightness of the image so that the storage space is utilized efficiently. Further, the disclosed display can disable some bit planes to fit into the storage space without dramatically reducing the quality of the displayed image.

Description

PIXEL DRIVER CONFIGURED FOR FAST SWITCHINGCROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims the benefit of U.S. Provisional Application No. 63 / 587,845, filed on October 4, 2023, which is hereby incorporated by reference in its entirety.FIELD OF THE DISCLOSURE

[0002] The present disclosure relates to a display and more specifically to a display configured to display images based on bit planes.BACKGROUND

[0003] Color or grayscale images can be represented as a weighted series (i.e., sequence) of bit planes. To generate a sequence of bit planes, binary numbers are determined from each pixel’s grayscale level. Each binary' number has a number of bits corresponding to the bit depth of the display. A bit plane can be generated for each bit of the binary number. A sequence of bit planes can be arranged from a most significant bit plane, which includes a most significant bit (MSB) of the binaty number for each pixel, to a least significant bit plane, which includes a least significant bit (LSB) of the binary7number for each pixel. Rendering images on a display using bit planes can help reduce the power and size of the display but can require careful control of the pixels in order to accurately display the image.SUMMARY

[0004] A display may include a two-dimensional array of micron-sized light emitting diode (i.e., micro-LED) pixels. Switching each micro-LED quickly may be desirable (e.g., for bit plane rendering) but can be limited by a low-pass response of the micro-LED. A pixel driver is disclosed to mitigate this low-pass response in order to increase the rate at which the micro-LED pixel may be switched.

[0005] In some aspects, the techniques described herein relate to a method for driving a pixel of a display, the method including: configuring a drive switch in an ON condition based on an ON signal received from a sequence timing generator of the display, the drive switch coupled between a current source and an LED of the pixel, configuring a charge switch in theON condition for a charge period based on the ON signal, the charge switch coupled between a voltage source and the drive switch of the pixel; conducting a drive current from the current source to the LED through the drive switch in the ON condition; conducting a charge current from the voltage source to the LED through the charge switch in the ON condition; and charging a capacitance of the LED with the drive current and the charge current during the charge period so that the LED is illuminated in response to the ON signal faster than by the drive current alone. For example, the charge current can be at least ten times greater than the drive current to reduce a time required to charge the capacitance of the LED.

[0006] In some aspects, the techniques described herein relate to a pixel driver circuit for a display, the pixel driver circuit including: a drive switch coupled to a current source; the drive switch configured in an ON condition by an ON signal received from a sequence timing generator; a charge switch coupled between a voltage source and the drive switch, the charge switch configured in the ON condition for a charge period by the ON signal; and an LED coupled to the drive switch, the LED configured to: receive a drive current from the current source through the drive switch in the ON condition; and receive a charge current from the voltage source through the charge switch in the ON condition, a capacitance of the LED being charged by the charge current and the drive current during the charge period so that the LED is illuminated in response to the ON signal faster than by the drive current alone. For example, the charge current can be at least ten times greater than the drive current to reduce a time required to charge the capacitance of the LED.

[0007] In some aspects, the techniques described herein relate to a display including: a pixel array; and a sequence timing generator configured to generate ON signals and an OFF signals to control pixels in the pixel array based on an image, wherein each pixel includes: a drive switch coupled to a current source, the drive switch configured in an ON condition based on an ON signal received from the sequence timing generator; a charge switch coupled between a voltage source and the drive switch, the charge switch configured in the ON condition for a charge period based on the ON signal; and an LED coupled to the drive switch, the LED configured to: receive a drive current from the current source through the drive switch in the ON condition; and receive a charge current from the voltage source through the charge switch in the ON condition, a capacitance of the LED being charged by the charge current and the drive current during the charge period so that the LED is illuminated in response to the ON signal faster than by the drive current alone. In a possible implementation, the LED a micro-LED.

[0008] The foregoing illustrative summan', as well as other exemplary objectives and / or advantages of the disclosure, and the manner in which the same are accomplished, are further explained within the following detailed description and its accompanying drawings.BRIEF DESCRIPTION OF THE DRAWINGS

[0009] FIG. 1 is a system block diagram of a display according to a possible implementation of the present disclosure.

[0010] FIG. 2 illustrates a bit-plane sequence based on an image according to a possible implementation of the present disclosure.

[0011] FIG. 3 illustrates a pixel modulated over time by a pulse width modulation (PWM) signal according to a possible implementation of the present disclosure.

[0012] FIG. 4 is a system block diagram of a controller for a display according to a possible implementation of the present disclosure.

[0013] FIG. 5 is a schematic of a pixel for a micro-LED display according to a possible implementation of the present disclosure.

[0014] FIG. 6 is schematic of a driver circuit for a display according to a possible implementation of the present disclosure.

[0015] FIG. 7 is a timing diagram illustrating signals of a driver circuit according to a possible implementation of the present disclosure.

[0016] FIG. 8 is a state diagram of a pixel driver circuit for a display according to a possible implementation of the present disclosure.

[0017] FIG. 9 is a flowchart of a method for driving a pixel of a display ON according to a possible implementation of the present disclosure.

[0018] FIG. 10 is a flowchart of a method for driving a pixel of a display OFF according to a possible implementation of the present disclosure.

[0019] The components in the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding parts throughout the several views.DETAILED DESCRIPTION

[0020] A delay between the start of a current pulse and the illumination of a micro-LED can be caused by the time required to charge a capacitance (C) of the micro-LED. This charging corresponds to a low-pass response that can be represented by a resistor-capacitor (RC) time constant of the micro-LED. where R is the forward resistance of the diode and C is the capacitance of the micro-LED. For many applications this low pass response of themicro-LED is negligible but may become significant in high-speed applications, especially when the drive current is low. One such application is a display driven by pulse width modulated (PWM) signals, to render a sequence of bit planes. One technical problem with these bit plane displays is that the ON / OFF transitions of the micro-LED pixels may be too slow for the bit plane rendering to accurately represent gray scale levels. To address this technical problem, a driver circuit for a micro-LED pixel display is disclosed that includes charging and discharging signals applied to the micro-LED in order to shorten the ON / OFF response time of the micro-LED pixels (i.e., reduce the low-pass response). This driver circuit may have the technical effect of reducing gray scale errors and can allow the display to use smaller driver currents, which can reduce its power consumption. The lower power consumption can facilitate the display's use in body-worn devices (e.g., augmented reality glasses, augmented reality goggles, smart watches, smart glasses, etc.).

[0021] FIG. 1 is a schematic block diagram of a display according to a possible implementation of the present disclosure. The display 100 includes a plurality of pixels arranged in a 2D grid (i.e., pixel array 120). Each pixel 121 includes a micro-LED configured to generate light while conducting a drive current from a drive current module 140, which can include one or more current sources shared by the pixels. Each pixel 121 further includes a memory7cell (e.g., SRAM) for setting and maintaining the illumination state of a micro-LED as ON or OFF. The state of an SRAM cell of a pixel can be controlled (i.e., set / reset) by a signal (e.g., bit-line signal) transmitted over a column conductor (i.e., bit- line) coupled to the SRAM cell. The SRAM cell of the pixel is coupled to the bit-line based on a signal (e.g., word-line signal) transmitted over a row conductor (i.e., word-line) to the pixel. Accordingly, the display 100 further includes a word-line driver 112 configured to transmit a word-line signal to a word-line (i.e., row) of the pixel array 120. The word-line signal can activate a row so that each pixel in an active row is coupled to its respective bit- line.

[0022] As shown in FIG. 1, the display 100 further includes a bit-line driver 113 configured to transmit bit-line signals to the bit-lines of the pixels in an active row. The bit- line signals may change or maintain the state of the SRAMs in the active row according to a bit plane for display. In a possible implementation, a bit-line signal is a differential signal. In this case, each bit-line may include a positive bit-line (BL+) configured to carry a positive bit-line signal and a negative bit-line configured to carry7a negative bit-line signal (BL-). In this differential configuration, the positive bit-line and the negative bit-line may be referred to collectively as the bit-line.

[0023] The display 100 further includes a controller 400 configured to control the operation of the word-line driver 112 and the bit-line driver 113 to render a bit plane on the pixel array 120. For example, the controller 400 may transmit a word-line signal (i.e. , ROW) to activate a row and then transmit the bit plane data (i.e., DATA(COLUMN)) to the columns of the activated row in parallel.

[0024] The controller 400 may be configured to address and write to the SRAMs of the pixel array 120 so that each micro-LEDs is illuminated (i.e. ON) or not illuminated (i.e. OFF) according to a bit plane. Each bit plane may be rendered on the pixel array 120 on a row-by- row basis until every row necessary for rendering the bit plane has been activated.

[0025] In a possible implementation, a rendering process includes transmitting a wordline signal to activate a row. After being activated, a bit-line signal for each pixel in the row controls the pixel ON / OFF according to the bit plane data for each pixel in the active row. After the bit-line signals configure (i.e., write to) the pixels of the active row, the row may be deactivated, and another row may be activated until all rows of a bit plane have been activated. The SRAM cells for pixels in deactivated rows can hold the pixels of the deactivated rows ON or OFF while the other rows of the bit plane are activated. After writing a bit plane to the SRAM cells of the pixel array 120, the SRAM cells can hold their values (e.g., 0, 1) until they are changed. As a result, updating the values in an SRAM display may only require a portion of the SRAM cells to change their state (i.e., flip) from bit plane to bit plane. This feature of the display contributes to the low power consumption of the display. A sequence of binary bit planes, in which each pixel is either ON (e.g., SRAM at binary 1) or OFF (e.g., SRAM at binary 0) may be rendered at a high rate to create a grayscale image perceived by an observer.

[0026] FIG. 2 illustrates a sequence of bit planes for an image according to a possible implementation of the present disclosure. In this example, an image 201 has four pixels. Each pixel defines a location and a grayscale level. The grayscale levels are represented as binary numbers. The binary numbers have a number of bits corresponding to the bit depth of the display. In the example shown, the display is a four-bit display in which the gray scale level of each pixel is represented by a binary number with four bits arranged left-to-right from the most significant bit (MSB) to the least significant bit (LSB).

[0027] A bit plane sequence 220 can be generated to have a bit plane for each bit of the binary' number. In other words, each pixel in a bit plane can be ON (e.g., 1) or OFF (e.g., 0) according to the bit. As shown, the bit plane sequence 220 includes four bit planes. A first bit plane in the sequence is a binary image that represents the most significant bit (MSB) ofeach pixel (i.e., the most significant bit plane 221). A second bit plane 222 is less significant than the most significant bit plane 221. A third bit plane 223 is less significant than the second bit plane 222 but is more significant than the least significant bit plane 224, which represents the least significant bit (LSB) of each pixel.

[0028] The significance of the bit planes with respect to the gray scale value decreases from the most significant bit plane 221 to the least significant bit plane 224. Accordingly, a first bit plane may be referred to as being below a second bit plane when the first bit plane is of lower significance (in the bit plane sequence 220) than the second bit plane. Likewise, the second bit plane may be referred to as being above the first bit plane when the second bit plane is of higher significance (in the bit plane sequence 220) than the first bit plane.

[0029] Rendering the gray scale image may include writing each bit plane to the pixel array (i.e., SRAM) in succession during a rendering period. When each bit plane is displayed at the same intensity, each bit plane may be weighted by the duration that it is displayed relative to the other bit planes during the sequence. As shown, the weights (W) of the bit planes may double for each bit plane from the least significant bit plane 224 to the most significant bit plane 221. In other words, the portions of a rendering period may double for each successive bit plane from the least significant bit plane 224 to the most significant bit plane 221.

[0030] The quality of an image may be determined by how well the sequence of bit planes represents the gray scale level of each pixel. The significance of the bit plane may correspond to how much its bit contributes to the binary value. More significant bit planes may contribute more image information than less significant bit planes.

[0031] FIG. 3 illustrates a pixel modulated over time by a pulse width modulation signal according to a possible implementation of the present disclosure. As mentioned, in order to represent a grayscale value (e.g., 1010), a pixel may be modulated ON and OFF by a PWM signal 300. For example, a PWM signal applied to a pixel according to its value in a bit plane sequence 220 (see FIG. 2). The PWM signal may control the pixel ON / OFF during a rendering period. A rendering period 301 may include bit periods that are weighted in duration according to their significance. To generate an intensity that corresponds to a four- bit grayscale value of 1010, the pixel can be controlled ON / OFF during four (different) bit periods.

[0032] The pixel is controlled ON (i.e., illuminated) during a first bit period 310, which corresponds to the MSB. The pixel is controlled OFF (i.e., not illuminated) during a second bit period 320, which corresponds to the next most significant bit. In this example, thesecond bit period 320 is one half the first bit period 310. The pixel is controlled ON (i.e., illuminated) during a third bit period 330, which corresponds to the next most significant bit. In this example, the third bit period 330 is one half the second bit period 320. The pixel is controlled OFF (i.e., not illuminated) during a fourth bit period 340, which corresponds to the least significant bit. In this example, the fourth bit period 340 is one half the third bit period 330. In other words, the rendering period 301 may be segmented into portions to display each bit, with more significant bit portions being larger than less significant portions. The actual size of each portion may vary.

[0033] The pixel may have a low-pass response (e.g., see dotted line in FIG. 3) to the PWM signal 300. As a result, transitions between bit values may not be instant. For example, a micro-LED of the pixel may have a response that charges according to an RC time constant. In other words, the micro-LED may have a capacitance that is charged on each transition to an ON condition and discharged at each transition to an OFF condition. Accordingly, a pixel brightness (i.e., intensity) during a bit period may be affected by a charge period 350 or a discharge period 351. Longer bit periods may be affected less than shorter bit periods. For example, the pixel may have a brightness that is significantly reduced during the third bit period 330 by the charge period 350, and the pixel may have a brightness that is significantly increased during the fourth bit period 340 by the discharge period 351.

[0034] Errors in brightness may correspond to grayscale levels that do not match their binary values. In other words, the low-pass response of the pixels may cause grayscale errors in the display. These errors may be noticed by a user, especially in low brightness images, in which the difference in the brightness between pixels may correspond to the less significant bit values. The present disclosure describes a circuit (and method) to mitigate this problem by reducing the charge period 350 and the discharge period 351 associated with driving (i.e.. controlling) pixels in a display.

[0035] FIG. 4 is a system block diagram of a controller for a display according to a possible implementation of the present disclosure. The controller may be implemented as a unitary device or may be part of a distributed computing system. The controller 400 includes digital processing, logic, and memory to perform the operations associated with controlling the pixels in a pixel array to render (i.e., display) an image. These operations may be performed by modules, which can include circuitry and / or software to perform one or more of the operations. In other words, the controller may be configured by software instructions stored in (and recalled from) a non-transitory computer readable memory to perform the methods to control the pixels of the display.

[0036] As shown in FIG. 4, the controller 400 includes a display preprocessor module (i. e. , display preprocessor 410). The display preprocessor 410 may be configured to receive an image for display. The image may be a grayscale image or a color image. A color image for display can include three color channels, each represented by a gray scale image. Accordingly, the example of a grayscale image for display will be discussed in detail. The preprocessing may include formatting and filtering (e g., thresholding) necessary to adapt the figure to the format and structures necessary for rendering.

[0037] The controller 400 further includes a bit plane generator 415 configured to generate a set of bit planes based on the image. The generation may result in a number of bit planes corresponding to the bit depth of the display. The bit planes can be written to a bit plane buffer 450 (i.e., memory), which can receive and store bit planes as they are generated.

[0038] The bit planes may be stored until all bit planes in a bit plane sequence are complete and ready for rendering. In a possible implementation compression (e.g., lossless compression) may be used to reduce the size (i.e., capacity ) of the bit plane buffer 450. The bit plane buffer 450 may be partitioned into segments defined by the memory’ locations associated with the segment. The segments can be configured to store particular bit planes. For example, pairs of bit planes may be written to each segment of the bit plane buffer 450.

[0039] As shown in FIG. 4, the controller 400 may further include a bit plane reader 455 configured to recall nonzero bit planes from the bit plane buffer 450. In particular, the bit plane reader may assemble the sequence of bit planes by recalling the bit planes from their respective segments in the bit plane buffer 450. In a possible implementation, the bit plane reader 455 may be further configured to decompress the recalled bit planes.

[0040] The controller 400 further includes a display post processor 460 that can create the weighted sequence of bit planes and the word-line and bit-line signals necessary for rendering the bit planes on the pixel array. For example, the display post processor 460 can include a sequence timing generator that is configured to control the timing of the bit periods of a rendering period. In other words, the display post processor 460 can generate PWM signals for the pixels of the display.

[0041] FIG. 5 is a schematic of a pixel for a micro-LED display according to a possible implementation of the present disclosure. As shown in FIG. 5, the pixel 500 includes a drive switch 520 coupled between a micro-LED 510 and a current source 521. The current source 521 may be part of the drive current module 140 shown in FIG. 1. The drive switch 520 can be in a short circuit state (i.e., ON-condition) so that the micro-LED 510 is illuminated (i.e., generates light) by the cunent of the current source 521. Alternatively, the drive switch 520can be in an open circuit state (i.e., OFF-condition) so that the micro-LED 510 is dark because it receives no current.

[0042] As shown in FIG. 5, the drive switch 520 can be controlled ON or OFF according to the state (i.e., the stored value) of a static random-access memory (SRAM 550) cell. The SRAM 550 receives power for operation from a power supply 511 which is coupled to each pixel of the pixel array 120. The SRAM 550 may be configured to output a HIGH voltage (e.g.. VDD) while in a HIGH state (i.e.. ON-state) or output a LOW voltage (e.g.. ground) while in a LOW state (i.e., OFF-state). An advantage of using an SRAM 550 to control the drive switch 520 is that while the SRAM 550 is in the HIGH-state (i.e., ON-state) or the LOW-state (i.e., OFF-state) it consumes very little current (e.g., approximately zero current) from the power supply 511. The SRAM 550 draws most of its current (e.g., approximately all of its current) as it transitions (i.e., is flipped) between states (i.e., during a write process).

[0043] As shown in FIG. 5, the SRAM 550 includes two inverters (i.e., a pair of inverters) coupled in parallel with their polarities reversed (i.e., coupled output to input). The pair of inverters function as a digital latch circuit (i.e.. latch 513). A write process (i.e., write operation) configures latch 513 into one of two states: an ON-state to output a signal corresponding to a logical HIGH (i.e., 1) and an OFF-state to output a signal corresponding to a logical LOW (i.e., 0).

[0044] As shown in FIG. 5, the pixel 500 further includes a bit line 515, and the state of the SRAM 550 may be flipped by bit-line signals (BL+, BL-) applied to the bit line 515. During the write process, the signals (BL+, BL-) are set to assert the desired state onto the latch 513. Once the desired state is set, the output of the latch 513 is stable and the signals (BL+, BL-) may be removed.

[0045] As shown in FIG. 5, the pixel 500 further includes a word line 514. During the write process, the latch circuit is coupled to the positive / negative signals of the bit line 515 by switches controlled by a signal (WL) transmitted on a word line 514. For example, a first level (e.g., HIGH) on the word line 514 turns the switches ON to couple the input / output of latch 513 to respective positive / negative lines of the bit line 515. A second level (e.g., LOW) on the word line 514 turns the switches OFF to decouple the input / output of the latch 513 from the bit-line drivers so that the state is stored. The state of the SRAM 550 appears as a voltage at the output of one of the inverters of the latch 513.

[0046] Changing the state of the latch (i.e., flipping the latch) can include changing the ON / OFF condition of the transistors. While the transistors are changing their condition (i.e.. transitioning), a low-resistance path to ground 512 may be created, and a shoot-throughcurrent may flow from the power supply 511 to the SRAM 550 until the transition is completed. Accordingly, in a possible implementation, the pixel 500 can include a currentlimiting transistor 575 to limit the current drawn by the SRAM during a write process. The current-limiting transistor 575 can biased according to the power supply 511 (VDD) and a bias voltage (VBIAS) to be in a partially-ON (i.e., partially-OFF) condition during the write process to clamp the current drawn by the SRAM 550.

[0047] The state of the SRAM may be toggled to form a PWM signal 590 that controls the drive switch 520 so that a drive current (ID) is received by the micro-LED 510 during the ON portions of the PWM signal 590. Ideally, the light 523, generated by the drive current (ID) matches the PWM signal 590, but due to a capacitance 580 (C) associated with the micro-LED 510, the light 523 may not be modulated to (precisely) match the PWM signal 590.

[0048] The capacitance 580 may result from the device physics of the micro-LED 510. For example, the capacitance 580 may be based on the size of the micro-LED, the drive current of the micro-LED and the color (i.e. wavelength) of the micro-LED. The capacitance can include a depletion layer capacitance (i.e.. depletion capacitance, space charge capacitance, juncti on capacitance, barrier capacitance, etc.). The depletion layer capacitance can be the capacitance generated by the space-charge separation in depletion layer between a P-type and N-type material (i.e. PN junction) within the micro-LED 510.

[0049] The capacitance can also include a quantum well capacitance. The micro-LED may include one or more quantum wells to confine charges in a particular area to increase the light-generating efficiency of the micro-LED 510. A quantum well may be a sandwich structure of different materials. Each of these structures may have an associated capacitance.

[0050] The capacitance 580 must be charged before the micro-LED 510 can generate light 523. One problem facing the pixel 500 is that the drive current (ID) may be very small (e.g., < 10 microamps) to minimize the power consumed by the pixel 500. As a result, the charging may be slower than desired (e.g., > 100 nanoseconds) for a PWM signal 590, especially when the frequency is high. This is further complicated by temperature effects which can change the current requirements of the micro-LED 510. Further, after the capacitance 580 is charged, it may be slower to discharge than desirable. The present disclosure describes a driver that includes circuitry to help charge the capacitance 580 and to help discharge the capacitance 580 after it is charged.

[0051] FIG. 6 is schematic of a pixel driver circuit for a display according to a possible implementation of the present disclosure. The pixel driver circuit 600 includes circuitry thatcan reduce a response time (i.e., tum-ON time) of a micro-LED 510 to an ON signal by charging (i.e., pre-charging) a capacitance 580, which is in a parallel connection with the micro-LED 510. As a result, the pixel driver circuit 600 can enable operation of the micro- LED 510 over a range of PWM frequencies that is larger than without the circuitry and does so in a way that consumes power efficiently.

[0052] The pixel driver circuit 600 includes a drive switch 640 coupled between a current source 521 and the micro-LED 510. The current source 521 can be a current source that the pixel shares with other pixels in the pixel array (e.g., see FIG. 1) or can be a current source that is dedicated to the pixel. The current source 521 is coupled to a power supply 511 to generate a drive current (ID). The drive current is conducted by the micro-LED 510 to a ground voltage 612 when the drive switch is in an ON condition. In a steady state (i.e., after the capacitance 580 is charged), the light 523 generated by the micro-LED 510 has qualities (e.g., brightness, color, etc.) that is based on the level of the drive current (ID). For example, the drive current may be controlled to a level based on a desired color of the light523 emitted by the micro-LED 510.

[0053] In a possible implementation, the current source 521 is controlled by a bias controller 620, which can adjust the drive current to accommodate for variations in the brightness of the micro-LED 510. The variations can be caused by process variations, and in this case, the bias controller 620 can adjust the brightness between pixels to minimize differences in brightness. The variations can be also caused by a temperature change, which can alter the drive current necessary for the micro-LED 510 to generate light of a particular brightness.

[0054] The drive current (ID) may be kept low (e.g., < 10 micro amps) to avoid overdriving the micro-LED 510. which can lead to color changes in the light emitted by the pixel. The drive current (ID) for each pixel may also be kept low to reduce the cumulative power consumed by the pixels in a display, which may include a large number (e.g., > 500 thousand) pixels. Each micro-LED may have a dimension (e.g., length, width) that is less than 10 microns.

[0055] The drive switch 640 can be a P-type metal oxide semiconductor (PMOS) transistor coupled at a source terminal (S) to the current source 521 and coupled at a drain terminal (D) to the micro-LED 510 (and the capacitance 580). The drive switch 640 can be configured in an ON condition (i.e., conducting) by a ON signal received at a gate terminal (G) of the drive switch 640 from a SRAM 550 and can be configured in an OFF condition (i.e., not conducting) by an OFF signal received at the gate terminal (G) from the SRAM 550.

[0056] The SRAM 550 is configured to output the ON signal or the OFF signal based on a corresponding ON signal or OFF signal generated by a sequence timing generator 610. In other words, the sequence timing generator 610 is configured to transmit an ON signal to the pixel driver circuit 600 to configure the drive switch 640 in the ON condition and is further configured to transmit an OFF signal to the pixel driver circuit 600 to configure the drive switch 640 in the OFF condition. In a possible implementation an ON signal is a first transition between binary levels, such as from a HIGH binary level (i.e., voltage) to a LOW binary level (i.e. voltage) and an OFF signal is a second transition between binary levels, such as from the LOW level to the HIGH level.

[0057] The ON signal and the OFF signal may trigger the pixel driver circuit 600 to operate according to timed sequence. In a possible implementation, the sequence timing generator 610 can control a charge timing generator 625 to generate a sequence of switching signals to control a charge switch 631 and a discharge switch 632.

[0058] The pixel driver circuit 600 includes the charge switch 631 coupled between a voltage source 615 and a source terminal (S) of the drive switch 640. An ON signal from the sequence timing generator 610 may configure the drive switch 640 in an ON condition and may configure (e.g., via the charge timing generator 625) the charge swatch 631 in the ON condition. In this condition, a voltage (Ven) generated by voltage source 615 may be coupled through the charge switch 631 and the drive switch 640 to the (uncharged) capacitance 580. This voltage may draw a charge cunent (ICH) from the voltage source 615. The charge current (ICH) drawn from the voltage source may be unregulated (i.e., uncontrolled) so can be much larger than the drive current (ID). For example, the charge current can be at least ten times greater than the drive current (e.g., ICH > 10 ID). Accordingly, the capacitance 580 may be charged to the voltage faster using the combination of drive current and charge current (i.e.. ID + ICH) than by the drive current alone. After a charge period (e.g., determine by the charge timing generator 625), the charge switch 631 may be configured, by the charge timing generator 625, in an OFF condition but the drive switch 640 can remain in the ON condition for the remainder of a drive period during (e.g., corresponding to a PWM signal).

[0059] The pixel driver circuit 600 includes the discharge switch 632 coupled between the drain terminal (D) of the drive switch 640 and the ground 512. The discharge switch 632 is in an OFF condition while the capacitance 580 is during the charge period and the drive period. An OFF signal from the sequence timing generator 610 may configure the drive switch 640 in an OFF condition and may configure (e.g., via the charge timing generator 625) the discharge switch 632 in the ON condition. The discharge switch 632 in the ON conditionmay conduct a discharge current from the capacitance 580. The discharge current (IDCH) drawn from the capacitance 580 may be unregulated and can be very large so that the capacitance 580 of the light 523 may be discharged very quickly. In other words, the discharge current may reduce a time to discharge the capacitance 580. After a discharge period (e.g., determined by the charge timing generator 625), the discharge switch 632 may be configured, by the charge timing generator 62, in an OFF condition.

[0060] In a possible implementation the voltage source 615 is a voltage regulator, such as a low dropout regulator (i.e. LDO). The voltage source 615 may receive an input voltage from a power supply 611 that may be higher than the voltage (Ven) at the output. The input voltage may or may not be equal to the voltage (VDD) of the power supply 511. In a possible implementation, the charge switch 631 is a PMOS transistor and the discharge switch 632 is an N-type metal oxide semiconductor (NMOS) transistor.

[0061] FIG. 7 is a timing diagram illustrating signals of a driver circuit according to a possible implementation of the present disclosure. The timing signal illustrates a charge period 711. a drive period 712, and a discharge period 713. The signals here may be part of a PWM signal corresponding to a gray scale level of a pixel (e.g., of a bit plane).

[0062] A drive signal 710 applied to a gate terminal (G) of the drive switch 640 is shown in the first graph. An ON signal 715 may be the first transition (e.g., falling edge) of the drive signal 710 from the HIGH level to the LOW level. The drive switch 640, being a PMOS transistor, is in an ON condition (i.e., active) while the drive signal 710 is LOW (i.e.. active level) and in an OFF condition while the drive signal 710 is HIGH. The drive signal 710 may be generated by the sequence timing generator 610. The micro-LED 510 is activated during the drive period 712. Accordingly, the drive period 712 may correspond to an ON portion of a PWM signal used to drive a pixel.

[0063] The ON signal 715 triggers a charge signal 720 to be applied to a gate terminal of the charge switch 631. The charge switch, being a PMOS transistor, is in an ON condition while the charge signal 720 is at the LOW level and in an OFF condition while the charge signal 720 is at the HIGH level. The charge signal 720 configures the charge switch in the ON condition for the charge period 71 1. After the charge period 711, the charge signal 720 returns to the HIGH level, which configures the charge switch in the OFF condition. The capacitance 580 is charged during the charge period 711. The charge signal 720 may be generated by the charge timing generator 625 based on the ON signal. For example, the ON signal 715 may trigger the charge timing generator 625 to turn ON the charge signal 720 andstart a counter that counts clock cycles until a predetermined number of clock cycles is counted, at which point the charge signal 720 may be turned OFF.

[0064] An OFF signal 725 may be the second transition (e.g., rising edge) of the drive signal 710 from the LOW level to the HIGH level. The OFF signal 725 configures the drive switch 640 in an OFF condition and triggers a discharge signal 730 to be applied to a gate terminal of the discharge switch 632. The discharge switch 632, being an NMOS transistor, is in an ON condition while the discharge signal 730 is HIGH (i.e., active) and in an OFF condition while the discharge signal 730 is LOW. The discharge signal 730 configures the discharge switch in the ON condition for the discharge period 713. After the discharge period 713. the discharge signal 730 returns to the LOW level, which configures the discharge switch in the OFF condition. The capacitance 580 is discharged during the discharge period 713. The discharge signal 730 may be generated by the charge timing generator 625 based on the OFF signal. For example, the OFF signal 725 may trigger the charge timing generator 625 to turn ON the discharge signal 730 and start a counter that counts clock cycles until a predetermined number of clock cycles is counted, at which point the discharge signal 730 may be turned OFF.

[0065] The discharge period 713 may be longer than the charge period 711. The charge period 711 may be tuned to balance capacitor charging with power consumption. The charge period 711 may correspond to the time required to illuminate the micro-LED and therefore may be minimized so that the micro-LED can be illuminated quickly. As result the charge period 71 1 may be a small portion (e g., < 1 %) ofthe drive period 712. A charge period that is too long can overdrive the micro-LED and change its color. A charge period that is too short cannot completely charge the capacitance so that the LED is not fully illuminated at the end of the charge period. The charge period may be a die trimmable characteristic of the pixel driver circuit.

[0066] FIG. 8 is a state diagram of a pixel driver circuit for a display according to a possible implementation of the present disclosure. As shown, an ON signal may configure the pixel driver circuit in a charge state 810. In the charge state 810, the drive switch and the charge switch are in the ON condition to charge the capacitance, while the discharge switch is in the OFF condition to prevent the capacitance from being discharged. After a charge period has ended, the pixel driver circuit may be configured in an ON state 820. In the ON state 820, the drive switch is in the ON condition to illuminate the micro-LED. If. at the end of a drive period, another ON signal is received, the pixel driver circuit may remain in the ON state 820. If, at the end of a drive period an OFF signal is received the pixel driver circuitmay be configured in a discharge state 830. In the discharge state 830 the drive switch and the charge switch are in the OFF condition to prevent charging the capacitance, while the discharge switch is in the ON condition to discharge the capacitance. After a discharge period has ended, the pixel drive circuit may be configured in an OFF state 840. In the OFF state the drive switch, the charge switch, and the discharge switch are OFF. The pixel driver circuit may remain in the OFF state as long as OFF signals are received. Upon receiving an ON signal, however, the pixel driver circuit may return to the charge state 810.

[0067] FIG. 9 is a flowchart of a method for driving a pixel of a display according to a possible implementation of the present disclosure. The method 900 includes configuring 910 a drive switch in an ON condition based on (i.e., in response to) an ON signal 901 received at a pixel (e.g., from a sequence timing generator of the display). The drive switch in the ON condition can conduct a drive current (ID) to the pixel (e.g., to an LED of the pixel). The method 900 further includes configuring 920 a charge switch in an ON condition based on (i.e., in response to) the ON signal 901 received at the pixel. The charge switch in the ON condition can conduct a charge current (ICH). which may be larger than the drive current, to the pixel. The method 900 further includes charging 930 the capacitance (e.g.. depletion region capacitance, quantum well capacitance) of the pixel using the drive current and the charge current. The charging can be completed faster using the charge current compared to using the drive current alone. The charging can continue for a charge period. After determining 935 that the charge period has ended, the method 900 includes configuring 940 the charge switch in an OFF condition to not conduct (i.e. block) the charge current to the pixel and illuminating 950 the pixel using the drive current.

[0068] FIG. 10 is a flowchart of a method for driving a pixel of a display OFF according to a possible implementation of the present disclosure. The method 1000 includes configuring 1010 a drive switch in an OFF condition based on (i.e., in response to) an OFF signal 1001 received at a pixel (e.g., from a sequence timing generator of the display). The drive switch in the OFF condition does not conduct the drive current (ID) to the pixel. The charge switch is in the OFF condition already when the OFF signal 1001 is received. The method 1000 further includes configuring 1020 a discharge switch in an ON condition based on (i.e., in response to) the ON signal 901 received at the pixel. The discharge switch in the ON condition can conduct a discharge current (IDCH) from the pixel to a ground voltage. The method 1000 further includes discharging 1030 the capacitance (e.g., depletion region capacitance, quantum well capacitance) of the pixel using the discharge current (IDCH). The discharging can be completed faster using the discharge current compared to allowing thepixel to discharge without being short circuited to the ground voltage. The discharging can continue for a discharge period. After determining 1035 that the discharge period has ended, the method 1000 includes configuring 1040 the discharge switch in an OFF condition to not conduct (i.e. block) the discharge current from the pixel. For example, turning OFF the discharge switch can remove the ground voltage from being applied to the anode of an LED of the pixel.

[0069] In the specification and / or figures, typical embodiments have been disclosed. The present disclosure is not limited to such exemplary embodiments. The use of the term “and / or” includes any and all combinations of one or more of the associated listed items. The figures are schematic representations and so are not necessarily drawn to scale. Unless otherwise noted, specific terms have been used in a generic and descriptive sense and not for purposes of limitation.

[0070] Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. Methods and materials similar or equivalent to those described herein can be used in the practice or testing of the present disclosure. As used in the specification, and in the appended claims, the singular forms “a,” “an,” “the” include plural referents unless the context clearly dictates otherwise. The term “comprising” and variations thereof as used herein is used synonymously with the term “including” and variations thereof and are open, non-limiting terms. The terms “optional” or “optionally” used herein mean that the subsequently described feature, event or circumstance may or may not occur, and that the description includes instances where said feature, event or circumstance occurs and instances where it does not. Ranges may be expressed herein as from "about" one particular value, and / or to "about" another particular value. When such a range is expressed, an aspect includes from the one particular value and / or to the other particular value. Similarly, when values are expressed as approximations, by use of the antecedent "about," it will be understood that the particular value forms another aspect. It will be further understood that the endpoints of each of the ranges are significant both in relation to the other endpoint, and independently of the other endpoint.

[0071] While certain features of the described implementations have been illustrated as described herein, many modifications, substitutions, changes and equivalents will now occur to those skilled in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the scope of the implementations. It should be understood that they have been presented by way of exampleonly, not limitation, and various changes in form and details may be made. Any portion of the apparatus and / or methods described herein may be combined in any combination, except mutually exclusive combinations. The implementations described herein can include various combinations and / or sub-combinations of the functions, components and / or features of the different implementations described.

[0072] It will be understood that, in the foregoing description, when an element is referred to as being on, connected to, electrically connected to, coupled to, or electrically coupled to another element, it may be directly on, connected or coupled to the other element, or one or more intervening elements may be present. In contrast, when an element is referred to as being directly on, directly connected to or directly coupled to another element, there are no intervening elements present. Although the terms directly on, directly connected to, or directly coupled to may not be used throughout the detailed description, elements that are shown as being directly on, directly connected or directly coupled can be referred to as such. The claims of the application, if any, may be amended to recite exemplary7relationships described in the specification or shown in the figures.

[0073] As used in this specification, a singular form may. unless definitely indicating a particular case in terms of the context, include a plural form. Spatially relative terms (e g., over, above, upper, under, beneath, below, low er, and so forth) are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. In some implementations, the relative terms above and below can, respectively, include vertically above and vertically below. In some implementations, the term adjacent can include laterally adjacent to or horizontally adjacent to.

Claims

WHAT IS CLAIMED IS:

1. A method for driving a pixel of a display, the method comprising: configuring a drive switch in an ON condition based on an ON signal received from a sequence timing generator of the display, the drive switch coupled between a current source and an LED of the pixel, configuring a charge switch in the ON condition for a charge period based on the ON signal, the charge switch coupled between a voltage source and the drive switch of the pixel; conducting a drive current from the current source to the LED through the drive switch in the ON condition; conducting a charge current from the voltage source to the LED through the charge switch in the ON condition; and charging a capacitance of the LED with the drive current and the charge current during the charge period.

2. The method for driving the pixel of the display according to claim 1 , further comprising: configuring the charge switch in an OFF condition after the charge period; and continue to illuminate the LED after the charge period using the drive current without the charge current.

3. The method for driving the pixel of the display according to claim 1 or 2, further comprising: receiving an OFF signal from the sequence timing generator after a drive period; configuring the drive switch in the OFF condition based on the OFF signal; and configuring, based on the OFF signal, a discharge switch, coupled between the LED and a ground voltage, in the ON condition for a discharge period to conduct a discharge current to discharge the capacitance of the LED.

4. The method for driving the pixel of the display according to claim 3, further comprising,receiving other ON signals and other OFF signals from the sequence timing generator according to a pulse width modulation signal corresponding to a gray scale level for the pixel.

5. The method for driving the pixel of the display according to any one of the preceding claims, wherein: the drive current is controlled to a level based on a color of light emitted by the LED.

6. The method for driving the pixel of the display according to any one of claim 1 to 4, wherein: the charge current is uncontrolled and based on the capacitance of the LED being charged to a voltage generated by the voltage source.

7. The method for driving the pixel of the display according to any one of the preceding claims, wherein the charge current is at least ten times greater than the drive current.

8. A pixel driver circuit for a display, the pixel driver circuit comprising: a drive switch coupled to a current source; the drive switch configured in an ON condition by an ON signal received from a sequence timing generator; a charge switch coupled between a voltage source and the drive switch, the charge switch configured in the ON condition for a charge period by the ON signal; and an LED coupled to the drive switch, the LED configured to: receive a drive current from the current source through the drive switch in the ON condition; and receive a charge current from the voltage source through the charge switch in the ON condition, a capacitance of the LED being charged by the charge current and the drive current during the charge period.

9. The pixel driver circuit for the display according to claim 8. wherein: the charge switch is configured in an OFF condition after the charge period; and the drive switch remains in the ON condition after the charge period until an OFF signal is received from the sequence timing generator.

10. The pixel driver circuit for the display according to claim 8 or 9, wherein the charge current is at least ten times greater than the drive current.

11. The pixel driver circuit for the display according to any one of claims 8 to 10, wherein: the LED is a micro-LED having a dimension that is less than 10 microns; and the LED is a pixel of the display.

12. The pixel driver circuit for the display according to any one of claims 8 to 11, wherein: the charge switch is a p-t pe metal oxide semiconductor (PMOS) transistor.

13. The pixel driver circuit for the display according to any one of claims 8 to 12, further comprising: an SRAM memory coupled between the sequence timing generator and the drive switch, the drive switch being a p-type metal oxide semiconductor (PMOS) transistor.

14. The pixel driver circuit for the display according to any one of claims 8 to 13, wherein: the sequence timing generator is configured to generate an OFF signal after a drive period; the drive switch is configured in an OFF condition by the OFF signal; and a discharge switch, coupled between the LED and a ground voltage, is configured in the ON condition for a discharge period by the OFF signal.

15. The pixel driver circuit for the display according to claim 14, wherein: the discharge switch is an N-type metal oxide semiconductor (NMOS) transistor, the discharge switch conducting a discharge current to discharge the capacitance of the LED during the discharge period.

16. The pixel driver circuit for the display according to any one of claims 8 to 15, wherein: the capacitance includes a depletion region capacitance and a quantum well capacitance of the LED.

17. A display comprising: a pixel array; anda sequence timing generator configured to generate ON signals and an OFF signals to control pixels in the pixel array based on an image, wherein each pixel includes: a drive switch coupled to a current source, the drive switch configured in an ON condition based on an ON signal received from the sequence timing generator; a charge switch coupled between a voltage source and the drive switch, the charge switch configured in the ON condition for a charge period based on the ON signal; and an LED coupled to the drive switch, the LED configured to: receive a drive current from the current source through the drive switch in the ON condition; and receive a charge current from the voltage source through the charge switch in the ON condition, a capacitance of the LED being charged by the charge current and the drive current during the charge period.

18. The display according to claim 17. wherein: the drive switch is configured in the ON condition for a drive period between the ON signal and an OFF signal received from the sequence timing generator; and the charge period is a portion of the drive period, the charge switch being configured in the ON condition for the portion of the drive period and in an OFF condition otherwise.

19. The display according to claim 17 or 18, wherein each pixel further includes: a discharge switch coupled between the LED and a ground voltage, the discharge switch configured in the ON condition based on the OFF signal received from the sequence timing generator, wherein the discharge switch in the ON condition conducts a discharge current to discharge the capacitance after the drive period.

20. The display according to any one of claims 17 to 19, wherein the ON signals and the OFF signals generated by the sequence timing generator correspond to a bit plane sequence.

Images