High-transient-immunity gallium nitride transistor die and transistor chip

Abstract

Embodiments of the present disclosure relate to the field of transistors. Disclosed are a high-transient-immunity gallium nitride transistor die and a transistor chip. The high-transient-immunity gallium nitride transistor die comprises: a gallium nitride die body; a power transistor, arranged on the gallium nitride die body; and a first driving transistor, arranged on the gallium nitride die body, the first driving transistor being connected to a controlled end of the power transistor, and the first driving transistor being used for driving the power transistor to be turned on or off on the basis of a control signal. The power transistor and the first driving transistor are integrated on the same gallium nitride die body, and in the process of driving the power transistor by the first driving transistor, the parasitic resistance and parasitic inductance can be reduced without a wire, so that the transient immunity of the power transistor is improved, thereby reducing the switching loss of the power transistor and improving the power efficiency of the power transistor, and thus improving the performance of the power transistor on the gallium nitride die body.

Description

A gallium nitride transistor bare crystal and transistor chip with high transient immunity Technical Field

[0001] The present invention relates to the field of transistor technology, and in particular to a gallium nitride transistor bare crystal and a transistor chip with high transient immunity. Background Art

[0002] Gallium nitride (GaN) power tubes are high-performance power semiconductor devices with excellent high-frequency characteristics, high power density, fast response, wide operating temperature range and low switching loss. They are widely used in high-frequency, high-power scenarios.

[0003] In the prior art, referring to Figure 1, when GaN power tubes are used, a driving circuit on a silicon die (Si Die) is generally used. The silicon die and the GaN die (GaN Die) are connected by wire bonding or other means to connect the driving circuit on the silicon die to the GaN power tube on the GaN die. The driver drives the GaN power tube to turn on and off to operate.

[0004] However, the parasitic resistance (R par ) and parasitic inductance (L par ), which will affect the transient immunity of the GaN power tube, resulting in increased switching loss of the GaN power tube and reduced power efficiency, thereby reducing the performance of the GaN power tube.

[0005] Summary of the Invention

[0006] The present invention provides a gallium nitride transistor bare die and transistor chip with high transient immunity, which are used to solve the problem in the prior art that the parasitic resistance and parasitic inductance of the wires reduce the performance of the gallium nitride power transistor, thereby achieving the purpose of reducing switching losses and improving power efficiency.

[0007] The present invention provides a gallium nitride transistor bare crystal with high transient immunity, comprising: a gallium nitride bare crystal body; a power transistor, disposed on the gallium nitride bare crystal body; and a first driving transistor, disposed on the gallium nitride bare crystal body, the first driving transistor being connected to a controlled end of the power transistor and configured to drive the power transistor to be turned on or off according to a control signal.

[0008] According to a high transient immunity gallium nitride transistor bare die provided by the present invention, the power transistor is a first enhancement-mode gallium nitride high electron mobility transistor, and the first driving transistor is a second enhancement-mode gallium nitride high electron mobility transistor.

[0009] According to a high transient immunity gallium nitride transistor bare die provided by the present invention, the gate of the first enhancement-mode gallium nitride high electron mobility transistor is connected to the drain of the second enhancement-mode gallium nitride high electron mobility transistor, and the source of the first enhancement-mode gallium nitride high electron mobility transistor is connected to the source of the second enhancement-mode gallium nitride high electron mobility transistor.

[0010] According to a high transient immunity gallium nitride transistor bare die provided by the present invention, a drain pad, a first power gate pad, a first source pad, and a first drive gate pad are provided on the gallium nitride bare die body. The drain pad is connected to the drain of the first enhancement-mode gallium nitride high electron mobility transistor, the first power gate pad is respectively connected to the gate of the first enhancement-mode gallium nitride high electron mobility transistor and the drain of the second enhancement-mode gallium nitride high electron mobility transistor, the first source pad is respectively connected to the source of the first enhancement-mode gallium nitride high electron mobility transistor and the source of the second enhancement-mode gallium nitride high electron mobility transistor, and the first drive gate pad is connected to the gate of the second enhancement-mode gallium nitride high electron mobility transistor.

[0011] According to a high transient immunity gallium nitride transistor die provided by the present invention, the power transistor includes a plurality of sub-transistors connected in parallel, each of the sub-transistors including a first gate component, a first drain component, and a first source component disposed on the gallium nitride die body; the first driver transistor includes a second gate component, a second drain component, and a second source component; the first gate component is connected to the second drain component, and the connection distance between each of the first gate components and the second drain component is equal.

[0012] According to a high transient immunity gallium nitride transistor bare die provided by the present invention, the first gate member, the first drain member, and the first source member of each sub-transistor are all strip-shaped and arranged parallel to each other, the second gate member, the second drain member, and the second source member are all strip-shaped and arranged parallel to each other, and the first gate member and the second source member are arranged perpendicularly.

[0013] The present invention also provides a transistor chip, comprising the above-mentioned high transient immunity gallium nitride transistor bare crystal, and also comprising a silicon bare crystal body, on which a second driving transistor is provided, and the second driving transistor is connected to the controlled end of the power transistor.

[0014] According to a transistor chip provided by the present invention, the first driving transistor and the second driving transistor form a push-pull circuit.

[0015] According to a transistor chip provided by the present invention, the first driving transistor is a second enhancement-mode gallium nitride high electron mobility transistor, the second driving transistor is a P-doped field-effect transistor, the drain of the P-doped field-effect transistor is respectively connected to the controlled end of the power transistor and the drain of the second enhancement-mode gallium nitride high electron mobility transistor, and the gate of the second enhancement-mode gallium nitride high electron mobility transistor is connected to the gate of the P-doped field-effect transistor.

[0016] According to a transistor chip provided by the present invention, it also includes an amplification module arranged on the silicon bare crystal body, the output end of the amplification module is respectively connected to the controlled end of the first driving transistor and the controlled end of the second driving transistor, and the input end of the amplification module is used to receive a control signal.

[0017] According to a transistor chip provided by the present invention, the amplification module includes a first amplification unit and a second amplification unit, the input end of the first amplification unit is connected to the input end of the second amplification unit, the output end of the first amplification unit is connected to the controlled end of the first driving transistor, and the output end of the second amplification unit is connected to the controlled end of the second driving transistor.

[0018] According to a transistor chip provided by the present invention, a power supply pad, a control signal pad, a ground pad, a second power gate pad, a second drive gate pad and a second source pad are provided on the silicon bare crystal body, the power supply pad is respectively connected to the source of the P-doped field effect transistor and the amplifier module, the control signal pad is connected to the input end of the amplifier module, the ground pad is connected to the amplifier module and the ground pad is connected to the power transistor through the second source pad, the second power gate pad is respectively connected to the drain of the P-doped field effect transistor, the controlled end of the power transistor and the first drive transistor, and the second drive gate pad is respectively connected to the output end of the amplifier module and the drive end of the first drive transistor.

[0019] The present invention provides a high transient immunity gallium nitride transistor die, which has at least the following beneficial effects: by integrating a power transistor and a first driver transistor on the gallium nitride die body, the first driver transistor is turned on or off according to a control signal from the controlled terminal, which can change the voltage at the controlled terminal of the power transistor connected thereto, thereby achieving the purpose of turning the power transistor on or off. By integrating the power transistor and the first driver transistor on the same gallium nitride die body, the first driver transistor does not need to pass through a wire when driving the power transistor, which can reduce parasitic resistance and parasitic inductance, improve the transient immunity of the power transistor, and further reduce the switching loss of the power transistor and improve the power efficiency of the power transistor, which is conducive to improving the performance of the power transistor on the gallium nitride die body. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the present invention or the prior art, a brief introduction is given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0021] FIG1 is a schematic diagram of the application structure of an existing gallium nitride power tube;

[0022] FIG2 is a schematic diagram of a structure based on integrated GaN bare crystal;

[0023] FIG3 is a schematic structural diagram of a gallium nitride transistor bare die and chip with high transient immunity provided by the present invention;

[0024] FIG4 is a schematic structural diagram of part A in FIG3 ;

[0025] FIG5 is a layout diagram of a bare die of a gallium nitride transistor with high transient immunity provided by the present invention.

[0026] Figure markings: 100: GaN bare crystal body; 110: power transistor; 111: sub-transistor; 120: first driving transistor; 130: drain pad; 140: first power gate pad; 150: first source pad; 160 first driving gate pad; 200: silicon bare crystal body; 210: second driving transistor; 220: amplification module; 221: first amplification unit; 222: second amplification unit; 230: power supply pad; 240: control signal pad; 250: ground pad; 260 second power gate pad; 270: second driving gate pad; 280 second source pad. DETAILED DESCRIPTION

[0027] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure and not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present disclosure.

[0028] The following describes a high transient immunity gallium nitride transistor die according to the present invention in conjunction with Figures 3 to 5, including: a gallium nitride die body 100; a power transistor 110, disposed on the gallium nitride die body 100; and a first driver transistor 120, disposed on the gallium nitride die body 100. The first driver transistor 120 is connected to a controlled terminal of the power transistor 110 and is configured to drive the power transistor 110 to be turned on or off according to a control signal.

[0029] By integrating the power transistor 110 and the first driver transistor 120 on the gallium nitride die body 100, the first driver transistor 120 is turned on or off according to a control signal from the controlled terminal, thereby changing the voltage at the controlled terminal of the power transistor 110 connected thereto, thereby turning the power transistor 110 on or off. By integrating the power transistor 110 and the first driver transistor 120 on the same gallium nitride die body 100, the first driver transistor 120 drives the power transistor 110 without the need for wires, thereby reducing parasitic resistance and parasitic inductance, improving the transient immunity of the power transistor 110, and thereby reducing switching losses and improving the power efficiency of the power transistor 110. This facilitates improved performance of the power transistor 110 on the gallium nitride die body 100.

[0030] It should be noted that the gallium nitride bare crystal body 100 includes gallium nitride material, rather than being made solely of gallium nitride material. In some embodiments of the present invention, the gallium nitride bare crystal body 100 may include a silicon substrate, an insulating layer, a single crystal silicon layer, a gallium nitride layer, an aluminum gallium nitride layer, and a circuit layer.

[0031] 3 , in some embodiments of a high transient immunity GaN transistor die according to the present invention, the power transistor 110 is a first enhancement-mode GaN high electron mobility transistor, and the first driver transistor 120 is a second enhancement-mode GaN high electron mobility transistor.

[0032] The power transistor 110 and the first driver transistor 120 are both enhancement-mode gallium nitride high electron mobility transistors, i.e., GaN E-HEMT tubes. The heterojunction of the GaN E-HEMT tube forms a two-dimensional electron gas layer, which makes the GaN E-HEMT tube have the advantages of high electron mobility, high saturation electron velocity and high breakdown electric field.

[0033] It should be noted that although the power transistor 110 and the first driver transistor 120 are both enhancement-mode GaN high-electron-mobility transistors, their design parameters are different, and the process parameters during actual manufacturing are different, resulting in different specific performance of the two enhancement-mode GaN high-electron-mobility transistors. The first enhancement-mode GaN high-electron-mobility transistor, which serves as the power transistor 110, has greater current and voltage tolerances.

[0034] 3 , in some embodiments of the present invention, the gate of the first enhancement-mode GaN-HEMT is connected to the drain of the second enhancement-mode GaN-HEMT, and the source of the first enhancement-mode GaN-HEMT is connected to the source of the second enhancement-mode GaN-HEMT.

[0035] The source of the first enhancement-mode GaN high-electron-mobility transistor (EMG-HEM), serving as power transistor 110, is generally grounded. The drain of the second EMG-HEM transistor is connected to the gate of the first field-effect transistor, and the source of the second EMG-HEM transistor is connected to the source of the first field-effect transistor, i.e., also grounded. When the second EMG-HEM transistor is turned on, it can pull down the gate potential of the first EMG-HEM transistor, thereby controlling the first EMG-HEM transistor to be turned off. Because the source of the second field-effect transistor is grounded, i.e., the source potential is fixed, controlling the second EMG-HEM transistor only requires controlling the gate voltage of the second EMG-HEM transistor to be greater than or less than the conduction threshold. Using the second EMG-HEM transistor as a pull-down transistor helps simplify the control signal design.

[0036] In some embodiments of the present invention, the second enhancement-mode GaN high-electron-mobility transistor can also be used as a pull-up transistor. The source of the second enhancement-mode GaN high-electron-mobility transistor is connected to the gate of the first enhancement-mode GaN high-electron-mobility transistor, and the drain of the second enhancement-mode GaN high-electron-mobility transistor is connected to a power supply. When the second enhancement-mode GaN high-electron-mobility transistor is turned on, it can pull up the gate potential of the first enhancement-mode GaN high-electron-mobility transistor, thereby controlling the conduction of the first field-effect transistor.

[0037] Based on the above two situations, it should be noted that the first driving transistor 120 only needs to be able to determine whether the control power transistor 110 is operating in at least one of the on and off states, and is not required to be able to control the power transistor 110 to determine whether it is in the on or off state one by one.

[0038] 3 , in some embodiments of a high transient immunity gallium nitride transistor bare crystal of the present invention, a drain pad 130, a first power gate pad 140, a first source pad 150, and a first driver gate pad 160 are provided on the gallium nitride bare crystal body 100. The drain pad 130 is connected to the drain of the first enhancement-mode gallium nitride high electron mobility transistor, the first power gate pad 140 is respectively connected to the gate of the first enhancement-mode gallium nitride high electron mobility transistor and the drain of the second enhancement-mode gallium nitride high electron mobility transistor, the first source pad 150 is respectively connected to the source of the first enhancement-mode gallium nitride high electron mobility transistor and the source of the second enhancement-mode gallium nitride high electron mobility transistor, and the first driver gate pad 160 is connected to the gate of the second enhancement-mode gallium nitride high electron mobility transistor.

[0039] GaN die body 100 is provided with a drain pad 130, a first power gate pad 140, a first source pad 150, and a first driver gate pad 160. These facilitate connection to other die or pins via wire bonding or other processing methods, thereby achieving electrical connections between power transistor 110, first driver transistor 120, and other devices. Drain pad 130 is typically used for connection to a power load. This structure makes GaN die body 100 more convenient for actual soldering and packaging.

[0040] 5 , in some embodiments of a high transient immunity gallium nitride transistor die according to the present invention, the power transistor 110 includes a plurality of sub-transistors 111 connected in parallel. The sub-transistors 111 include a first gate component, a first drain component, and a first source component disposed on the gallium nitride die body 100. The first driver transistor 120 includes a second gate component, a second drain component, and a second source component. The first gate component is connected to the second drain component, and the connection distances between each of the first gate components and the second drain components are equal.

[0041] Multiple sub-transistors 111 are connected in parallel to form a power transistor 110, which can optimize parameters such as the maximum current value and withstand voltage of the power transistor 110, thereby improving the performance of the power transistor 110. The sub-transistors 111 are GaN E-HEMT transistors. Each sub-transistor 111 includes a first gate element, a first drain element, and a first source element. The first drain elements of each sub-transistor 111 are interconnected, and the first source elements are interconnected, achieving the purpose of connecting the sub-transistors 111 in parallel, thereby forming the power transistor 110. The connection distance between the first gate element of each sub-transistor 111 and the second drain element of the first driver transistor 120 is equal. The first gate element and the second drain element are connected. When the first driver transistor 120 drives the power transistor 110 on and off, the voltage change of the second drain element can simultaneously affect the voltage of each first gate element, avoiding the problem of asynchronous turning on and off of the sub-transistors 111 due to different connection distances, which is beneficial to improving the reliability and performance of the power transistor 110.

[0042] 5 , in some embodiments of a high transient immunity gallium nitride transistor bare die of the present invention, the first gate member, the first drain member, and the first source member of each of the sub-transistors 111 are all strip-shaped and arranged parallel to each other, the second gate member, the second drain member, and the second source member are all strip-shaped and arranged parallel to each other, and the first gate member and the second source member are arranged perpendicularly.

[0043] The first gate element, the first drain element and the first source element of each sub-transistor 111 are arranged parallel to each other, the second gate element, the second drain element and the second source element of the first driving transistor 120 are arranged parallel to each other, and the first gate element and the second source element are arranged perpendicularly, that is, the first gate element, the first drain element and the first source element are perpendicular to the second gate element, the second drain element and the second source element. With this structure, the distance between each first gate element and the second drain element can be easily made equal, and the structure is more regular, which is convenient for designing the layout.

[0044] In a conventional structure, a metal layer is provided to connect the gates of all sub-transistors 111, and then the metal layer is connected to the drain of the first driver transistor 120 at a single point. Due to the single-point connection, the distances between the first driver transistor 120 and the gates of each sub-transistor 111 vary, resulting in different clamping effects for different gates. In the present application, referring to FIG5 , in which G represents the gate, S represents the source, and D represents the drain, the first gate of each sub-transistor 111 is connected to the second drain of the first driver transistor 120 at the nearest connection distance, and the gates of each sub-transistor 111 are connected to the drain of the first driver transistor 120 at the same distance, resulting in a consistent gate clamping effect for each sub-transistor 111 in the power transistor 110.

[0045] 3 and 4 , the present invention further provides a transistor chip, comprising the above-mentioned high transient immunity gallium nitride transistor bare crystal, and also comprising a silicon bare crystal body 200 , on which a second driving transistor 210 is provided, and the second driving transistor 210 is connected to the controlled end of the power transistor 110 .

[0046] By connecting the second driver transistor 210 on the silicon die body 200 to the controlled terminal of the power transistor 110 on the gallium nitride die body 100, the second driver transistor 210 cooperates with the first transistor to drive and control the operating state of the power transistor 110 according to a control signal. Because the power transistor 110 and the first driver transistor 120 are integrated on the same gallium nitride die body 100, the first driver transistor 120 drives the power transistor 110 without the need for wires. This reduces parasitic resistance and inductance, improves the transient immunity of the power transistor 110, and further reduces switching losses and improves the power efficiency of the power transistor 110, thereby improving the performance of the power transistor 110 on the gallium nitride die body 100.

[0047] 3 and 4 , in some embodiments of a transistor chip according to the present invention, the first driving transistor 120 and the second driving transistor 210 form a push-pull circuit.

[0048] The first driver transistor 120 and the second driver transistor 210 can form two devices with complementary outputs. Furthermore, the first driver transistor 120 and the second driver transistor 210 can be connected to form a push-pull circuit. During operation, one of the first driver transistor 120 and the second driver transistor 210 is turned on, while the other is turned off. Using the push-pull circuit to drive the power transistor 110 can more quickly change the voltage at the controlled terminal of the power transistor 110, thereby increasing the response speed of the power transistor 110, thereby further reducing the switching loss of the power transistor 110 and improving the efficiency of the power transistor 110.

[0049] On the gallium nitride die 100, the circuit structure required to drive the power transistor 110 based on a control signal is complex. As shown in the circuit of Figure 2, an additional circuit module must be added after the PWM terminal to process the control signal in order to achieve the effect of controlling one of the two transistors to be turned on and the other to be turned off during operation. This leads to complex design and high cost. In addition, this structure has the disadvantage of large static current.

[0050] By adopting the aforementioned transistor chip structure, both N-type and P-type transistors can be easily fabricated on the silicon die body 200. The type of the second driver transistor 210 can be designed as required, enabling one of the first driver transistor 120 and the second driver transistor 210 to be turned on and the other turned off under the same control signal, thereby achieving rapid control of the operating state of the power transistor 110. This structure utilizes the respective characteristics of the silicon die body 200 and the gallium nitride die body 100, fabricating the second driver transistor 210 on the silicon die body 200, thereby reducing circuit design complexity and manufacturing costs. Fabricating the power transistor 110 and the first driver transistor 120 on the gallium nitride die body 100 improves the transient immunity of the power transistor 110, reduces switching losses of the power transistor 110, and improves the power efficiency of the power transistor 110, thereby achieving a balanced circuit design complexity, manufacturing costs, and improved power transistor performance. Furthermore, this structure can reduce quiescent current.

[0051] 3 and 4 , in some embodiments of a transistor chip according to the present invention, the first driver transistor 120 is a second enhancement-mode GaN high-electron-mobility transistor, the second driver transistor 210 is a P-doped field-effect transistor, the drain of the P-doped field-effect transistor is respectively connected to the controlled end of the power transistor 110 and the drain of the second enhancement-mode GaN high-electron-mobility transistor, and the gate of the second enhancement-mode GaN high-electron-mobility transistor is connected to the gate of the P-doped field-effect transistor.

[0052] By fabricating a P-doped field-effect transistor on the silicon die body 200 as the second driving transistor 210, the drain of the P-doped field-effect transistor is connected to the drain of the second enhancement-mode GaN high-electron-mobility transistor to form a push-pull circuit, which is conducive to simplifying the circuit design. Generally, the source of the P-doped field-effect transistor is connected to the power supply terminal, and the source of the second enhancement-mode GaN high-electron-mobility transistor is grounded. When the P-doped field-effect transistor is turned on and the second enhancement-mode GaN high-electron-mobility transistor is turned off, the voltage at the controlled terminal of the power transistor 110 can be quickly increased; when the P-doped field-effect transistor is turned off and the second enhancement-mode GaN high-electron-mobility transistor is turned on, the charge at the controlled terminal of the power transistor 110 can be quickly released to quickly reduce the voltage at the controlled terminal of the power transistor 110, thereby achieving the effect of quickly controlling the working state of the power transistor 110.

[0053] In addition, the push-pull circuit structure only needs to control the gate voltage to accurately control the working state of the transistor, which is conducive to simplifying the control signal design.

[0054] Referring to Figures 3 and 4, in some embodiments of a transistor chip of the present invention, it also includes an amplification module 220 arranged on the silicon bare crystal body 200, and the output end of the amplification module 220 is respectively connected to the controlled end of the first driving transistor 120 and the controlled end of the second driving transistor 210, and the input end of the amplification module 220 is used to receive a control signal.

[0055] The input end of the amplifier module 220 receives a control signal and, after amplifying the control signal, transmits it to the controlled end of the first driver transistor 120 and the controlled end of the second driver transistor 210, namely, the gate of the second enhancement-mode GaN high-electron-mobility transistor and the gate of the P-doped field-effect transistor. This ensures that the amplified control signal can drive the P-doped field-effect transistor and the second enhancement-mode GaN high-electron-mobility transistor to switch to the desired operating state. The provision of the amplifier module 220 thus reduces the driving capability requirements of the control signal and improves the reliability of the control signal driving the first driver transistor 120 and the second driver transistor 210.

[0056] It should be noted that the amplifier module 220 on the silicon die body 200 transmits the amplified control signal to the controlled terminal of the first driver transistor 120 via a wire. Although the parasitic resistance and parasitic inductance on the wire will affect the first driver transistor 120, the first driver transistor 120 can reduce the impact of the parasitic resistance and parasitic inductance on the transient immunity of the power transistor 110. It can be considered that the impact of the parasitic resistance and parasitic inductance of the wire is transferred to the first driver transistor 120. Since the operating power of the first driver transistor 120 is lower than the operating power of the power transistor 110, the switching loss generated by the first driver transistor 120 due to the parasitic resistance and parasitic inductance is significantly reduced compared to the power transistor 110, and the transient immunity of the power transistor 110 can be improved, thereby reducing the switching loss of the power transistor 110 and improving the power efficiency of the power transistor 110.

[0057] In some embodiments of the present invention, the control signal may be a PWM (Pulse Width Modulation) signal.

[0058] 3 and 4 , in some embodiments of a transistor chip of the present invention, the amplification module 220 includes a first amplification unit 221 and a second amplification unit 222, the input end of the first amplification unit 221 is connected to the input end of the second amplification unit 222, the output end of the first amplification unit 221 is connected to the controlled end of the first driving transistor 120, and the output end of the second amplification unit 222 is connected to the controlled end of the second driving transistor 210.

[0059] The same control signal is inputted through the input ends of the first amplifying unit 221 and the second amplifying unit 222. The first amplifying unit 221 amplifies the control signal and transmits it to the first driving transistor. The second amplifying unit 222 amplifies the control signal and transmits it to the second driving transistor 210. In this way, the first driving transistor and the second driving transistor 210 are driven by the first amplifying unit 221 and the second amplifying unit 222 respectively, which can reduce the driving capability requirements of the first amplifying unit 221 and the second amplifying unit 222 separately.

[0060] In some embodiments of the present invention, the first amplifying unit 221 and the second amplifying unit 222 may be implemented as a transistor amplifier circuit, a bootstrap circuit, or an integrated operational amplifier circuit. In some embodiments of the present invention, the amplifying module 220 may also be implemented as an amplifying circuit including only one transistor amplifier circuit, a bootstrap circuit, or an integrated operational amplifier circuit. Using the output of one amplifying circuit to drive the first driver transistor 120 and the second transistor, such an embodiment provides a higher driving capability for the amplifying circuit.

[0061] 3 and 4 , in some embodiments of a transistor chip according to the present invention, a power supply pad 230, a control signal pad 240, a ground pad 250, a second power gate pad 260, a second drive gate pad 270 and a second source pad 280 are provided on the silicon bare crystal body 200. The power supply pad 230 is respectively connected to the source of the P-doped field effect transistor and the amplification module 220, the control signal pad 240 is connected to the input end of the amplification module 220, the ground pad 250 is connected to the amplification module 220 and the ground pad 250 is connected to the power transistor 110 through the second source pad 280, the second power gate pad 260 is respectively connected to the drain of the P-doped field effect transistor, the controlled end of the power transistor 110 and the first drive transistor 120, and the second drive gate pad 270 is respectively connected to the output end of the amplification module 220 and the drive end of the first drive transistor 120.

[0062] The power supply pad 230, control signal pad 240, ground pad 250, second power gate pad 260, second drive gate pad 270, and second source pad 280 provided on the silicon die body 200 facilitate connection to the silicon die body 200 via wire bonding or other processing methods, thereby electrically connecting the second drive transistor 210 and the amplifier module 220 to the power transistor 110 and the first drive transistor 120. This structure facilitates connection between the silicon die body 200 and the gallium nitride die body 100, and also facilitates connection between the silicon die body 200 and other die or pins, making actual welding, use, and packaging more convenient.

[0063] 3, the power supply pad 230 receives the input power supply driving voltage (V DRV ), the control signal pad 240 receives an input pulse width modulation signal (PWM), and the ground pad is grounded (GND).

[0064] Finally, it should be noted that the above embodiments are intended only to illustrate the technical solutions of the present invention and are not intended to limit them. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art will appreciate that modifications may be made to the technical solutions described in the aforementioned embodiments, or that some of the technical features may be replaced with equivalents. Such modifications or replacements do not deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A gallium nitride transistor bare die with high transient immunity, characterized in that: include: GaN die body (100); A power transistor (110) is disposed on the gallium nitride bare crystal body (100); A first driving transistor (120) is disposed on the gallium nitride bare crystal body (100), the first driving transistor (120) is connected to a controlled end of the power transistor (110), and the first driving transistor (120) is used to drive the power transistor (110) to be turned on or off according to a control signal.

2. The high transient immunity gallium nitride transistor bare die according to claim 1, characterized in that: The power transistor (110) is a first enhancement-mode gallium nitride high electron mobility transistor, and the first driving transistor (120) is a second enhancement-mode gallium nitride high electron mobility transistor.

3. The high transient immunity gallium nitride transistor bare die according to claim 2, characterized in that: The gate of the first enhancement-mode gallium nitride high electron mobility transistor is connected to the drain of the second enhancement-mode gallium nitride high electron mobility transistor, and the source of the first enhancement-mode gallium nitride high electron mobility transistor is connected to the source of the second enhancement-mode gallium nitride high electron mobility transistor.

4. The high transient immunity gallium nitride transistor bare die according to claim 2, characterized in that: The gallium nitride bare crystal body (100) is provided with a drain pad (130), a first power gate pad (140), a first source pad (150) and a first driving gate pad (160); the drain pad (130) is connected to the drain of the first enhancement-mode gallium nitride high electron mobility transistor; the first power gate pad (140) is respectively connected to the gate of the first enhancement-mode gallium nitride high electron mobility transistor and the drain of the second enhancement-mode gallium nitride high electron mobility transistor; the first source pad (150) is respectively connected to the source of the first enhancement-mode gallium nitride high electron mobility transistor and the source of the second enhancement-mode gallium nitride high electron mobility transistor; and the first driving gate pad (160) is connected to the gate of the second enhancement-mode gallium nitride high electron mobility transistor.

5. The high transient immunity gallium nitride transistor bare die according to claim 1, characterized in that: The power transistor (110) comprises a plurality of sub-transistors (111) connected in parallel, the sub-transistor (111) comprising a first gate component, a first drain component and a first source component arranged on the gallium nitride bare crystal body (100), the first driving transistor (120) comprising a second gate component, a second drain component and a second source component, the first gate component is connected to the second drain component, and the connection distance between each of the first gate components and the second drain component is equal.

6. The high transient immunity gallium nitride transistor bare die according to claim 5, characterized in that: The first gate member, the first drain member and the first source member of each sub-transistor (111) are all strip-shaped and arranged in parallel with each other, the second gate member, the second drain member and the second source member are all strip-shaped and arranged in parallel with each other, and the first gate member and the second source member are arranged perpendicularly.

7. A transistor chip, characterized in that: The invention comprises a gallium nitride transistor bare crystal with high transient immunity as claimed in any one of claims 1 to 6, and further comprises a silicon bare crystal body (200), on which a second driving transistor (210) is arranged, and the second driving transistor (210) is connected to the controlled end of the power transistor (110).

8. A transistor chip according to claim 7, characterized in that: The first driving transistor (120) and the second driving transistor (210) form a push-pull circuit.

9. A transistor chip according to claim 8, characterized in that: The first driving transistor (120) is a second enhancement-mode gallium nitride high electron mobility transistor, the second driving transistor (210) is a P-doped field effect transistor, the drain of the P-doped field effect transistor is respectively connected to the controlled end of the power transistor (110) and the drain of the second enhancement-mode gallium nitride high electron mobility transistor, and the gate of the second enhancement-mode gallium nitride high electron mobility transistor is connected to the gate of the P-doped field effect transistor.

10. A transistor chip according to any one of claims 9, characterized in that: It also includes an amplification module (220) disposed on the silicon bare crystal body (200), wherein the output end of the amplification module (220) is respectively connected to the controlled end of the first driving transistor (120) and the controlled end of the second driving transistor (210), and the input end of the amplification module (220) is used to receive a control signal.

11. The transistor chip according to claim 10, characterized in that: The amplification module (220) comprises a first amplification unit (221) and a second amplification unit (222), wherein the input end of the first amplification unit (221) is connected to the input end of the second amplification unit (222), the output end of the first amplification unit (221) is connected to the controlled end of the first driving transistor (120), and the output end of the second amplification unit (222) is connected to the controlled end of the second driving transistor (210).

12. The transistor chip according to claim 10, characterized in that: The silicon bare crystal body (200) is provided with a power supply pad (230), a control signal pad (240), a ground pad (250), a second power gate pad (260), a second drive gate pad (270) and a second source pad (280); the power supply pad (230) is respectively connected to the source of the P-doped field effect transistor and the amplification module (220); the control signal pad (240) is connected to the input end of the amplification module (220); the ground pad (250) is connected to the amplifier module (220); The large module (220) is connected and the ground pad (250) is connected to the power transistor (110) through the second source pad (280), the second power gate pad (260) is respectively connected to the drain of the P-doped field effect transistor, the controlled end of the power transistor (110) and the first driving transistor (120), and the second driving gate pad (270) is respectively connected to the output end of the amplification module (220) and the driving end of the first driving transistor (120).

Images