Memory cell, memory and access method therefor, and electronic device

Abstract

A memory cell, a memory and an access method therefor, and an electronic device. The memory comprises: multiple layers of memory arrays stacked in a direction perpendicular to a substrate, and a plurality of first word lines (WL1) in one-to-one correspondence with the multiple layers of memory arrays. The memory arrays comprise a plurality of memory cells distributed along the arrays, and a plurality of second word lines (WL2) corresponding to rows of the multiple layers of memory arrays. Each memory cell comprises a transistor, the transistor comprising a first gate (G1) and a second gate (G2); the first gates (G1) of memory cells of the same layer are connected to first word lines (WL1) corresponding to the layer, and the second gates (G2) of memory cells in the same row of different layers are connected to second word lines (WL2) corresponding to the row.

Description

Storage unit, memory and access method thereof, and electronic device

[0001] This application claims priority to the Chinese patent application filed on October 24, 2023, with application number 202311386826.1 and invention name “A storage unit, a memory and its access method, and an electronic device”, the contents of which should be understood as incorporated into this application by reference. Technical Field

[0002] The embodiments of the present disclosure relate to, but are not limited to, device design and manufacturing in the field of semiconductor technology, and in particular to a storage unit, a memory and an access method thereof, and an electronic device. Background Art

[0003] With the advancement of integrated circuit technology, device critical dimensions are shrinking, and the number and variety of devices contained in a single chip are increasing. Consequently, any slight variation in process production can affect device performance. To minimize product costs while still achieving the desired functionality, it is desirable to minimize the number of components used. In conventional 1T1C memory, each memory cell consists of an access transistor and a capacitor. The access transistor connects to a word line and a bit line. The word line connects to a word line driver, which connects to a sense amplifier. The word line selects the access transistor, and data is read and written via the bit line. If each word line is connected to a separate word line driver, the number of word line drivers would be enormous if the memory contained a large number of memory cells, leading to complex and costly processes and excessive device size. Therefore, for reasons of device size, cost, and process difficulty, it is necessary to reduce the number of word line drivers.

[0004] Summary of the Invention

[0005] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0006] An embodiment of the present disclosure provides a storage unit, including a transistor and a capacitor connected to the transistor, wherein the transistor includes a first gate electrode and a second gate electrode, and the first gate electrode is connected to a first word line, the second gate electrode is connected to a second word line, and the first word line and the second word line are connected to different signal terminals.

[0007] An embodiment of the present disclosure provides a memory, comprising: a multi-layer memory array stacked along a third direction perpendicular to a substrate, and a plurality of first word lines corresponding one-to-one to the multi-layer memory array, wherein the memory array includes a plurality of memory cells distributed in an array along a first direction parallel to the substrate and along a second direction parallel to the substrate. The memory also includes a plurality of second word lines corresponding to rows of the multi-layer memory array, each second word line corresponding to the same row of the multi-layer memory array, the memory cells including transistors, the transistors including a first gate electrode and a second gate electrode, the first gate electrodes of memory cells in the same layer being connected to the first word lines corresponding to the layer, and the second gate electrodes of memory cells in the same row distributed along the first direction in different layers being connected to the second word lines corresponding to the row.

[0008] In some embodiments, each layer of the storage array further includes a plurality of first sub-word lines extending along the second direction, the first gate electrodes of the storage cells in the same layer and the same column are connected to a first sub-word line, the first gate electrodes of the storage cells in different columns of the same layer are connected to different first sub-word lines, and the plurality of first sub-word lines in the same layer are connected to form a first word line.

[0009] In some embodiments, each layer of the storage array further includes a plurality of first sub-word lines extending along a first direction, the first gate electrodes of the storage cells in the same layer and the same row are connected to a first sub-word line, the first gate electrodes of the storage cells in different rows of the same layer are connected to different first sub-word lines, and the plurality of first sub-word lines in the same layer are connected to form a first word line.

[0010] In some embodiments, each layer of the storage array further includes a plurality of second sub-word lines extending along the first direction, the second gate electrodes of the storage cells in the same layer and the same row are connected to a second sub-word line, the second gate electrodes of the storage cells in different rows of the same layer are connected to different second sub-word lines, and the plurality of second sub-word lines in the same layer are connected to form a second word line.

[0011] In some embodiments, the memory further includes: a plurality of bit lines extending along the third direction and a plurality of common bit lines extending along the second direction, one bit line connecting storage cells at the same position in a multi-layer storage array, bit lines in the same column distributed along the second direction being connected to the same common bit line, and bit lines in different columns being connected to different common bit lines.

[0012] In some embodiments, each of the bit lines is connected to the common bit line via a gating sub-circuit, the gating sub-circuit is also connected to a gating control line, and a plurality of first gating sub-circuits respectively connected to a plurality of bit lines distributed along a first direction are connected to the same gating control line, and the gating sub-circuit is configured to connect or disconnect the bit line and the common bit line according to the control of the gating control line.

[0013] In some embodiments, the gating control line connected to the plurality of gating sub-circuits respectively connected to the plurality of bit lines in the i-th row is connected to the second word line corresponding to the memory cells in the i-th row.

[0014] The present disclosure provides a method for accessing the memory, including:

[0015] During the data reading and writing stage, according to the target layer and target row where the storage unit to be operated is located, an activation signal is loaded on the first word line corresponding to the target layer, and a non-activation signal is loaded on the first word line corresponding to the non-target layer; an activation signal is loaded on the second word line corresponding to the target row, and a non-activation signal is loaded on the second word line corresponding to the non-target row.

[0016] In some embodiments, the method further includes, during the data reading and writing phase, loading an on-level signal on a strobe control line connected to the bit line of the target row, and loading an off-level signal on a strobe control line connected to the bit line of a non-target row.

[0017] In some embodiments, the activation signal loaded on the second word line corresponding to the target row and the turn-on level signal loaded on the selection control line connected to the bit line of the target row are the same signal, and the non-activation signal loaded on the second word line corresponding to the non-target row and the turn-off level signal loaded on the selection control line connected to the bit line of the non-target row are the same signal.

[0018] In some embodiments, the method further includes, in the precharge phase, for each memory cell, loading an inactivation signal on at least one of the first word line and the second word line connected to the memory cell, and loading an on-level signal on all the selection control lines.

[0019] An embodiment of the present disclosure provides an electronic device, comprising the memory described in any of the above embodiments.

[0020] In some embodiments, the electronic device further includes a control circuit, and the control circuit is configured to access the memory according to the access method described in any of the above embodiments.

[0021] Other features and advantages of the present application will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present application. Other advantages of the present application can be realized and obtained by the solutions described in the description and the drawings.

[0022] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0023] Summary of the Figures

[0024] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0025] FIG1 is a schematic diagram of an equivalent circuit of a memory cell provided by an exemplary embodiment;

[0026] FIG2 is a schematic diagram of an equivalent circuit of a memory provided by an exemplary embodiment;

[0027] FIG. 3 is a schematic diagram of an equivalent circuit of a memory provided by another exemplary embodiment.

[0028] Details

[0029] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Unless there is a conflict, the embodiments of the present disclosure and the features therein may be combined with each other in any manner.

[0030] Unless otherwise defined, technical or scientific terms used in the present disclosure should have the same meaning as commonly understood by a person having ordinary skills in the field to which the present disclosure belongs.

[0031] The embodiments of the present disclosure are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically illustrate ideal examples, and the embodiments of the present disclosure are not limited to the shapes or values ​​shown in the drawings.

[0032] In the present disclosure, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements and do not indicate any order, quantity or importance.

[0033] In this disclosure, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, it should not be understood as a limitation of this disclosure. The positional relationships of constituent elements may be appropriately changed according to the direction in which each constituent element is described. Therefore, the words and phrases described in this disclosure are not limited and may be appropriately replaced according to the circumstances.

[0034] In this disclosure, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be interpreted broadly. For example, they can refer to physical or signal connections, contact connections, or integral connections. They can be direct connections, indirect connections through intermediaries, or internal connections between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure based on the specific circumstances.

[0035] In the present disclosure, the first electrode may be a drain electrode and the second electrode may be a source electrode, or vice versa. The functions of the "source electrode" and "drain electrode" may be reversed when using transistors with opposite polarities or when the direction of current changes during circuit operation. Therefore, in the present disclosure, the terms "source electrode" and "drain electrode" may be reversed.

[0036] In this disclosure, "connection" includes the connection of components via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0037] In this disclosure, "parallel" means approximately parallel or nearly parallel. For example, the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes the angle of greater than -5° and less than 5°. In addition, "perpendicular" means approximately perpendicular. For example, the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes the angle of greater than 85° and less than 95°.

[0038] One way to reduce word line drivers is to set a gate transistor to enable word line gating to reduce word line drivers. However, the gate transistor needs to be manufactured in addition to the memory array, which increases the process steps and increases the cost.

[0039] In the embodiment of the present disclosure, a dual-gate transistor is used in the memory cell, and the two gate electrodes of the transistor are respectively connected to different word lines. The first gate electrodes of the memory cells in the same layer are connected to the same first word line, and the second gate electrodes of the memory cells in the same layer and the same row are connected to the same second word line. A row of memory cells is selected by the first word line and the second word line, and the purpose of selecting a row of memory cells and reducing the number of word line drivers can be achieved without the need for a selection transistor.

[0040] Figure 1 is a schematic diagram of an equivalent circuit of a memory cell provided by an exemplary embodiment. As shown in Figure 1, the memory cell provided by this embodiment includes a transistor (also called an access transistor) and a capacitor Cs. The transistor includes a first gate electrode G1, a second gate electrode G2, a first electrode E1, and a second electrode E2. The first gate electrode G1 is connected to a first word line WL1, the second gate electrode G2 is connected to a second word line WL2, the first electrode E1 is connected to a bit line BL, the second electrode E2 is connected to a first terminal of the capacitor Cs, and the second terminal of the capacitor Cs is connected to a preset voltage terminal Vs. The first terminal of the capacitor Cs serves as a storage node SN. The first word line WL1 and the second word line WL2 are connected to different signal terminals, meaning that the first word line WL1 and the second word line WL2 are independently controlled. The memory cell can be applied to a 3D stacked 1T1C memory, enabling selection of a row of memory cells through the first word line WL1 and the second word line WL2 without the need for a gate transistor. Compared to single-gate 1T1C memory cells, the solution provided by this embodiment supports the implementation of a 3D stacked 1T1C memory with a simpler process.

[0041] In some embodiments, the transistor may be an N-type transistor or a P-type transistor.

[0042] In some embodiments, when both the first word line WL1 and the second word line WL2 are loaded with an activation signal, the transistor is turned on; when at least one of the first word line WL1 and the second word line WL2 is loaded with an inactivation signal, the transistor is turned off. The activation signal and the inactivation signal vary depending on the type of transistor. When the transistor is an N-type transistor, when both the first word line WL1 and the second word line WL2 are loaded with a high-level signal, the transistor is turned on; when at least one of the first word line WL1 and the second word line WL2 is loaded with a low-level signal, the transistor is turned off; alternatively, when the transistor is a P-type transistor, when both the first word line WL1 and the second word line WL2 are loaded with a low-level signal, the transistor is turned on; when at least one of the first word line WL1 and the second word line WL2 is loaded with a high-level signal, the transistor is turned off.

[0043] FIG2 is a schematic diagram of an equivalent circuit of a memory provided by an exemplary embodiment. As shown in FIG2 , the memory may include: a multi-layer stacked memory array (k layer, memory array L1 to memory array Lk), wherein the multi-layer memory array is stacked along a third direction z. Each layer of the memory array includes a plurality of memory cells 100 arrayed along a first direction x and a second direction y, respectively, as well as a plurality of first sub-word lines Sub_WL1 extending along the second direction y, and a plurality of second sub-word lines Sub_WL2 extending along the first direction x. The structure of the memory cell 100 is referred to FIG1 and will not be described in detail. The plurality of first sub-word lines Sub_WL1 of each layer are spaced apart along the first direction x, and the plurality of second sub-word lines Sub_WL2 of each layer are spaced apart along the second direction y. The memory further includes a plurality of bit lines BL extending along a third direction z, and the plurality of bit lines BL are arrayed along the first direction x and the second direction y. Each layer of the memory array includes n rows and m columns of memory cells 100, as well as m first sub-word lines Sub_WL1 and n second sub-word lines Sub_WL2. The first sub-word line in the r-th layer, j-th column is Sub_WL1_Cj_r, where j ranges from 1 to m and r ranges from 1 to k; the second sub-word line in the r-th layer, i-th row is Sub_WL2_Ri_r, where i ranges from 1 to n and r ranges from 1 to k. The memory array includes n rows and m columns of bit lines BL, and the bit line in the i-th row, j-th column is bit line BL_i_j, where i ranges from 1 to n and j ranges from 1 to m. The first gate electrode G1 of the memory cell C_i_j_r in the r-th layer, i-th row, j-th column is connected to the first sub-word line Sub_WL1_Cj_r, the second gate electrode G2 is connected to the second sub-word line Sub_WL2_Ri_r, and the first electrode E1 is connected to the bit line BL_i_j. The first direction x and the second direction y are parallel to the substrate (the substrate is not shown in FIG2 ), and the third direction z is perpendicular to the substrate. The first direction x and the second direction y may intersect. In some embodiments, the first direction x and the second direction y may be perpendicular. The first direction x is also referred to as the row direction, and the second direction y is also referred to as the column direction. The preset voltage terminal Vs may be, for example, a fixed potential, such as a value between the voltage corresponding to the logic data “0” and the voltage corresponding to the logic data “1”. For example, the voltage corresponding to the logic data “0” is “0”, and the voltage corresponding to the logic data 1 is VDD, then Vs may be 1 / 2VDD.

[0044] In some embodiments, multiple first sub-word lines Sub_WL1 in the same layer are connected to form a first word line WL1. Each layer of memory cells corresponds to a first word line WL1. That is, m first sub-word lines Sub_WL1_C1_r to Sub_WL1_Cm_r in the rth layer are connected to form the rth first word line WL1_r, where r is 1 to k. For example, m first sub-word lines Sub_WL1_C1_1 to Sub_WL1_Cm_1 in the 1st layer are connected to form the 1st first word line WL1_1, and m first sub-word lines Sub_WL1 C1_k to Sub_WL1 Cm_k in the kth layer are connected to form the kth first word line WL1_k. Each first word line WL1_r is connected to a first word line driver. Different first word lines WL1_r are connected to different first word line drivers.

[0045] In some embodiments, the first word line drivers connected to the first word lines WL1_r may be disposed on the same side of the memory array, but the present disclosure is not limited thereto and may be disposed on different sides as needed, for example, on two opposite sides of the memory array.

[0046] In some embodiments, multiple first sub-word lines Sub_WL1 in the same layer may be connected via one or two connection lines disposed at the periphery of the memory array and extending along the first direction x. However, the present disclosure is not limited thereto and multiple first sub-word lines Sub_WL1 in the same layer may be connected via other methods.

[0047] In some embodiments, multiple second sub-word lines Sub_WL2 in the same row of different layers are connected to form one second word line WL2. Each row in different layers corresponds to one second word line WL2. Specifically, k second sub-word lines Sub_WL2_Ri_1 to Sub_WL2_Ri_k in the i-th row of layers 1 to k-th are connected to form the i-th second word line WL2_i, where i ranges from 1 to n. k second sub-word lines Sub_WL2_R1_1 to Sub_WL2_R1_k in the 1-th row of layers 1 to k-th are connected to form the 1-th second word line WL2_1. K second sub-word lines Sub_WL2_Rn_1 to Sub_WL2_Rn_k in the n-th row of layers 1 to k-th are connected to form the n-th second word line WL2_n, where i ranges from 1 to n. Each second word line WL2_i is connected to a second word line driver.

[0048] In some embodiments, the second word line WL2_i may be connected to the second word line driver on the side of the memory array facing the substrate, but the disclosed embodiments are not limited thereto. The second word line WL2_i may be connected to the second word line driver on the side of the memory array facing away from the substrate.

[0049] In some embodiments, multiple second sub-word lines Sub_WL2 in the same row on different layers can be connected by one or two connecting lines extending along a third direction Z arranged on the periphery of the memory array, but the embodiments of the present disclosure are not limited thereto, and multiple second sub-word lines Sub_WL2 in the same row on different layers can be connected by other means.

[0050] The memory provided in this embodiment can select a row of memory cells by activating a first word line and a second word line. For example, when the target layer is the pth layer and the target row is the qth row, an activation signal can be applied to the second word line WL2_q and the first word line WL1_p, thereby selecting m memory cells in the qth row of the pth layer. The solution provided in this embodiment does not require setting a gate transistor for the word line to select a row of memory cells. Compared with the solution of setting a gate transistor for the word line, there is no need to increase the manufacturing process steps for the gate transistor. The number of word line drivers is small, with k first word line drivers and n second word line drivers. The number of word line drivers increases slightly as the number of stacked layers increases (one word line driver for each layer). In addition, the circuit control logic is simple.

[0051] In some embodiments, the memory may further include multiple common bit lines CBL. Multiple bit lines BL in the same column distributed along the second direction y may be connected to the same common bit line CBL, while bit lines BL in different columns may be connected to different common bit lines CBL. For example, the first column bit line BL is connected to the first common bit line CBL1, the second column bit line BL is connected to the second common bit line CBL2, and the m-th column bit line BL is connected to the m-th common bit line CBLm. One common bit line CBL is connected to one sense amplifier SA. Compared to a solution in which each bit line BL is connected to one sense amplifier SA, the solution provided in this embodiment uses common bit lines CBL, which can significantly reduce the number of sense amplifiers SA. Adjacent memory arrays can share the same SA.

[0052] In some embodiments, the common bit line CBL may be disposed on a side of the memory array facing away from the substrate, as shown in FIG2 , or on a side of the memory array facing the substrate. When the memory includes multiple stacked memory arrays, the common bit line CBL may be disposed on a side of the stacked memory array facing the substrate, or on a side facing away from the substrate.

[0053] In some embodiments, each bit line BL can be connected to the common bit line CBL through a gating sub-circuit 10. The gating sub-circuit 10 can also be connected to a gating control line, and the gating sub-circuit 10 is configured to connect or disconnect the bit line BL and the common bit line CBL under the control of the gating control line (that is, to make the bit line BL and the common bit line CBL electrically connected, or disconnected). That is, the signal of the common bit line CBL is loaded or not loaded onto the bit line BL under the control of the gating control line. The solution provided in this embodiment can only gating the target bit line to be read and turning off the non-target bit line by setting the gating sub-circuit, thereby reducing the capacitive reactance of the CBL, reducing power consumption, and improving the reading speed. However, the embodiment of the present disclosure is not limited to this. In another exemplary embodiment, the gating sub-circuit 10 may not be set.

[0054] In some embodiments, the gating subcircuit 10 may be disposed on the side of the memory array facing away from the substrate, between the bit line BL and the common bit line CBL. However, the present disclosure is not limited thereto, and the gating subcircuit 10 may be disposed on the side of the memory array facing the substrate.

[0055] In some embodiments, the gating sub-circuits 10 connected to the same row of bit lines BL distributed along the first direction x can be connected to the same gating control line, while the gating sub-circuits of bit lines BL in different rows are connected to different gating control lines. Thus, n rows of bit lines BL are connected to n different gating control lines. For example, as shown in FIG2 , the gating sub-circuits 10 connected to the first row of bit lines BL are all connected to the first gating control line S_1, the gating sub-circuits 10 connected to the second row of bit lines BL are all connected to the second gating control line S_2, and so on. The gating sub-circuits 10 connected to the nth row of bit lines BL are all connected to the nth gating control line S_n. Thus, a single bit line BL can be selected via the common bit line CBL and the gating control line. For example, the jth common bit line CBLj is loaded with an activation signal (the other common bit lines are loaded with an inactivation signal), the i-th selection control line S_i selects the corresponding selection sub-circuit 10 (the other selection control lines do not select the corresponding selection sub-circuit 10), then the bit line BL_i_j in the i-th row and j-th column is loaded with an activation signal.

[0056] In some embodiments, only one bit line BL is enabled at a time, which can reduce the capacitance load of the SA and the capacitance of the memory cell.

[0057] In some embodiments, the gating sub-circuit 10 may include a first transistor T1, wherein a gate electrode of the first transistor T1 is connected to the gating control line, a first electrode of the first transistor T1 is connected to the bit line BL, and a second electrode of the first transistor T1 is connected to the common bit line CBL. The structure of the gating sub-circuit 10 described in this embodiment is merely an example, and other circuits capable of implementing gating may be used.

[0058] In some embodiments, the first transistor T1 is, for example, an N-type transistor, but the embodiments of the present disclosure are not limited thereto. The first transistor T1 may be a P-type transistor.

[0059] In some embodiments, when the second word line WL2_i corresponding to the i-th row is loaded with an activation signal, the gating control line S_i connected to the gating sub-circuit 10 connected to the bit line BL of the i-th row is loaded with an on-level signal to turn on the gating sub-circuit 10 connected to the bit line BL of the i-th row. When the first word line WL1_r corresponding to the r-th layer is loaded with an activation signal, the memory cells in the i-th row of the r-th layer are enabled, and the memory cells in the i-th row of the r-th layer can be accessed (read or written) through the BL of the i-th row.

[0060] In some embodiments, the second word line WL2_i can be connected to the selection control line S_i connected to the selection sub-circuit 10 connected to the bit line BL of the i-th row, where i is 1 to n, that is, the same signal driver can be used to load the same signal to the second word line WL2_i and the selection control line S_i, that is, the activation signal and the turn-on level signal of the selection sub-circuit 10 use the same signal. The solution provided in this embodiment can reduce the number of control lines, as well as reduce the control circuit that generates the control signal, reduce the device occupied area, and simplify the control logic. At this time, the selection sub-circuit 10 can be set on the side of the memory array facing the substrate. The disclosed embodiment is not limited to this, and the selection sub-circuit 10 can be set on the side of the memory array away from the substrate, and the second word line WL2_i can be connected to the second word line driver on the side of the memory array away from the substrate.

[0061] Figure 3 is a schematic diagram of a memory provided by another exemplary embodiment. As shown in Figure 3, in the memory provided by this embodiment, the extension direction of the first sub-wordline Sub_WL1 is consistent with the extension direction of the second sub-wordline Sub_WL2. That is, in this embodiment, the memory includes multiple first sub-wordlines Sub_WL1 extending along a first direction x. The multiple first sub-wordlines Sub_WL1 in each layer are spaced apart along a second direction y. The first sub-wordline in the i-th row of the r-th layer is Sub_WL1_Ri_r, where i ranges from 1 to n and r ranges from 1 to k. The memory cell C_i_j_r in the i-th row and j-th column of the r-th layer is connected to the first sub-wordline Sub_WL1_Ri_r. The multiple first wordline drivers connected to the multiple first wordlines WL1_r can be arranged on the same side of the memory. The multiple first sub-wordlines Sub_WL1 in the same layer can be connected via two connecting lines extending along the second direction y, arranged at the periphery of the memory array. The description of the memory cells, first wordlines, etc. in Figure 3 refers to the previous embodiment and is not repeated here. The solution provided by this embodiment is easier to manufacture than the solution shown in FIG. 2 in which the first sub-word line Sub_WL1 and the second sub-word line Sub_WL2 extend in different directions.

[0062] In some embodiments, multiple first sub-word lines Sub_WL1 in the same layer are connected to form a first word line WL1, with one first word line WL1 for each layer. For example, n first sub-word lines Sub_WL1_R1_r through Sub_WL1_Rn_r in the rth layer are connected to form the rth first word line WL1_r, where r is 1 to k. The n first sub-word lines Sub_WL1_R1_1 through Sub_WL1_Rn_1 in the 1st layer are connected to form the 1st first word line WL1_1, and the n first sub-word lines Sub_WL1_R1_k through Sub_WL1_Rn_k in the kth layer are connected to form the kth first word line WL1_k. Each first word line WL1_r is connected to a first word line driver.

[0063] An embodiment of the present disclosure provides a memory access method, which is applied to the memory described in any of the above embodiments. The access method may include:

[0064] During the data reading and writing stage, according to the target layer and target row where the storage unit to be operated is located, an activation signal is loaded on the first word line corresponding to the target layer, and a non-activation signal is loaded on the first word line corresponding to the non-target layer; an activation signal is loaded on the second word line corresponding to the target row, and a non-activation signal is loaded on the second word line corresponding to the non-target row (at this time, only the first gate electrode and the second gate electrode of the transistor of the storage unit of the target row of the target layer are loaded with the activation signal, so that the transistor of the storage unit of the target row of the target layer can be turned on); an on-level signal is loaded on the selection control line connected to the bit line of the target row (so that the selection subcircuit connected to the bit line of the target row is in a connected state), and an off-level signal is loaded on the selection control line connected to the bit line of the non-target row (so that the selection subcircuit connected to the bit line of the non-target row is in an off state).

[0065] This embodiment provides a memory access method, which can implement access to a row of memory cells through a first word line, a second word line, and a strobe control line, and has simple control logic.

[0066] The on-level signal is a signal that can make the corresponding gating subcircuit in a connected state, and the off-level signal is a signal that can make the corresponding gating subcircuit in a closed state. The data reading and writing phase may include a data reading phase and a data writing phase.

[0067] In some embodiments, it may also include:

[0068] During the precharge phase, for each memory cell, an inactive signal is applied to at least one of the first word line and the second word line connected to the memory cell, and an on-level signal is applied to all the gating control lines. This turns off all access transistors, connects all gating sub-circuits, and precharges the bit lines.

[0069] In some embodiments, the activation signal loaded on the second word line corresponding to the target row and the turn-on level signal loaded on the selection control line connected to the bit line of the target row are the same signal, and the non-activation signal loaded on the second word line corresponding to the non-target row and the turn-off level signal loaded on the selection control line connected to the bit line of the non-target row are the same signal.

[0070] That is, the same signal can be used to control the gating control lines connected to the bit lines in the same row, as well as the corresponding second word lines. This reduces control signals, simplifies control, and reduces signal drivers, which helps reduce costs and device area. In this case, the second word line WL2_i and the gating control line S_i connected to the gating sub-circuit 10 connected to the bit line BL in the i-th row can be connected together, where i ranges from 1 to n, and n is the number of rows of memory cells included in each layer of the memory array.

[0071] The following describes the operation of a memory using an embodiment. Taking the memory shown in FIG2 as an example, in this embodiment, the memory cell 100 has a 1T1C structure, the access transistor is an N-type MOS transistor, the first transistor T1 is an N-type MOS transistor, the selection control line S_i is connected to the second word line WL2_i, where i is 1 to n, and the common bit line CBL can also be connected to a precharge sub-circuit. The operation phases of the memory may include a precharge phase, a data read phase, and a data write-back phase, wherein:

[0072] During the precharge phase, the first word lines WL1_1 to WL1_k are all loaded with a low-level signal, which is then loaded onto the first sub-word line Sub_WL1. The second word lines WL2_1 to WL2_n are all loaded with a high-level signal (i.e., the selection control line S_i is loaded with a high-level signal). At this time, the selection sub-circuit 10 is turned on, the access transistors of all memory cells are turned off, the precharge sub-circuit is turned on, and a precharge voltage of 1 / 2VDD is loaded onto each common bit line CBL. Each common bit line CBL then loads the precharge voltage onto a column of bit lines BL to which it is connected.

[0073] During the data reading phase, the precharge sub-circuit is turned off. Taking the data of the memory cell 100 in the p-th layer and the q-th row as an example, among the first word lines WL1_1 to WL1_k, the first word line WL1_p corresponding to the p-th layer is loaded with a high-level signal, and the remaining first word lines WL1_r (where r is 1 to k and r≠p) are loaded with low-level signals. Among the second word lines WL2_1 to WL2_n, the second word line WL2_q corresponding to the q-th row is loaded with a high-level signal, and the remaining WL2_i (where i is 1 to n and i≠q) are loaded with low-level signals. As a result, the access transistor of the memory cell 100 in the qth row of the pth layer is turned on, and the access transistors of the remaining memory cells 100 are turned off. The selection sub-circuit 10 connected to the bit line of the qth row is turned on, and the common bit lines CBL1 to CBLm are respectively connected to the m bit lines of the qth row, and charge is shared with the storage nodes of the m memory cells 100 in the pth layer and the qth row respectively. The sense amplifiers respectively connected to CBL1 to CBLm sense the voltages of CBL1 to CBLm to determine the data stored in the memory cell 100 in the pth layer and the qth row.

[0074] In the data write back stage, among the first word lines WL1_1 to WL1_k, WL1_p is loaded with a high-level signal, and the remaining WL1_r (where r is 1 to k and r≠p) are loaded with a low-level signal. Among the second word lines WL2_1 to WL2_n, WL2_q is loaded with a high-level signal, and the remaining WL2_i (where i is 1 to n and i≠q) are loaded with a low-level signal. The common bit lines CBL1 to CBLm are respectively connected to the m bit lines in the qth row, and charge is shared with the storage nodes of the m storage cells 100 in the pth layer and the qth row to realize data write back.

[0075] The solution provided by this embodiment does not require the use of a selection transistor to select the memory cell. A row of memory cells can be selected using the first word line and the second word line. It has a simple structure and simple control logic. The same control signal is used to control the selection control line and the second word line of the same row, which reduces the number of control signal lines, reduces the required control circuit, and simplifies the control logic.

[0076] The present disclosure also provides an electronic device comprising the memory device of the aforementioned embodiment. The electronic device may be a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply. The storage device may include, but is not limited to, computer memory.

[0077] In some embodiments, the electronic device may further include a control circuit configured to access the memory according to any of the access methods described above. The control circuit may include a driver that generates control signals to the first word line, the second word line, and a gate control line. The control circuit, together with the SA, etc., enables access to the memory.

[0078] Although the embodiments disclosed herein are as described above, the contents described herein are merely embodiments for facilitating understanding of the present invention and are not intended to limit the present invention. Any person skilled in the art may make any modifications and variations in the form and details of the embodiments without departing from the spirit and scope of the present invention. However, the scope of patent protection of the present invention shall remain subject to the scope defined by the appended claims.

Claims

1. A storage unit, comprising: A transistor and a capacitor connected to the transistor, wherein the transistor includes a first gate electrode and a second gate electrode, wherein the first gate electrode is connected to a first word line, the second gate electrode is connected to a second word line, and the first word line and the second word line are connected to different signal terminals.

2. A memory comprising: A multi-layer memory array stacked along a third direction perpendicular to a substrate, and a plurality of first word lines corresponding to the multi-layer memory array one by one, wherein the memory array includes a plurality of memory cells distributed in an array along a first direction parallel to the substrate and along a second direction parallel to the substrate, the memory also includes a plurality of second word lines corresponding to rows of the multi-layer memory array, each second word line corresponds to the same row of the multi-layer memory array, the memory cell includes a transistor, the transistor includes a first gate electrode and a second gate electrode, the first gate electrode of the memory cell in the same layer is connected to the first word line corresponding to the layer, and the second gate electrode of the memory cell in the same row distributed along the first direction in different layers is connected to the second word line corresponding to the row.

3. The memory according to claim 2, wherein: Each layer of the storage array also includes multiple first sub-word lines extending along the second direction, the first gate electrodes of the storage cells in the same layer and the same column are connected to a first sub-word line, the first gate electrodes of the storage cells in different columns of the same layer are connected to different first sub-word lines, and multiple first sub-word lines in the same layer are connected to form one first word line.

4. The memory according to claim 2, wherein: Each layer of the storage array also includes multiple first sub-word lines extending along the first direction, the first gate electrodes of the storage cells in the same layer and the same row are connected to a first sub-word line, the first gate electrodes of the storage cells in different rows of the same layer are connected to different first sub-word lines, and multiple first sub-word lines in the same layer are connected to form one first word line.

5. The memory according to claim 2, wherein: Each layer of the storage array also includes multiple second sub-word lines extending along the first direction, the second gate electrodes of the storage cells in the same layer and the same row are connected to a second sub-word line, the second gate electrodes of the storage cells in different rows of the same layer are connected to different second sub-word lines, and multiple second sub-word lines in the same layer are connected to form one second word line.

6. The memory according to claim 5, wherein: The memory also includes: a plurality of bit lines extending along the third direction and a plurality of common bit lines extending along the second direction, one bit line connects storage cells at the same position of a multi-layer storage array, bit lines in the same column distributed along the second direction are connected to the same common bit line, and bit lines in different columns are connected to different common bit lines.

7. The memory according to claim 6, wherein: Each of the bit lines is connected to the common bit line via a gating subcircuit, the gating subcircuit is also connected to a gating control line, and a plurality of first gating subcircuits respectively connected to a plurality of bit lines distributed along the first direction are connected to the same gating control line, and the gating subcircuit is configured to connect or disconnect the bit line and the common bit line according to the control of the gating control line.

8. The memory according to claim 7, wherein: The gating control line connected to the plurality of gating subcircuits respectively connected to the plurality of bit lines in the i-th row is connected to the second word line corresponding to the memory cell in the i-th row.

9. A method for accessing a memory as claimed in any one of claims 2 to 8, comprising: During the data reading and writing stage, according to the target layer and target row where the storage unit to be operated is located, an activation signal is loaded on the first word line corresponding to the target layer, and a deactivation signal is loaded on the first word line not corresponding to the target layer; an activation signal is loaded on the second word line corresponding to the target row, and a deactivation signal is loaded on the second word line not corresponding to the target row.

10. The memory access method according to claim 9, wherein: The memory is a memory as described in any one of claims 6 to 8, and the method also includes, in the data reading and writing stage, loading an on-level signal on a selection control line connected to the bit line of the target row, and loading an off-level signal on a selection control line connected to the bit line of a non-target row.

11. The memory access method according to claim 10, wherein: The activation signal loaded on the second word line corresponding to the target row and the turn-on level signal loaded on the selection control line connected to the bit line of the target row are the same signal, and the inactivation signal loaded on the second word line corresponding to the non-target row and the turn-off level signal loaded on the selection control line connected to the bit line of the non-target row are the same signal.

12. The memory access method according to claim 10, wherein: The method further includes, in the precharge phase, for each memory cell, loading an inactive signal on at least one of the first word line and the second word line connected to the memory cell, and loading an on-level signal on all the selection control lines.

13. An electronic device comprising the memory according to any one of claims 2 to 8.

14. The electronic device according to claim 13, wherein: The electronic device further comprises a control circuit, wherein the control circuit is configured to access the memory according to the memory access method according to any one of claims 9 to 12.

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