Oscillating mirror driving apparatus, laser projection device, driving method, and storage medium

Abstract

The present application belongs to the technical field of laser projection. Disclosed are an oscillating mirror driving apparatus, a laser projection device, a driving method, and a storage medium. The oscillating mirror driving apparatus comprises a DLP unit circuit, a delay circuit, a switch circuit and an oscillating mirror driving circuit, wherein the DLP unit circuit is used for outputting, when the DLP unit circuit is successfully configured, a successful configuration command signal to the delay circuit by means of a command signal output end, and for outputting an oscillating mirror sub-frame synchronization signal to the oscillating mirror driving circuit by means of a sub-frame synchronization signal output end; the delay circuit is used for outputting, when an input end of the delay circuit receives the successful configuration command signal and after a first delay, an enable signal to the switch circuit by means of an output end of the delay circuit; and the switch circuit is used for enabling the electric connection between an input end of the switch circuit and an output end of the switch circuit when a control end of the switch circuit receives the enable signal. The present application can solve the problem of an oscillating mirror coil being prone to burnout.

Description

Galvanometer drive device, laser projection equipment, drive method and storage medium

[0001] This application claims priority to Chinese patent application No. 202311389658.1, filed on October 25, 2023, entitled “Galvanometer drive circuit, projection device and galvanometer drive method”, priority to Chinese patent application No. 202311395207.9, entitled “Digital drive waveform generation device, method and projection device for galvanometer”, and priority to Chinese patent application No. 202311395199.8, entitled “Galvanometer power supply control circuit and laser projection device”, all of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of laser projection technology, and in particular to a galvanometer drive device, a laser projection device, a drive method, and a storage medium. Background Art

[0003] Laser projection technology uses solid-state lasers (red, green, and blue (R, G, B)) as a light source. This technology offers advantages such as low power consumption and a longer lifespan, nearly 10 times that of traditional light bulbs. Laser projection can realistically reproduce the rich, vibrant colors of the real world, providing exceptional expressiveness. Laser display's color gamut coverage can reach over 90% of the human eye's color space, more than double the coverage of traditional display technologies, surpassing the color gamut limitations of the previous three generations of display technologies.

[0004] Resolution is also an important indicator to characterize the performance of laser projection equipment. The higher the resolution, the higher the precision of the image that can be projected onto the screen, the more information displayed, and the clearer the picture. However, the resolution of laser projection equipment is limited by the hardware process, and it is difficult to improve the resolution. Currently, many laser projection devices use digital micromirror devices (DMDs) as key components, and the resolution of laser projection equipment is mainly determined by the resolution of the DMD. With the help of micro-oscillating mirror (galvanometer for short) technology, a low-resolution DMD can be used to project high-resolution images. By dividing a high-resolution frame image into two low-resolution sub-images, and then controlling the galvanometer in the DMD to deflect, the two sub-images are sequentially staggered within an image display cycle, thereby achieving high-resolution image projection. How to ensure the reliability and accuracy of galvanometer deflection is a research focus in the industry.

[0005] Summary of the Invention

[0006] This application provides a galvanometer drive device, laser projection equipment, drive method, and storage medium, which can effectively prevent the galvanometer coil from burning out and ensure the reliability and accuracy of the galvanometer deflection. The technical solution is as follows:

[0007] In a first aspect, a galvanometer drive device is provided, comprising a digital light processing (DLP) unit circuit, a delay circuit, a switch circuit, and a galvanometer drive circuit; a command signal output terminal of the DLP unit circuit is connected to an input terminal of the delay circuit, a subframe synchronization signal output terminal of the DLP unit circuit is connected to the galvanometer drive circuit, an output terminal of the delay circuit is connected to a control terminal of the switch circuit, an input terminal of the switch circuit is connected to a power supply of the galvanometer drive circuit, and an output terminal of the switch circuit is connected to a power input terminal of the galvanometer drive circuit;

[0008] The DLP unit circuit is configured to output a configuration success command signal through the command signal output terminal and output a galvanometer sub-frame synchronization signal through the sub-frame synchronization signal output terminal when the DLP unit circuit is successfully configured, wherein the galvanometer sub-frame synchronization signal is used to instruct the galvanometer drive circuit to drive the galvanometer deflection;

[0009] The delay circuit is configured to output a start signal through the output end of the delay circuit after a first delay when the configuration success command signal is received at the input end of the delay circuit;

[0010] The switch circuit is configured to conduct the electrical connection between the input end of the switch circuit and the output end of the switch circuit when the control end of the switch circuit receives the start signal.

[0011] In a second aspect, a laser projection device is provided, comprising a galvanometer and a galvanometer driving device as described in the first aspect, wherein the galvanometer driving device is connected to the galvanometer.

[0012] In a third aspect, a galvanometer mirror driving method is provided, comprising: upon successful configuration of a DLP unit circuit, transmitting a galvanometer mirror sub-frame synchronization signal, and powering a galvanometer mirror driving circuit after a first delay, wherein the galvanometer mirror sub-frame synchronization signal is used to instruct the galvanometer mirror driving circuit to drive the galvanometer mirror for deflection. This method can be applied to the galvanometer mirror driving device described in the first aspect.

[0013] In a fourth aspect, a computer-readable storage medium is provided, in which at least one instruction, at least one program, a code set or an instruction set is stored. The at least one instruction, the at least one program, the code set or the instruction set is loaded and executed by a processor to implement the galvanometer driving method provided in the third aspect.

[0014] In a fifth aspect, a computer program product is provided, wherein the computer program product includes program instructions, and when the program instructions are executed by a processor, the galvanometer driving method provided in the third aspect is implemented.

[0015] As can be seen from the above technical solutions, the galvanometer drive device, drive method and laser projection equipment provided by the present application control the power supply of the galvanometer drive circuit through the DLP unit circuit, the delay circuit and the switch circuit. The DLP unit circuit can only output a configuration success command signal to the delay circuit when the configuration is successful. At this time, the DLP unit circuit also outputs a galvanometer surface frame synchronization signal to the galvanometer drive circuit. After receiving the configuration success command signal, the delay circuit will output an open signal to the control end of the switch circuit after a preset delay, so that the power supply supplies power to the galvanometer drive circuit. By setting this delay, it can be ensured that the galvanometer surface frame synchronization signal is first transmitted to the galvanometer drive circuit, and only then is the power supply supplied to the galvanometer drive circuit. This can avoid the phenomenon that the power supply is turned on first to generate a DC high-voltage pulse before the galvanometer surface frame synchronization signal is transmitted to the galvanometer drive circuit, causing the galvanometer coil to burn out, thereby solving the problem of the galvanometer coil being easily burned out and improving the reliability of the laser projection equipment. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0017] FIG1 shows a schematic structural diagram of a laser projection device in some embodiments;

[0018] FIG2 is a schematic diagram illustrating display resolution expansion in some embodiments;

[0019] FIG3 shows a schematic structural diagram of another laser projection device in some embodiments;

[0020] FIG4 is a schematic structural diagram of a lens assembly in a laser projection device in some embodiments;

[0021] FIG5 shows a diagram showing the position of a first sub-image when a galvanometer mirror is deflected in some embodiments;

[0022] FIG6 shows a diagram showing the position of a second sub-image when the galvanometer mirror is deflected in some embodiments;

[0023] FIG7 shows a schematic structural diagram of a single-axis galvanometer in some embodiments;

[0024] FIG8 is a schematic structural diagram of a galvanometer drive device in some embodiments;

[0025] FIG9 shows a circuit diagram of a galvanometer power supply control device in some embodiments;

[0026] FIG10 shows a circuit diagram of another galvanometer power supply control device in some embodiments;

[0027] FIG11 shows a circuit diagram of yet another galvanometer power supply control device in some embodiments;

[0028] FIG12 shows a partial circuit diagram of a laser projection device in some embodiments;

[0029] FIG13 is a schematic structural diagram of a galvanometer drive circuit in some embodiments;

[0030] FIG14 shows a schematic structural diagram of another galvanometer drive circuit in some embodiments;

[0031] FIG15 shows a schematic structural diagram of an operational amplifier module in some embodiments;

[0032] FIG16 shows a schematic structural diagram of another galvanometer drive circuit in some embodiments;

[0033] FIG17 shows a schematic structural diagram of another galvanometer drive circuit in some embodiments;

[0034] FIG18 shows a waveform diagram of a first driving voltage in some embodiments;

[0035] FIG19 shows a waveform diagram of the second driving voltage in some embodiments;

[0036] FIG20 shows a waveform diagram of a driving signal in some embodiments;

[0037] FIG21 shows a schematic structural diagram of a digital waveform generation module in some embodiments;

[0038] FIG22 is a schematic diagram showing analog driving waveforms and digital driving waveforms in some embodiments;

[0039] FIG23 shows a timing diagram of subframe synchronization in some embodiments;

[0040] FIG24 shows a schematic diagram of digital drive waveform generation in some embodiments;

[0041] FIG25 is a schematic diagram showing the waveform output working principle in some embodiments;

[0042] FIG26 shows a block diagram of another digital waveform generation module in some embodiments;

[0043] FIG27 shows a block diagram of another digital waveform generation module in some other embodiments;

[0044] FIG28 shows a block diagram of another digital waveform generation module in some other embodiments;

[0045] FIG29 shows a block diagram of another digital waveform generation module in some other embodiments;

[0046] FIG30 is a flowchart showing a galvanometer driving method in some embodiments;

[0047] FIG31 shows a flow chart of another galvanometer driving method in some embodiments. DETAILED DESCRIPTION

[0048] In order to make the purpose and implementation of this application clearer, the exemplary implementation of this application will be clearly and completely described below in conjunction with the drawings in the exemplary embodiments of this application. Obviously, the described exemplary embodiments are only part of the embodiments of this application, not all of the embodiments.

[0049] It should be noted that the brief descriptions of terms in this application are only for the purpose of facilitating the understanding of the embodiments described below, and are not intended to limit the embodiments of this application. Unless otherwise specified, these terms should be understood according to their ordinary and usual meanings.

[0050] The terms "comprise," "include," and "have," and any variations thereof, are intended to cover but not exclude inclusion; for example, a product or device comprising a list of components is not necessarily limited to all the components expressly listed but may include other components not expressly listed or inherent to such product or device.

[0051] An embodiment of the present application provides a galvanometer drive device, which is applied to a laser projection device (which may be simply referred to as a projection device). Figure 1 is a structural schematic diagram of a laser projection device provided by an embodiment of the present application. As shown in Figure 1, the laser projection device may include: a display control component 10, a light source drive component 20, a light source 30, a light valve 40, a galvanometer drive component 50, a galvanometer 60, and a lens 70. The display control component 10 is connected to the light source drive component 20, the light valve 40, and the galvanometer drive component 50 respectively. The light source drive component 20 is also connected to the light source 30. The galvanometer drive component 50 is also connected to the galvanometer 60. The galvanometer 60 is located on the light output side of the light valve 40, and the galvanometer 70 is located on the light output side of the galvanometer 60. Simply put, the galvanometer 60 is located between the light valve 40 and the lens 70. In some embodiments, the display control component may also be referred to as a processor, and the light source drive component may also be referred to as a laser drive component. The galvanometer drive device provided by an embodiment of the present application may include a display control component 10 and a galvanometer drive component 50, wherein the galvanometer drive component 50 includes a galvanometer drive circuit (detailed description is provided below).

[0052] There are one or more light source driver assemblies 20 (a plurality includes two or more, and three are shown in FIG1 ). The light source 30 includes one or more groups of lasers, with a plurality including two or more groups. Each group of lasers may include one or more lasers. A group of lasers corresponds to one light source driver assembly 20, and different groups of lasers correspond to different light source driver assemblies 20. The display control assembly 10 is connected to each light source driver assembly 20, and each light source driver assembly 20 is connected to a corresponding group of lasers.

[0053] The light source 30 may be a laser light source. For example, referring to FIG1 , the laser projection device includes three light source driving assemblies 20. Accordingly, the light source 30 includes three groups of lasers corresponding to the three laser driving assemblies 20. The three groups of lasers may be a blue laser 301, a red laser 302, and a green laser 303. The blue laser 301, the red laser 302, and the green laser 303 are connected to the corresponding light source driving assemblies 20, respectively. The blue laser 301 is used to emit blue laser light, the red laser 302 is used to emit red laser light, and the green laser 303 is used to emit green laser light. The laser projection device may be referred to as a three-color laser projection device.

[0054] In one possible implementation, if the light source 30 in a laser projection device includes two integrated groups of red lasers 302, a group of blue lasers 301, and a group of green lasers 303, then the laser projection device can be called a full-color laser projection device. The blue laser 301 in the laser projection device can be positioned between the red lasers 302 and the green lasers 303. Because the blue laser 301 can withstand higher temperatures, positioning the blue laser 301 between the red lasers 302 and the green lasers 303 facilitates rapid heat dissipation from the red lasers 302 and the green lasers 303, thereby increasing the reliability of the integrated multiple laser groups.

[0055] The display control component 10 outputs a blue PWM signal B_PWM corresponding to the blue laser 301 based on the blue primary color component of each frame sub-image, and outputs an enable signal B_EN corresponding to the blue laser 301 based on the lighting duration of the blue laser 301 within the driving cycle. The display control component 10 transmits the blue PWM signal B_PWM and the enable signal B_EN corresponding to the blue primary color component of each frame sub-image to the light source driver component 20, which is the light source driver component corresponding to the blue laser 301. In response to the blue PWM signal B_PWM and the enable signal B_EN, the light source driver component 20 corresponding to the blue laser 301 can provide a corresponding laser driving current to the blue laser 301 to drive the blue laser 301 to emit blue laser light.

[0056] The display control component 10 outputs a red PWM signal R_PWM corresponding to the red laser 302 based on the red primary color component of each frame sub-image, and outputs an enable signal R_EN corresponding to the red laser 302 based on the lighting duration of the red laser 302 within the driving cycle. The display control component 10 transmits the red PWM signal R_PWM and the enable signal R_EN corresponding to the red primary color component of each frame sub-image to the light source driver component 20, which is the light source driver component corresponding to the red laser 302. In response to the red PWM signal R_PWM and the enable signal R_EN, the light source driver component 20 corresponding to the red laser 302 can provide a corresponding laser driving current to the red laser 302, thereby driving the red laser 302 to emit red laser light.

[0057] The display control component 10 outputs a green PWM signal G_PWM corresponding to the green laser 303 based on the green primary color component of each frame sub-image, and outputs an enable signal G_EN corresponding to the green laser 303 based on the lighting duration of the green laser 303 within the driving cycle. The display control component 10 transmits the green PWM signal G_PWM and the enable signal G_EN corresponding to the green primary color component of each frame sub-image to the light source driver component 20, which is the light source driver component corresponding to the green laser 303. In response to the green PWM signal G_PWM and the enable signal G_EN, the light source driver component 20 corresponding to the green laser 303 can provide a corresponding laser driving current to the green laser 303 to drive the green laser 303 to emit green laser light.

[0058] After controlling the laser to start emitting laser light, the display control component 10 can control the light valve 40 to flip according to the primary color level value of the pixel in each frame sub-image, and realize the primary color level value by the length of time the micromirror in the light valve 40 flips, and forms the grayscale of the three primary colors of the corresponding pixel in conjunction with the corresponding color light irradiated on the light valve 40, and then project multiple frames of sub-images in sequence onto the projection screen (also called a display screen), and display the frame sub-image to different positions of the display screen 130 by controlling the deflection of the galvanometer 60.

[0059] In this embodiment of the present application, the multiple sub-image frames include two sub-image frames. When the laser light emitted by each laser irradiates the light valve 40, the display control component 10 can control the light valve 40 to flip according to the primary color scale values ​​of the pixels in each sub-image frame, so as to sequentially project the two sub-image frames onto the projection screen. The primary color scale values ​​can be red, green, and blue (RGB) color scale values.

[0060] In some embodiments, the display control component includes a field-programmable gate array (FPGA), and the digital waveform generation module in the galvanometer drive circuit provided in the embodiments of the present application can be integrated into the FPGA. In this way, the digital drive waveform signal (referred to as the digital drive waveform) that drives the galvanometer can be generated by the FPGA, saving device space and facilitating further miniaturization of the projection device.

[0061] In one possible implementation, the display control component 10 may include a digital light processing chip (DLPC). Exemplarily, the digital light processing chip may be DLPC 3437, or may be other DLPCs, which is not limited in the embodiments of the present application. The light valve 40 may be a digital micro-mirror device (DMD) or other devices with similar functions. The galvanometer 60 may be used to offset sub-images of different frames to different positions of the projection screen, thereby realizing the superimposed display of multiple sub-images (also referred to as sub-frame images) of a frame image, thereby achieving the effect of expanding the resolution of the laser projection device. In the embodiment of the present application, the galvanometer 60 may have two deflection positions, that is, the galvanometer 60 may offset the sub-image to two different positions of the projection screen, thereby increasing the resolution of the laser projection device by 1 times, for example, increasing the 720p resolution to 2K resolution, increasing the 3K resolution to 4K resolution, etc.

[0062] In an embodiment of the present application, multiple sub-images are obtained by splitting a target image to be projected. The resolution of the target image is greater than the resolution of the light valve, and the resolution of each sub-image after the splitting is no greater than the resolution of the light valve, for example, it can be equal to the resolution of the light valve. For example, the resolution of the target image can be M×N, where M is the number of pixels per row in the target image, and N is the number of pixels per column. The resolution of the light valve is M1×N1, where M1 is the number of pixels per row in the image that the light valve can project, and N1 is the number of pixels per column. The resolution of each sub-image can be m1×n1, where m1 is the number of pixels per row in each sub-image frame, and n1 is the number of pixels per column. M, N, M1, N1, m1, and n1 are all positive integers greater than 1, and M is greater than M1, N is greater than N1, m1 is no greater than M1, and n1 is no greater than N1.

[0063] For example, the resolution of the target image can be 3840×2160, that is, M is 3840 and N is 2160. The resolution of the light valve can be 2880×1620, that is, M1 is 2880 and N1 is 1620. The resolution of the subframe image is 2715×1527, that is, m1 is 2715 (approximately 3840). One percent), n1 is 1527 (about 2160 The sum of the resolutions of the two sub-images (2715×1527×2) is approximately equal to the target image resolution of 3840×2160, thereby doubling the displayed image resolution using a low-resolution light valve. The target image resolution of 3840×2160 is greater than the light valve resolution of 2880×1620, while the resolution of each sub-image (2715×1527) is less than the light valve resolution of 2880×1620.

[0064] In one possible implementation, a frame of target image to be projected (which may be an image with a lower resolution, such as an image with a 720p resolution) is processed into two frames of sub-images via the display control component 10. In the process of projecting and displaying each frame of sub-image, the display control component 10 can control the galvanometer drive component 50 to generate a digital drive waveform signal corresponding to the frame of sub-image. The galvanometer drive component 50 converts the digital drive waveform signal into an analog drive waveform signal (referred to as the analog drive waveform for short), and generates a first drive voltage and a second drive voltage with opposite phases based on the analog drive waveform signal. The first drive voltage is applied to the positive pole of the coil of the galvanometer, and the second drive voltage is applied to the negative pole of the coil of the galvanometer. The voltage difference between the first drive voltage and the second drive voltage (i.e., the drive signal) is used to drive the galvanometer 60 to deflect. Different frames of sub-images correspond to different digital drive waveform signals, thereby enabling the two frames of sub-images to be projected to different positions on the projection screen, thereby achieving the superposition display of the two frames of sub-images to display a frame of target image, that is, enabling the lower resolution image to be displayed at a higher resolution. The voltage direction of the driving signal may remain unchanged, so the deflection direction of the galvanometer 60 is a fixed direction, and the changing waveform of the driving signal may be a sine wave.

[0065] For example, referring to FIG. 2 , the galvanometer mirror 60 can deflect back and forth between position A and position B under the drive signal described above. Thus, during the projection and display of sub-image a of a target image, the display control component 10 controls the galvanometer mirror drive component 50 to generate a digital drive waveform signal corresponding to sub-image a. The galvanometer mirror drive component 50 applies a drive signal to the galvanometer mirror 60 based on the digital drive waveform signal, causing the galvanometer mirror 60 to deflect to position A. Thereafter, the galvanometer mirror 60 remains unchanged, thereby completing the display of sub-image a. During the projection and display of sub-image b of the target image, the display control component 10 controls the galvanometer mirror drive component 50 to generate a digital drive waveform signal corresponding to sub-image b. The galvanometer mirror drive component 50 applies a drive signal to the galvanometer mirror 60 based on the digital drive waveform signal, causing the galvanometer mirror 60 to deflect to position B. Thereafter, the galvanometer mirror 60 remains unchanged, thereby completing the display of sub-image b. Thus, for each target image, its two sub-images are projected at different deflection positions of the galvanometer mirror 60, thereby enabling the projection and display of different sub-images at different positions on the projection screen.

[0066] FIG3 is a schematic diagram of the structure of another laser projection device provided in an embodiment of the present application. In some embodiments, referring to FIG3 , the laser projection device may further include a main control chip 80, a power supply 90, a startup control component 100, and a program storage component 200. The main control chip 80 is connected to the startup control component 100 and the display control component 10, respectively. The power supply 90 is connected to the light source driving component 20, and the program storage component 200 is connected to the display control component 10. In some embodiments, the startup control component may include a power management chip. The laser projection device may be a projection television or other device.

[0067] The main control chip 80 sends a startup command to the startup control component 100. Upon receiving the startup command, the startup control component 100 begins operation, sequentially supplying 1.1 volts (V), 1.8V, 3.3V, 2.5V, and 5V to the display control component 10 according to its power-up sequence. After the power supply voltage and timing are correct, the startup control component 100 sends a reset signal to the display control component 10, reads the program from the external program storage component 200, and initializes the display control component 10. At this point, the entire laser projection device begins operation. Upon receiving the reset signal, the display control component 100 configures the startup control component 100 via the serial peripheral interface (SPI) and instructs the startup control component 100 to begin supplying power to the light valve 40. The control component 100 then starts outputting three voltages to the light valve 40: voltage bias (VBIAS) (e.g., 18V), voltage reset (VRST) (e.g., -14V), and voltage offset (VOFS) (e.g., 10V). Once the voltages on the light valve 40 are normal, the light valve 40 begins operating. The display control component 10 transmits the primary color scale values ​​of the sub-image to the light valve 40 via LVDS communication to enable display of the sub-image. The power supply in the laser projection device can be provided by a power board that converts 100V to 240V AC power into DC power to power various components.

[0068] In some embodiments, referring to FIG3 , the laser projection device further includes a detector 101 connected to the display control assembly 10 . The detector 101 can be used to calibrate the galvanometer mirror. The detector 101 can be a camera, a charge-coupled device (CCD), or other device.

[0069] Before projecting the target image, the galvanometer is calibrated. During the galvanometer calibration stage, the display control component 10 is configured to split the galvanometer calibration image into a first sub-image (also referred to as a first sub-frame) and a second sub-image (also referred to as a second sub-frame). For the first sub-frame, the galvanometer 60 is moved to a first position, and the first sub-image is projected at a first display position on the projection screen through the lens; for the second sub-frame, the galvanometer 60 is moved to a second position, and the second sub-image is projected at a second display position on the projection screen through the lens. Then, according to the offset between the first sub-image and the second sub-image captured by the detector 101, the first position and the second position of the galvanometer 60 are calibrated.

[0070] During the process of projecting and displaying the galvanometer calibration image, the main control chip 80 can decode the image signal of the galvanometer calibration image and send the decoded image signal of the galvanometer calibration image to the display control component 10 at a certain frequency (e.g., 60 Hz). Accordingly, the display control component 10 can receive the decoded image signal of the galvanometer calibration image sent by the main control chip 80. Thereafter, the display control component 10 can split the received decoded image signal of the galvanometer calibration image into a signal of a first sub-image and a signal of a second sub-image, thereby dividing the galvanometer calibration image into two frame sub-images.

[0071] After dividing the galvanometer calibration image to be projected into a first sub-image and a second sub-image, the display control component 10 can output at least one enable signal corresponding to the three primary colors of each frame of the sub-image, and transmit the at least one enable signal to the corresponding light source driver component 20. The at least one enable signal can also be called a laser current control signal, which is used to instruct the light source driver component 20 to provide a corresponding laser drive current to the laser to drive the laser to emit laser light. The laser current control signal can be a pulse width modulation (PWM) signal.

[0072] FIG4 is a schematic diagram of the structure of a lens assembly in a laser projection device provided in an embodiment of the present application. The lens assembly may include four reflective lenses 700, a lens assembly 800, a diffusion wheel 900, a light pipe 1000, a total internal reflection (TIR) ​​lens 1100, and a lens 70. The laser projection device also includes a display screen 130 (i.e., a projection screen), which is located on the light-emitting side of the lens 70. The lens assembly 800 includes a first lens 8001, a second lens 8002, and a third lens 8003, and each laser is provided with a reflective lens 700. In some embodiments, the galvanometer 60 can be regarded as a component in the lens assembly. The galvanometer 60 can be located on the light-incident side of the lens 70 and on the light-emitting side when the TIR lens 1100 is fully transmitted. Simply put, the galvanometer 60 can be located between the lens 70 and the TIR lens 1100.

[0073] It should be understood that the four reflective lenses in FIG4 correspond one-to-one to the four lasers, and the four lasers may include the two groups of red lasers 302 , a group of blue lasers 301 , and a group of green lasers 303 described above.

[0074] During the projection and display of the first sub-image, the blue laser light emitted by the blue laser 301 is reflected by the corresponding reflective lens 700, focused by the first lens 8001, homogenized by the diffuser wheel 900, and then homogenized by total internal reflection through the light guide 1000. The red laser light emitted by the red laser 302 is reflected by the corresponding reflective lens 700, focused by the first lens 8001, homogenized by the diffuser wheel 900, and homogenized by total internal reflection through the light guide 1000. The green laser light emitted by the green laser 303 is reflected by the corresponding reflective lens 700, focused by the first lens 8001, homogenized by the diffuser wheel 900, and homogenized by total internal reflection through the light guide 1000. After homogenization by the light pipe 1000, the blue, red, and green laser lights are shaped by the second lens 8002 and the third lens 8003 in a time-sharing manner and then enter the TIR lens 1100 for total internal reflection. As the three primary colors (i.e., blue, red, and green) are sequentially irradiated onto the light valve 40, the display control assembly 10 controls the light valve 40 to flip according to the primary color scale values ​​of the pixels in the first sub-image. The flipped light valve 40 reflects the light totally reflected by the TIR lens 1100, transmits it through the TIR lens 1100 again, is deflected by the galvanometer 60, and finally projects it onto the display screen 130 through the lens 70, thereby displaying the first sub-image on the display screen 130. Subsequently, the second sub-image is projected and displayed in a similar manner.

[0075] During the projection and display of each sub-image frame, the display control component 10 may transmit a galvanometer current control signal corresponding to the sub-image frame to the galvanometer drive component 50. The galvanometer current control signal is used to control the galvanometer drive component 50 to provide a galvanometer drive current to the galvanometer 60 to drive the galvanometer 60 to deflect. Alternatively, the display control component 10 may transmit a galvanometer voltage control signal corresponding to the sub-image frame to the galvanometer drive component 50. The galvanometer voltage control signal is used to control the galvanometer drive component 50 to provide a galvanometer drive voltage to the galvanometer 60 to drive the galvanometer 60 to deflect. For example, under the control of the galvanometer voltage control signal, the galvanometer drive component 50 generates a digital drive waveform signal corresponding to the sub-image frame, converts the digital drive waveform signal into an analog drive waveform signal, and generates a first drive voltage and a second drive voltage with opposite phases based on the analog drive waveform signal. The first drive voltage is applied to the positive electrode of the galvanometer coil, and the second drive voltage is applied to the negative electrode of the galvanometer coil. The voltage difference between the first drive voltage and the second drive voltage (i.e., the drive signal, or drive voltage) is used to drive the galvanometer 60 to deflect.

[0076] Different galvanometer mirror current control signals or galvanometer mirror voltage control signals correspond to different frame sub-images, thereby enabling the projection of multiple frame sub-images to different positions on the projection screen, thereby achieving superimposed display of the multiple frame sub-images, and thus displaying the target image on the display screen 130. Furthermore, during the process of projecting and displaying the multiple frame sub-images, the current direction of the galvanometer mirror drive current can alternate, and the waveform of the changing galvanometer mirror drive current can be a sine wave.

[0077] Taking the galvanometer circuit control signal as an example, during the projection and display of each sub-image frame, the light valve 40 sequentially receives illumination from the three primary colors. When the light valve 40 receives illumination from the target primary color of the three primary colors, the display control component 10 transmits the galvanometer current control signal corresponding to the sub-image to the galvanometer driver component 50. This galvanometer current control signal controls the galvanometer driver component 50 to supply a galvanometer drive current to the galvanometer mirror 60, driving the galvanometer mirror 60 to deflect. The galvanometer mirror 60 then remains unchanged, completing the display of the sub-image frame. Subsequently, during the display of the next sub-image frame, the display control component 10 and the galvanometer driver component 50 can again drive the galvanometer mirror 60 to deflect, and so on, thereby projecting different sub-image frames onto different locations on the projection screen.

[0078] During the projection and display of the first sub-image, the light valve 40 sequentially receives illumination from the three primary colors. When the light valve 40 receives illumination from the target primary color among the three primary colors, the display control component 10 may transmit a first galvanometer current control signal to the galvanometer driver component 50. The first galvanometer current control signal is used to control the galvanometer driver component 50 to drive the galvanometer 60 to rotate to the first position.

[0079] During the projection and display of the second sub-image, the light valve 40 sequentially receives illumination from the three primary colors. When the light valve 40 receives illumination from the target primary color among the three primary colors, the display control component 10 may transmit a second galvanometer mirror current control signal to the galvanometer mirror driving component 50. The second galvanometer mirror current control signal is used to control the galvanometer mirror driving component 50 to drive the galvanometer mirror 60 to rotate to the second position.

[0080] As shown in FIG5 , during the projection and display of the first sub-image P1, the light valve 40 sequentially receives illumination from the three primary colors. When the light valve 40 receives illumination from the blue primary color of the three primary colors, the display control assembly 10 transmits a first galvanometer current control signal to the galvanometer driver assembly 50. The galvanometer driver assembly 50 supplies a first galvanometer drive current to the coil in the galvanometer 60, which drives the galvanometer 60 to rotate a certain angle. This allows the center pixel in the first sub-image P1 to be offset by a certain distance in the positive direction of the A-axis relative to the coordinate origin o, i.e., the center pixel in the first sub-image P1 is located at position a on the A-axis.

[0081] As shown in FIG6 , during the projection and display of the second sub-image P2, the light valve 40 sequentially receives illumination from the three primary colors. When the light valve 40 receives illumination from the blue primary color of the three primary colors, the display control component 10 transmits a second galvanometer current control signal to the galvanometer driver component 50. The galvanometer driver component 50 supplies a second galvanometer drive current to the coil in the galvanometer 60, which drives the galvanometer 60 to rotate a certain angle. This allows the center pixel in the second sub-image P2 to be offset by a certain distance in the negative direction of the A-axis relative to the coordinate origin o, i.e., the center pixel in the second sub-image P2 is located at position b on the A-axis.

[0082] The galvanometer current control signals corresponding to different frame sub-images are different, so the galvanometer 60 can be driven to deflect to different positions, so that the multiple frame sub-images are superimposed and displayed on the display screen 130, and a high-resolution target image can be displayed on a low-resolution laser projection device without losing the pixel information of the target image.

[0083] FIG7 is a schematic diagram of the structure of a galvanometer provided in an embodiment of the present application. Referring to FIG7 , the galvanometer may include a base 61, a fixed plate 62, a spring (not shown in the figure, covered by a swinging member 63), a swinging member 63 and an optical lens 64; the base 61 has a first hollow area (also referred to as a first light-transmitting area), and one side of the base 61 is provided with two pillars 611, and the two pillars 611 are located at both ends of a diagonal of the first hollow area, that is, a pillar 611 is provided at each end of a diagonal of the first hollow area, and a magnetic component is also provided on this side of the base 61, and the magnetic component is located at one side of the first hollow area, that is, a magnetic component is provided at one side of the first hollow area, and the magnetic component includes a coil 612 and a magnet 613, and a connector 614 is provided at the end of the base 61, and the connector 614 They are respectively connected to the coil 612 and the output end of the galvanometer drive circuit; the fixed plate 62 is located on the side of the base 61 opposite to the magnetic component, the fixed plate 62 has a second hollow area (also called a second light-transmitting area), and the fixed plate 62 is used to fix the base 61; the spring is fixed on two pillars 611, for example, the two ends of the spring are respectively fixed on a pillar 611, and one pillar 611 fixes one end of the spring, and the swinging member 63 is covered on the spring with these two pillars 611 as a fulcrum, and the swinging member 63 has a third hollow area (also called a third light-transmitting area), and the third hollow area is used to support the optical lens 64, and the orthographic projection of the optical lens 64 on the base 61 and the orthographic projection of the second hollow area on the base 61 both overlap with the first hollow area.

[0084] In one possible implementation, as shown in FIG7 , a support plate 621 and an insert 622 extending from the base 61 are provided on one side of the second hollowed-out region of the fixed plate 62. The support plate 621 abuts against the side of the base 61 and serves to secure the coil 612 and magnet 613. The galvanometer provided in this embodiment is a two-dimensional galvanometer, or a single-axis galvanometer. When the galvanometer drive circuit inputs a drive signal to the coil 612 via the connector 614, the magnetic component generates an attraction or repulsion effect. This attraction or repulsion causes the side ends of the swing member 63 to swing about a virtual axis L (i.e., a diagonal of the swing member 63, also known as the diagonal along which the two struts 611 are located). This causes the two sub-images to be projected to different locations, thereby doubling the resolution of the laser projection device. The position of the virtual axis L shown in FIG7 deviates from the actual swing axis; the actual swing axis is determined by the diagonal along which the struts of the specific device are located.

[0085] In the related art, when a galvanometer is vibrating at high speed, high-voltage DC drive is easily generated when the galvanometer is turned on and off, causing the galvanometer coil to burn out and rendering the galvanometer inoperable. For example, the power supplies of various components in a laser projection device are immediately powered on upon startup, but the galvanometer drive waveform signals required by the galvanometer drive device have not yet been properly output. Therefore, high-voltage pulses are output to the galvanometer for a period of time during startup. However, for example, galvanometer specifications require a DC voltage of no more than 1.2V. If the voltage across the galvanometer exceeds 1.2V in DC voltage mode, the galvanometer coil will burn out. The higher the DC voltage, the shorter the time to burn out, and the higher the probability of coil burnout. Similarly, high-voltage DC drive is not allowed during startup, but also at any time during galvanometer operation. For example, when shutting down the device, or if a DLP chip malfunction causes the galvanometer drive circuit to stop outputting the galvanometer drive waveform signals, while the power supplies to the galvanometer drive circuit are not turned off, this can also result in high-voltage DC output, which can in turn burn out the galvanometer coil.

[0086] In order to solve this problem, an embodiment of the present application provides a galvanometer drive device. FIG8 is a structural schematic diagram of a galvanometer drive device provided by an embodiment of the present application. Referring to FIG8 , the galvanometer drive device includes a DLP unit circuit, a delay circuit, a switch circuit, and a galvanometer drive circuit (not shown). Part or all of the DLP unit circuit, the delay circuit, and the switch circuit can be set in the display control component 10 introduced above, or can be set inside other components. The embodiment of the present application does not limit this. In some embodiments, the DLP unit circuit, the delay circuit, and the switch circuit can be circuits in the galvanometer power supply control circuit, that is, the galvanometer drive device includes the galvanometer power supply control circuit and the galvanometer drive circuit, wherein the galvanometer power supply control circuit includes the DLP unit circuit, the delay circuit, and the switch circuit.

[0087] As shown in Figure 8, the command signal output end of the DLP unit circuit is connected to the input end of the delay circuit, the subframe synchronization signal output end (not shown) of the DLP unit circuit is connected to the galvanometer drive circuit, the output end of the delay circuit is connected to the control end of the switching circuit, the input end of the switching circuit is connected to the power supply of the galvanometer drive circuit, and the output end of the switching circuit is connected to the power input end of the galvanometer drive circuit, which power input end is, for example, P12V.

[0088] Among them, the DLP unit circuit is configured as follows: when the DLP unit circuit is successfully configured, a configuration success command signal is output through the command signal output end, and a galvanometer sub-frame synchronization signal is output through the sub-frame synchronization signal output end. The galvanometer sub-frame synchronization signal is used to instruct the galvanometer drive circuit to drive the galvanometer deflection.

[0089] The delay circuit is configured to: when the input end of the delay circuit receives the configuration success command signal output by the DLP unit circuit, after a first delay (such as a preset delay), output an opening signal to the control end of the switch circuit.

[0090] The switch circuit is configured to: when the control end of the switch circuit receives the start signal, conduct the electrical connection between the input end of the switch circuit and the output end of the switch circuit.

[0091] It can be seen from this that in the embodiment of the present application, the DLP unit circuit can only output a configuration success command signal to the delay circuit when the configuration is successful. At this time, the DLP unit circuit also outputs a galvanometer mirror frame synchronization signal to the galvanometer drive circuit. After receiving the configuration success command signal, the delay circuit will output an on signal to the control end of the switch circuit after a first delay, so that the power supply supplies power to the galvanometer drive circuit. By setting this delay, it can be ensured that the galvanometer mirror frame synchronization signal is first transmitted to the galvanometer drive circuit, and only then is the power supply supplied to the galvanometer drive circuit. This can avoid the phenomenon that the power supply is turned on first to generate a DC high-voltage pulse before the galvanometer mirror frame synchronization signal is transmitted to the galvanometer drive circuit, causing the galvanometer coil to burn out. This solves the problem of the galvanometer coil being easily burned out and improves the reliability of the laser projection equipment.

[0092] Figure 9 is a circuit diagram of a galvanometer power supply control device provided in an embodiment of the present application. In some embodiments, as shown in Figure 9, the delay circuit includes an MCU (which can be a single-chip microcomputer), which is denoted as N10. The command signal output terminal of the DLP unit circuit is connected to the input terminal of the MCU (denoted as IO1, also known as the detection port), and the output terminal of the MCU (denoted as IO2) is connected to the control terminal of the switch circuit. The MCU is configured such that when the input terminal of the MCU receives the configuration success command signal output by the DLP unit circuit, after a first delay, the output terminal of the MCU outputs an on signal to the control terminal of the switch circuit.

[0093] In some embodiments, the MCU further includes an abnormal signal port, which is used to receive an abnormal signal, and the abnormal signal indicates that there is an abnormality in the device, such as a fan failure and / or device overheating. As shown in Figure 9, the abnormal signal port may include a fan failure signal port and an overheating signal port, wherein the fan failure signal port is used to receive a fan failure signal, and the overheating signal port is used to receive an overheating signal, that is, the abnormal signal includes a fan failure signal and an overheating signal. The MCU is configured as follows: when the input terminal IO1 of the MCU receives the configuration success command signal output by the DLP unit circuit, and does not receive the fan failure signal and the overheating signal, after a first delay, the output terminal IO2 outputs a start signal to the control terminal of the switch circuit, thereby ensuring that the MCU will only output a start signal when there is no fan failure, overheating or other faults in the system.

[0094] In other embodiments, the MCU may include a fan fault signal port but not an overheat signal port, that is, the abnormal signal port includes a fan fault signal port, and the MCU is configured such that: when the input terminal IO1 of the MCU receives a configuration success command signal output by the DLP unit circuit and does not receive a fan fault signal, after a first delay, the output terminal IO2 outputs an enable signal to the control terminal of the switch circuit. In still other embodiments, the MCU may include an overheat signal port but not a fan fault port, that is, the abnormal signal port includes an overheat signal port, and the MCU is configured such that: when the input terminal IO1 of the MCU receives a configuration success command signal output by the DLP unit circuit and does not receive an overheat signal, after a first delay, the output terminal IO2 outputs an enable signal to the control terminal of the switch circuit.

[0095] In some embodiments, as shown in FIG9 , the DLP unit circuit includes a master DLP chip (denoted as N5) and a slave DLP chip (denoted as N6). The DLP unit circuit is configured to output a configuration success command signal to the input terminal of the delay circuit via the command signal output terminal when both the master DLP chip and the slave DLP chip are successfully configured.

[0096] In some embodiments, as shown in FIG9 , the DLP unit circuit further includes a first transistor (denoted as N7), a second transistor (denoted as N8), and an AND gate circuit (denoted as N9). The first transistor is configured to, upon receiving a low-level configuration success signal output by the master DLP chip, output a high-level configuration success command signal to one input terminal of the AND gate circuit. The second transistor is configured to, upon receiving a low-level configuration success signal output by the slave DLP chip, output a high-level configuration success command signal to the other input terminal of the AND gate circuit. The AND gate circuit is configured to, upon receiving a high-level configuration success command signal at both input terminals of the AND gate circuit, output a configuration success command signal to the input terminal of the delay circuit. For ease of distinction, in some embodiments, the input terminals of the AND gate circuit connected to the master DLP chip and the slave DLP chip may be referred to as the first input terminal and the second input terminal, respectively.

[0097] In one possible implementation, as shown in FIG9 , the command signal output terminal of the master DLP chip is connected to the base of the first transistor via resistor R10. The collector of the first transistor is connected to a 3.3V high-level power supply via resistor R11. The base of the first transistor is grounded via resistor R12. The collector of the first transistor is also connected to the first input of an AND gate circuit, and the emitter of the first transistor is grounded. The command signal output terminal of the slave DLP chip is connected to the base of the second transistor via resistor R13. The collector of the second transistor is connected to a 3.3V high-level power supply via resistor R14. The base of the second transistor is grounded via resistor R15. The collector of the second transistor is also connected to the second input of the AND gate circuit, and the emitter of the second transistor is grounded. The output of the AND gate circuit is connected to the input of the MCU.

[0098] The resistance values ​​of resistors R10, R11, R12, R13, R14, and R15 can be 1K, 10K, 100K, 1K, 10K, and 100K ohms, respectively. Of course, these resistance values ​​are only examples and are not intended to limit the embodiments of the present application. These resistors can also have other resistance values. The voltage level of the high-level power supply can also be other than 3.3V, for example, it can be 3.8V, 5V, etc., and this embodiment of the present application is not limited to this.

[0099] The configuration success signals output by the master DLP chip and the slave DLP chip are usually valid at low level. Through the first transistor and the second transistor, the configuration success signal is pulled up to a high-level configuration success command signal of 3.3V, and then output to the MCU after passing through the AND gate circuit, so that the MCU can receive and identify it.

[0100] In some embodiments, the switch circuit includes a transistor configured to: conduct an electrical connection between a source of the transistor and a drain of the transistor when a gate of the transistor receives a turn-on signal.

[0101] In one possible implementation, as shown in FIG9 , the transistor is a PMOS (denoted as N12 ), and the switching circuit further includes a third transistor (denoted as N11 ). The base of the third transistor is connected to the output terminal of the MCU via a resistor R16 , and is also grounded via a resistor R17 . The emitter of the third transistor is grounded, and the collector of the third transistor is connected to the gate of the PMOS via a resistor R18 . The source of the PMOS is connected to the power supply VIN . A capacitor C5 and a resistor R19 are connected in parallel between the gate and source of the PMOS . The drain of the PMOS is connected to the power input terminal P12V of the galvanometer drive circuit.

[0102] When the base of the third transistor receives a high-level start-up signal, the third transistor is turned on and grounded, the gate of the PMOS is at a low level, the PMOS is turned on, and the system's 12V power supply VIN is input to P12V, and the power supply P12V of the operational amplifier circuit N4 of the galvanometer drive circuit is powered on to provide driving voltage for the galvanometer.

[0103] The embodiment of the present application can ensure that the galvanometer mirror frame synchronization signal is first transmitted to the galvanometer mirror drive circuit by setting a first delay, and the galvanometer mirror drive circuit is powered by the power supply only after that. This can avoid the phenomenon that the power supply is turned on first to generate a DC high-voltage pulse before the galvanometer mirror frame synchronization signal is transmitted to the galvanometer mirror drive circuit, causing the galvanometer mirror coil to burn out, thereby solving the problem of the galvanometer mirror coil being easily burned out and improving the safety and reliability of the laser projection equipment.

[0104] In some embodiments, the duration of the first delay may range from 20 to 500 ms, thereby providing sufficient time for the galvanometer mirror frame synchronization signal to be transmitted to the galvanometer drive circuit, thereby ensuring the safety and reliability of the laser projection device.

[0105] In some embodiments, as shown in FIG10 , the DLP unit circuit may also include only one DLP chip (denoted as N5) and a first transistor (denoted as N7). The first transistor N7 is configured to output a high-level configuration success command signal to the input terminal of the delay circuit upon receiving a low-level configuration success signal output by the DLP chip.

[0106] In one possible implementation, as shown in Figure 10 , the command signal output terminal of the DLP chip is connected to the base of the first transistor via resistor R10. The collector of the first transistor is connected to a 3.3V high-level power supply via resistor R11. The base of the first transistor is grounded via resistor N12. The collector of the first transistor is also connected to the input of the delay circuit, and the emitter of the first transistor is grounded. The configuration success signal output by the DLP chip is typically active low. The first transistor N7 pulls the configuration success signal up to a 3.3V high-level configuration success command signal, facilitating its reception and recognition by the MCU.

[0107] In some embodiments, as shown in FIG11 , the MCU does not have a delay function, and a delay circuit (denoted as N13) is separately provided between the output terminal IO2 of the MCU and the third transistor N11. After the delay circuit N13 receives the start signal output by the MCU, it transmits the start signal to the base of the third transistor after a first delay.

[0108] In some embodiments, as shown in FIG12 , a voltage divider resistor R20 is connected in series between the galvanometer drive circuit and the galvanometer coil. The figure only shows a partial circuit between the output terminals V_p and V_n of the galvanometer drive circuit and the galvanometer. The output terminal of the galvanometer drive circuit is connected to the galvanometer via a connector, and the voltage divider resistor R20 is connected in series between the output terminal V_p and the connector. V_p and V_n correspond to the first drive voltage and the second drive voltage, respectively.

[0109] A series voltage-dividing resistor R20 is added to the galvanometer path. This voltage-dividing resistor R20 can be equal to or different from the resistance of the galvanometer coil. This voltage-dividing resistor R20 is used to divide the voltage with the galvanometer coil. When a DC high-voltage pulse occurs, the DC voltage applied to both ends of the galvanometer coil is reduced. In other words, the current of the galvanometer coil is reduced in DC mode, thereby reducing the heating of the galvanometer coil and further reducing the possibility of burning the galvanometer coil. For example, if the galvanometer coil resistance is 12.1 ohms, a 12.1 ohm series resistor is added to the path of the output terminal V_p of the operational amplifier circuit. After voltage division with the galvanometer coil, the voltage applied to both ends of the galvanometer coil is reduced to half of the original voltage, thereby reducing the DC voltage applied to the galvanometer coil and reducing the heating of the galvanometer coil, thereby further protecting the galvanometer coil.

[0110] In addition to the problem that the coil is easily burned, the related art also has the problem of high circuit cost. For example, the related art drives the galvanometer deflection by directly applying a driving current to the coil. However, the current driving method requires both a positive voltage generating circuit and a negative voltage generating circuit. The circuit requires more components, which increases the cost of the galvanometer driving circuit. Based on this, an embodiment of the present application provides a galvanometer driving device, which drives the galvanometer deflection by applying a driving voltage at both ends of the coil, thereby reducing the negative voltage generating circuit and reducing costs. For example, the difference between the above-mentioned first driving voltage and the second driving voltage is used to drive (i.e., drive signal) the galvanometer deflection. That is to say, the method of using the difference between the first driving voltage and the second driving voltage mentioned above to drive the galvanometer deflection is designed by the embodiment of the present application to reduce costs. This will be introduced below.

[0111] Figure 13 is a block diagram of a galvanometer drive circuit provided in an embodiment of the present application. As shown in Figure 13 , the galvanometer drive circuit may include: a digital waveform generation module 1, a digital-to-analog conversion module 2, and an operational amplifier module 3. The digital waveform generation module 1 is connected to the digital-to-analog conversion module 2. The digital waveform generation module 1 is configured to generate a digital waveform signal and transmit the digital waveform signal to the digital-to-analog conversion module 2. Wherein, the digital waveform signal includes a digital drive waveform signal; the digital-to-analog conversion module 2 is also connected to the operational amplifier module 3, and the digital-to-analog conversion module 2 is used to perform digital-to-analog conversion on the digital drive waveform signal to obtain an analog drive waveform signal, and transmit the analog drive waveform signal converted from the digital-to-analog conversion to the operational amplifier module 3, that is, transmit the analog drive waveform signal to the operation method module 3; the operational amplifier module 3 is also connected to the positive pole and the negative pole of the coil of the galvanometer, and the operational amplifier module 3 is used to generate a first drive voltage and a second drive voltage with opposite phases based on the analog drive waveform signal, and transmit the first drive voltage to the positive pole of the coil and the second drive voltage to the negative pole of the coil, that is, transmit the first drive voltage to the positive pole of the coil of the galvanometer and transmit the second drive voltage to the negative pole of the coil of the galvanometer. Wherein, the difference between the first drive voltage and the second drive voltage is the drive signal of the galvanometer, and the drive signal is used to drive the galvanometer deflection.

[0112] In this embodiment, the digital waveform generation module 1 may include a positive voltage generation circuit, specifically a waveform generator, such as a galvanometer drive waveform generator. The digital waveform generation module 1 may be built into an FPGA. The amplitudes of the waveform corresponding to the digital drive waveform signal may be stored in a lookup table. By setting the number of amplitudes required to generate the digital drive waveform signal (e.g., a target number of segments) and the number of clock cycles (clock cycles of the digital-to-analog conversion module 2) required to output each amplitude (e.g., a target segment length), the digital waveform generation module 1, in conjunction with the lookup table, can sequentially output the amplitudes for the target number of segments, thereby generating the digital drive waveform signal.

[0113] The digital-to-analog conversion module 2 may include a DAC converter, also referred to as a digital-to-analog converter. Upon receiving the digital drive waveform signal transmitted by the digital waveform generation module 1, the digital-to-analog conversion module 2 is capable of converting the digital drive waveform signal into an analog drive waveform signal. Since the operational amplifier module 3 cannot directly amplify digital signals, the operational amplifier module 3 can then amplify the analog drive waveform signal after the digital-to-analog conversion module 2 converts the digital drive waveform signal into an analog drive waveform signal.

[0114] In addition, the operational amplifier module 3 may include at least one operational amplifier group, and one operational amplifier group may include two operational amplifiers. In the embodiment of the present application, the operational amplifier module 3 includes one operational amplifier group, that is, the analog drive waveform signal is amplified by two operational amplifiers to obtain a first drive voltage and a second drive voltage with opposite phases. In one possible implementation, the two operational amplifiers can be implemented by a dual operational amplifier chip. In this embodiment, since the first drive voltage and the second drive voltage are in opposite phases, the amplitude of the drive signal obtained by using the difference between the first drive voltage and the second drive voltage is at least twice the amplitude of the analog drive waveform signal. In this way, a voltage signal with a smaller amplitude can be used to generate a voltage drive signal with a larger amplitude. This not only avoids the operational amplifier module 3 from being burned due to the excessive amplitude of the analog drive waveform signal, but also improves the stability of the voltage drive.

[0115] Based on the above technical solution, the digital waveform generation module 1 can generate a corresponding digital driving waveform signal according to the actual sub-image, thereby generating driving signals with different phases to drive the galvanometer to deflect to different positions, thereby realizing the offset of the two frames of sub-images, thereby improving the image display resolution.

[0116] The galvanometer drive circuit provided in the embodiment of the present application adopts an operational amplifier module to split the analog drive waveform signal into two, thereby obtaining a first drive voltage and a second drive voltage with opposite phases, and applies the first drive voltage to the positive pole of the coil of the galvanometer, and applies the second drive voltage to the negative pole of the coil of the galvanometer, and utilizes the difference between the first drive voltage and the second drive voltage to realize voltage drive of the galvanometer. In this way, the galvanometer drive circuit provided in the embodiment of the present application only needs to adopt one voltage generation circuit (corresponding to the digital waveform generation module in the embodiment of the present application), and processes the analog drive waveform signal generated by the digital waveform generation module and converted by the digital-to-analog conversion module into two drive voltages with opposite phases through the operational amplifier module, and utilizes the difference between the two drive voltages to realize voltage drive of the galvanometer to drive the galvanometer deflection, thereby saving one voltage generation circuit and reducing the cost of the galvanometer drive circuit.

[0117] In addition, in the related art, when the galvanometer is driven by current driving, since the galvanometer is connected in series in the galvanometer driving circuit, when the galvanometer works abnormally, it is impossible to determine whether it is a galvanometer driving circuit fault or a galvanometer fault by detecting the driving current. However, the embodiment of the present application drives the galvanometer by voltage driving. When the galvanometer works abnormally, it can be determined whether it is a galvanometer driving circuit fault or a galvanometer fault by detecting the first driving voltage and the second driving voltage. For example, when the first driving voltage and the second driving voltage are normal, it indicates that the galvanometer driving circuit is working normally, and the galvanometer fault can be determined at this time; when the first driving voltage and the second driving voltage are abnormal, it indicates that the galvanometer driving circuit is faulty. Therefore, the driving method provided by the embodiment of the present application is more conducive to troubleshooting the cause of the fault.

[0118] Based on the above description, in some embodiments, referring to FIG14 , the operational amplifier module 3 includes a first operational amplifier A1 and a second operational amplifier A2. The output terminal of the digital-to-analog conversion module 2 for outputting the analog drive waveform signal is connected to an input terminal of the first operational amplifier A1 and an input terminal of the second operational amplifier A2, respectively. The output terminal of the first operational amplifier A1 is connected to the positive electrode of the coil, and the output terminal of the second operational amplifier A2 is connected to the negative electrode of the coil. For ease of distinction, in some embodiments, the input terminal of the first operational amplifier A1 for receiving the analog drive waveform signal and the input terminal of the first operational amplifier A2 for receiving the analog drive waveform signal are referred to as the first input terminal and the second input terminal, respectively. It should be understood that the first input terminal and the second input terminal here are not the first input terminal and the second input terminal of the AND gate circuit discussed above.

[0119] Among them, one of the first operational amplifier A1 and the second operational amplifier A2 implements in-phase amplification, and the other implements inverting amplification. For example, the output end of the digital-to-analog conversion module 2 is respectively connected to the inverting input end of the first operational amplifier A1 and the non-inverting input end of the second operational amplifier A2. The output end of the first operational amplifier A1 is connected to the positive pole of the coil, and the output end of the second operational amplifier A2 is connected to the negative pole of the coil. Wherein, the first operational amplifier A1 implements inverting amplification, and the analog drive waveform signal is input from the inverting input end of the first operational amplifier A1, so the output of the first operational amplifier A1 is in phase with the input. The second operational amplifier A2 implements in-phase amplification, and the analog drive waveform signal is input from the non-inverting input end of the second operational amplifier A2, so the output of the second operational amplifier A2 is in phase with the input. It should be understood that an operational amplifier includes two input ends, namely, a non-inverting input end and an inverting input end. By designing the connection between the output end of the digital-to-analog conversion module 2 and the non-inverting input end and the inverting input end of the operational amplifier, in-phase amplification or inverting amplification can be achieved. The embodiment of the present application uses an operational amplifier for in-phase amplification and an operational amplifier for inverting amplification to generate a first driving voltage and a second driving voltage with opposite phases.

[0120] In some embodiments, as shown in Figure 15, the first input terminal of the first operational amplifier A1 is an inverting input terminal, and the operational amplifier module further includes a first resistor R2, a second resistor R3, a third resistor R4 and a fourth resistor R5; the first resistor R2 is respectively connected to the output terminal of the digital-to-analog conversion module for outputting the analog drive waveform signal and the inverting input terminal of the first operational amplifier A1, the second resistor R3 is respectively connected to the inverting input terminal of the first operational amplifier A1 and the output terminal of the first operational amplifier A1, the third resistor R4 and the fourth resistor R5 are connected in series between the power supply voltage V_DAC and ground, and the non-inverting input terminal of the first operational amplifier A1 is connected between the third resistor R4 and the fourth resistor R5.

[0121] The voltages at the non-inverting input terminal A1+ and the inverting input terminal A1- of the operational amplifier A1 are recorded as V_A1+ and V_A1- respectively. According to the virtual short and virtual open principles of the operational amplifier, we can obtain:

[0122] From formula (2), we can get:

[0123] Substituting formula (1) into formula (3) yields:

[0124] Therefore, the analog driving waveform signal Vi is inverted and amplified by the first operational amplifier A1 to obtain the first driving voltage V_p.

[0125] In some embodiments, continuing to refer to Figure 15, the second input terminal of the second operational amplifier A2 is the non-inverting input terminal, and the operational amplifier module also includes a fifth resistor R6, a sixth resistor R7, a seventh resistor R8 and an eighth resistor R9; the fifth resistor R6 is respectively connected to the output terminal of the digital-to-analog conversion module for outputting the analog drive waveform signal and the non-inverting input terminal of the second operational amplifier A2, the sixth resistor R7 is respectively connected to the power supply voltage V_DAC and the non-inverting input terminal of the second operational amplifier A2, the seventh resistor R8 and the eighth resistor R9 are connected in series between the output terminal of the second operational amplifier A2 and the ground, and the inverting input terminal of the second operational amplifier A2 is connected between the seventh resistor R8 and the eighth resistor R9.

[0126] According to the virtual short and virtual open principles of the operational amplifier, we can get:

[0127] V A2 =V A2 (5)

[0128] Substituting formula (7) into formula (6) yields:

[0129] Therefore, the analog driving waveform signal Vi is amplified in phase by the second operational amplifier A2 to obtain the second driving voltage V_n.

[0130] According to formula (4) and formula (8), the formula of the driving signal can be obtained:

[0131] Therefore, based on the above formula (9), various parameters such as resistance can be configured according to the actual galvanometer requirements, and the digital driving waveform signal output by the digital waveform generation module can be converted into an amplified driving signal that can drive the galvanometer to achieve galvanometer deflection.

[0132] Referring to FIG. 15 , the first operational amplifier A1 and the second operational amplifier A2 described above can be implemented by a dual operational amplifier chip N4. Dual operational amplifier chip N4 has multiple pins, including pins 1 to 16. Pins 7, 8, and 2 are the inverting input, non-inverting input, and output of the first operational amplifier A1, respectively. Pins 10, 9, and 16 are the inverting input, non-inverting input, and output of the second operational amplifier A2, respectively. Pin 1 is connected to the power supply P12V, while pins 4, 5, 12, and 13 are connected to ground. The remaining pins are not used in this embodiment of the present application.

[0133] In some embodiments, the digital waveform signal also includes a waveform output clock signal and a waveform output enable signal, wherein the waveform output clock signal is used to provide a control clock for generating a digital drive waveform signal and an analog drive waveform signal, and the waveform output enable signal is used to instruct the digital-to-analog conversion module to perform digital-to-analog conversion on the digital drive waveform signal and output an analog drive waveform signal.

[0134] In some embodiments, referring to Figures 16 and 17 , the galvanometer drive circuit further includes a level conversion module 4 (a level conversion chip in Figure 17 ); the level conversion module 4 is capable of performing logic level conversion based on VCCA and VCCB, for example, performing logic level conversion on a digital waveform signal having a logic level equal to VCCB to obtain a digital waveform signal having a logic level equal to VCCB. Specifically, the level conversion module 4 is connected to the digital waveform generation module 1 and the digital-to-analog conversion module 2, respectively. The level conversion module 4 is configured to convert the logic level of the digital waveform signal to a logic level that matches the operating level of the digital-to-analog conversion module 2, thereby enabling the normal operation of the digital-to-analog conversion module 2 and achieving conversion of the digital drive waveform signal by the digital-to-analog conversion module 2.

[0135] For example, the waveform output clock signal (referred to as the clock signal) WG_CLK and the waveform output enable signal (also known as the synchronization signal) WG_SYNCz are at a 1.8V level, and the amplitude level (i.e., logic level) of the digital drive waveform signal (also known as drive waveform data) WG_DATA is 1.8V, while the operating level of the digital-to-analog conversion module 2 is 3.3V. In this case, the logic level of the digital waveform signal needs to be converted to 3.3V by the level conversion module 4, and then the converted digital waveform signal is transmitted to the digital-to-analog conversion module 2. The converted digital waveform signal includes the digital drive waveform signal DAC_DATA, the waveform output clock signal DAC_CLK, and the waveform output enable signal SYNCz.

[0136] Based on the above embodiment, the embodiment of the present application discloses the first drive voltage, the second drive voltage and the drive signal by configuring the parameters of the circuit elements. In some embodiments, referring to Figure 17, C1, C2, C3, and C4 are all 100nF, R1 = 100K, R2 = 40.2K, R3 = 121K, R4 = 10K, R5 = 47.5K, R6 = 5.6K, R7 = 56K, R8 = 5.1K, R9 = 12K, and the V_DAC voltage is 3.3V. Among them, C1, C2, C3, and C4 can be filter capacitors. Substituting the above parameters into the above formulas (4) and (7), formulas (10) and (11) can be obtained.

[0137] V_p=10.9-3Vi (10)

[0138] V_n=1+3.05Vi (11)

[0139] Referring to Figure 18, Vi is a waveform with a maximum amplitude of 3.3V. This waveform is input to the inverting input terminal A1- of the first operational amplifier A1, and the output waveform is inverted and amplified. The amplified relationship between the output waveform of the first operational amplifier A1 and the input waveform corresponds to the relationship in formula (8). The output voltage waveform V_p of the first operational amplifier A1 is the input waveform inverted and amplified. The actual output waveform Vi_L voltage is approximately 1.3V, corresponding to the output waveform V_p_H voltage of approximately 7V. The Vi_H voltage is approximately 1.96V, corresponding to the output waveform V_p_L voltage of approximately 5V. The waveform after the peak-to-valley difference is amplified is approximately three times that of the input waveform. The actual input and output waveforms correspond one-to-one with the relationship in the formula and are consistent.

[0140] Vi is also input to the in-phase input terminal A2+ of the second operational amplifier A2. The input waveform Vi is the same as the input waveform input to the first operational amplifier A1. The output waveform is amplified in-phase and the waveforms are in-phase. The amplification relationship between the output waveform of the second operational amplifier A2 and the input waveform is the corresponding relationship in formula (9). Referring to Figure 19, the actual waveform output Vi_L voltage is about 1.3V, corresponding to the output waveform V_n_L voltage of about 4.965V, and the Vi_H voltage is about 1.96V, corresponding to the output waveform V_n_H voltage of about 6.978V. Its actual input and output waveforms correspond to the formula relationship one by one. This verifies that the maximum and minimum amplitudes of the V_p and V_n waveforms are approximately the same, the parameter configuration is correct, and it is the required driving waveform. The voltage applied to both ends of the galvanometer is the difference between the output waveform V_p of the first operational amplifier A1 and the output waveform V_n of the second operational amplifier A2. As shown in Figure 20, the waveform with the largest amplitude is the waveform of the final voltage signal of the galvanometer, and the amplitude V is twice the input amplitude Vid. The galvanometer moves under the drive of this voltage driving waveform. The voltage level of driving the galvanometer is relatively high (eg, the peak high level part reaches 8V), which improves the driving stability.

[0141] The galvanometer drive circuit provided in the embodiments of the present application can be applied to the galvanometer drive device (including the DLP chip) in the related art, and can also be applied to the galvanometer drive device provided in the embodiments of the present application, such as the galvanometer drive device shown in Figures 8 to 12. However, it should be understood that if the galvanometer drive circuit provided in the embodiments of the present application is applied to the galvanometer drive device in the related art, the problem of the coil being easily burned out still exists. This is described below with reference to the galvanometer drive circuit shown in Figure 17.

[0142] The embodiment of the present application is explained by taking the use of two-dimensional voltage (i.e., a first driving voltage and a second driving voltage) to drive a galvanometer as an example. The galvanometer driving circuit is shown in Figure 17, including a digital waveform generation module (which can be a video image processing chip N1), a level conversion module (which can be a level conversion chip N2), a digital-to-analog conversion module (which can be a digital-to-analog converter N3), an operational amplifier module (which can include an operational amplifier A1 and an operational amplifier A2), etc.

[0143] The video image processing chip N1 of the laser projection device can be implemented using a field programmable gate array (FPGA) or other methods. After receiving the galvanometer mirror frame synchronization signal from the DLP chip (included in the DLP unit circuit), N1 outputs the galvanometer mirror synchronization signal WG_SYNCz, clock signal WG_CLK and drive waveform data WG_DATA. This drive waveform data is converted from the level of VCCA (1.8V) to VCCB (3.3V) by the level conversion chip N2, and then converted to a matching level that can be recognized by the back-end digital-to-analog converter N3. The synchronization signal SYNCz, clock signal DAC_CLK and drive waveform data DAC_DATA are output to the digital-to-analog converter N3. The drive waveform data is converted from digital quantity to analog quantity Vi by the digital-to-analog converter N3 and then output to the operational amplifier circuit N4. The analog drive waveform Vi is simultaneously input to two operational amplifiers, A1 and A2, in N4. On one hand, it is input to the inverting input of operational amplifier A1. After amplification by operational amplifier A1, it outputs a voltage waveform V_p, which serves as the positive terminal voltage of the galvanometer, applied to the positive terminal of the galvanometer coil. On the other hand, it is input to the non-inverting input of operational amplifier A2. After amplification by operational amplifier A2, it outputs a negative terminal voltage V_n, applied to the negative terminal of the galvanometer coil. Therefore, the drive voltage across the galvanometer is V_p - V_n. Under normal operation, the galvanometer moves, i.e., deflects, driven by the analog drive voltage waveform V_p - V_n.

[0144] The normal drive circuit design is such that when the FPGA outputs the galvanometer drive waveform data, the VCCA and VCCB power supplies for N2, the V_DAC power supply for N3, the P12V power supply for N4, the V_DAC power supply for the voltage divider resistor at the non-inverting terminal of op amp A1, and the V_DAC power supply for the pull-up resistor of op amp A2 (Figure 17) are immediately powered on upon startup. During this time, the galvanometer drive waveform data sent by the FPGA has not yet been correctly output. Therefore, there will be a period of high-voltage pulse output to the galvanometer during startup. However, the galvanometer specifications require a DC voltage not exceeding 1.2V. In DC voltage mode, a voltage across the galvanometer exceeding 1.2V will burn out the galvanometer coil. The higher the DC voltage, the shorter the time it takes for the coil to burn out, and the higher the probability of burnout. Similarly, DC high voltage is not allowed to exist not only when the power is turned on, but also at any time when the galvanometer is working. For example, when the power is turned off, or when the DLP fails and the FPGA does not output the galvanometer drive waveform data, but the power supply of the galvanometer drive circuit is not turned off at this time, it will also cause the output of DC high voltage and cause the galvanometer coil to burn out.

[0145] The specific reasons for the generation of DC high voltage include power on, power off or malfunction. These reasons result in the video image processing chip N1 not outputting the drive waveform data WG_SYNCz, WG_CLK, WG_DATA, but the power supply ends of each chip in the galvanometer drive circuit are always powered. In this case, each chip in the galvanometer drive circuit works normally, but there is no galvanometer drive waveform data output. Therefore, the output Vi of the digital-to-analog converter N3 is not output, which is equivalent to the disconnected state.

[0146] N4 contains two operational amplifiers A1 and A2, as shown in Figure 17. The configuration resistors of the operational amplifiers and their corresponding resistance values ​​are marked in the circuit schematic. Based on the working principle of the operational amplifier, the two outputs V_p and V_n of the two operational amplifiers can be calculated by combining formulas (1) to (9). Substituting the resistance parameters of R4 and R5 into formula (1), V A1+ =47.5 / (47.5+10)×3.3=2.726V. According to the principle of virtual short and virtual disconnection, V A1- =V A1+ =2.726V, the current flowing through R2 and R3 is the same, and the resistance values ​​of R2, R6, and R7 are adjusted to V_DAC and V A1- Substitute the voltage value into formula (2), and we can get I R3 =(3.3-2.726) / (56+5.6+40.2)=5.639×10 -6 A, the voltage drop across resistor R3 is V_ R3 =I R3 ×R3=5.639×10 -6 ×121×10 3 =0.682V. Output voltage of operational amplifier A1 V_p = V A1- -V R3 =2.726-0.682=2.044V.

[0147] The non-inverting input voltage of operational amplifier A2 is V A2+ =V_DAC-I R3 ×R7=3.3-5.639×10 -6 ×56×10 3 =2.984V. The voltage at the inverting input of operational amplifier A2 is V A2- =V A2+ =2.984V. Output voltage of operational amplifier A2 V_n = (R8+R9) / R8×V A2- =(5.1+12) / 5.1×2.984=10.005V.

[0148] Therefore, when the galvanometer drive waveform data has not been output, the operational amplifier is working, and the output DC voltage added to the two ends of the galvanometer is V_p-V_n=10.005-2.044=7.961V. The coil resistance of the galvanometer is usually only 12.1 ohms. Therefore, the coil of the galvanometer generates heat flow under a high current of about 0.7A, which eventually burns the fixing glue of the coil. The fixing glue melts and causes the coil to collapse, making the galvanometer unusable.

[0149] The present invention provides a galvanometer drive circuit for laser projection equipment that protects the galvanometer coil and prevents it from burning out. The galvanometer drive circuit shown in FIG17 prevents the output of high-voltage DC pulses. Specifically, when the input voltage V_DAC of the operational amplifier circuit N4 and the power supply P12V are powered on, the galvanometer drive waveform data is ensured to be output. The situation in which the operational amplifier operates but the drive waveform Vi is not output is not permitted.

[0150] With reference to FIG9 and FIG17 , the working process of the laser projection device provided in the embodiment of the present application is as follows:

[0151] After powering on, the master DLP chip and the slave DLP chip of the laser projection device are initialized and configured first. If the configuration is successful and there is no fault interruption, a configuration success signal is output. The configuration success signal includes mHOST_IRQ (issued by the master DLP chip) and sHOST_IRQ (issued by the slave DLP chip) as shown in Figure 9.

[0152] mHOST_IRQ and sHOST_IRQ are 1.8V signals, active low. They are pulled up to 3.3V by the collectors of the first N-type transistor N7 and the second N-type transistor N8. Therefore, the low-level mHOST_IRQ and sHOST_IRQ signals, output by the master and slave control chips after successful power-on initialization, are converted to a 3.3V active high by the first N-type transistor N7 and the second N-type transistor N8. These two high-level outputs pass through the AND gate circuit N9, outputting a high-level configuration success command signal to the MCU. This means that both mHOST_IRQ and sHOST_IRQ must be output simultaneously, and only after passing through the AND gate circuit will they reach a high level. If one or both control chips fail to configure successfully, the system will not boot. Both the master and slave DLP chips must be successfully configured simultaneously for the system to boot normally; otherwise, the system will not boot.

[0153] Under the premise that the input terminal IO1 of the MCU obtains a high level and there is no system error, fan failure error, or overheating error, the MCU will output a high-level start signal through the output terminal IO2 after a delay. Under the control of the high-level start signal, the third transistor N11 is turned on and grounded, the gate of the PMOS N12 is at a low level, the PMOS is turned on, and the system's 12V power supply VIN is input to P12V, and the galvanometer drive circuit starts to work. For example, the power supply P12V of the operational amplifier in the galvanometer drive circuit is powered on and starts to work.

[0154] During the first delay, when the MCU's detection port IO1 registers a high level, the master DLP chip sends a synchronization signal for the galvanometer drive waveform output to FPGA N1. As shown in Figure 6, the FPGA, under the control of the synchronization signal, begins outputting the galvanometer drive waveform data. Passing through level conversion circuit N2 and digital-to-analog converter N3, the drive waveform data arrives before the operational amplifier circuit N4's power supply P12V is powered on, thus preventing the output of a DC high-voltage pulse to the galvanometer coil. When the MCU's output signal IO2 is not output, the base of N11 is pulled low by resistor R17, rendering N11 non-conductive. The gate of N12 is high, and therefore N12 is also non-conductive. P12V has no voltage output, and N4 is non-operating, preventing the output of a DC high-voltage pulse.

[0155] When a DLP system error or failure occurs, either or both of mHOST_IRQ and sHOST_IRQ will be pulled high, turning on either or both of N7 and N8. This causes one or both inputs of AND gate circuit N9 to be low, and thus N9's output. At this point, the MCU's input IO1 registers a low level, causing the MCU's output IO2 to be low, shutting off the P12V power supply to operational amplifier circuit N4. In the event of a system failure, the FPGA outputs drive waveform data, which is disabled after the master or slave DLP chip ceases operation, and after the P12V power supply to N4 is disconnected.

[0156] In the event of a complete system failure in the laser projection device, such as a fan failure, overtemperature fault, or normal shutdown, the shutdown sequence first shuts down the P12V power supply to the galvanometer's operational amplifier chip N4, thereby shutting down the galvanometer. A shutdown command is then sent to shut down the DLP chip. Therefore, in the event of a fan failure, overtemperature fault, or normal shutdown, the MCU's output terminal IO2 will output a low level, shutting down the P12V power supply to the galvanometer's operational amplifier circuit N4 and shutting down the galvanometer. This prevents the galvanometer from being burned by a DC high-voltage pulse generated by the absence of drive waveform data output.

[0157] The embodiment of the present application eliminates the DC high voltage pulse by changing the timing between the galvanometer drive waveform data WG_SYNCz, WG_CLK, and WG_DATA outputs and the power supply P12V of the operational amplifier circuit N4.

[0158] The power-on timing of the embodiment of the present application is that the galvanometer drive waveform data WG_SYNCz, WG_CLK, and WG_DATA are output first, followed by the power supply V_DAC of the digital-to-analog converter N3, and then the power supply P12V of the operational amplifier circuit N4, or the power supply V_DAC of the digital-to-analog converter N3 and the power supply P12V of the operational amplifier circuit N4 are output at the same time.

[0159] The power-off sequence of the embodiment of the present application is as follows: if a fault or shutdown occurs during product operation, the power supply P12V of the operational amplifier circuit N4 is first turned off, followed by the power supply V_DAC of the digital-to-analog converter N3, and then the galvanometer drive waveform data. Alternatively, the power supply V_DAC of the digital-to-analog converter N3 and the power supply P12V of the operational amplifier circuit N4 are turned off simultaneously. As shown in FIG17 , P12V is the power supply of the operational amplifier circuit N4. If the power supply P12V of the operational amplifier circuit N4 is turned off first, the operational amplifier circuit N4 will not operate, so there will be no output voltage. Even if the power supply V_DAC of the digital-to-analog converter N3 and the galvanometer drive waveform are not turned off, no DC high-voltage pulse will occur, and the galvanometer coil will not burn.

[0160] The power supply P12V of the operational amplifier circuit N4 directly controls whether N4 is working, that is, the power supply P12V is the key to whether the DC high-voltage pulse is output. Therefore, the key to eliminating the DC high-voltage pulse lies in the timing control of the power supply P12V of the operational amplifier circuit N4. The optimal timing control of the power-on timing and the power-off timing is to control the power supply P12V of the operational amplifier circuit N4. In order to solve the problem of galvanometer coil burning, the embodiment of the present application adds the galvanometer power supply control circuit shown in Figure 9 on the basis of the galvanometer drive circuit shown in Figure 17, controls the power-on and power-off timing of the power supply P12V of the operational amplifier N4 in Figure 17, thereby eliminating the DC high-voltage pulse that drives the galvanometer.

[0161] In addition to resolving the issue of coil burnout and reducing circuit costs, the embodiments of this application further design a method for generating digital drive waveform signals to enable the galvanometer to move to the precise position required for sub-image display, ensuring correct projection. This will be described below.

[0162] The present application also provides a digital waveform generation module, and Figure 21 is a schematic diagram of the structure of a digital waveform generation module provided in the present application. The digital waveform generation module can be used as the digital waveform generation module shown in Figures 13, 14, 16, and 17 in the above embodiments.

[0163] As shown in Figure 21, the digital waveform generation module may include: a subframe delay submodule 11, a clock control submodule 12, an address control submodule 13 and an amplitude storage submodule 14; the subframe delay submodule 11 is connected to the address control submodule 13, and the subframe delay submodule 11 is used to delay the subframe signal to obtain a delayed subframe signal, and transmit the delayed subframe signal obtained by delay to the address control submodule 13, that is, transmit the delayed subframe signal to the address control submodule 13. Among them, the subframe signal is the subframe signal of the two sub-frames of the image decomposed into a frame, and the delayed subframe signal is used to synchronize or align the display of the sub-image with the movement of the galvanometer; the clock control submodule 12 is connected to the address control submodule 13, and the clock control submodule 12 is used to provide the address control submodule 13 with a control clock for generating a digital drive waveform signal (which can be simply referred to as a digital drive waveform); the amplitude storage submodule 14 is connected to the address control submodule 13, and the amplitude storage submodule 14 is used to store multiple amplitudes of the digital drive waveform signal, and the multiple amplitudes can be stored in a certain storage order, such as according to a preset storage order; the address control submodule 14 is connected to the address control submodule 13, and the amplitude storage submodule 14 is used to store multiple amplitudes of the digital drive waveform signal. The multiple amplitudes can be stored in a certain storage order, such as according to a preset storage order; The control sub-module 13 is used to respond to the delayed sub-frame signal. When the edge of the delayed sub-frame signal arrives, the multiple amplitudes are read from the amplitude storage sub-module 14 according to the target galvanometer type (the total number is the target number segments), and the multiple amplitudes are output in sequence according to the reading order to generate a digital drive waveform signal, wherein the first to the second to last amplitudes read are output at the target segment length, and the last amplitude read is output until the next edge of the delayed sub-frame signal arrives. The target galvanometer type represents the amplitude reading method, the target segment number represents the number of amplitudes stored in the amplitude storage sub-module 14, and the target segment length represents the clock length of multiple control clocks.

[0164] The previous edge of the delayed subframe signal may be a rising edge or a falling edge, and the next edge of the delayed subframe signal may be a falling edge or a rising edge, that is, the two adjacent edges are opposite.

[0165] 21 , the target galvanometer type may be a preset galvanometer type, which may include multiple galvanometer types. The target number of segments may be a preset number of segments, such as 256 or 512. The target segment length may be a preset segment length, such as a clock length of two control clocks, or a clock length of four, six, eight, or another number of control clocks.

[0166] In the embodiment of the present application, referring to FIG22 , based on the desired waveform required to drive the galvanometer, i.e., the analog drive waveform, in the digital circuit, it is necessary to convert the analog drive waveform into a digital drive waveform, and use the digital drive waveform to approximate the analog drive waveform, i.e., the analog drive waveform can be estimated and realized by many equal-length segments to form an editable digital drive waveform, wherein both the amplitude and the number of amplitudes of the digital drive waveform can be edited. To this end, each amplitude of the digital drive waveform to be generated can be stored in the amplitude storage submodule 14 according to a preset storage order, wherein the preset storage order can be the order of the amplitudes of the digital drive waveform. For example, each amplitude can be an 8-bit unsigned number, and the amplitude storage submodule 14 can include a 256×8 memory, i.e., it can store 256 8-bit unsigned amplitudes, and each amplitude can be stored in the form of a lookup table. In order to adapt to the two positions of the galvanometer movement, a frame image is divided into two subframe images (i.e., two subframes in the embodiment of the present application), and accordingly, each subframe image corresponds to a position of the galvanometer movement. Referring to Figure 23, the display control component decomposes a frame image into two sub-frame images and triggers the sub-frame signal output through the sub-frame synchronization bit timing signal. In order to ensure that the display of the sub-image is synchronized with the movement of the galvanometer when the generated digital drive waveform is driven by the galvanometer drive component, the embodiment of the present application delays the sub-frame signal through the sub-frame delay sub-module 11 to generate a delayed sub-frame signal, which is transmitted to the address control sub-module 13. When the rising edge or falling edge of the delayed sub-frame signal arrives, the address control sub-module 13 sequentially outputs the multiple amplitudes in the amplitude storage sub-module 14 according to the target segment length, thereby generating a digital drive waveform.

[0167] In one possible implementation, the subframe delay submodule 11 can delay the subframe signal based on a set subframe delay value. Exemplarily, the subframe delay value is a programmable value, such as a certain number of system clocks. After the subframe signal is input into the digital waveform generation module of the galvanometer, the time for delaying the subframe signal to be input into the address control submodule 13 is first obtained from the timer, and the clock used for the subframe delay is obtained according to the system clock. If the system clock uses a 24 MHz crystal oscillator, the system clock period is 41.667 ns. The clock used for the subframe delay is the system clock, such as 24 MHz, and not the programmable DAC clock used to drive the waveform generation functions. The clock control submodule 12 provides the address control submodule 13 with a control clock for generating the digital drive waveform signal, referred to as the DAC clock. The clock control submodule 12 is also connected to the digital-to-analog conversion module of the laser projection device (directly or through a level conversion module). The clock control submodule 12 is also used to transmit the control clock to the digital-to-analog conversion module to provide the clock for the data input of the digital-to-analog conversion module. If the system clock is 24MHz, the DAC clock range is 2 to 16 system clocks. For example, the relationship between the DAC clock and the system clock is that the DAC clock is a system clock with a step size of 2, that is, the DAC clock is 83.33ns to 666.67ns. The DAC clock is used to drive various functions for waveform generation and is input into the back-end digital-to-analog conversion module as the data input clock of the digital-to-analog conversion module, that is, the digital waveform output clock WG_CLK.

[0168] The target galvanometer type characterizes the amplitude reading method, and the embodiments of the present application provide two reading methods.

[0169] The first reading method is positive to reverse order. That is, after the rising edge of the delayed sub-frame signal arrives, the first amplitude value of the amplitude storage sub-module 14 will be output. This amplitude will be output for the number of DAC clocks specified by the target segment length. The second amplitude value will then be output for the same number of DAC clocks specified by the target segment length, and so on, until the number of output amplitudes reaches the target number of segments. The last amplitude value will remain output until the falling edge of the delayed sub-frame signal arrives. After the falling edge of the delayed sub-frame signal arrives, the last amplitude value from the amplitude storage sub-module 14 will be output first. The output method is the same as the rising edge, except that the amplitude values ​​are read from the amplitude storage sub-module 14 in reverse order, that is, the amplitudes are read and output in reverse order. That is, after the falling edge of the delayed sub-frame signal arrives, the last stored amplitude value is output first, and the last amplitude value is output for the number of DAC clocks specified by the target segment length. Then, the second-to-last amplitude value from the amplitude storage sub-module 14 will be output, also for the number of DAC clocks specified by the target segment length. This continues until the number of output amplitudes reaches the target number of segments. It can be seen that the amplitude output orders corresponding to two adjacent subframes are opposite.

[0170] The second reading method is positive sequence → positive sequence inversion (inverse code or complement), that is, during the positive sequence reading process, the first stored amplitude will continue to be output for the number of DAC clocks specified by the target segment length, and then the second amplitude will also be output for the number of DAC clocks specified by the target segment length, and so on, until the number of output amplitudes reaches the preset number of segments. Among them, the last amplitude will remain output until the falling edge of the delayed sub-frame signal arrives. After the falling edge of the delayed sub-frame signal arrives, the first amplitude of the amplitude storage submodule 14 will be inverted and output. Inversion means taking the amplitude in the amplitude storage submodule 14 in the form of the inverse code (complement), and the reading order of these inverted amplitudes is the same as the rising edge, still starting from the first amplitude in the amplitude storage submodule 14.

[0171] The target number of segments is the number of amplitudes used to generate the digital drive waveform, and is also the number of amplitudes stored in the amplitude storage submodule 14. In some embodiments, the target number of segments can be set in a range of 2 to 255. The target segment length is the clock length of each amplitude, i.e., one amplitude maintains multiple DAC clock outputs. The target segment length can be set in a range of 2 to 65535 DAC clocks. It will be understood that the target number of segments and the target segment length jointly determine the degree of similarity between the digital drive waveform signal and the analog drive waveform signal. For example, a greater number of target segments and a shorter target segment length result in a greater degree of similarity between the digital drive waveform signal and the analog drive waveform signal.

[0172] The address control submodule 13 has multiple address bits, which store numerical values ​​representing the target galvanometer type, target number of segments, target segment length, and the address of the amplitude stored in the amplitude storage submodule 14. Thus, by setting the target galvanometer type, target number of segments, and target segment length, address control of the digital drive waveform is achieved under the triggering of the control clock.

[0173] Based on the above technical solution, in a specific embodiment of data-driven waveform generation, as shown in Figure 24, after the rising edge or falling edge of the sub-frame signal arrives, the amplitude in the lookup table (amplitude storage submodule 14) is started to be output under the trigger of the DAC clock (control clock), and the first amplitude output is 0. After 2 DAC clock cycles, the second amplitude is output, and the second amplitude is 2. After another 2 DAC clock cycles, the third amplitude is output, and the third amplitude is 7. And so on. After every 2 clock cycles, the fourth and fifth amplitudes of 12 and 17 are output in sequence. After 2 clock cycles, the last amplitude 20 in the lookup table is output, and this amplitude 20 will be output until the falling edge or rising edge of the delayed sub-frame signal arrives, and then the amplitudes in the lookup table are output according to a certain regular order (such as reverse order or inverse of positive order).

[0174] As can be seen from the above example, the lookup table contains six amplitudes: 0, 2, 7, 12, 17, and 20. This means that the generated waveform has six amplitudes, i.e., the preset number of segments = 6. Each of these six amplitudes is output for at least two DAC clocks, meaning the same amplitude is output for two DAC clock cycles, i.e., the preset segment length = 2. Thus, by setting the target number of segments required for the digital drive waveform, the lookup table contains the waveform amplitudes for each segment generated by the set target number of segments. The number of DAC clocks required for waveform output is determined based on the set target segment length. The amplitudes in the lookup table are sequentially output for the target number of segments, with the target segment length as the time period. When the last amplitude is output, it is output continuously until the edge of the delayed sub-frame signal arrives, at which point the amplitudes in the lookup table are output again in a predetermined pattern, thus generating the digital drive waveform.

[0175] In addition, FIG25 illustrates a schematic diagram of the waveform output operating principle in some embodiments. As shown in FIG25 , upon the arrival of the rising edge of the delayed subframe signal, the amplitude is read from the lookup table in positive sequence, and the amplitudes for the number of segments specified in the lookup table are sequentially output. The last amplitude in the lookup table remains output until the arrival of the falling edge of the delayed subframe signal. The amplitude is then read in reverse sequence or in reverse order using the inverse code, and the amplitudes for the number of segments specified in the lookup table are sequentially output. The final waveform output data WG_DATA[7:0] is converted by a digital-to-analog converter and amplified by an operational amplifier to ultimately output the galvanometer drive waveform, which is an analog signal waveform with drive capability. Triggered by the rising edge of the delayed subframe signal, the digital drive waveform begins to be output in positive sequence, thereby outputting the galvanometer drive waveform (i.e., an analog drive waveform) to drive the galvanometer to begin moving, causing the galvanometer to move to position A or position B, at which point subframe A is synchronously output. When the falling edge of the delayed subframe signal arrives, the digital drive waveform begins to output inverse code, driving the galvanometer to move to position B or position A. At this position, subframe B is output. Therefore, in the display of a frame of image, the galvanometer will move two positions, and subframe A or subframe B is output at different positions. Therefore, the number of pixels in the final displayed frame of image is doubled, and the resolution is increased to twice the original resolution. It should be noted that if the position of the galvanometer movement does not correspond to the subframe, the target galvanometer type can be edited to make the galvanometer movement position correspond to the subframe.

[0176] The digital waveform generation module of the galvanometer provided in the embodiment of the present application first delays the subframe signal through the subframe delay submodule to ensure that when the generated digital drive waveform signal drives the galvanometer, the display of the sub-image is synchronized with the movement of the galvanometer; combined with the multiple amplitudes of the digital drive waveform corresponding to the analog drive waveform required to drive the galvanometer stored in the amplitude storage submodule, the address control submodule reads the amplitude of the target number of segments from the amplitude storage submodule according to the target galvanometer type, and uses the control clock provided by the clock control submodule and the target segment length to limit the duration of the amplitude output, so that the multiple amplitudes form a digital drive waveform that approximates the analog drive waveform. Therefore, based on the rising edge or falling edge of the delayed subframe signal, the embodiment of the present application triggers the address control submodule to read and output the multiple amplitudes of the digital drive waveform from the amplitude storage submodule, forming a digital drive waveform containing multiple amplitudes, which can move the galvanometer to the exact position required for image display, with low noise and better image quality.

[0177] In some embodiments, as shown in FIG26 , the digital waveform generation device for the galvanometer further includes a multiplication submodule 15; the multiplication submodule 15 is connected to the address control submodule 13, and the address control submodule 13 is configured to output a digital drive waveform signal to the multiplication submodule 15. The multiplication submodule 15 is configured to multiply the digital drive waveform signal by a first gain value so that the amplitude of the digital drive waveform signal reaches the desired amplitude of the corresponding analog drive waveform. In one implementation, the multiplication submodule 15 is also connected to the digital-to-analog conversion module (directly or through a level conversion module), and is configured to transmit the amplitude-adjusted digital drive waveform signal to the digital-to-analog conversion module.

[0178] In one possible implementation, the multiplication submodule 15 may include a multiplier. Since the amplitude read and output from the lookup table cannot reach the expected amplitude of the analog drive waveform, a first gain value may be edited based on the multiple relationship between the expected amplitude of the analog drive waveform and the amplitude in the lookup table. The digital drive waveform, specifically each amplitude of the digital drive waveform, is multiplied by the first gain value through the multiplication submodule 15. This allows the amplitude of the digital drive waveform output by the multiplication submodule 15 to reach the expected amplitude of the analog drive waveform, thereby improving the accuracy of the galvanometer movement position. Exemplarily, the first gain value may be a preset gain value, which may be an 8-bit unsigned number, whose value range is, for example, 0 to 1.9921875.

[0179] In some embodiments, as shown in FIG27 , the galvanometer's digital waveform generation module further includes an addition submodule 16 ; the addition submodule 16 is connected to the address control submodule 13 and is configured to apply a first bias voltage to the digital drive waveform to adjust the galvanometer's central deflection angle during deflection. In one implementation, the addition submodule 16 is also connected to the digital-to-analog conversion module (directly or via a level conversion module) and is configured to transmit the amplitude-adjusted digital drive waveform signal to the digital-to-analog conversion module.

[0180] Typically, the center deflection angle of the galvanometer is 0, that is, the galvanometer deflects between symmetrical positive and negative deflection angles with a deflection angle of 0 degrees as the axis. However, according to actual applications, the galvanometer can be deflected only at a positive deflection angle. At this time, it is necessary to apply a first bias voltage to the digital drive waveform signal through an adder module 16 (such as an adder) so that the deflection of the galvanometer meets the needs of actual applications. In one embodiment, referring to Figure 27, the adder module 16 can be directly connected to the address control submodule 13. In another embodiment, referring to Figure 28, the adder module 16 can be connected to the address control submodule 13 through the multiplication submodule 15. Similarly, in yet another embodiment, the positions of the multiplication submodule 15 and the adder module 16 in Figure 28 can be interchanged, that is, the multiplication submodule 15 can be connected to the address control submodule 13 through the adder module 16.

[0181] The first bias voltage may be a preset bias voltage, and the first bias voltage may be a 5-bit unsigned number with a value range of 0 to 32.

[0182] In some embodiments, as shown in FIG29 , the digital waveform generation module of the galvanometer further includes a selection submodule 17. The selection submodule 17 includes two input terminals and an output enable terminal. For ease of distinction, in some embodiments, the two input terminals can be referred to as a first input terminal and a second input terminal, respectively, and the output enable terminal can be referred to as a fixed output enable terminal. It should be understood that the first input terminal and the second input terminal here are input terminals in different devices and are not the same input terminals as the first input terminal and the second input terminal mentioned above. The first input terminal of the selection submodule 17 is connected to the address control submodule 13 (in the example shown in FIG29 , the first input terminal of the selection submodule 17 is connected to the address control submodule 13 via the addition submodule 16 and the multiplication submodule 15), and the second input terminal of the selection submodule 17 is connected to a first fixed amplitude. The selection submodule 17 is configured to output a digital drive waveform signal to drive the galvanometer deflection if the enable signal of the fixed output enable terminal is invalid (i.e., the fixed output enable is invalid); if the enable signal of the fixed output enable terminal is valid (i.e., the fixed output enable is valid), output the first fixed amplitude to turn off the galvanometer. The first fixed amplitude may be a preset fixed amplitude, and the first fixed amplitude may be an 8-bit unsigned number, with a value range of, for example, 0 to 255.

[0183] For example, according to the actual needs of the user, if the user wants to display the image at a higher resolution, the user can turn on the galvanometer. At this time, the fixed output enable is invalid, the digital drive waveform is output normally, and the galvanometer is driven to deflect back and forth between two different positions, thereby improving the display resolution; if the user wants to display the image at the original resolution (the resolution of the projection device), the user can turn off the galvanometer. At this time, the fixed output enable is valid, the preset fixed amplitude is output, the galvanometer no longer deflects, and the resolution remains unchanged.

[0184] In summary, the galvanometer drive device and laser projection equipment provided in the embodiments of the present application control the power supply of the galvanometer drive circuit through the DLP unit circuit, the delay circuit and the switch circuit. The DLP unit circuit can output a configuration success command signal to the delay circuit only when the configuration is successful. At this time, the DLP unit circuit also outputs a galvanometer head frame synchronization signal to the galvanometer drive circuit. After receiving the configuration success command signal, the delay circuit will output an on signal to the control end of the switch circuit after a certain delay, so that the power supply supplies power to the galvanometer drive circuit. By setting this delay, it can be ensured that the galvanometer head frame synchronization signal is first transmitted to the galvanometer drive circuit, and only then is the power supply supplied to the galvanometer drive circuit. This can avoid the phenomenon that the power supply is turned on first to generate a DC high-voltage pulse before the galvanometer head frame synchronization signal is transmitted to the galvanometer drive circuit, causing the galvanometer coil to burn out, thereby solving the problem that the galvanometer coil is easily burned out and improving the reliability of the laser projection equipment.

[0185] Among them, the galvanometer drive circuit may include a digital waveform generation module, a digital-to-analog conversion module and an operational amplifier module. The operational amplifier module is used to split the analog drive waveform signal into two to obtain a first drive voltage and a second drive voltage with opposite phases, and the first drive voltage is applied to the positive pole of the coil of the galvanometer, and the second drive voltage is applied to the negative pole of the coil of the galvanometer. The difference between the first drive voltage and the second drive voltage is used to realize voltage drive of the galvanometer. In this way, the galvanometer drive circuit provided in the embodiment of the present application only needs to use one voltage generation circuit (corresponding to the digital waveform generation module of the present application), and the analog drive waveform signal generated by the digital waveform generation module and converted by the digital-to-analog conversion module is processed into two drive voltages with opposite phases through the operational amplifier module. The difference between the two drive voltages is used to realize voltage drive of the galvanometer to drive the galvanometer deflection, thereby saving one voltage generation circuit and reducing the cost of the galvanometer drive circuit.

[0186] Among them, the digital waveform generation module includes a subframe delay submodule, a clock control submodule, an address control submodule and an amplitude storage submodule. The subframe signal is first delayed by the subframe delay submodule to ensure that when the generated digital drive waveform signal is driven by the digital-to-analog conversion module and the operational amplifier module, the display of the sub-image is synchronized with the movement of the galvanometer. Combined with the multiple amplitudes of the digital drive waveform signal corresponding to the analog drive waveform signal required to drive the galvanometer stored in the amplitude storage submodule, the address control submodule reads the amplitude of the target number of segments from the amplitude storage submodule according to the target galvanometer type, and uses the control clock provided by the clock control submodule and the target segment length to limit the duration of the amplitude output, so that the amplitudes of multiple digital quantities form a digital drive waveform signal that approximates the analog drive waveform signal. Therefore, the embodiment of the present application triggers the address control submodule to read and output multiple amplitudes of the digital drive waveform signal from the amplitude storage submodule based on the rising edge or falling edge of the delayed subframe signal, forming a digital drive waveform signal containing multiple digital amplitudes, which can move the galvanometer to the accurate position required for image display.

[0187] An embodiment of the present application further provides a laser projection device, which includes a galvanometer and a galvanometer driving device provided by any of the above embodiments, wherein the galvanometer driving device is connected to the galvanometer.

[0188] In one possible implementation, the galvanometer drive device includes a galvanometer power supply control circuit and a galvanometer drive circuit. That is, an embodiment of the present application further provides a laser projection device, including a galvanometer, a galvanometer drive circuit, and the galvanometer power supply control circuit provided in the above embodiment. The output end of the galvanometer power supply control circuit is connected to the power input end of the galvanometer drive circuit, and the output end of the galvanometer drive circuit is connected to the galvanometer coil. The galvanometer power supply control circuit includes a DLP unit circuit, a delay circuit, and a switching circuit. The galvanometer drive circuit can be the galvanometer drive circuit provided in any of the above embodiments.

[0189] In one possible implementation, the laser projection device further includes a light source drive assembly, a light source, a light valve, and a lens. The galvanometer drive device is further connected to the source drive assembly and the light valve, respectively. The light source drive assembly is further connected to the light source. The light valve is located on the light output side of the light source. The galvanometer is located on the light output side of the light valve. The lens is located on the light output side of the galvanometer. The galvanometer may be the galvanometer shown in FIG. 7 .

[0190] The laser projection device provided in the embodiment of the present application has the same technical features as the galvanometer drive device provided in the above-mentioned embodiment of the present application, so it can also solve the same technical problems and achieve the same technical effects.

[0191] The present application also provides a galvanometer mirror driving method, which can be applied to any of the laser projection devices provided in the above embodiments, and more specifically, to a galvanometer mirror driving device in the laser projection device, wherein the galvanometer mirror driving device is any of the galvanometer mirror driving devices provided in the above embodiments. The method includes: upon successful configuration of the DLP unit circuit, transmitting a galvanometer mirror sub-frame synchronization signal, and after a first delay, powering the galvanometer mirror driving circuit, wherein the galvanometer mirror sub-frame synchronization signal is used to instruct the galvanometer mirror driving circuit to drive the galvanometer mirror for deflection.

[0192] In a possible implementation, after transmitting the galvanometer mirror frame synchronization signal, as shown in FIG30 , the method further includes the following steps:

[0193] S3010: Generate a digital waveform signal.

[0194] The digital waveform signal includes a digital driving waveform signal.

[0195] S3020 , performing digital-to-analog conversion on the digital driving waveform signal to obtain an analog driving waveform signal.

[0196] S3030. Generate a first drive voltage and a second drive voltage with opposite phases based on the analog drive waveform signal, and apply the first drive voltage to the positive pole of the coil of the galvanometer, and apply the second drive voltage to the negative pole of the coil of the galvanometer, so that the difference between the first drive voltage and the second drive voltage serves as the drive signal of the galvanometer to drive the galvanometer to deflect.

[0197] The galvanometer driving method provided in the embodiment of the present application can be implemented using the galvanometer driving circuit provided in the embodiment of the present application. The specific steps can refer to the functions of the relevant modules in the galvanometer driving circuit, which will not be repeated here.

[0198] In a possible implementation, after transmitting the galvanometer mirror frame synchronization signal, as shown in FIG31 , the method further includes the following steps:

[0199] S3110: Acquire a subframe signal, and delay the subframe signal to obtain a delayed subframe signal.

[0200] The sub-frame signal includes sub-frame signals of two sub-frames of images decomposed from one frame of image, and the delayed sub-frame signal is used to synchronize the display of the sub-images with the movement of the galvanometer;

[0201] S3120: Obtain a control clock for generating a digital driving waveform signal.

[0202] S3130 , in response to the delayed sub-frame signal, when the edge of the delayed sub-frame signal arrives, read multiple amplitudes according to the target galvanometer type, and output the multiple amplitudes in sequence according to the read order to generate a digital driving waveform signal.

[0203] Among them, the first to the second to last amplitudes read all maintain the target segment length output, and the last amplitude read maintains the output until the next edge of the delayed subframe signal arrives. The target galvanometer type represents the amplitude reading method, and the target segment length represents the clock length of multiple control clocks.

[0204] S3140: Use the digital driving waveform signal to drive the galvanometer deflection.

[0205] In some embodiments, the above step 3010 may include steps S3110 to S3130. In other embodiments, the above step 3010 may also include other steps, that is, other methods are used to generate the digital driving waveform signal.

[0206] In some embodiments, the above step 3140 may include steps S3020 to S3030. In other embodiments, the above step 3140 may also include other steps, that is, using other methods to drive the polarization of the galvanometer.

[0207] The two sub-image frames include a first sub-image and a second sub-image. In some embodiments, multiple amplitudes are read according to the target galvanometer type, including:

[0208] Based on the first galvanometer type of the first sub-image, read the amplitudes of a preset number of segments in positive sequence from the amplitude storage submodule;

[0209] Based on the second galvanometer type of the second sub-image, the amplitude of the preset number of segments is read in reverse order from the amplitude storage submodule, or the amplitude in the amplitude storage submodule is inverted and the inverted amplitude of the preset number of segments is read in positive order from the amplitude storage submodule.

[0210] In some embodiments, after sequentially outputting the multiple amplitudes in the reading order to generate the digital driving waveform signal, the method further includes:

[0211] multiplying the digital driving waveform signal by a first gain value so that the amplitude of the digital driving waveform signal reaches a desired amplitude of the corresponding analog driving waveform signal; and / or,

[0212] A first bias voltage is applied to the digital driving waveform signal to adjust the central deflection angle of the galvanometer during the deflection process.

[0213] In some embodiments, the method further comprises:

[0214] In response to the galvanometer start-up operation, selecting a digital drive waveform signal output;

[0215] In response to the galvanometer closing operation, a first fixed amplitude output is selected.

[0216] The galvanometer driving method provided in the embodiment of the present application can be implemented using the galvanometer driving device provided in the embodiment of the present application. The specific steps can refer to the functions of the relevant modules in the galvanometer driving device, which will not be repeated here.

[0217] An embodiment of the present application also provides a computer-readable storage medium, which stores a computer program or program instructions. When the computer program or program instructions are executed by a processor, a galvanometer driving method as shown in any of the above method embodiments is implemented. The specific implementation method and technical effect are similar and will not be repeated here.

[0218] In a specific implementation, the computer-readable storage medium may include: a USB flash drive, a mobile hard disk, a ROM, a RAM, a magnetic disk, an optical disk, or other media that can store program codes.

[0219] An embodiment of the present application also provides a computer program product, which includes a computer program or instructions, and the computer program is stored in a computer-readable storage medium. The laser projection device can read the computer program from the computer-readable storage medium and execute the read computer program to implement the galvanometer driving method shown in any of the above method embodiments. The specific implementation method and technical effect are similar and will not be repeated here.

[0220] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

[0221] For ease of explanation, the above description has been presented in conjunction with specific embodiments. However, the above exemplary discussion is not intended to be exhaustive or to limit the embodiments to the specific forms disclosed above. Based on the above teachings, various modifications and variations are possible. The above embodiments have been selected and described to better explain the principles and practical applications, thereby enabling those skilled in the art to better utilize the embodiments and various variations of the embodiments suitable for specific use considerations.

[0222] The serial numbers of the above embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0223] Those skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware, or by a program to instruct the relevant hardware, and the program may be stored in a computer-readable storage medium, which may be a read-only memory, a disk, or an optical disk, etc.

[0224] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A galvanometer drive device, characterized in that: The galvanometer driving device comprises a digital light processing DLP unit circuit, a delay circuit, a switch circuit and a galvanometer driving circuit; the command signal output end of the DLP unit circuit is connected to the input end of the delay circuit, the subframe synchronization signal output end of the DLP unit circuit is connected to the galvanometer driving circuit, the output end of the delay circuit is connected to the control end of the switch circuit, the input end of the switch circuit is connected to the power supply of the galvanometer driving circuit, and the output end of the switch circuit is connected to the power input end of the galvanometer driving circuit; The DLP unit circuit is used to output a configuration success command signal through the command signal output terminal when the DLP unit circuit is successfully configured, and to output a galvanometer sub-frame synchronization signal through the sub-frame synchronization signal output terminal, wherein the galvanometer sub-frame synchronization signal is used to instruct the galvanometer drive circuit to drive the galvanometer deflection; The delay circuit is used to output a start signal through the output end of the delay circuit after a first delay when the configuration success command signal is received at the input end of the delay circuit; The switch circuit is used to conduct the electrical connection between the input end of the switch circuit and the output end of the switch circuit when the control end of the switch circuit receives the start signal.

2. The galvanometer drive device according to claim 1, characterized in that: The delay circuit further comprises an abnormal signal port, the abnormal signal port being used to receive an abnormal signal, the abnormal signal indicating a fan failure and / or device overheating; The delay circuit is used to output the start signal through the output end of the delay circuit after the first delay when the configuration success command signal is received at the input end of the delay circuit and if the abnormal signal port does not receive the abnormal signal.

3. The galvanometer drive device according to claim 2, characterized in that: The abnormal signal port includes a fan fault signal port and / or an overheat signal port, the fan fault signal port is used to receive a fan fault signal, the overheat signal port is used to receive an overheat signal, the abnormal signal includes the fan fault signal and / or the overheat signal, the fan fault signal indicates a fan fault, and the overheat signal indicates device overheating.

4. The galvanometer drive device according to any one of claims 1 to 3, characterized in that: The DLP unit circuit includes a master control DLP chip and a slave control DLP chip; The DLP unit circuit is used for outputting the configuration success command signal through the command signal output terminal when both the master control DLP chip and the slave control DLP chip are configured successfully.

5. The galvanometer drive device according to claim 4, characterized in that: The DLP unit circuit also includes a first triode, a second triode and an AND gate circuit; The first transistor is used to output a high-level configuration success command signal to an input terminal of the AND gate circuit when receiving a low-level configuration success signal output by the master control DLP chip; The second transistor is used to output a high-level configuration success command signal to another input terminal of the AND gate circuit when receiving a low-level configuration success signal output by the slave control DLP chip; The AND gate circuit is used to output the configuration success command signal to the input end of the delay circuit when both input ends of the AND gate circuit receive the configuration success command signal of a high level.

6. The galvanometer drive device according to any one of claims 1 to 5, characterized in that: The galvanometer drive circuit includes a digital waveform generation module, a digital-to-analog conversion module and an operational amplifier module; the subframe synchronization signal output end is connected to the digital waveform generation module, the digital waveform generation module is also connected to the digital-to-analog conversion module, the digital-to-analog conversion module is also connected to the operational amplifier module, and the operational amplifier module is also connected to the positive pole and the negative pole of the coil of the galvanometer; The digital waveform generation module is used to generate a digital waveform signal when receiving the galvanometer mirror frame synchronization signal, and transmit the digital waveform signal to the digital-to-analog conversion module, wherein the digital waveform signal includes a digital drive waveform signal; The digital-to-analog conversion module is used to perform digital-to-analog conversion on the digital driving waveform signal to obtain an analog driving waveform signal, and transmit the analog driving waveform signal to the operational amplifier module; The operational amplifier module is used to generate a first drive voltage and a second drive voltage with opposite phases based on the analog drive waveform signal, and transmit the first drive voltage to the positive electrode of the coil and transmit the second drive voltage to the negative electrode of the coil, wherein the difference between the first drive voltage and the second drive voltage is the drive signal of the galvanometer, and the drive signal is used to drive the galvanometer to deflect.

7. The galvanometer drive device according to claim 6, characterized in that: The operational amplifier module includes a first operational amplifier and a second operational amplifier; the output end of the digital-to-analog conversion module for outputting the analog drive waveform signal is respectively connected to the inverting input end of the first operational amplifier and the non-inverting input end of the second operational amplifier, the output end of the first operational amplifier is connected to the positive pole of the coil, and the output end of the second operational amplifier is connected to the negative pole of the coil; wherein the first operational amplifier is used to perform in-phase amplification on the analog drive waveform signal, and the second operational amplifier is used to perform inverting amplification on the analog drive waveform signal.

8. The galvanometer drive device according to claim 6 or 7, characterized in that: The digital waveform signal also includes a waveform output clock signal and a waveform output enable signal, wherein the waveform output clock signal is used to provide a control clock for generating the digital drive waveform signal, and the waveform output enable signal is used to instruct the digital-to-analog conversion module to perform digital-to-analog conversion on the digital drive waveform signal and output the analog drive waveform signal.

9. The galvanometer drive device according to any one of claims 6 to 8, characterized in that: The galvanometer drive circuit further includes a level conversion module; the level conversion module is connected to the digital waveform generation module and the digital-to-analog conversion module respectively; The level conversion module is used to convert the logic level of the digital waveform signal into a logic level matching the working level of the digital-to-analog conversion module.

10. The galvanometer drive device according to any one of claims 1 to 9, characterized in that: The galvanometer drive circuit includes a digital waveform generation module, which includes a subframe delay submodule, a clock control submodule, an address control submodule and an amplitude storage submodule; the subframe delay submodule, the clock control submodule and the amplitude control submodule are all connected to the address control submodule; The subframe delay submodule is used to delay the subframe signal to obtain a delayed subframe signal, and transmit the delayed subframe signal to the address control submodule, wherein the subframe signal is a subframe signal of two subframes of a frame image decomposed into, and the delayed subframe signal is used to synchronize the display of the subimage with the movement of the galvanometer; The clock control submodule is used to provide the address control submodule with a control clock for generating a digital drive waveform signal, and the digital drive waveform signal is used to drive the galvanometer to deflect; The amplitude storage submodule is used to store multiple amplitudes of the digital driving waveform signal; The address control submodule is used to respond to the delayed subframe signal. When the edge of the delayed subframe signal arrives, the multiple amplitudes are read from the amplitude storage submodule according to the target galvanometer type, and the multiple amplitudes are output in sequence according to the reading order to generate the digital drive waveform signal, wherein the first to the second to last amplitudes read are all output at the target segment length, and the last amplitude read is output until the next edge of the delayed subframe signal arrives. The target galvanometer type represents the reading method of the amplitude, and the target segment length represents the clock length of multiple control clocks.

11. The galvanometer driving device according to claim 10, characterized in that: The edge is a rising edge or a falling edge.

12. The galvanometer drive device according to claim 10 or 11, characterized in that: The digital waveform generation module further includes a multiplication submodule, and the galvanometer drive circuit further includes a digital-to-analog conversion module; the multiplication submodule is connected to the address control submodule and the digital-to-analog conversion module respectively; The address control submodule is further used to output the digital drive waveform signal to the multiplication submodule; The multiplication submodule is used to multiply the digital driving waveform signal by a first gain value so that the amplitude of the digital driving waveform signal reaches the expected amplitude of the corresponding analog driving waveform signal; The digital-to-analog conversion module is used to perform digital-to-analog conversion on the digital driving waveform signal to obtain the analog driving waveform signal, and the analog driving waveform signal is used to drive the galvanometer to deflect.

13. The galvanometer drive device according to any one of claims 10 to 12, characterized in that: The digital waveform generation module further includes an addition submodule, and the addition submodule is connected to the address control submodule; The adding submodule is used to apply a first bias voltage to the digital driving waveform signal to adjust the central deflection angle of the galvanometer during the deflection process.

14. The galvanometer drive device according to any one of claims 10 to 13, characterized in that: The digital waveform generation module further comprises a selection submodule, one input end of the selection submodule is connected to the address control submodule to access the digital drive waveform signal, and the other input end is connected to the first fixed amplitude; The selection submodule is used to output the digital drive waveform signal to drive the galvanometer to deflect if the enable signal of the fixed output enable end of the selection submodule is invalid, and output the first fixed amplitude to turn off the galvanometer if the enable signal of the fixed output enable end is valid.

15. A laser projection device, characterized in that: The laser projection device comprises a galvanometer and a galvanometer driving device as described in any one of claims 1 to 14, wherein the galvanometer driving device is connected to the galvanometer.

16. The laser projection device according to claim 15, characterized in that: The laser projection device also includes a light source driving component, a light source, a light valve and a lens. The galvanometer driving device is also connected to the light source driving component and the light valve respectively. The light source driving component is also connected to the light source. The light valve is located on the light output side of the light source, the galvanometer is located on the light output side of the light valve, and the lens is located on the light output side of the galvanometer.

17. The laser projection device according to claim 15 or 16, characterized in that: The galvanometer comprises a base, a fixing plate, a spring, a swinging member and an optical lens; The base has a first hollow area, two pillars are provided on one side of the base, and the two pillars are located at two ends of a diagonal line of the first hollow area. A magnetic component is also provided on one side of the base, and the magnetic component is located at one side of the first hollow area. The magnetic component includes a coil and a magnet. A connector is provided at the end of the base, and the connector is respectively connected to the coil and the output end of the galvanometer drive circuit; The fixing plate is located on a side of the base opposite to the magnetic component, the fixing plate has a second hollow area, and the fixing plate is used to fix the base; The spring sheet is fixed on the two pillars, and the swinging member is covered on the spring sheet with the two pillars as fulcrums. The swinging member has a third hollow area, and the third hollow area is used to support the optical lens. The orthographic projection of the optical lens on the base and the orthographic projection of the second hollow area on the base both overlap with the first hollow area.

18. A galvanometer driving method, characterized in that: The method comprises: When the DLP unit circuit is successfully configured, a galvanometer mirror frame synchronization signal is transmitted, and after a first delay, the galvanometer mirror drive circuit is powered, wherein the galvanometer mirror frame synchronization signal is used to instruct the galvanometer mirror drive circuit to drive the galvanometer mirror to deflect.

19. The method according to claim 18, characterized in that After transmitting the galvanometer mirror frame synchronization signal, the method further includes: generating a digital waveform signal, wherein the digital waveform signal comprises a digital driving waveform signal; Performing digital-to-analog conversion on the digital driving waveform signal to obtain an analog driving waveform signal; A first driving voltage and a second driving voltage with opposite phases are generated based on the analog driving waveform signal, and the first driving voltage is applied to the positive pole of the coil of the galvanometer, and the second driving voltage is applied to the negative pole of the coil of the galvanometer, so that the difference between the first driving voltage and the second driving voltage serves as a driving signal of the galvanometer to drive the galvanometer to deflect.

20. The method of claim 18, wherein: After transmitting the galvanometer mirror frame synchronization signal, the method further includes: Acquire a subframe signal, and delay the subframe signal to obtain a delayed subframe signal, wherein the subframe signal includes subframe signals of two sub-images decomposed from a frame image, and the delayed subframe signal is used to synchronize the display of the sub-image with the movement of the galvanometer; Obtaining a control clock for generating a digital drive waveform; When the edge of the delayed subframe signal arrives, multiple amplitudes are read according to the target galvanometer type, and the multiple amplitudes are output in sequence according to the reading order to generate the digital driving waveform signal, wherein the first to the second to last amplitudes read are outputted with a target segment length, and the last amplitude read is outputted until the next edge of the delayed subframe signal arrives, the target galvanometer type represents the reading method of the amplitude, and the target segment length represents the clock length of multiple control clocks; The digital driving waveform signal is used to drive the galvanometer to deflect.

21. The method of claim 20, wherein: The two frames of sub-images include a first sub-image and a second sub-image; The step of reading multiple amplitudes according to the target galvanometer type includes: Based on the first galvanometer type of the first sub-image, read the plurality of amplitudes in positive order from the amplitude storage submodule; Based on the second galvanometer type of the second sub-image, the multiple amplitudes are read from the amplitude storage submodule in reverse order, or the multiple amplitudes in the amplitude storage submodule are respectively inverted and the inverted multiple amplitudes are read from the amplitude storage submodule in positive order.

22. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores at least one instruction, at least one program, a code set or an instruction set, and the at least one instruction, the at least one program, the code set or the instruction set is loaded and executed by the processor to implement the method as described in any one of claims 18-21.

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