Data processing chip and manufacturing method therefor, and data processing system

Abstract

Provided in the present disclosure are a data processing chip and a manufacturing method therefor, and a data processing system. The data processing chip comprises a first wafer and a first die stacked with the first wafer, wherein the first wafer comprises an arithmetic device, which comprises a plurality of arithmetic units; and the first die comprises a buffer, which is coupled to the arithmetic device by means of bonding, and comprises a plurality of cache units, each of the plurality of cache units being arranged corresponding to each of the plurality of arithmetic units, and the arithmetic units being configured to access the cache units corresponding to the arithmetic units.

Description

Data processing chip and manufacturing method thereof, and data processing system

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on the Chinese patent application with application number 202311409896.4 and application date October 27, 2023, and claims the priority of the Chinese patent application. The entire content of the Chinese patent application is hereby introduced into this application as a reference. Technical Field

[0003] The present disclosure relates to the field of data processing technology, and in particular to a data processing chip and a manufacturing method thereof, and a data processing system. Background Art

[0004] With the development of science and technology, more and more fields, such as artificial intelligence and secure computing, involve large amounts of data processing (i.e., big data processing). Big data processing will generate frequent and large amounts of data interaction between processors and memory.

[0005] However, during the data exchange process, data transmission delays will lead to reduced data processing efficiency. Therefore, how to reduce data transmission delays to improve data processing efficiency has become a technical problem that needs to be solved urgently.

[0006] Summary of the Invention

[0007] The present disclosure provides a data processing chip and a manufacturing method thereof, and a data processing system.

[0008] A first aspect of the present disclosure provides a data processing chip. The data processing chip includes:

[0009] The first wafer comprises: an arithmetic unit; wherein the arithmetic unit comprises a plurality of arithmetic units;

[0010] The first die is stacked with the first wafer and includes: a cache, which is coupled to the operator by bonding; wherein the cache includes a plurality of cache units, each of the plurality of cache units is respectively arranged corresponding to each of the plurality of operator units; the operator unit is configured to access the cache unit arranged corresponding to the operator unit.

[0011] A second aspect of the present disclosure provides a method for manufacturing a data processing chip. The manufacturing method comprises:

[0012] Providing a first wafer; wherein the first wafer includes an arithmetic unit; the arithmetic unit includes a plurality of arithmetic units;

[0013] A first die is formed and stacked with the first wafer; wherein the first die includes a cache, and the cache is coupled to the operator by bonding; the cache includes a plurality of cache units, and each of the plurality of cache units is respectively arranged corresponding to each of the plurality of operator units; the operator unit is configured to access the cache unit arranged corresponding to the operator unit.

[0014] A third aspect of the present disclosure provides a data processing system. The data processing system includes:

[0015] The data processing chip provided in the first aspect;

[0016] At least one memory is arranged in parallel with the first wafer along a first direction, where the first direction is perpendicular to a direction in which the first die and the first wafer are stacked.

[0017] In the present disclosure, on the first hand, by setting a first crystal grain and a first wafer stack, the cache and the operator are coupled by bonding, thereby providing a higher bandwidth for data transmission, achieving high computing power while reducing the bandwidth requirements of the system; on the second hand, each of the multiple cache units is respectively set to correspond to each of the multiple operation units, and the operation unit is configured to access the cache unit set corresponding to the operation unit, thereby simplifying the transmission path, reducing the delay in the data transmission process, improving the efficiency of data processing, and facilitating the maximum bandwidth of the data processing chip; on the third hand, compared with the operation unit that can access all cache units, the present disclosure facilitates the simplification of the interface protocol, reduces the design complexity of the on-chip system, reduces the design and production costs of the data processing chip, and facilitates the reuse of the data processing chip in other devices by setting each of the multiple cache units respectively to correspond to each of the multiple operation units.

[0018] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the embodiments of the present disclosure.

[0020] Fig. 1a is a schematic diagram showing a buffer according to an exemplary embodiment.

[0021] FIG. 1 b is a schematic diagram showing a wiring layer according to an exemplary embodiment.

[0022] FIG1c is a schematic diagram of an operator according to an exemplary embodiment.

[0023] FIG2 is a schematic diagram of a data processing chip according to an embodiment of the present disclosure.

[0024] FIG3 is a cross-sectional view of a data processing chip according to an embodiment of the present disclosure.

[0025] FIG4 a is a schematic diagram of a buffer according to an embodiment of the present disclosure.

[0026] FIG4 b is a schematic diagram showing a wiring layer according to an embodiment of the present disclosure.

[0027] FIG4 c is a schematic diagram of an operator according to an embodiment of the present disclosure.

[0028] FIG5 is a schematic diagram of a data processing system according to an embodiment of the present disclosure.

[0029] FIG6 is a schematic diagram of another data processing system according to an embodiment of the present disclosure.

[0030] FIG7 is a flow chart of a method for manufacturing a data processing chip according to an embodiment of the present disclosure;

[0031] FIG8 a is a first schematic diagram of a manufacturing process of a data processing chip according to an embodiment of the present disclosure.

[0032] FIG8 b is a second schematic diagram of a manufacturing process of a data processing chip according to an embodiment of the present disclosure.

[0033] FIG8c is a third schematic diagram of a manufacturing process of a data processing chip according to an embodiment of the present disclosure.

[0034] Description of Reference Numerals

[0035] Buffers 1210 and 2210; cache units 1220, 2220, 2220a, 2220b, and 2220c; wiring layers 1310 and 2310; arithmetic units 1110 and 2110; arithmetic units 1120, 2120, 2120a, 2120b, and 2120c; and a data processing chip 1000. First wafer 2100; processors 2130 and 2140; memory interface circuit 2150; node interface circuit 2160; first die 2200; memory array chip 2221; second die 2300; bridge circuits 2320, 2320a, 2320b, and 2320c; first region 2100-1; second region 2100-2; data processing systems 3000 and 4000; memories 2000a, 2000b, 2000c, 2000d, 2000e, 2000f, 2000g, and 2000h; node chips 4000a, 4000b, 4000c, and 4000d; second wafer 2200A; and third wafer 2300A. DETAILED DESCRIPTION

[0036] Exemplary embodiments are described in detail herein, with examples illustrated in the accompanying drawings. When the following description refers to the drawings, identical numerals in different drawings represent identical or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all possible implementations consistent with the present disclosure. Rather, they are merely examples of apparatuses and methods consistent with certain aspects of the present disclosure.

[0037] The terms used in the embodiments of the present disclosure are for the purpose of describing specific embodiments only and are not intended to limit the embodiments of the present disclosure. The singular forms "a," "the," and "the" used in the present disclosure are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0038] It should be understood that although the terms first, second, third, etc. may be used to describe various information in the embodiments of the present disclosure, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, without departing from the scope of the embodiments of the present disclosure, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0039] Figure 1a is a schematic diagram of a buffer according to an exemplary embodiment, Figure 1b is a schematic diagram of a wiring layer according to an exemplary embodiment, and Figure 1c is a schematic diagram of an arithmetic unit according to an exemplary embodiment. Referring to Figures 1a to 1c, the arithmetic unit 1110 includes multiple arithmetic units 1120, and the buffer 1210 includes multiple cache units 1220. Each arithmetic unit 1120 is coupled to multiple cache units 1220 via a wiring layer 1310. The longer the transmission path between the arithmetic unit 1120 and the cache unit 1220, the greater the delay in data transmission. For example, when the arithmetic unit 1120 in the lower left corner of Figure 1c needs to access the cache unit 1220 in the upper right corner of Figure 1a, the transmission path in the wiring layer 1310 is as shown in Figure 1b. The longer the transmission path will result in a larger delay in data transmission, thereby reducing the efficiency of data processing.

[0040] In view of this, the present disclosure provides a data processing chip and a manufacturing method thereof, and a data processing system.

[0041] FIG2 is a schematic diagram of a data processing chip according to an embodiment of the present disclosure. Referring to FIG2 , the data processing chip 1000 includes:

[0042] The first wafer 2100 includes: an arithmetic unit 2110; wherein the arithmetic unit 2110 includes a plurality of arithmetic units 2120;

[0043] The first die 2200 is stacked with the first wafer 2100, and includes: a cache 2210, which is coupled to the operator 2110 by bonding; wherein the cache 2210 includes a plurality of cache units 2220, each of the plurality of cache units 2220 is respectively arranged corresponding to each of the plurality of operation units 2120; the operation unit 2120 is configured to access the cache unit 2220 arranged corresponding to the operation unit 2120.

[0044] The first wafer 2100 includes, but is not limited to, a system-on-chip (SOC) integrated with multiple functional circuits. As shown in FIG5 , the first wafer 2100 includes an arithmetic unit 2110 and a processor 2130, a memory interface circuit 2150, and a node interface circuit 2160, etc. The processor 2130, the memory interface circuit 2150, and the node interface circuit 2160 will be described below. It should be noted that the functional circuits shown in FIG2 or FIG5 are shown only as examples, and the first wafer 2100 may also include other functional circuits known in the art, for example, the first wafer 2100 also includes a power supply, a power management circuit, and a timing control circuit, etc.

[0045] The operator 2110 is configured to perform specific calculations in response to control commands and output calculation results. The operator 2110 includes a central processing unit (CPU), a graphics processing unit (GPU), a tensor processing unit (TPU), a data processing unit (DPU), an intelligent processing unit (IPU), or a neural network processing unit (NPU). The operator 2110 can execute a hash algorithm, a convolution algorithm, or a neural network algorithm.

[0046] In one example, the operator 2110 is a tensor processor TPU, which includes a matrix multiplication unit (MXU). The matrix multiplication unit is also called a systolic array, which can process 65536 multiplications and additions of 8-bit integers, greatly improving the computing power of the data processing chip.

[0047] The first die 2200 and the first wafer 2100 can be stacked by using chip on wafer (CoW) bonding technology, and the first die 2200 and the first wafer 2100 can be electrically connected by at least one of a bonding layer, through-silicon via (TSV), wiring or bump.

[0048] Buffer 2210 can cache data to be written to the memory during a write operation; cache data read from the memory during a read operation; cache data to be computed by operator 2110; or cache data output by operator 2110 after performing a computation. Buffer 2210 may include dynamic random access memory (DRAM), flash memory, phase change memory (PCM), or magnetic tunnel junction memory (MTJ). In other embodiments, buffer 2210 may also be other types of memory known in the art, and this disclosure is not particularly limited thereto.

[0049] In one example, cache 2210 is a dynamic random access memory (DRAM). DRAM typically has a gigabyte (GB) capacity and a higher number of pins, allowing it to achieve high bandwidth by running low-speed digital circuits. It is understood that in this example, by using DRAM with a larger storage capacity and a higher number of pins as a cache for the data processing chip, the system's bandwidth requirements can be significantly reduced. Furthermore, compared to using expensive SRAM as a cache, using DRAM as a cache in this example significantly reduces costs.

[0050] The operator 2110 includes multiple operation units 2120, and the cache 2210 includes multiple cache units 2220. In some embodiments, the number of operation units 2120 and cache units 2220 is the same, and each of the multiple cache units 2220 is respectively set to correspond to each of the multiple operation units 2120. Each operation unit 2120 can access the corresponding cache unit 2220, which can reduce the transmission path between the operation unit 2120 and the cache unit 2220, which is beneficial to reducing the delay of data transmission and thereby improving the efficiency of data processing.

[0051] In some embodiments, the cache unit 2220 includes a plurality of memory array tiles 2221 (MAT).

[0052] It should be noted that the first wafer 2100 generally adopts an advanced process technology, such as a 5nm process, a 3nm process or a 1nm process, etc. Advanced process technology requires higher design and production costs, and integrating an on-chip cache in the on-chip system will undoubtedly lead to a waste of costs. Based on this, in other embodiments, the cache 2210 can also be an SRAM, and the SRAM can adopt a process technology greater than 20nm, such as a 22nm process, a 25nm process or a 28nm process, etc. It can be understood that in this example, by stacking the SRAM with lower process technology requirements with the first wafer 2100 and using it as a cache, the design and production costs of the data processing chip can be saved.

[0053] In some embodiments, the first wafer 2100 is manufactured using a first process technology, and the first die 2200 is manufactured using a second process technology; wherein the feature size corresponding to the second process technology is larger than the feature size corresponding to the first process technology.

[0054] Of course, in other embodiments, the feature size corresponding to the second process technology may be smaller than or equal to the feature size corresponding to the first process technology.

[0055] In the embodiments of the present disclosure, on the one hand, by setting a first crystal grain and a first wafer stack, the cache and the operator are coupled by bonding, thereby providing a higher bandwidth for data transmission, achieving high computing power while reducing the bandwidth requirements of the system; on the second hand, each of the multiple cache units is respectively set to correspond to each of the multiple operation units, and the operation unit is configured to access the cache unit set corresponding to the operation unit, thereby simplifying the transmission path, reducing the delay in the data transmission process, improving the efficiency of data processing, and facilitating the maximum bandwidth of the data processing chip; on the third hand, compared with the operation unit that can access all cache units, the present disclosure facilitates the simplification of the interface protocol, reduces the design complexity of the on-chip system, reduces the design and production costs of the data processing chip, and facilitates the reuse of the data processing chip in other devices by setting each of the multiple cache units respectively to correspond to each of the multiple operation units.

[0056] In some embodiments, as shown in FIG. 2 , the data processing chip 1000 further includes:

[0057] A routing layer 2310 is located in the second die 2300 between the first wafer 2100 and the first die 2200 ; or is located in the first wafer 2100 and between the operator 2110 and the first die 2200 ;

[0058] Multiple bridge circuits 2320 are located in the wiring layer 2310 and are respectively arranged in one-to-one correspondence with multiple operation units 2120; wherein, the first port of the bridge circuit 2320 is coupled to the operation unit 2120 through a first interface protocol, and the second port of the bridge circuit 2320 is coupled to the cache unit 2220 through a second interface protocol; wherein, the second interface protocol is different from the first interface protocol.

[0059] 2 shows that the wiring layer 2310 is located in the second die 2300, and the first wafer 2100, the second die 2300, and the first die 2200 are stacked in sequence. In another example, the wiring layer 2310 is located in the first wafer 2100 (not shown in the figure), that is, the first wafer 2100 and the first die 2200 are stacked in sequence.

[0060] In some embodiments, the number of computing units 2120, the number of cache units 2220, and the number of bridge circuits 2320 are the same. In one embodiment, the number of computing units 2120, the number of cache units 2220, and the number of bridge circuits 2320 are all 1024. It will be appreciated that, in this embodiment, each of the plurality of computing units 2120 can be coupled to each of the plurality of cache units 2220 via each of the plurality of bridge circuits 2320, and each computing unit 2120 can manage the data cached in the corresponding cache unit 2220, thereby improving the computing performance of the data processing chip.

[0061] In some embodiments, the second die 2300 is manufactured using a third process, and the feature size corresponding to the third process is larger than the feature size corresponding to the first process. Of course, in other embodiments, the feature size corresponding to the third process may be smaller than or equal to the feature size corresponding to the first process.

[0062] In some embodiments, the feature size corresponding to the third process technology may be the same as or different from the feature size corresponding to the second process technology.

[0063] The wiring layer 2310 includes an insulating layer and wiring (not shown) located in the insulating layer. The insulating layer may be made of silicon oxide, oxynitride, or silicon oxynitride; the wiring may be made of a conductive material, such as at least one of copper, aluminum, platinum, titanium, or tin.

[0064] In some embodiments, as shown in FIG2 , each of the plurality of bridge circuits 2320 is respectively configured to correspond to each of the plurality of computing units 2120. Since each of the plurality of computing units 2120 is also configured to correspond to each of the plurality of cache units 2220, each of the plurality of computing units 2120, each of the plurality of bridge circuits 2320, and each of the plurality of cache units 2220 are all configured to correspond to each other. The bridge circuit 2320 is configured to perform protocol conversion on data transmitted between the computing units 2120 and the cache units 2220. The bridge circuit 2320 includes a first port, a conversion unit, and a second port. The first port is configured to couple to the computing units 2120, and the second port is configured to couple to the cache units 2220. The conversion unit is configured to convert a first interface protocol between the first port and the computing units 2120 into a second interface protocol between the second port and the cache units 2220, thereby ensuring data transmission between the computing units 2110 and the cache units 2210.

[0065] Figure 4a is a schematic diagram of a buffer 2210 according to an embodiment of the present disclosure, Figure 4b is a schematic diagram of a wiring layer 2310 according to an embodiment of the present disclosure, and Figure 4c is a schematic diagram of an arithmetic unit 2110 according to an embodiment of the present disclosure. Referring to Figures 2 and 4a through 4c, each of the plurality of arithmetic units 2120, each of the plurality of bridge circuits 2320, and each of the plurality of cache units 2220 are correspondingly configured, and an arithmetic unit 2120 accesses the corresponding cache unit 2220 via the bridge circuit 2320. Data can be transmitted between the plurality of arithmetic units 2120.

[0066] In one embodiment, arithmetic unit 2120a, bridge circuit 2320a, and cache unit 2220a are provided in a one-to-one correspondence; arithmetic unit 2120b, bridge circuit 2320b, and cache unit 2220b are provided in a one-to-one correspondence; and arithmetic unit 2120c, bridge circuit 2320c, and cache unit 2220c are provided in a one-to-one correspondence. Arithmetic unit 2120a can access cache unit 2220a via bridge circuit 2320a, arithmetic unit 2120b can access cache unit 2220b via bridge circuit 2320b, and arithmetic unit 2120c can access cache unit 2220c via bridge circuit 2320c. Data can be transmitted between arithmetic units 2120a, 2120b, and 2120c via internal interconnects. Consequently, the transmission path between arithmetic unit 2120 and cache unit 2220 is significantly shortened, reducing data transmission delay and thereby improving data processing efficiency.

[0067] It can be understood that in this embodiment, each of the multiple operating units 2120 can be coupled to each of the multiple cache units 2220 through multiple bridge circuits 2320, and each operating unit 2120 can manage the data cached in the corresponding cache unit 2220, which is beneficial to improving the computing performance of the data processing chip while reducing data delay.

[0068] In one example, the first port of the bridge circuit 2320 is coupled to the input / output interface of the corresponding computing unit 2120, and the communication between the first port of the bridge circuit 2320 and the computing unit 2120 may comply with the SRAM interface protocol (SRAM protocol); the second port of the bridge circuit 2320 is coupled to the input / output interface of the corresponding cache unit 2220, and the communication between the second port of the bridge circuit 2320 and the cache unit 2220 may comply with the DRAM interface protocol (DRAM protocol). Of course, in other embodiments, the conversion unit may be omitted, and the communication between the first port of the bridge circuit 2320 and the computing unit 2120, as well as between the second port of the bridge circuit 2320 and the cache unit 2220, may comply with the DRAM interface protocol.

[0069] In the disclosed embodiments, by providing a wiring layer within the first wafer or the second die and including a bridge circuit within the wiring layer, the arithmetic unit accesses its corresponding cache unit through the wiring layer, further reducing data transmission latency while enabling data transmission between the arithmetic unit and the cache. Furthermore, the provision of a bridge circuit enables data transmission between the arithmetic unit and the cache, making it compatible with existing interface protocols.

[0070] Figure 3 is a cross-sectional view of a data processing chip 1000 according to an embodiment of the present disclosure. In some embodiments, referring to Figure 3 , the first wafer 2100 includes a first region 2100-1 and a second region 2100-2; wherein the operator 2110 is located in the first region 2100-1, and the first die 2200 is located above the first region 2100-1; the data processing chip 1000 also includes: a heat dissipation structure (not shown in the figure), which is located above the second region 2100-2.

[0071] In some embodiments, as shown in Figure 3, the processor 2130 and the operator 2110 are both located in the first wafer 2100 and are arranged side by side in a direction perpendicular to the stacking direction of the first wafer 2100 and the first die 2200. The operator 2110 is located in the first area 2100-1, and the processor 2130 is located in the second area 2100-2 other than the first area 2100-1. The processor 2130 is configured to control the logical operations of the memory, such as write operations, read operations, or erase operations.

[0072] The material of the heat dissipation structure includes heat dissipation materials, for example, metals such as copper.

[0073] In the embodiment of the present disclosure, a heat dissipation structure is provided on the second area of ​​the first wafer to rationally utilize the space of the data processing chip and improve space utilization. In addition, the heat dissipation structure can dissipate heat in a timely and effective manner to avoid damage to the data processing chip caused by high temperature.

[0074] In some embodiments, the orthographic projection of the first die 2200 substantially coincides with the orthographic projection of the operator 2110. That is, the first die 2200 and the operator 2110 have the same size.

[0075] In some embodiments, the data processing chip 1000 further includes a second die 2300 , the first die 2200 , the second die 2300 and the operator 2110 are of the same size, and the orthographic projections of the first die 2200 and the second die 2300 substantially coincide with the orthographic projection of the operator 2110 .

[0076] It should be noted that basic overlap includes complete overlap or deviation, but the deviation is within the allowable error range.

[0077] In some embodiments, the storage capacity of the buffer 2210 is greater than a preset value; wherein the preset value is greater than 0 mebiByte (MB) and less than 1 gigaByte (GB).

[0078] It should be noted that, for cost considerations, the capacity of on-chip SRAM is typically less than 1GB. For example, the capacity of on-chip SRAM can be in the MB range. In the disclosed embodiments, by setting the storage capacity of the buffer to be larger than a preset value, the storage capacity of the off-chip buffer can be increased, thereby reducing the bandwidth requirements of the system.

[0079] In one embodiment, in a system-on-chip (SoC) using SRAM as a buffer, the SRAM has a storage capacity of megabytes, corresponding to a system bandwidth requirement of several terabytes per second. This requires the use of higher-bandwidth memory, such as high-bandwidth memory (HBM), to meet the system bandwidth requirement, at the expense of design complexity and high production costs. The present disclosure reduces the system bandwidth requirement to several gigabytes per second by using DRAM, with a storage capacity of gigabytes, as an off-chip buffer in buffer 2210. This eliminates the need for higher-bandwidth memory, such as HBM, simplifying the design complexity of the data processing chip while reducing costs.

[0080] In some embodiments, the data processing chip 1000 is applied to the field of artificial intelligence, and the data processing chip 1000 includes but is not limited to an artificial intelligence chip (AI).

[0081] Based on the aforementioned data processing chip, embodiments of the present disclosure further provide a data processing system. The data processing system comprises: the data processing chip of any of the aforementioned embodiments; and at least one memory device arranged in parallel with the first wafer along a first direction perpendicular to the direction in which the first die and the first wafer are stacked.

[0082] FIG5 is a schematic diagram of a data processing system 3000 according to an embodiment of the present disclosure. Referring to FIG5 , a first wafer 2100 and a plurality of memories are arranged in parallel along a first direction. The first wafer 2100 is coupled to the memories via a memory interface circuit 2150. For example, FIG5 shows eight memories 2000a, 2000b, 2000c, 2000d, 2000e, 2000f, 2000g, and 2000h. Memories 2000a, 2000b, 2000c, and 2000d are located on one side of the first wafer 2100, while memories 2000e, 2000f, 2000g, and 2000h are located on the other side of the first wafer 2100.

[0083] Memory includes: Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), Graphics Double Data Rate (GDDR), and High Bandwidth Memory (HBM). In one embodiment, the buffer 2210 is a dynamic random access memory (DRAM), and the memory is the fifth-generation low-power DRAM LPDDR5, referred to as LP5.

[0084] In some embodiments, as shown in FIG2 and FIG5 , after the buffer 2210 is provided in the first die 2200, the SRAM cache 2140 in the first wafer 2100 (as shown in the dotted box in FIG5 ) can be omitted, which helps reduce the planar size of the data processing chip 1000. In other embodiments, after the buffer 2210 is provided in the first die 2200, the SRAM cache 2140 in the first wafer 2100 can also be retained. The SRAM and the buffer 2210 in the first die 2200 can be used together as a cache, which helps further reduce bandwidth requirements. Those skilled in the art can make reasonable settings according to actual needs, and this disclosure is not limited here.

[0085] In some embodiments, the first wafer 2100 and the plurality of memories are located in a first level of the data processing system 3000, the second die 2300 is located in a second level of the data processing system 3000, and the first die 2200 is located in a third level of the data processing system 3000. That is, the first wafer 2100 and the plurality of memories are located in the same level, the second die 2300 and the plurality of memories are located in a different level, and the first die 2200 and the plurality of memories are located in a different level.

[0086] It should be noted that the same level used in this disclosure means that the two grains (or the grain and the wafer) have the same distance from the top surface or bottom surface of the packaging substrate (not shown in the figure), and different levels means that the two grains (or the grain and the wafer) have different distances from the top surface or bottom surface of the packaging substrate.

[0087] In some embodiments, a data processing chip and a memory constitute a node chip; the data processing system includes: a plurality of node chips; wherein the plurality of node chips are arranged in parallel and connected in a cluster along a second direction, the second direction being perpendicular to the direction in which the first die and the first wafer are stacked, and the second direction intersecting the first direction. Here, cluster connection includes a series arrangement, a mesh network arrangement, a ring arrangement, or a one-to-many arrangement, etc. The embodiments of the present disclosure do not specifically limit the connection method of the plurality of node chips.

[0088] The data processing chip 1000 and at least one memory device in FIG5 may constitute a node chip. FIG6 is a schematic diagram of another data processing system 4000 according to an embodiment of the present disclosure. Referring to FIG6 , data processing system 4000 includes multiple node chips. For example, FIG6 shows four node chips 4000a, 4000b, 4000c, and 4000d. As shown in FIG5 , the node chips can be connected via node interface circuit 2160. By connecting multiple node chips, the computing power of the data processing system can be further improved.

[0089] Based on the above data processing chip, an embodiment of the present disclosure further provides a method for manufacturing the data processing chip.

[0090] FIG7 is a flow chart of a method for manufacturing a data processing chip according to an embodiment of the present disclosure. Referring to FIG7 , the manufacturing method includes at least the following steps:

[0091] S2001: providing a first wafer; wherein the first wafer includes an arithmetic unit; the arithmetic unit includes a plurality of arithmetic units;

[0092] S2002: forming a first die stacked with a first wafer; wherein the first die includes a cache, the cache is coupled to the operator by bonding; the cache includes a plurality of cache units, each of the plurality of cache units is respectively arranged corresponding to each of the plurality of operator units; the operator unit is configured to access the cache unit arranged corresponding to the operator unit.

[0093] It should be noted that the steps shown in FIG. 7 are not exclusive, and other steps may be performed before, after or between any steps in the shown operation; the steps shown in FIG. 7 may be adjusted in order according to actual needs.

[0094] 8a to 8c are schematic diagrams illustrating a manufacturing process of a data processing chip according to an embodiment of the present disclosure. The manufacturing method of the data processing chip provided by the embodiment of the present disclosure will be described in detail below in conjunction with FIG. 7 and FIG. 8a to 8c.

[0095] In step S2001 , as shown in FIG. 8 a , a first wafer 2100 is provided. The first wafer 2100 includes an operator 2110 . The operator 2110 includes a plurality of operation units.

[0096] In some embodiments, as shown in FIG. 8 a , the manufacturing method further includes: providing a second wafer 2200A, where the second wafer 2200A includes a plurality of first dies 2200 .

[0097] The first wafer 2100 and the second wafer 2200A can be manufactured using processes known in the semiconductor field (for example, a thin film deposition process, a photolithography process, an etching process, a particle implantation process, etc.). The first wafer 2100 adopts a first process technology, and the second wafer 2200A adopts a second process technology. The characteristic size corresponding to the second process technology is larger than the characteristic size corresponding to the first process technology. Here, the characteristic size represents the minimum size in the first wafer 2100 or the second wafer 2200A. Of course, in other embodiments, the characteristic size corresponding to the second process technology may be less than or equal to the characteristic size corresponding to the first process technology.

[0098] The second wafer 2200A includes a plurality of first dies 2200 and a first scribe line between two adjacent first dies 2200 .

[0099] In step S2002, a first die is formed and stacked with the first wafer. Here, the second wafer is cut along the first scribe line to obtain multiple first dies. The first die is then inverted and aligned with the computing unit in the first wafer and bonded. In one example, multiple cache units are bonded to multiple computing units in a one-to-one correspondence, so that the computing units can access the corresponding cache units.

[0100] In some embodiments, referring to FIG. 8a to FIG. 8c , the manufacturing method further includes:

[0101] Providing a third wafer 2300A; wherein the third wafer 2300A includes a plurality of second dies 2300; the second dies 2300 include a wiring layer and a plurality of bridge circuits located in the wiring layer;

[0102] bonding the third wafer 2300A to the second wafer 2200A so that the second port of the bridge circuit is coupled to the cache unit via the second interface protocol;

[0103] A dicing process is performed on the bonded third wafer 2300A and the second wafer 2200A to form a bonded second die 2300 and a bonded first die.

[0104] The above step S2002 includes: bonding the bonded second die 2300 and the first die to the first wafer 2100, so that the first port of the bridge circuit is coupled to the computing unit via a first interface protocol; wherein the second interface protocol is different from the first interface protocol.

[0105] 8a, a third wafer 2300A is provided, and the third wafer 2300A includes a plurality of second dies 2300. The third wafer 2300A can be manufactured using processes known in the semiconductor field (e.g., thin film deposition process, photolithography process, etching process, particle implantation process, etc.). The third wafer 2300A uses a third process technology, and the feature size corresponding to the third process technology is larger than the feature size corresponding to the first process technology. The feature size corresponding to the third process technology and the feature size corresponding to the second process technology can be the same or different. Of course, in other embodiments, the feature size corresponding to the third process technology can be less than or equal to the feature size corresponding to the first process technology.

[0106] The third wafer 2300A includes a plurality of second dies 2300 and second scribe lines between two adjacent second dies 2300 .

[0107] As shown in Figure 8b, after the second wafer 2200A and the third wafer 2300A are manufactured, the second wafer 2200A is inverted and aligned with the third wafer 2300A and bonded, and the bonded second wafer 2200A and the third wafer 2300A are cut into multiple chips along the first cutting street and the second cutting street. The chip includes a stacked first die (not shown in the figure) and a second die 2300. As shown in Figure 2, the first die 2200 includes a cache unit 2220, and the second die 2300 includes a bridge circuit 2320. The second port of the bridge circuit 2320 is coupled to the cache unit 2220 by bonding. The bridge circuit 2320 transmits data to the cache unit 2220 through the second interface protocol, and then the two chips are packaged together. Here, the bonding method between the second wafer 2200A and the third wafer 2300A includes wafer-on-wafer bonding (WoW). In one embodiment, the size of the first die is the same as the size of the second die 2300, and the size of the first cutting street is the same as the size of the second cutting street.

[0108] 8c , the bonded and packaged chip is aligned with the arithmetic unit 2110 in the first wafer 2100. Here, the first port of the bridge circuit in the second die 2300 is coupled to the arithmetic unit via bonding, and the bridge circuit receives data transmitted by the arithmetic unit via a first interface protocol. The chip is then packaged together with the first wafer 2100. Here, the bonding method between the chip and the first wafer 2100 includes chip-on-wafer (CoW) bonding, and the first interface protocol and the second interface protocol are different.

[0109] In some embodiments, the above step S2001 includes: forming an operator and forming a wiring layer on the operator; forming multiple bridge circuits in the wiring layer; wherein, the first port of the bridge circuit is coupled to the operator unit through a first interface protocol; the above step S2002 includes: inverting the first grain so that the wiring layer is located between the operator and the first grain; bonding the bridge circuit and the first grain so that the second port of the bridge circuit is coupled to the cache unit through a second interface protocol; wherein, the second interface protocol is different from the first interface protocol.

[0110] In some embodiments, after forming the arithmetic units, an insulating layer is formed covering the arithmetic units. Wiring and bridge circuits are formed in the insulating layer through processes such as photolithography, etching, and thin film deposition. The bridge circuits are provided in a one-to-one correspondence with the arithmetic units. The bridge circuits and corresponding arithmetic units are coupled via interconnecting contacts and / or interconnecting lines. The bridge circuits receive data transmitted by the arithmetic units via a first interface protocol. After dicing the second wafer to form a first die, the first die is inverted and aligned with the first wafer and bonded. In one example, multiple cache units, multiple bridge circuits, and multiple arithmetic units are aligned one-to-one and then bonded. The arithmetic units can access the corresponding cache units via the bridge circuits.

[0111] In some embodiments, as shown in FIG. 8 c , the first wafer 2100 includes a first region 2100 - 1 and a second region 2100 - 2 ; wherein the operator 2110 is located in the first region 2100 - 1 ;

[0112] The above step S2002 includes: forming a first crystal grain on the first region 2100 - 1 ;

[0113] The manufacturing method further includes: forming a heat dissipation structure (not shown in the figure) on the second region 2100 - 2 .

[0114] In some embodiments, as shown in FIG8c , the first wafer 2100 further includes a processor 2130, which is located in the second region 2100-2 of the first wafer 2100. After bonding and packaging, the chip is bonded to the arithmetic unit 2110 located in the first region 2100-1 and is located in the first region 2100-1. The orthographic projections of the first die, the second die 2300, and the arithmetic unit 2110 substantially overlap. Therefore, vacant space exists in the second region 2100-2 of the first wafer 2100, excluding the first region 2100-1. A heat dissipation structure is provided in the vacant space. The heat dissipation structure is made of a metal such as copper. By providing the heat dissipation structure in the vacant space, the space of the data processing chip is rationally utilized, improving space utilization. Furthermore, the heat dissipation structure can dissipate heat promptly and effectively, preventing damage to the data processing chip due to high temperature.

[0115] In the above embodiments, the description of each embodiment has different emphases. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0116] The foregoing description is merely an illustrative example of the specific embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any modifications or substitutions that can be readily conceived by a person skilled in the art within the technical scope disclosed herein are intended to be encompassed within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be determined in accordance with the scope of protection of the claims.

Claims

1. A data processing chip, comprising: The first wafer comprises: an operator; wherein the operator comprises a plurality of operation units; The first die is stacked with the first wafer, and includes: a cache, which is coupled to the operator by bonding; wherein the cache includes a plurality of cache units, each of the plurality of cache units is respectively arranged corresponding to each of the plurality of operator units; and the operator unit is configured to access the cache unit arranged corresponding to the operator unit.

2. The data processing chip according to claim 1, wherein: The data processing chip also includes: A wiring layer is located in a second die between the first wafer and the first die; or, is located in the first wafer and between the operator and the first die; A plurality of bridge circuits are located in the wiring layer, and each of the plurality of bridge circuits is respectively arranged corresponding to each of the plurality of operation units; wherein the first port of the bridge circuit is coupled to the operation unit via a first interface protocol, and the second port of the bridge circuit is coupled to the cache unit via a second interface protocol; wherein the second interface protocol is different from the first interface protocol.

3. The data processing chip according to claim 1, wherein: The first wafer includes a first region and a second region; wherein the operator is located in the first region, and the first die is located on the first region; The data processing chip further includes a heat dissipation structure located above the second area.

4. The data processing chip according to claim 1, wherein: The orthographic projection of the first grain substantially coincides with the orthographic projection of the operator.

5. A method for manufacturing a data processing chip, comprising: Providing a first wafer; wherein the first wafer includes an operator; the operator includes a plurality of operation units; A first crystal grain is formed and stacked with the first wafer; wherein the first crystal grain includes a cache, and the cache is coupled to the operator by bonding; the cache includes a plurality of cache units, and each of the plurality of cache units is respectively arranged corresponding to each of the plurality of operator units; the operator unit is configured to access the cache unit arranged corresponding to the operator unit.

6. The manufacturing method according to claim 5, wherein: The manufacturing method further comprises: Providing a second wafer; wherein the second wafer includes a plurality of the first dies; Providing a third wafer; wherein the third wafer includes a plurality of second dies; the second dies include a wiring layer and a plurality of bridge circuits located in the wiring layer; Bonding the third wafer and the second wafer so that the second port of the bridge circuit is coupled to the cache unit through a second interface protocol; The bonded third wafer and the second wafer are cut to form the bonded second die and the the first grain; The forming of the first die stacked with the first wafer includes: bonding the bonded second die and the first die to the first wafer, so that the first port of the bridge circuit is coupled to the operation unit through a first interface protocol; wherein the second interface protocol is different from the first interface protocol.

7. The manufacturing method according to claim 5, wherein: The providing of a first wafer comprises: forming the operator; forming a wiring layer on the operator; A plurality of bridge circuits are formed in the wiring layer; wherein a first port of the bridge circuit is coupled to the operation unit via a first interface protocol; The forming of a first die stacked with the first wafer includes: Inverting the first die so that the wiring layer is located between the operator and the first die; The bridge circuit and the first die are bonded so that a second port of the bridge circuit is coupled to the cache unit via a second interface protocol; wherein the second interface protocol is different from the first interface protocol.

8. The manufacturing method according to claim 5, wherein: The first wafer includes a first area and a second area; wherein the operator is located in the first area; The forming of a first die stacked with the first wafer includes: forming the first grain on the first region; The manufacturing method further includes: forming a heat dissipation structure on the second area.

9. A data processing system comprising: The data processing chip according to any one of claims 1 to 4; At least one memory is arranged in parallel with the first wafer along a first direction, and the first direction is perpendicular to a direction in which the first die and the first wafer are stacked.

10. The data processing system according to claim 9, wherein: The data processing chip and the memory constitute a node chip; The data processing system includes: a plurality of the node chips; wherein the plurality of the node chips are arranged in parallel and connected in a cluster along a second direction, the second direction is perpendicular to a direction in which the first crystal grains and the first wafer are stacked, and the second direction intersects with the first direction.

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