Method for manufacturing semiconductor device

Abstract

A base layer (3) and a gold layer (4) are sequentially formed on a semiconductor substrate (1). A resist pattern (5) is formed on the gold layer (4). A plating film (6) is formed on portions of the gold layer (4), which are not covered with the resist pattern (5). Portions of the gold layer (4), which are exposed by removing the resist pattern (5), and the base layer (3) are etched by ion milling so as to form a metal mask (8). The semiconductor substrate (1) is plasma-etched using the metal mask (8) so as to form a via (9). The base layer (3) is composed of at least one metal layer that is formed of any one metal selected from among Ti, Ta, W, Ni, Co, and Nb or an alloy of two or more of those metals. The film thickness of the gold layer (4) is 20 nm or less, and the film thickness of the base layer (3) is 100 nm or more.

Description

Semiconductor device manufacturing method

[0001] The present disclosure relates to a method for manufacturing a semiconductor device.

[0002] SiC single crystal substrates or GaN single crystal substrates are used in power devices or high-frequency devices. During the manufacture of semiconductor devices, etching is performed to form through electrodes (vias) in the substrate. However, SiC and GaN compounds are stable covalently bonded crystals and are difficult-to-process materials with low reactivity. Therefore, resist masks cannot achieve a selectivity relative to the substrate processing speed, so metal masks are used (see, for example, Patent Document 1).

[0003] When forming a metal mask by electroplating, it is necessary to secure a power supply area on the periphery of the wafer. However, no plating film is formed on the power supply area. This creates the problem that the periphery of the wafer is etched and damaged when the substrate is etched. Therefore, electroless plating is suitable for forming metal masks.

[0004] Conventionally, titanium (Ti) and gold (Au) are first formed in this order on a substrate as a seed layer, and a resist pattern is then formed on top of that. Next, a plating film is formed by electroless plating. Next, the resist is removed and the exposed seed film is etched to form a metal mask. Vias are formed in the substrate by plasma etching using the metal mask. During this process, etching progresses due to a chemical reaction of the etching gas in the plasma.

[0005] Japanese Patent Publication No. 2010-141178

[0006] Conventionally, the Au in the seed layer was exposed on the side of the opening in the metal mask. If this Au gets mixed in during via etching, the chemical reactivity of the etching gas decreases. This causes the via etching to stop. This via etching anomaly causes poor conductivity due to incomplete vias, resulting in reduced yield.

[0007] The present disclosure has been made to solve the above-mentioned problems, and its object is to provide a method for manufacturing a semiconductor device that can suppress via etching abnormalities.

[0008] A method for manufacturing a semiconductor device according to the present disclosure includes the steps of: forming an underlayer on a semiconductor substrate; forming a gold layer on the underlayer; forming a resist pattern on the gold layer; forming a plating film on the gold layer that is not covered by the resist pattern; etching the gold layer and the underlayer exposed by removing the resist pattern by ion milling to form a metal mask using the remaining underlayer, the gold layer, and the plating film; and plasma etching the semiconductor substrate using the metal mask to form a via; wherein the underlayer is at least one metal layer made of any one of Ti, Ta, W, Ni, Co, and Nb or an alloy of two or more of these metals, and the gold layer has a thickness of 20 nm or less, and the underlayer has a thickness of 100 nm or more.

[0009] In the present disclosure, when a gold layer and an underlayer are ion milled to form a metal mask, material from the underlayer is ejected and re-adheres to the sidewalls of the etched portion, forming a coating film. Because the gold layer is 20 nm or less in thickness and the underlayer is 100 nm or more in thickness, the sidewalls of the etched gold layer can be covered with a coating film. This prevents Au from being mixed in during via etching, thereby suppressing via etching abnormalities.

[0010] FIG. 1 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment. FIG. 2 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment. FIG. 3 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment. FIG. 4 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment. FIG. 5 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment. FIG. 6 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment. FIG. 7 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment. FIG. 8 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment.

[0011] 1 to 11 are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment. First, as shown in Fig. 1, a plurality of via receiving pads 2 are formed at intervals on the surface of a semiconductor substrate 1 by sputtering, vapor deposition, plating, or the like. The semiconductor substrate 1 is a SiC single crystal substrate or a GaN single crystal substrate. After depositing a film of Ti or W, which has high adhesion to the semiconductor substrate 1, as the via receiving pads 2, a film of a highly conductive metal, such as Au, Ag, or Cu, is deposited.

[0012] 2, the back surface of the semiconductor substrate 1 is ground and polished to reduce the thickness of the semiconductor substrate 1 to approximately 50 μm to 200 μm. This makes it possible to improve the thermal characteristics and high-frequency characteristics. The back surface of the thinned semiconductor substrate 1 is then subjected to mirror finishing.

[0013] Next, as shown in Figure 3, an underlayer 3 and a gold layer 4 are formed in this order as seed layers on the back surface of the semiconductor substrate 1 by continuous film deposition using sputtering. The underlayer 3 has higher adhesion to the semiconductor substrate 1 than the gold layer 4. The gold layer 4 is resistant to surface oxidation and has high conductivity. A plurality of resist patterns 5 are formed on the gold layer 4 on the back surface of the substrate using photoresist so as to face the plurality of via receiving pads 2 on the front surface of the substrate. The width of the resist patterns 5 is narrower than the width of the via receiving pads 2.

[0014] Next, as shown in Figure 4, a plating film 6 made of nickel (Ni) or copper (Cu) is formed by electroless plating. Specifically, the substrate is immersed in a pretreatment solution to apply a catalytic metal such as Pd to the gold layer 4, and then immersed in a plating solution. This results in a plating film formed in proportion to the immersion time. Because Au itself has catalytic properties for electroless plating, even the application of only a small amount of Pd can stably initiate the electroless plating deposition reaction. Therefore, it is important that the surface to be electrolessly plated is an Au surface.

[0015] Next, as shown in FIG. 5, the resist pattern 5 is removed. Next, the gold layer 4 is exposed through the openings in the plating film 6. Next, the gold layer 4 and the underlayer 3 are etched by ion milling using Ar ions. The ion milling acceleration voltage is 600 to 700 V, the current is 400 to 800 mA, the Ar flow rate is 10 to 15 sccm, and the incidence angle is perpendicular to the back surface of the substrate. During this process, as shown in FIG. 6, the material of the underlayer 3 is ejected by the physical impact of the Ar ions and re-adheres to the sidewalls of the etched gold layer 4, forming a coating film 7.

[0016] Ion milling is carried out until it penetrates the gold layer 4 and the underlayer 3. As a result, as shown in Fig. 7, the remaining underlayer 3, gold layer 4, and plating film 6 form a metal mask 8 for via etching. The gold layer 4 on the sidewall of the opening in the metal mask 8 is completely covered by the coating film 7 and is not exposed.

[0017] Next, as shown in Fig. 8, the semiconductor substrate 1 is plasma etched from the backside using a metal mask 8. As a result, vias 9 are formed that reach from the backside of the semiconductor substrate 1 to the via receiving pads 2, as shown in Fig. 9. The width of the opening in the metal mask 8 and the via 9 is w, and the depth of the via 9 is d.

[0018] For via etching, for example, inductively coupled plasma (ICP) is used. That is, plasma of a reactive gas is generated, and the plasma is attracted to the semiconductor substrate 1 by applying a bias to the semiconductor substrate 1. Etching is performed by a chemical reaction between the plasma and the semiconductor substrate 1 and physical impact. For example, SF is used as a reactive gas for etching SiC or GaN. ６ is used.

[0019] 10, the metal mask 8 is removed by immersion in an etching solution. When the plating film 6 is a Ni plating film, for example, nitric acid is used as the etching solution.

[0020] 11 , a back electrode 10 is formed to cover the back surface of the semiconductor substrate 1, the side surfaces of the vias 9, and the via receiving pads 2 exposed within the vias 9. To form the back electrode 10, a Ti film and an Au film are formed in this order by sputtering, for example, and then an Au plated film is formed. Since the back surface of the semiconductor substrate 1 is die-bonded, the back electrode 10 is formed on the entire back surface of the semiconductor substrate 1 without being patterned. Through the above steps, the semiconductor device according to this embodiment is manufactured.

[0021] Next, Table 1 shows the results of evaluating the dependency of via etching abnormalities on the opening width and seed layer structure. The semiconductor substrate 1 is SiC. The underlayer 3 is Ti. Evaluation was performed for a case where the opening in the metal mask 8 is rectangular (20 μm × 40 μm) and the via 9 is 50 μm deep, and a case where the opening in the metal mask 8 is round (80 μmφ) and the via 9 is 100 μm deep. The "opening width" is the width in the short diameter direction of the rectangular opening in the metal mask 8, i.e., the minimum width of the planar shape of the opening.

[0022] [Table 1]

[0023] As a result of the evaluation, when the opening width was 80 μm, no via etching abnormalities occurred regardless of the Ti thickness and Au thickness. Therefore, it was found that if the opening area is large, the effect of Au inclusion is small, making via etching abnormalities less likely to occur. On the other hand, it can be assumed that the smaller the opening width, the greater the effect of Au on the plasma gas during via etching. Experiments have shown that via etching abnormalities can occur when the opening width is 20 μm or less. However, even when the opening width is 20 μm or less, no via etching abnormalities occurred as long as the Ti thickness was 100 nm or more and the Au thickness was 20 nm or less.

[0024] Next, the effects of this embodiment will be explained in comparison with a comparative example. In the comparative example, the thickness of the underlayer 3 is about 50 nm. Since the underlayer 3 is formed for adhesion, it has been conventionally thought that it is sufficient to ensure a thickness that allows for uniform film formation, and there has been no motivation to make it thicker than 50 nm.

[0025] As described above, if the opening area of ​​the metal mask 8 is large, via etching defects are unlikely to occur. However, if the opening area of ​​the metal mask 8 is 20×40=400 μm２ Below this, that is, when the minimum width of the opening in the metal mask 8 is 20 μm or less, via etching abnormalities occur.

[0026] As described above, when the gold layer 4 and the underlayer 3 are ion milled to form the metal mask 8, material from the underlayer 3 is ejected and re-adheres to the sidewalls of the etched portion, forming the coating film 7. However, in the comparative example, the underlayer 3 is thin, so the sidewalls of the etched gold layer 4 cannot be sufficiently covered with the coating film 7. This causes Au to get mixed in during via etching, resulting in via etching abnormalities.

[0027] In contrast, in this embodiment, the thickness of the gold layer 4 is 20 nm or less, while the thickness of the underlayer 3 is 100 nm or more, which is sufficiently thick, so that the sidewall of the etched gold layer 4 can be covered with the coating film 7. This prevents Au from being mixed in during via etching, thereby suppressing via etching abnormalities.

[0028] In order for the material of the base layer 3 that has been thrown off to re-adhere to the sidewall of the gold layer 4, the material of the base layer 3 needs to be a material that has good adhesion to the gold layer 4. However, noble metals such as Pd, Ag, and Pt inhibit via etching, just like Au. Therefore, the base layer 3 is made of at least one metal layer made of any one of Ti, Ta, W, Ni, Co, and Nb, or an alloy of two or more of these metals.

[0029] If the underlayer 3 is thinner than 100 nm, the gold layer 4 cannot be completely covered with the coating film 7, resulting in via etching abnormalities. On the other hand, if the underlayer 3 is thicker than 500 nm, peeling or cracking occurs due to film stress. Therefore, the film thickness of the underlayer 3 (the total film thickness when the underlayer 3 has a laminated structure of multiple metal layers) is set to 100 nm or more and 500 nm or less.

[0030] If the gold layer 4 is thinner than 5 nm, the surface coating is unstable and some areas are not covered with Au, exposing the underlayer 3 and resulting in areas where electroless Ni plating does not grow. On the other hand, if the gold layer 4 is thicker than 20 nm, the gold layer 4 cannot be completely covered with the coating film 7, resulting in via etching abnormalities. Therefore, the thickness of the gold layer 4 is set to 5 nm or more and 20 nm or less.

[0031] When the semiconductor substrate 1 is a SiC substrate or a GaN substrate, SF ６ Gas (SF ６ + Ar + O ２ Fluorine-based gases such as chlorine-based gases (Cl ２ +BCl ３ Although fluorine-based gases can etch Au to some extent, the chemical reactivity of fluorine-based gases decreases when Au is mixed in, so the suppression of via etching abnormalities according to this embodiment is effective. Fluorine-based gases have the advantage of being selective to the GaN epitaxial layer formed on the surface of the SiC substrate.

[0032] Although the above description has been given of a case where via etching is performed from the back surface side of the substrate, the method of the present disclosure can also be applied to a case where via etching is performed from the front surface side of the substrate to partway through the substrate, and then the back surface side of the substrate is ground.

[0033] REFERENCE SIGNS LIST 1 semiconductor substrate, 3 underlayer, 4 gold layer, 5 resist pattern, 6 plating film, 7 coating film, 8 metal mask, 9 via

Claims

1. A method for manufacturing a semiconductor device, comprising the steps of: forming an underlayer on a semiconductor substrate; forming a gold layer on the underlayer; forming a resist pattern on the gold layer; forming a plating film on parts of the gold layer that are not covered by the resist pattern; etching the gold layer and underlayer exposed by removing the resist pattern by ion milling to form a metal mask from the remaining underlayer, gold layer and plating film; and plasma etching the semiconductor substrate using the metal mask to form a via, wherein the underlayer is at least one metal layer made of any one of Ti, Ta, W, Ni, Co, and Nb, or an alloy of two or more of these metals, the gold layer having a thickness of 20 nm or less, and the underlayer having a thickness of 100 nm or more.

2. The method for manufacturing a semiconductor device according to claim 1, wherein the material of the underlayer is ejected by the ion milling and re-adheres to the sidewalls of the etched gold layer to form a coating film.

3. The method for manufacturing a semiconductor device according to claim 2, wherein the gold layer on the side walls of the openings in the metal mask is completely covered by the coating film and is not exposed.

4. The method for manufacturing a semiconductor device according to any one of claims 1 to 3, characterized in that the minimum width of the opening in the metal mask is 20 μm or less.

5. The method for manufacturing a semiconductor device according to any one of claims 1 to 4, wherein the semiconductor substrate is a SiC substrate or a GaN substrate, and a fluorine-based gas is used when plasma etching the semiconductor substrate.

6. The method for manufacturing a semiconductor device according to any one of claims 1 to 5, wherein the thickness of the underlayer is 500 nm or less.

7. The method for manufacturing a semiconductor device according to any one of claims 1 to 6, wherein the gold layer has a thickness of 5 nm or more.

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