Integrated passive component

Abstract

In the present invention, a capacitor is disposed on one surface of a support substrate, namely the upper surface. A first insulating film that covers the capacitor is disposed on the support substrate. A second insulating film is disposed on the first insulating film. A multilayer wiring layer that includes a plurality of wiring layers and a plurality of third insulating films which are alternately stacked is disposed on the second insulating film. The multilayer wiring layer includes an inductor constituted by conductor patterns in the wiring layers. The weight average molecular weight of the resin forming the second insulating film is greater than the weight average molecular weight of the resin forming the third insulating films.

Description

Integrated Passive Components

[0001] The present invention relates to integrated passive components.

[0002] To achieve high integration in communication modules, integrated passive components that integrate passive elements are used (see Patent Document 1). The integrated passive component includes a support substrate and a capacitor, an inductor, and the like disposed thereon. The capacitor is covered with an insulating film made of an inorganic insulating material. The inductor is formed by a conductor pattern in a multilayer wiring layer disposed on the insulating film that covers the capacitor. The support substrate is made of a ceramic material such as silicon nitride, and the insulating layer of the multilayer wiring layer is made of an insulating resin.

[0003] Japanese Patent Application Laid-Open No. 2021-174803

[0004] Thermal stress caused by the difference between the linear expansion coefficients of the support substrate and inorganic insulating film and the insulating layers constituting the multilayer wiring layer can cause cracks at the interface between the inorganic insulating layer and the multilayer wiring layer. Peeling can also occur at the interface between the inorganic insulating layer and the multilayer wiring layer. In particular, thickening the conductor patterns and insulating layers constituting the multilayer wiring layer to improve electrical characteristics can make cracks and peeling more likely to occur. An object of the present invention is to provide an integrated passive component that is less susceptible to cracks and peeling.

[0005] According to one aspect of the present invention, there is provided an integrated passive component comprising: a support substrate; a capacitor arranged on an upper surface, which is one surface of the support substrate; a first insulating film arranged on the support substrate and covering the capacitor; a second insulating film arranged on the first insulating film; and a multilayer wiring layer including a plurality of wiring layers and a plurality of third insulating films alternately stacked on the second insulating film, wherein the multilayer wiring layer includes an inductor formed of a conductor pattern within the wiring layer, and the weight average molecular weight of a resin forming the second insulating film is greater than the weight average molecular weight of a resin forming the third insulating film.

[0006] According to another aspect of the present invention, there is provided an integrated passive component comprising: a support substrate; a capacitor arranged on an upper surface, which is one surface of the support substrate; a first insulating film arranged on the support substrate and covering the capacitor; a second insulating film arranged on the first insulating film; and a multilayer wiring layer including a plurality of wiring layers and a plurality of third insulating films alternately stacked on the second insulating film, wherein the multilayer wiring layer includes an inductor formed of a conductor pattern in the wiring layer, and the breaking elongation of a resin forming the second insulating film is greater than the breaking elongation of a resin forming the third insulating film.

[0007] The second insulating film, which has a relatively large weight-average molecular weight, has higher toughness than the third insulating film, which has a relatively small weight-average molecular weight. Therefore, cracks and peeling are less likely to occur at the interface between the first insulating film and the second insulating film. Furthermore, by adopting a configuration in which the fracture elongation of the resin forming the second insulating film is greater than the fracture elongation of the resin forming the third insulating film, cracks and peeling are less likely to occur at the interface between the first insulating film and the second insulating film.

[0008] FIG. 1 is a cross-sectional view of an integrated passive component according to a first embodiment. FIG. 2A is a diagram showing the positional relationship of components of an integrated passive component according to a second embodiment in a plan view, and FIG. 2B is an equivalent circuit diagram of the integrated passive component according to the second embodiment. FIG. 3A is a diagram showing the positional relationship between the conductor pattern of the lower electrode layer and the conductor pattern of the upper electrode layer in a plan view. FIG. 3B is a diagram showing the positional relationship between the conductor pattern of the upper electrode layer and the conductor pattern of the first wiring layer in a plan view. FIG. 3C is a diagram showing the positional relationship between the conductor pattern of the first wiring layer and the conductor pattern of the second wiring layer in a plan view. FIG. 4A is a diagram showing the positional relationship between the conductor pattern of the second wiring layer and the conductor pattern of the third wiring layer in a plan view. FIG. 4B is a diagram showing the positional relationship between the conductor pattern of the third wiring layer and multiple external connection terminals in a plan view. FIG. 5 is a cross-sectional view taken along dashed line 5-5 in FIG. 2A. FIGS. 6A, 6B, and 6C are cross-sectional views of an integrated passive component according to the second embodiment during manufacturing. 7A and 7B are cross-sectional views of an integrated passive component according to a second embodiment at an intermediate stage of manufacture. FIG. 8A is an equivalent circuit diagram of an integrated passive component according to a third embodiment, and FIG. 8B is a diagram showing the positional relationship in a plan view of conductor patterns constituting the integrated passive component according to the third embodiment. FIG. 9A is a graph showing the insertion loss (S ２１ 9B is a graph showing the simulation results of the insertion loss S ２１ 10 is a graph showing the relationship between the peak value of the second insulating film and the thickness of the second insulating film.

[0009] First Embodiment An integrated passive component according to a first embodiment will be described with reference to Figure 1. Figure 1 is a cross-sectional view of the integrated passive component according to the first embodiment. The integrated passive component according to the first embodiment includes a support substrate 10, a capacitor C disposed on one surface (hereinafter referred to as the upper surface) of the support substrate 10, a first insulating film 20, a second insulating film 30, and a multilayer wiring layer 40. The capacitor C includes a lower electrode 21, an upper electrode 22, and a dielectric film 23 disposed between the lower electrode 21 and the upper electrode 22.

[0010] The first insulating film 20 is disposed on the support substrate 10 and covers the capacitor C. The second insulating film 30 is disposed on the first insulating film 20, and the multilayer wiring layer 40 is disposed on the second insulating film 30. The multilayer wiring layer 40 includes a plurality of wiring layers and a plurality of third insulating films 41 that are alternately stacked. Each of the plurality of wiring layers includes a plurality of conductor patterns 42. Some of the plurality of conductor patterns 42 form an inductor L. A terminal 44 for external connection is disposed on the multilayer wiring layer 40. The terminal 44 is connected to the upper electrode 22 of the capacitor C via the plurality of conductor patterns 42 in the multilayer wiring layer 40.

[0011] The "third insulating film 41" is present, for example, between the conductor patterns 42 of two vertically adjacent wiring layers, and in regions where no conductor patterns 42 are arranged, the two vertically adjacent third insulating films 41 are in contact with each other. In regions where the two third insulating films 41 are in contact with each other, the interface between them may not be clearly observed. The "third insulating film 41" also includes an insulating layer that covers the surfaces of the conductor patterns 42 of the uppermost wiring layer and the third insulating film 41 that forms the underlying layer thereof, and an insulating layer between the conductor patterns 42 of the lowermost wiring layer and the first insulating film 20.

[0012] Next, the materials of each component will be described. The support substrate 10, the dielectric film 23 of the capacitor C, and the first insulating film 20 are formed of inorganic insulating materials containing primarily silicon and nitrogen as constituent elements. For example, silicon nitride (SiN) ceramic is used for the support substrate 10, and amorphous silicon nitride is used for the dielectric film 23 and the first insulating film 20 of the capacitor C. Here, "the inorganic insulating material contains primarily a specific element as a constituent element" means that the inorganic insulating material may contain elements other than the specific element to the extent that they do not significantly affect the linear expansion coefficient and volume resistivity of the material.

[0013] For example, when the molar concentration of an element contained as a constituent element in an inorganic insulating material is 50 mol% or more, it can be said that "the inorganic insulating material mainly contains that element as a constituent element." The "element contained as a constituent element" may be multiple elements, such as SiN. In this case, when the sum of the molar concentrations of the multiple elements is 50 mol% or more, it can be said that "the inorganic insulating material mainly contains the multiple elements as constituent elements." For example, when the inorganic insulating material is SiN, if the sum of the molar concentration of Si and the molar concentration of N is 50 mol% or more, it can be said that the inorganic insulating material mainly contains Si and N as constituent elements. For example, in silicon oxynitride (SiON) obtained by adding oxygen to silicon nitride, if the sum of the molar concentrations of Si, O, and N is 50 mol% or more, it can be said that the inorganic insulating material mainly contains Si, O, and N. Similarly, in silicon carbonitride (SiCN), which is silicon nitride containing carbon, when the total molar concentration of Si, C, and N is 50 mol % or more, this inorganic insulating material can be said to contain primarily Si, C, and N. Any inorganic insulating material can be said to contain at least Si and N primarily.

[0014] Alternatively, an SiN ceramic substrate having an amorphous SiN film disposed thereon may be used as the support substrate 10. In this case, the lower electrode 21 of the capacitor C is disposed on the amorphous SiN film.

[0015] The second insulating film 30 and the third insulating film 41 are made of an insulating resin, such as an epoxy-based, polyimide-based, or benzocyclobutene-based resin. The second insulating film 30 and the third insulating film 41 may be made of a resin containing a photosensitive material. The lower electrode 21, upper electrode 22, and conductor pattern 42 of the capacitor C are made of a metal material, and particularly preferably, a metal material with high conductivity such as Au, Al, Cu, or a metal material mainly composed of Cu. The conductor pattern 42 is preferably made of Cu or a metal material mainly composed of Cu, which can be easily formed into a thick film.

[0016] The weight-average molecular weight of the resin used for the second insulating film 30 is larger than the weight-average molecular weight of the resin used for the plurality of third insulating films 41 in the multilayer wiring layer 40. The second insulating film 30 and the third insulating film 41 can be formed by, for example, vacuum lamination, spin coating, or the like. The second insulating film 30 and the third insulating film 41 having different weight-average molecular weights can be formed by appropriately selecting a semi-cured film used in the vacuum lamination method or a coating agent used in the spin coating method.

[0017] Next, the advantages of the first embodiment will be described. Resins with a relatively large weight-average molecular weight are characterized by higher toughness (elongation at break) than resins with a relatively small weight-average molecular weight. That is, the toughness of the second insulating film 30 is higher than that of the third insulating film 41. Therefore, when stress is applied between the support substrate 10 and the multilayer wiring layer 40, the second insulating film 30 can expand and contract significantly without breaking its molecular chains. The stress-induced energy required for resin breakdown (peeling) is consumed by the expansion and contraction deformation of the second insulating film 30. As a result, cracks and peeling due to differences in the linear expansion coefficients of the support substrate 10 and the third insulating film 41 can be suppressed. This improves the reliability of integrated passive components.

[0018] Generally, the linear expansion coefficient of resin is higher than that of inorganic materials such as SiN ceramic. By incorporating an inorganic filler into the second insulating film 30 and the third insulating film 41 and bringing the linear expansion coefficients of the second insulating film 30 and the third insulating film 41 closer to that of the support substrate 10, it is possible to suppress the occurrence of cracks and peeling due to thermal stress. However, using a filler-containing resin for the second insulating film 30 and the third insulating film 41 makes it difficult to perform microfabrication. As a result, it is difficult to achieve miniaturization of integrated passive components.

[0019] In the first embodiment, it is possible to miniaturize the integrated passive components because there is no need to use a filler-containing resin for the second insulating film 30 and the third insulating film 41. Note that filler may be contained to the extent that it does not impair micro-processability.

[0020] Furthermore, in order to prevent cracks and peeling due to thermal stress, it is preferable to minimize the difference in linear expansion coefficient between the materials on both sides of the interface. In the first embodiment, the linear expansion coefficients of the support substrate 10 and the first insulating film 20, which are made of an inorganic insulating material, are smaller than the linear expansion coefficient of the third insulating film 41. In order to avoid an increase in the difference in linear expansion coefficient at the interface between different materials, it is preferable to use a resin material for the second insulating film 30 that has a linear expansion coefficient equal to or lower than that of the third insulating film 41.

[0021] Next, we will explain an example of a method for measuring the weight-average molecular weight of an insulating resin material. First, all parts of the integrated passive component other than the insulating film to be measured are removed, and the insulating film to be measured is extracted as a single film or powder. The weight-average molecular weight of the extracted film or powder can be measured using gel permeation chromatography or mass spectrometry.

[0022] Next, a modification of the first embodiment will be described. In the first embodiment, the magnitude relationship between the weight-average molecular weights of the second insulating film 30 and the third insulating film 41 is limited. However, the magnitude relationship between the crosslink densities may also be limited. For example, if a resin having a lower crosslink density than that of the third insulating film 41 is used as the second insulating film 30, the toughness of the second insulating film 30 will generally be higher than that of the third insulating film 41. Therefore, similar to the first embodiment, the excellent effect of increasing the reliability of the integrated passive component can be obtained.

[0023] Second Embodiment Next, an integrated passive component according to a second embodiment will be described with reference to Figures 2A to 7B. Below, a description of the components common to the integrated passive component shown in Figure 1 will be omitted.

[0024] 2A is a diagram showing the positional relationship of the components of an integrated passive component according to a second embodiment in a plan view, and FIG. 2B is an equivalent circuit diagram of the integrated passive component according to the second embodiment. The integrated passive component according to the second embodiment has a capacitor C, an inductor L, an input terminal In, an output terminal Out, a ground terminal GND, and a dummy terminal DMY, which are provided on a single insulating substrate.

[0025] On a substrate, multiple conductor layers and multiple insulating films that insulate adjacent conductor layers from one another are alternately stacked. In the second embodiment, five conductor layers are stacked, and these conductor layers are referred to, in order from the substrate side, as a lower electrode layer, an upper electrode layer, a first wiring layer, a second wiring layer, and a third wiring layer. Multiple external connection terminals, such as an input terminal In, an output terminal Out, and a ground terminal GND, are arranged on the top insulating film. In FIG. 2A, hatching with different shading and orientation is applied to each conductor layer. The shape and positional relationship of the conductor patterns arranged on each conductor layer will be described in detail later with reference to FIGS. 3A to 4B.

[0026] 2B, an inductor L is connected between the input terminal In and the output terminal Out, and a capacitor C is connected between the input terminal In and the ground terminal GND. The integrated passive component according to the second embodiment functions as a low-pass filter.

[0027] The configuration of the conductor patterns of two vertically adjacent conductor layers will be described with reference to Figures 3A to 4B. In Figures 3A to 4B, the conductor patterns of the relatively lower wiring layer are indicated by dashed lines.

[0028] 3A is a diagram showing the positional relationship between the conductor patterns on the lower electrode layer and the conductor patterns on the upper electrode layer in a plan view. A lower electrode 21 of a capacitor C is arranged on the lower electrode layer. An upper electrode 22 of the capacitor C and another conductor pattern 24 are arranged on the upper electrode layer. In a plan view, the upper electrode 22 and the conductor pattern 24 overlap the lower electrode 21. The conductor pattern 24 is connected to the lower electrode 21 through a via hole H1 provided in the insulating film.

[0029] FIG. 3B illustrates the positional relationship between the conductor patterns of the upper electrode layer and the first wiring layer in a plan view. Conductor patterns 42A1, 42B1, and 42C1 are arranged on the first wiring layer. Conductor pattern 42C1 extends approximately once around the periphery of a rounded square located at a position that does not overlap capacitor C in a plan view. Conductor pattern 42A1 extends from one end of conductor pattern 42C1 toward conductor pattern 24 of the upper electrode layer and passes through a position where it overlaps with conductor pattern 24. Conductor pattern 42C1 forms part of inductor L. Conductor pattern 42A1 is connected to conductor pattern 24 of the upper electrode layer through via hole H2. That is, conductor patterns 42A1 and 42C1 are connected to the lower electrode 21 ( FIG. 3A ) of capacitor C via conductor pattern 24.

[0030] One end of the conductor pattern 42B1 overlaps the upper electrode 22 of the capacitor C. The conductor pattern 42B1 is connected to the upper electrode 22 through a via hole H3.

[0031] 3C is a diagram showing the positional relationship between the conductor patterns of the first wiring layer and the conductor patterns of the second wiring layer in a plan view. The second wiring layer includes a conductor pattern 42C2 constituting part of the inductor L, as well as other conductor patterns 42A2 and 42B2. The conductor pattern 42C2 is composed of a portion that substantially overlaps the conductor pattern 42C1 of the first wiring layer and a portion that is disposed inside the overlapping portion and runs parallel to the outer portion, completing a substantial circle. That is, the conductor pattern 42C2 has a spiral shape with approximately two turns. The outer peripheral end of the conductor pattern 42C2 is connected to one end of the conductor pattern 42C1 of the first wiring layer through a via hole H4.

[0032] The conductor pattern 42A2 is connected to an end of the conductor pattern 42A1 in the first wiring layer through a via hole H5, and the conductor pattern 42B2 is connected to an end of the conductor pattern 42B1 in the first wiring layer through a via hole H6.

[0033] 4A is a diagram showing the positional relationship between the conductor patterns of the second wiring layer and the conductor patterns of the third wiring layer in a plan view. A conductor pattern 42C3 constituting part of the inductor L, as well as other conductor patterns 42A3, 42B3, and 42D3, are arranged on the third wiring layer. The conductor pattern 42C3 has a spiral shape and is arranged to overlap the conductor patterns on the inner and outer peripheries of the conductor pattern 42C2 of the second wiring layer. The inner end of the conductor pattern 42C3 is connected to the inner end of the conductor pattern 42C2 of the second wiring layer through a via hole H7. The outer end of the conductor pattern 42C3 is an inner-layer land having a circular planar shape.

[0034] The conductor patterns 42A3 and 42B3 are connected to the conductor patterns 42A2 and 42B2 on the second wiring layer through via holes H8 and H9, respectively. The ends of the conductor patterns 42A3 and 42B3 are each formed as inner-layer lands having a circular planar shape. Furthermore, an isolated conductor pattern 42D3 having a circular planar shape that is not connected to other conductor patterns on the third wiring layer below is arranged on the third wiring layer.

[0035] 4B is a diagram showing the positional relationship between the conductor pattern of the third wiring layer and multiple external connection terminals in a plan view. The multiple external connection terminals include an input terminal In, an output terminal Out, a ground terminal GND, and a dummy terminal DMY. The output terminal Out is connected to the inner-layer land portion of the conductor pattern 42C3 through a via hole H10. The input terminal In is connected to the inner-layer land portion of the conductor pattern 42A3 through a via hole H11. The ground terminal GND is connected to the inner-layer land portion of the conductor pattern 42B3 through a via hole H12. The dummy terminal DMY is connected to the conductor pattern 42D3 through a via hole H13.

[0036] That is, the conductor patterns 42C1, 42C2, and 42C3 form an inductor L whose coil axis direction is the thickness direction of the substrate. One end of this inductor L is connected to the lower electrode 21 (FIG. 3A) of the capacitor C via the conductor pattern 24 (FIGS. 3A and 3B). The other end of the inductor L is connected to the output terminal Out (FIG. 4B). The upper electrode 22 (FIG. 3A) of the capacitor C is connected to the ground terminal GND (FIG. 4B) via the conductor patterns 42B1, 42B2, and 42B3 (FIGS. 3B, 3C, and 4A). In a plan view, the inductor L (FIG. 2A) is positioned so as not to overlap with the capacitor C (FIG. 2A).

[0037] 5 is a cross-sectional view taken along dashed line 5-5 in FIG. 2A. The support substrate 10 is composed of a base substrate 10A and a base insulating film 10B covering the upper surface thereof. The base substrate 10A may be made of, for example, single crystal silicon, ceramics, aluminum nitride, glass, or the like. A substrate obtained by oxidizing the surface of a single crystal silicon substrate may also be used. The base insulating film 10B may be made of, for example, an insulating material containing primarily Si and O as constituent elements, or an insulating material containing primarily Si and N as constituent elements.

[0038] A lower electrode 21 is disposed on a portion of the surface (hereinafter referred to as the upper surface) of the underlying insulating film 10B facing away from the underlying substrate 10A. A dielectric film 23 is disposed on the upper surface of the lower electrode 21, and an upper electrode 22 and a conductor pattern 24 are disposed thereon. The conductor pattern 24 is connected to the lower electrode 21 through a via hole H1 provided in the dielectric film 23. The materials used for the lower electrode 21, upper electrode 22, and conductor pattern 24 are the same as those used for the lower electrode 21 and upper electrode 22 of the integrated passive component according to the first embodiment ( FIG. 1 ). The material used for the dielectric film 23 is the same as that used for the dielectric film 23 of the capacitor C of the integrated passive component according to the first embodiment ( FIG. 1 ).

[0039] A first insulating film 20 made of an inorganic insulating material is disposed on the upper surface of the support substrate 10 so as to cover the capacitor C made of the lower electrode 21, upper electrode 22, and dielectric film 23, and the conductor pattern 24.

[0040] A second insulating film 30 made of an insulating resin is disposed on the first insulating film 20. A multilayer wiring layer 40 is disposed on the second insulating film 30. The multilayer wiring layer 40 includes a first wiring layer, a second wiring layer, and a third wiring layer stacked in this order from the second insulating film 30, a third insulating film 41 that insulates between these wiring layers, and a third insulating film 41 that covers the third wiring layer. The materials used for the second insulating film 30 and the third insulating film 41 are the same as the materials used for the second insulating film 30 and the third insulating film 41 of the integrated passive component according to the first embodiment ( FIG. 1 ).

[0041] Conductor patterns 42A1, 42B1, and 42C1 are arranged on the first wiring layer. The conductor pattern 42A1 is connected to the conductor pattern 24 through a via hole H2 provided in the second insulating film 30 and the first insulating film 20. The conductor pattern 42B1 is connected to the upper electrode 22 through a via hole H3 provided in the second insulating film 30 and the first insulating film 20. As shown in FIG. 3B , the conductor pattern 42C1 is continuous with the conductor pattern 42A1 at a location other than the cross section shown in FIG. 5 .

[0042] Conductor patterns 42A2 and 42C2 are arranged in the second wiring layer. Conductor pattern 42A2 is connected to conductor pattern 42A1 through a via hole H5 provided in the third insulating film 41 of the first layer. Conductor patterns 42A3 and 42C3 are arranged in the third wiring layer. Conductor pattern 42A3 is connected to conductor pattern 42A2 through a via hole H8 provided in the third insulating film 41 of the second layer.

[0043] An input terminal In is disposed on the third insulating film 41. The input terminal In is connected to a conductor pattern 42A3 through a via hole H11 provided in the third insulating film 41. The material used for the conductor pattern in the multilayer wiring layer 40 is the same as the material used for the conductor pattern 42 of the integrated passive component according to the first embodiment ( FIG. 1 ).

[0044] Next, a method for manufacturing an integrated passive component according to a second embodiment will be described with reference to Figures 6A to 7B, which are cross-sectional views of an integrated passive component according to the second embodiment at intermediate stages in its manufacture.

[0045] As shown in FIG. 6A , an insulating base layer 10B made of an inorganic insulating material such as amorphous SiN is formed on the upper surface of an underlying substrate 10A made of an inorganic insulating material such as SiN ceramic. The insulating base layer 10B can be formed by, for example, sputtering, plasma-enhanced chemical vapor deposition (plasma CVD), or metal-organic chemical vapor deposition (MOCVD). Through these steps, a support substrate 10 is formed, consisting of the underlying substrate 10A and the insulating base layer 10B. A lower electrode 21 is formed on the upper surface of the support substrate 10. The lower electrode 21 can be formed by, for example, vacuum deposition or lift-off.

[0046] As shown in FIG. 6B , a dielectric film 23 having a via hole H1 formed therein is formed on the lower electrode 21. The dielectric film 23 may be made of, for example, amorphous SiN. The dielectric film 23 may be formed by, for example, sputtering, plasma CVD, MOCVD, or the like. The dielectric film 23 may be patterned and the via hole H1 may be formed by, for example, dry etching. In FIG. 6B , the dielectric film 23 is left only on the lower electrode 21 and not on the upper surface of the support substrate 10; however, the dielectric film 23 may also be left on the upper surface of the support substrate 10.

[0047] 6C, an upper electrode 22 and a conductor pattern 24 are formed on the dielectric film 23. The methods for forming and patterning the upper electrode 22 and the conductor pattern 24 are the same as those for forming and patterning the lower electrode 21. Through the steps up to this point, a capacitor C including the lower electrode 21, the upper electrode 22, and the dielectric film 23 is formed.

[0048] A first insulating film 20 is formed so as to cover the upper surface of the support substrate 10 and the capacitor C, and then the via holes H2 and H3 are formed. The first insulating film 20 can be formed by, for example, sputtering, plasma CVD, MOCVD, etc. The via holes H2 and H3 can be formed by, for example, dry etching.

[0049] As shown in FIG. 7A , a second insulating film 30 is formed on the first insulating film 20. Vacuum lamination, spin coating, or the like can be used to form the second insulating film 30. Then, via holes H2 and H3 are formed through the second insulating film 30 at positions that overlap the via holes H2 and H3 formed in the first insulating film 20 in a planar view. When a resin containing a photosensitive material is used as the second insulating film 30, the via holes H2 and H3 can be formed by exposure and development. When a resin not containing a photosensitive material is used as the second insulating film 30, the via holes H2 and H3 can be formed by irradiating with an ultraviolet laser.

[0050] As shown in FIG. 7B , conductor patterns 42A1, 42B1, and 42C1 are formed on the second insulating film 30. The conductor patterns 42A1, 42B1, and 42C1 can be formed, for example, by a semi-additive method. The conductor pattern 42A1 is connected to the conductor pattern 24 through a via hole H2, and the conductor pattern 42B1 is connected to the upper electrode 22 through a via hole H3. Thereafter, as shown in FIG. 5 , the third insulating film 41 and the conductor patterns of the multilayer wiring layer 40 are alternately stacked on the second insulating film 30.

[0051] Next, an example of the dimensions of each component of the integrated passive component according to the second embodiment will be described. The thickness of the support substrate 10 is 100 μm or less. The thickness of the capacitor C is approximately 1 μm. The thickness of the first insulating film 20 is 1 μm or more. The thickness of the second insulating film 30 is 1 μm or more. The thickness of each of the multiple third insulating films 41 is 10 μm or more. The thickness H of the multiple conductor patterns in the multilayer wiring layer 40 is 5 μm or more. The height of the input terminal In for external connection, etc. is approximately 70 μm.

[0052] The thickness H (FIG. 5) of each of the conductor patterns 42C1, 42C2, and 42C3 constituting the inductor L is greater than the thickness of each of the lower electrode 21 and upper electrode 22 of the capacitor C. Furthermore, the spacing G (FIG. 5) in the thickness direction of the conductor patterns in the multilayer wiring layer 40 is equal to or greater than the thickness H of the conductor patterns.

[0053] Next, the advantageous effects of the second embodiment will be described. As in the first embodiment, the second insulating film 30 in the second embodiment uses a highly tough resin material, which can suppress the occurrence of cracks and peeling. Furthermore, the conductor patterns 42C1, 42C2, and 42C3 that make up the inductor L are arranged across multiple wiring layers of the multilayer wiring layer 40, which increases the inductance value that can be designed. This allows for a high-performance, compact integrated passive component to be obtained.

[0054] In the second embodiment, the thickness of each of the conductor patterns 42C1, 42C2, and 42C3 constituting the inductor L is greater than the thickness of each of the lower electrode 21 and upper electrode 22 of the capacitor C. By making each of the conductor patterns 42C1, 42C2, and 42C3 constituting the inductor L relatively thick, the parasitic resistance of the inductor L can be reduced. Furthermore, by making the thickness of the lower electrode 21 and upper electrode 22 of the capacitor C relatively thin, the dimensional accuracy of the lower electrode 21 and upper electrode 22 can be improved. This can increase the accuracy of the capacitance value of the capacitor C.

[0055] Furthermore, in the second embodiment, the spacing G between the conductor patterns in the multilayer wiring layer 40 in the thickness direction is equal to or greater than the thickness H of the conductor patterns. This reduces the parasitic capacitance between conductor patterns that overlap in the thickness direction, thereby improving the performance of the integrated passive components.

[0056] Furthermore, by using Cu or a metal material containing Cu as a main component for the conductor patterns in the multilayer wiring layer 40, it is easy to increase the thickness of the conductor patterns, and it is possible to reduce the parasitic resistance of the conductor patterns.

[0057] [Third Practical Example] Next, an integrated passive component according to a third embodiment will be described with reference to Figures 8A, 8B, 9A, and 9B. Hereinafter, a description of the components common to the integrated passive component according to the second embodiment described with reference to Figures 2A to 7B will be omitted.

[0058] 8A is an equivalent circuit diagram of an integrated passive component according to the third embodiment. In the second embodiment (FIG. 2B), the inductor L and the capacitor C form a low-pass filter, but in the third embodiment, an LC parallel resonant circuit is formed. The LC parallel resonant circuit is inserted between the input terminal In and the output terminal Out.

[0059] 8B is a diagram showing the positional relationship in a plan view of the conductor patterns constituting the integrated passive component according to the third embodiment. The conductor patterns in the first wiring layer are represented by thick solid lines, the conductor patterns in the second wiring layer are represented by relatively dark hatching slanting upward to the right, and the conductor patterns in the third wiring layer are represented by relatively light hatching slanting downward to the right. One end of the conductor pattern W1 in the first wiring layer is connected to the input terminal In, and the other end is connected to one electrode of the capacitor C. One end of the conductor pattern W4 in the first wiring layer is connected to the other electrode of the capacitor C, and the other end is connected to the output terminal Out.

[0060] The conductor pattern W2 of the second wiring layer and the conductor pattern W3 of the third wiring layer form an inductor L. The conductor pattern W2 is arranged along the periphery of a square, and the conductor pattern W3 is arranged along three sides of the square along which the conductor pattern W2 extends. One end of the conductor pattern W2 is connected to the conductor pattern W1 at a connection point P1. The other end of the conductor pattern W2 is connected to one end of the conductor pattern W3 at a connection point P2. The other end of the conductor pattern W3 is connected to the conductor pattern W4 at a connection point P3.

[0061] In a plan view, the capacitor C is disposed at a position overlapping the conductor pattern W2. The conductor patterns W1 and W4 are disposed so as to overlap one side of the square along which the conductor pattern W2 extends.

[0062] FIG. 9A shows the insertion loss (S ２１ ) is a graph showing the simulation results. The horizontal axis represents frequency in units of GHz, and the vertical axis represents insertion loss in units of dB. Note that insertion loss is represented by a negative value, and S ２１The larger the absolute value of , the larger the insertion loss. The numerical values ​​attached to each solid line in Fig. 9A represent the thickness of the second insulating film 30 (Fig. 5). The simulation conditions other than the thickness of the second insulating film 30 are the same.

[0063] FIG. 9B shows the insertion loss S ２１ 1 is a graph showing the relationship between the peak value of the second insulating film 30 and the thickness of the second insulating film 30. The horizontal axis represents the thickness of the second insulating film 30 in units of μm, and the vertical axis represents the insertion loss S ２１ The peak value is expressed in units of dB.

[0064] 9A, the resonance frequency increases as the thickness of the second insulating film 30 increases. As shown in FIGS. 9A and 9B, the insertion loss S ２１ It can be seen that the peak value of the insertion loss S ２１ It can be seen that the increase in the peak value of

[0065] Insertion loss S ２１ The peak value of the insertion loss S can be used to determine the approximate Q value (loss index) of the LC parallel resonant circuit. ２１ The more negative the peak value of Q, the larger the Q value. When the thickness of the second insulating film 30 is 10 μm or more, the electrical characteristics of the integrated passive component can be almost optimized. This is because, when the second insulating film 30 is thicker, the distance in the thickness direction between the capacitor C and the conductor pattern in the multilayer wiring layer 40 increases, and the parasitic capacitance decreases.

[0066] Next, the advantageous effects of the third embodiment will be described. In the third embodiment, the capacitor C and the inductor L are arranged so as to overlap each other in a plan view, thereby enabling the integrated passive component to be miniaturized. Furthermore, even if the capacitor C and the inductor L are arranged so as to overlap each other in a plan view, the deterioration of the electrical characteristics of the integrated passive component is suppressed by setting the thickness of the second insulating film 30 to 10 μm or more.

[0067] If the thickness of the second insulating film 30 is made too thick, the parasitic inductance of the conductor patterns in the via holes H2 and H3 (FIG. 5) provided in the second insulating film 30 increases. In order to suppress the increase in parasitic inductance, it is preferable to set the thickness of the second insulating film 30 to 20 μm or less.

[0068] Each embodiment is merely an example, and it goes without saying that partial substitution or combination of the configurations shown in different embodiments is possible. Similar effects resulting from similar configurations of multiple embodiments will not be mentioned sequentially for each embodiment. Furthermore, the present invention is not limited to the above-described embodiments. For example, it will be obvious to those skilled in the art that various modifications, improvements, combinations, etc. are possible.

[0069] Based on the above-described embodiments described in this specification, the following invention is disclosed: <1> An integrated passive component comprising: a support substrate, a capacitor arranged on an upper surface that is one surface of the support substrate, a first insulating film arranged on the support substrate and covering the capacitor, a second insulating film arranged on the first insulating film, and a multilayer wiring layer including a plurality of wiring layers and a plurality of third insulating films alternately stacked on the second insulating film, the multilayer wiring layer including an inductor formed of a conductor pattern in the wiring layer, and a resin forming the second insulating film having a weight average molecular weight greater than a weight average molecular weight of a resin forming the third insulating film.

[0070] <2> The integrated passive component according to <1>, wherein the second insulating film has a thickness of 10 μm or more.

[0071] <3> The integrated passive component according to <1> or <2>, wherein the conductor pattern constituting the inductor is arranged across a plurality of wiring layers in the multilayer wiring layer.

[0072] <4> The integrated passive component according to <3>, wherein the interval in the thickness direction of the conductor patterns constituting the inductor is equal to or greater than the thickness of the conductor patterns.

[0073] <5> The integrated passive component according to any one of <1> to <4>, wherein the capacitor includes a dielectric film, and an upper electrode and a lower electrode disposed above and below the dielectric film, and the conductor pattern constituting the inductor is thicker than both the upper electrode and the lower electrode.

[0074] <6> The integrated passive component according to any one of <1> to <5>, wherein the conductor pattern constituting the inductor is made of Cu or a metal material containing Cu as a main component.

[0075] <7> An integrated passive component comprising: a support substrate; a capacitor arranged on an upper surface that is one surface of the support substrate; a first insulating film arranged on the support substrate and covering the capacitor; a second insulating film arranged on the first insulating film; and a multilayer wiring layer including a plurality of wiring layers and a plurality of third insulating films alternately stacked on the second insulating film, wherein the multilayer wiring layer includes an inductor constituted by a conductor pattern in the wiring layer, and the fracture elongation of a resin forming the second insulating film is greater than the fracture elongation of a resin forming the third insulating film.

[0076] REFERENCE SIGNS LIST 10 Support substrate 10A Base substrate 10B Base insulating film 20 First insulating film 21 Lower electrode 22 Upper electrode 23 Dielectric film 24 Conductor pattern 30 Second insulating film 40 Multilayer wiring layer 41 Third insulating film 42 Conductor pattern 42A1, 42A2, 42A3 Conductor pattern connected to input terminal 42B1, 42B2, 42B3 Conductor pattern connected to ground 42C1, 42C2, 42C3 Conductor pattern constituting inductor 42D3 Conductor pattern connected to dummy terminal 44 Terminal

Claims

1. An integrated passive component comprising: a support substrate; a capacitor disposed on an upper surface, which is one surface of the support substrate; a first insulating film disposed on the support substrate and covering the capacitor; a second insulating film disposed on the first insulating film; and a multilayer wiring layer including a plurality of wiring layers and a plurality of third insulating films alternately stacked on the second insulating film, the multilayer wiring layer including an inductor formed of a conductor pattern in the wiring layer, and the weight average molecular weight of a resin forming the second insulating film is greater than the weight average molecular weight of a resin forming the third insulating film.

2. An integrated passive component according to claim 1, wherein the thickness of said second insulating film is 10 μm or more.

3. An integrated passive component according to claim 1 or 2, wherein the conductor pattern constituting the inductor is arranged across a plurality of wiring layers within the multilayer wiring layer.

4. An integrated passive component according to claim 3, wherein the spacing in the thickness direction of the conductor patterns constituting the inductor is equal to or greater than the thickness of the conductor patterns.

5. An integrated passive component according to any one of claims 1 to 4, wherein the capacitor includes a dielectric film, and an upper electrode and a lower electrode arranged above and below the dielectric film, and the conductor pattern constituting the inductor is thicker than both the upper electrode and the lower electrode.

6. An integrated passive component according to any one of claims 1 to 5, wherein the conductor pattern constituting the inductor is made of Cu or a metal material containing Cu as a main component.

7. An integrated passive component comprising: a support substrate; a capacitor disposed on an upper surface, which is one surface of the support substrate; a first insulating film disposed on the support substrate and covering the capacitor; a second insulating film disposed on the first insulating film; and a multilayer wiring layer including a plurality of wiring layers and a plurality of third insulating films alternately stacked on the second insulating film, the multilayer wiring layer including an inductor formed of a conductor pattern in the wiring layer; and the fracture elongation of a resin forming the second insulating film is greater than the fracture elongation of a resin forming the third insulating film.

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