Frequency control method for precisely controlling frequency and frequency control device using same

Abstract

The present disclosure provides a frequency control method for controlling the frequency of an AC voltage applied to a load according to a variable resonant frequency of the load. Particularly, the method may comprise: outputting a first control signal for controlling a first AC voltage having a first frequency to be applied to the load during a first period; shifting a wave of the first control signal by a predetermined time so as to assume a wave of a virtual signal corresponding to the first frequency; on the basis of a clock corresponding to a frequency control device, determining a delay time between the wave of the virtual signal and a wave of the output current of an inverter in the first period in at least a partial period in the first period; determining a second frequency on the basis of the first frequency and the delay time; and outputting a second control signal for controlling an AC voltage having the second frequency to be applied to the load during a second period immediately after the first period.

Description

Frequency control method for precisely controlling frequency and frequency control device using the same

[0001] The present disclosure relates to a frequency control method for precisely controlling frequency and a frequency control device using the same, and more particularly, to a frequency control device and a control method thereof that precisely controls the output frequency of an AC voltage according to a change in impedance of a variable load in order to maximize energy transfer efficiency when providing an AC voltage to a variable load whose impedance changes over time, and outputs an AC voltage having a precisely controlled frequency to the load.

[0002] Technologies utilizing plasma are being used in a variety of industrial fields, including semiconductor, display, and medical equipment technologies, as well as environmental technologies such as air, water, and soil purification, and energy technologies such as solar cells and hydrogen energy.

[0003] There are many ways to generate such plasma, including direct current discharges such as corona discharge, glow discharge, and arc discharge, alternating current discharges such as capacitive coupled discharge and inductive coupled discharge, shock waves, and high-energy beams. Among them, the inductive coupling method, which is highly versatile due to its simple structure, is attracting attention.

[0004] Meanwhile, in order to efficiently generate plasma, it is desirable to apply an AC voltage having a frequency identical to or similar to the resonant frequency of the load generating plasma to the load.

[0005] However, the resonant frequency of the load can continuously change depending on plasma generation, making it difficult to control the frequency of the AC voltage applied to the load in real time in response to these frequency changes. Therefore, to ensure stable plasma generation and maintenance, a method is required to precisely control the frequency of the AC voltage applied to the load so that it can track the variable resonant frequency of the load as closely as possible.

[0006] The problem that the present disclosure seeks to solve is to provide a frequency control method for changing the frequency of an AC voltage provided to a load and a device using the same.

[0007] The problem to be solved by the present disclosure is to provide a frequency control method and a device using the same that predicts an output voltage output from an inverter and changes the frequency of an AC voltage provided to a load in real time based on a delay time between the predicted output voltage and the output current of the load.

[0008] The problem to be solved by the present disclosure is to provide a frequency control method and a device using the same for determining how much to change the frequency of the AC voltage when changing the frequency of the AC voltage provided to a load and changing the frequency of the AC voltage accordingly.

[0009] The problem to be solved by the present disclosure is to provide a frequency control method and a device using the same that generates a frequency closest to the frequency of the AC voltage determined to be changed by using a plurality of frequencies when the frequency of the AC voltage determined to be changed cannot be created through the clock of the processor of the frequency control device.

[0010] The problems to be solved by the present disclosure are not limited to the problems described above, and problems not mentioned can be clearly understood by a person having ordinary skill in the technical field corresponding to the present disclosure from this specification and the attached drawings.

[0011] According to the present disclosure, a frequency control device for controlling the frequency of an AC voltage applied to a load according to a variable resonant frequency of the load, comprising: an inverter having at least two switches electrically interposed between a DC power source and terminals electrically connected to the load, and applying the AC voltage to the load through the terminals, wherein the AC voltage has a frequency determined by the operation of the at least two switches; And a controller having a processor and generating a control signal for controlling the operation of the at least two switches based on a clock of the processor; wherein the controller outputs a first control signal for controlling the at least two switches so that a first AC voltage having a first frequency is applied to the load during a first period, shifts a wave of the first control signal by a predetermined time to assume a wave of a virtual signal corresponding to the first frequency, determines a delay time between the wave of the virtual signal and the wave of the output current of the inverter in the first period in at least a portion of the first period based on the clock, determines a second frequency based on (i) the first frequency, (ii) the delay time, and (iii) at least one outputtable frequency that can be determined using the clock, and generates a control signal for controlling the operation of the at least two switches so that an AC voltage having the second frequency is applied to the load during a second period immediately after the first period. It may be characterized by outputting a second control signal that controls the switches.

[0012] At this time, the delay time may be a difference value between a first count value counted according to the clock for a first time length from a rising edge of the wave of the virtual signal to a falling edge of the wave of the virtual signal that first appears after the rising edge, and a second count value counted according to the clock for a second time length from the rising edge to a falling edge of the wave of the output current that first appears after the rising edge.

[0013] Additionally, the second frequency is increased from the first frequency when the delay time exceeds the first value, decreased from the first frequency when the delay time is less than the second value, and is the same as the first frequency when the delay time is a value between the first value and the second value, but the first value and the second value may be the same or different.

[0014] Additionally, the predetermined time may be equal to the time difference between a first time point at which the wave of the first control signal is input to the inverter and a second time point at which the wave of the first control signal is expected to be output from the inverter.

[0015] Additionally, the predetermined time may be greater than or less than the time difference between a first time point at which the wave of the first control signal is input to the inverter and a second time point at which the wave of the first control signal is expected to be output from the inverter.

[0016] Additionally, the controller may determine the second frequency based on a difference value between the first frequency and a frequency adjacent to the first frequency among the at least one outputtable frequency multiplied by a factor based on the delay time.

[0017] Additionally, the controller can determine the delay time based on an average value of the last N delay times (N is a natural number) among the delay times between the wave of the virtual signal and the wave of the output current that can be obtained during the first section.

[0018] In addition, the controller may determine difference values ​​between each of a plurality of outputtable frequencies closest to the second frequency among the at least one outputtable frequency and the second frequency when the second frequency is not included in the at least one outputtable frequency, and output a plurality of third control signals corresponding to each of the plurality of outputtable frequencies instead of the second control signal according to the number of times each of the plurality of outputtable frequencies is output based on the ratio between the difference values ​​during the second section.

[0019] Additionally, the controller can output the plurality of control signals so that the dispersion between the plurality of third control signals is uniform according to the number of outputs of each of the plurality of outputtable frequencies.

[0020] According to an embodiment of the present disclosure, a frequency control method in which a frequency control device controls the frequency of an AC voltage applied to a load according to a variable resonant frequency of the load may include: outputting a first control signal for controlling a first AC voltage having a first frequency to be applied to the load during a first period; shifting a wave of the first control signal by a predetermined time to assume a wave of a virtual signal corresponding to the first frequency; determining a delay time between the wave of the virtual signal and the wave of the output current of the inverter in the first period based on a clock corresponding to the frequency control device in at least a portion of the first period; determining a second frequency based on (i) the first frequency, (ii) the delay time, and (iii) at least one outputtable frequency that can be determined using the clock; and outputting a second control signal for controlling an AC voltage having the second frequency to be applied to the load during a second period immediately after the first period.

[0021] At this time, the delay time may be a difference value between a first count value counted according to the clock for a first time length from the rising edge of the wave of the virtual signal to the falling edge of the wave of the virtual signal that first appears after the rising edge, and a second count value counted according to the clock for a second time length from the rising edge to the falling edge of the wave of the output current that first appears after the rising edge.

[0022] Additionally, the second frequency is increased from the first frequency when the delay time exceeds the first value, decreased from the first frequency when the delay time is less than the second value, and is the same as the first frequency when the delay time is a value between the first value and the second value, but the first value and the second value may be the same or different.

[0023] Additionally, the predetermined time may be equal to the time difference between a first time point at which the wave of the first control signal is input to the inverter and a second time point at which the wave of the first control signal is expected to be output from the inverter.

[0024] Additionally, the predetermined time may be greater than or less than the time difference between a first time point at which the wave of the first control signal is input to the inverter and a second time point at which the wave of the first control signal is expected to be output from the inverter.

[0025] In addition, determining the second frequency may include determining the second frequency based on a difference value between the first frequency and a frequency adjacent to the first frequency among the at least one outputtable frequency multiplied by a factor based on the delay time.

[0026] In addition, determining the delay time may include determining the delay time based on an average value of the last N delay times (N is a natural number) among the delay times between the wave of the virtual signal and the wave of the output current that can be obtained during the first section.

[0027] In addition, if the second frequency is not included in the at least one outputtable frequency: determining difference values ​​between each of a plurality of outputtable frequencies closest to the second frequency among the at least one outputtable frequency and the second frequency; and outputting a plurality of third control signals corresponding to each of the plurality of outputtable frequencies as the second control signal according to the number of times each of the plurality of outputtable frequencies is output, which is determined based on the ratio between the difference values ​​during the second section.

[0028] In addition, outputting the plurality of third control signals may include outputting the plurality of third control signals so that the dispersion between the plurality of third control signals is uniform according to the number of outputs of each of the plurality of outputtable frequencies.

[0029] According to the present disclosure, plasma generation can be induced and the generated plasma can be maintained by applying an AC voltage having an appropriate frequency to a variable load.

[0030] According to the present disclosure, the frequency of the AC voltage applied to the load can be adjusted to correspond to the resonant frequency of the variable load, thereby stably maintaining the plasma formed from the load.

[0031] According to the present disclosure, the plasma sustaining power can be improved by determining how much to change the frequency of the AC voltage applied to the load and generating a frequency closest to the frequency of the AC voltage using a plurality of frequencies.

[0032] The effects of the present disclosure are not limited to the effects described above, and effects not mentioned can be clearly understood by a person having ordinary skill in the art corresponding to the embodiments described in the present disclosure from this specification and the attached drawings.

[0033] FIG. 1 is a drawing of a plasma system according to one embodiment of the present specification.

[0034] FIG. 2 is a drawing of an RF generator according to one embodiment of the present specification.

[0035] FIG. 3 is a drawing of an RF generator structure for frequency control according to one embodiment of the present specification.

[0036] FIG. 4 is a diagram for explaining the relationship between a signal (of control or output current) and a wave (of control signal or output current) in one embodiment of the present specification.

[0037] FIG. 5 is a diagram for explaining why a delay time occurs according to one embodiment of the present specification.

[0038] FIG. 6 is a drawing for explaining the necessity of a method for controlling frequency according to one embodiment of the present specification.

[0039] FIG. 7 is a diagram illustrating a method for controlling frequency according to one embodiment of the present specification.

[0040] FIG. 8 is a diagram illustrating various examples of assuming a wave of a virtual signal according to one embodiment of the present specification.

[0041] FIG. 9 is a diagram for explaining the process of changing the resonant frequency and the resulting effect in each of various examples assuming a wave of a virtual signal according to one embodiment of the present specification.

[0042] FIG. 10 is a drawing for explaining the discharge stabilization effect when using the capacitive mode, among various examples assuming a wave of a virtual signal according to one embodiment of the present specification.

[0043] FIGS. 11 and 12 are diagrams illustrating a method for generating an AC voltage having a frequency close to the resonant frequency of a variable load according to one embodiment of the present specification.

[0044] FIGS. 13 and 14 are diagrams for explaining the effect of a method for generating an AC voltage having a frequency close to the resonant frequency of the variable load described above according to one embodiment of the present specification.

[0045] FIGS. 15 to 20 are diagrams illustrating a method for generating an AC voltage having a frequency close to the resonant frequency of a variable load according to another embodiment of the present specification.

[0046] FIG. 21 is a diagram illustrating the effect of a method for generating an AC voltage having a frequency close to the resonant frequency of a variable load according to another embodiment of the present specification.

[0047] The above-described purposes, features, and advantages of the present disclosure will become more apparent through the following detailed description taken in conjunction with the accompanying drawings. However, since the present disclosure is susceptible to various modifications and various embodiments, specific embodiments will be illustrated in the drawings and described in detail below.

[0048] Since the embodiments described in this specification are intended to clearly explain the spirit of the present disclosure to a person having ordinary skill in the art to which the present disclosure pertains, the present disclosure is not limited to the embodiments described in this specification, and the scope of the present disclosure should be interpreted to include modified or altered examples that do not depart from the spirit of the present disclosure.

[0049] The drawings attached to this specification are intended to facilitate explanation of the present disclosure, and the shapes depicted in the drawings may be exaggerated as necessary to help understanding of the present disclosure, and thus the present disclosure is not limited by the drawings.

[0050] If a detailed description of a known function or configuration related to this disclosure is deemed to unnecessarily obscure the gist of this disclosure, such detailed description will be omitted. Furthermore, numbers (e.g., "first," "second," etc.) used throughout the description of this specification are merely identifiers used to distinguish one component from another.

[0051] In addition, the suffixes "unit," "module," and "part" used for components in the description below are given or used interchangeably only for the convenience of writing the specification, and do not have distinct meanings or roles in themselves.

[0052]

[0053] According to the present disclosure, a frequency control device for controlling the frequency of an AC voltage applied to a load according to a variable resonant frequency of the load comprises at least two switches electrically interposed between a DC power source and terminals electrically connected to the load, and an inverter for applying the AC voltage to the load through the terminals, wherein the AC voltage has a frequency determined by the operation of the at least two switches; And a controller having a processor and generating a control signal for controlling the operation of the at least two switches based on a clock of the processor; wherein the controller outputs a first control signal for controlling the at least two switches so that a first AC voltage having a first frequency is applied to the load during a first period, shifts a wave of the first control signal by a predetermined time to assume a wave of a virtual signal corresponding to the first frequency, determines a delay time between the wave of the virtual signal and the wave of the output current of the inverter in the first period in at least a portion of the first period based on the clock, determines a second frequency based on (i) the first frequency, (ii) the delay time, and (iii) at least one outputtable frequency that can be determined using the clock, and controls the at least two switches so that an AC voltage having the second frequency is applied to the load during a second period immediately after the first period. It can be characterized by outputting a signal.

[0054] At this time, the delay time may be a difference value between a first count value counted according to the clock for a first time length from a rising edge of the wave of the virtual signal to a falling edge of the wave of the virtual signal that first appears after the rising edge, and a second count value counted according to the clock for a second time length from the rising edge to a falling edge of the wave of the output current that first appears after the rising edge.

[0055]

[0056] Additionally, the second frequency is increased from the first frequency when the delay time exceeds the first value, decreased from the first frequency when the delay time is less than the second value, and is the same as the first frequency when the delay time is a value between the first value and the second value, but the first value and the second value may be the same or different.

[0057] Additionally, the predetermined time may be equal to the time difference between a first time point at which the wave of the first control signal is input to the inverter and a second time point at which the wave of the first control signal is expected to be output from the inverter.

[0058] Additionally, the predetermined time may be greater than or less than the time difference between a first time point at which the wave of the first control signal is input to the inverter and a second time point at which the wave of the first control signal is expected to be output from the inverter.

[0059] Additionally, the controller may determine the second frequency based on a difference value between the first frequency and a frequency adjacent to the first frequency among the at least one outputtable frequency multiplied by a factor based on the delay time.

[0060] Additionally, the controller can determine the delay time based on an average value of the last N delay times (N is a natural number) among the delay times between the wave of the virtual signal and the wave of the output current that can be obtained during the first section.

[0061] In addition, the controller may determine difference values ​​between each of a plurality of outputtable frequencies closest to the second frequency among the at least one outputtable frequency and the second frequency when the second frequency is not included in the at least one outputtable frequency, and output a plurality of third control signals corresponding to each of the plurality of outputtable frequencies instead of the second control signal according to the number of times each of the plurality of outputtable frequencies is output based on the ratio between the difference values ​​during the second section.

[0062] Additionally, the controller can output the plurality of control signals so that the dispersion between the plurality of third control signals is uniform according to the number of outputs of each of the plurality of outputtable frequencies.

[0063] According to the present disclosure, a frequency control method in which a frequency control device controls the frequency of an AC voltage applied to a load according to a variable resonant frequency of the load may include: outputting a first control signal for controlling a first AC voltage having a first frequency to be applied to the load during a first period; shifting a wave of the first control signal by a predetermined time to assume a wave of a virtual signal corresponding to the first frequency; determining a delay time between the wave of the virtual signal and the wave of an output current of the inverter in the first period, based on a clock corresponding to the frequency control device, in at least a portion of the first period; determining a second frequency based on (i) the first frequency, (ii) the delay time, and (iii) at least one outputtable frequency that can be determined using the clock; and outputting a second control signal for controlling an AC voltage having the second frequency to be applied to the load during a second period immediately after the first period.

[0064] At this time, the delay time may be a difference value between a first count value counted according to the clock for a first time length from the rising edge of the wave of the virtual signal to the falling edge of the wave of the virtual signal that first appears after the rising edge, and a second count value counted according to the clock for a second time length from the rising edge to the falling edge of the wave of the output current that first appears after the rising edge.

[0065]

[0066] Additionally, the second frequency is increased from the first frequency when the delay time exceeds the first value, decreased from the first frequency when the delay time is less than the second value, and is the same as the first frequency when the delay time is a value between the first value and the second value, but the first value and the second value may be the same or different.

[0067] Additionally, the predetermined time may be equal to the time difference between a first time point at which the wave of the first control signal is input to the inverter and a second time point at which the wave of the first control signal is expected to be output from the inverter.

[0068] Additionally, the predetermined time may be greater than or less than the time difference between a first time point at which the wave of the first control signal is input to the inverter and a second time point at which the wave of the first control signal is expected to be output from the inverter.

[0069] In addition, determining the second frequency may include determining the second frequency based on a difference value between the first frequency and a frequency adjacent to the first frequency among the at least one outputtable frequency multiplied by a factor based on the delay time.

[0070] In addition, determining the delay time may include determining the delay time based on an average value of the last N delay times (N is a natural number) among the delay times between the wave of the virtual signal and the wave of the output current that can be obtained during the first section.

[0071] In addition, the frequency control method according to the present disclosure may further include: when the second frequency is not included in the at least one outputtable frequency, determining difference values ​​between each of a plurality of outputtable frequencies closest to the second frequency among the at least one outputtable frequency and the second frequency; and outputting a plurality of third control signals corresponding to each of the plurality of outputtable frequencies instead of the second control signal according to the number of times each of the plurality of outputtable frequencies is output, which is determined based on a ratio between the difference values ​​during the second period.

[0072] In addition, outputting the plurality of control signals may include outputting the plurality of third control signals so that the dispersion between the plurality of control signals is uniform according to the number of outputs of each of the plurality of outputtable frequencies.

[0073]

[0074] This specification relates to a frequency control method for precisely controlling frequency and a frequency control device using the same.

[0075] Specifically, according to a frequency control method and a frequency control device using the same according to one embodiment of the present specification, when the frequency control device applies voltage, current or power having a specific frequency to a load, the frequency control device can change the specific frequency periodically or aperiodically.

[0076] Here, the specific frequency refers to the frequency of the voltage, current or power applied to the load, and may refer to the driving frequency.

[0077] Here, the "load" may refer to a component to which power is supplied. For example, the "load" may refer to an electrical component including electrical elements such as resistors, inductors, and capacitors. The load may have a resonant frequency depending on the electrical properties or characteristics of the electrical elements constituting the load. In this case, if the electrical properties or characteristics of the load change over time, the resonant frequency of the load may change over time.

[0078] Hereinafter, for the convenience of explanation, a frequency control method and a frequency control device using the same in a plasma system are described; however, the technical idea of ​​the present specification is not limited thereto, and it goes without saying that the frequency control device can be similarly applied to devices or applications that require AC power to be supplied by periodically or aperiodically adjusting a specific frequency (e.g., driving frequency). For example, in the fields of wireless power transmission and induction heating, the frequency control method described below and a device using the same can be used to control the frequency of AC power to correspond to the variable resonance frequency of a load.

[0079] According to one embodiment of the present disclosure, a frequency control method may be used to apply power to an antenna or antenna structure in a plasma system that generates and maintains plasma.

[0080] Here, plasma is a state (phase) in which a substance is separated into negatively charged electrons and positively charged ions by applying high energy, and can be induced or generated by various methods. Among them, inductively coupled plasma (ICP) is a plasma generated by supplying power to a coil or antenna, etc., thereby forming an induced electric field or a capacitive electric field in a specific space, and can generally be driven by a high-frequency power source such as a radio frequency (RF). Meanwhile, for the convenience of explanation, the following description assumes that the plasma generated by the plasma system is inductively coupled plasma, but the technical idea of ​​the present specification is not limited thereto.

[0081] Here, the antenna is an inductive element or load that forms an electric or magnetic field around it when voltage or current is applied, such as a coil or inductor, and may further mean an equivalent circuit implemented with elements other than inductive elements.

[0082] Here, the antenna structure may mean a structure including at least one antenna. Furthermore, the antenna structure may include at least one capacitive element or load, and may be implemented in a form in which at least one antenna or capacitive element is connected or arranged in a specific manner.

[0083] Meanwhile, the plasma system according to one embodiment of the present specification can be widely used in various fields such as semiconductors, display processing, environment, and energy, and it is to be noted in advance that the plasma generating device described below is not limited to being used in a specific field, and can be commonly used in fields where plasma is utilized.

[0084]

[0085] Hereinafter, a plasma system according to one embodiment of the present specification will be described with reference to FIG. 1.

[0086] FIG. 1 is a drawing of a plasma system (100) according to one embodiment of the present specification. Referring to FIG. 1, the plasma system (100) may include a radio frequency generator (RF) (1000), an antenna structure (2000), and a plasma generation unit (3000). The plasma system (100) may use the RF generator (1000) to supply RF alternating current (or RF alternating current power) to the antenna structure (2000) to induce inductively coupled plasma generation in the plasma generation unit (3000).

[0087] The RF generator (1000) can provide voltage, current, or power to the antenna structure (2000). For example, the RF generator (1000) can apply an AC voltage, current, or power having a specific frequency (e.g., a driving frequency) to the antenna structure (2000). At this time, the frequency of the AC power, the frequency of the AC current, or the frequency of the AC voltage provided to the antenna structure (2000) can be changed as described below.

[0088] Hereinafter, for convenience of explanation, it is described that an AC voltage having a frequency is applied to the antenna structure (2000) or the load, but a person skilled in the art of the present disclosure can easily understand that an AC current or AC electric power having a frequency is applied to the antenna structure (2000) or the load.

[0089] The antenna structure (2000) may include at least one antenna. Alternatively, the antenna structure (2000) may include at least one antenna and at least one capacitor.

[0090] The antenna structure (2000) may be electrically connected to the RF generator (1000). The antenna structure (2000) may be connected in series or in parallel with the RF generator (1000) via a wire or may be connected in series or in parallel via an electrical element.

[0091] The antenna structure (2000) may be physically or electrically connected to the plasma generator (3000). Specific details regarding the connection relationship between the antenna structure (2000) and the plasma generator (3000) will be described later.

[0092] When the antenna structure (2000) receives RF power from the RF generator (1000), a current (i.e., an AC current) whose phase (or direction and magnitude) varies with time flows through the antenna structure (200), and based on this, an induced electric field is generated in the plasma generator (3000), which can induce plasma.

[0093] The antenna structure (2000) may have a resonant frequency determined by the electrical properties and / or characteristics of the components. Here, the resonant frequency is a resonant frequency determined by the inductance and / or capacitance included in the antenna structure (2000), and may be defined as the resonant frequency of the antenna structure (2000).

[0094] Meanwhile, in the present disclosure, the resonant frequency of the load may also mean the resonant frequency of the synthetic impedance in which the influence of the antenna structure (2000) and the plasma is taken into account. For example, while the plasma is formed and maintained by the plasma system (100), the frequency that must be applied from the RF generator (1000) to the antenna structure (2000) in order to minimize the phase difference between the voltage and current applied to the load including the plasma and the antenna structure (2000) may change over time. In this case, it can be viewed that the resonant frequency of the load changes as the synthetic impedance of the plasma generated from the antenna structure (2000) and the plasma generator (3000) (i.e., the synthetic impedance of the load including the antenna structure (2000) and the time-varying plasma) varies over time.

[0095] The plasma generation unit (3000) may include a region or space where plasma generation is induced. Specifically, the plasma generation unit (3000) may refer to a space where plasma can be generated and maintained, such as a chamber or tube.

[0096]

[0097] Below, the configuration and structure of the RF generator (1000) are described with reference to FIG. 2.

[0098] FIG. 2 is a drawing of an RF generator (1000) according to one embodiment of the present specification.

[0099] Referring to FIG. 2, an RF generator (1000) may include an AC power source (1100), a rectifier (1200), an inverter (1300), a controller (1500), and a sensor module (1400). The RF generator (1000) may convert AC supplied from the AC power source (1100) into another AC and supply it to a load. For example, the RF generator (1000) may convert AC used in typical households or industries into another AC having a frequency of several hundred kHz to several tens of MHz and a power of several kW or more and supply it to a load.

[0100] Meanwhile, the RF generator (1000) and the load may be electrically and / or physically connected by one or more nodes. Referring to FIG. 2, two nodes (1610, 1630) on the RF generator (1000) side and two nodes (1710, 1730) on the load side may be electrically and / or physically connected. For example, node (1610) may be connected to node (1710), and node (1630) may be connected to node (1730). For example, node (1610) may be connected to node (1710) with one conductor, and node (1630) and node (1730) may be connected with another conductor.

[0101] Meanwhile, nodes (1610, 1630, 1710, 1730) may also be implemented in the form of terminals. In this case, the terminal of node (1610) and the terminal of node (1710) may be connected by wires, cables, or connectors, and the terminal of node (1630) and the unit price of node (1730) may be connected by wires, cables, or connectors.

[0102] Hereinafter, for convenience of explanation, it is assumed and explained that the RF generator (1000) and the load are connected through nodes (1610, 1630, 1710, 1730). That is, for convenience of explanation, the configurations of the nodes (1610, 1630, 1710, 1730) may be omitted from the drawing or may be omitted from the specific description of the specification, but it can be easily inferred from the above description and a person skilled in the art that the RF generator (1000) and the load are connected through nodes (1610, 1630, 1710, 1730).

[0103] Here, the load may include an antenna structure (2000) and plasma generated by the antenna structure (2000). At this time, the impedance of the load becomes a composite impedance of the impedance of the antenna structure (2000) and the impedance of the plasma, and since the impedance of the plasma varies with time depending on the state of the plasma, the load has a resonant frequency that varies with time depending on the plasma induction.

[0104] The rectifier (1200) can convert the output of the AC power source (1100) into DC. The rectifier (1200) can convert the AC supplied from the AC power source (1100) into DC and apply it to both ends of the inverter (1300) (e.g., input terminals of the inverter (1300)).

[0105] The inverter (1300) can receive direct current from the rectifier (1200) and supply alternating current to the load. For example, the inverter (1300) can receive a control signal from the controller (1500) and provide alternating current to the load using the received control signal. Here, the inverter (1300) can include at least one switching element controlled by the control signal, and the alternating current supplied from the inverter (1300) to the load can have a specific frequency (e.g., a driving frequency) set based on the control signal provided to the inverter (1300) from the controller (1500).

[0106] According to some embodiments disclosed by the present application, the inverter (1300) may be provided as a half bridge type or a full bridge type.

[0107] Meanwhile, a capacitive element may be placed between the rectifier (1200) and the inverter (1300). For example, the RF generator (1000) includes a capacitor connected in parallel with the rectifier (1200) and the inverter (1300), and the capacitor can discharge the AC component of the voltage or current applied to the inverter (1300) to the ground node (GND).

[0108] The controller (1500) can receive sensed data from the sensor module (1400) described below and generate a control signal. For example, the controller (1500) can be implemented to obtain data related to the resonant frequency, such as the current and voltage of the load, from the sensor module (1400) and generate a control signal. Specifically, the controller (1500) can use information about the wave of the output current output from the inverter (1300) obtained from the sensor module (1400) to obtain a phase difference or delay time with respect to the wave of a virtual signal that delays the wave of a control signal for converting a DC voltage applied to the inverter (1300) into an AC voltage by a predetermined time, and generate a control signal for controlling the frequency of the AC voltage output from the inverter (1300) based on the obtained phase difference or delay time. Here, obtaining the phase difference or delay time can mean detecting / sensing the phase difference or delay time. Hereinafter, it is to be noted in advance that in the description of this specification, the acquisition of a phase difference or delay time can be interpreted as the detection / detection of a phase difference or delay time.

[0109] The controller (1500) can be implemented using FPGA (Field Programmable Gate Array) technology. The specific configuration and structure of the controller (1500) will be described later.

[0110] The wave of the output current sensed from the sensor module (1400) may be a signal or data regarding the direction of the current applied to the load (i.e., output from the inverter (1300)) and the time for which the current flows in each direction. That is, the wave of the output current may be a square wave signal as a digitized signal that measures the direction in which the current flows and the time for which the current flows in the corresponding direction. For example, the wave of the output current may be a +I (I is an integer) value output during the first time when the current flows in one direction for a first time, and a -I value output during the second time when the current flows in the other direction for a second time that is the same as or different from the first time. For example, the wave of the output current may be output in a form such as 510 of FIG. 6.

[0111] The sensor module (1400) can obtain data on the resonant frequency of the load or data on the current or power supplied to the load from the controller (1500). Referring again to FIG. 2, the sensor module (1400) can include a current transformer (1410), a filter (1420), and a comparator (1430). The sensor module (1400) can receive a current or voltage signal flowing in the load through the current transformer (1410), convert the current or voltage signal into a current or voltage signal of different magnitude, filter the converted current or voltage signal using the filter (1420), and output the wave of the output current to the controller (1500) through the comparator (1430).

[0112] Here, the current transformer (1410) can be inductively coupled to the wiring between the inverter (1300) and the load and can convert a voltage or current signal applied to the load and provide it to the filter (1420). Specifically, the current transformer (1410) can convert a current flowing in a wire connected to the load into a voltage signal.

[0113] Here, the filter (1420) can remove high-frequency noise from the input current or voltage signal and output it to the comparator (1430). To this end, the filter (1420) can perform high-pass filtering or low-pass filtering.

[0114] Here, the comparator (1430) can obtain information about the wave of the output current. For example, the comparator (1430) can obtain information about the wave of the output current by comparing the voltage signal obtained from the current transformer (1410) or the filter (1420) with a preset value. At this time, the information about the wave of the output current can mean phase data of the current applied to the load (i.e., output from the inverter (1300)) or data about the magnitude and direction of the current.

[0115] At least one of the components included in the above-described sensor module (1400) may be omitted.

[0116] Although not shown in FIG. 2, the RF generator (1000) may include memory.

[0117] Here, the memory can store various types of data. Various types of data can be stored in the memory temporarily or semi-permanently. Examples of the memory may include a hard disk drive (HDD), a solid state drive (SSD), flash memory, read-only memory (ROM), random access memory (RAM), etc. The memory may be provided in a form built into the RF generator (1000) or in a detachable form.

[0118] As described above, the RF generator (1000) can control the frequency of the AC supplied to the load based on data regarding the resonant frequency of the load. In other words, the RF generator (1000) can track the resonant frequency of the load, which changes according to changes in the state of the plasma, control the frequency of the output AC to correspond to the resonant frequency of the load, and output AC having the controlled frequency. This can prevent unnecessary power consumption and improve the durability of the plasma system.

[0119] The RF generator (1000) described above may omit at least one of its components. For example, the RF generator (1000) may not include a sensor module (1400) and may acquire electrical data on a load from an external sensor. For another example, the RF generator (1000) may not include an AC power source (1100) and a rectifier (1200) and may receive direct current or rectified direct current from an external source.

[0120]

[0121] Hereinafter, a frequency control method according to one embodiment of the present specification will be described. An RF generator (1000) can adjust the frequency of an alternating current applied to a load such as an antenna structure (2000) through a frequency control method. Specifically, the RF generator (1000) can detect the resonant frequency of the load including the antenna structure (2000) or the electrical properties such as current and voltage over time to periodically or aperiodically change or set the frequency of the output for forming or maintaining plasma (e.g., the frequency of the output alternating current voltage or the frequency of the output alternating current).

[0122]

[0123] Hereinafter, a method for controlling the frequency of an alternating current applied to a load by a frequency control device will be described with reference to FIGS. 3 to 13.

[0124] FIG. 3 is a drawing of a structure of an RF generator (1000) for frequency control according to one embodiment of the present specification.

[0125] Referring to FIG. 3, the RF generator (1000) may include an inverter (1300), a sensor module (1400), and a controller (1500) including a processor (1510), a current detector (1530), a frequency determination unit (1550), and a control signal output unit (1570). The RF generator (1000) may obtain information on the waves of the output current of the inverter (1300) applied to the load using the sensor module (1400) and transmit the information to the current detector (1530). In addition, the current detector (1530) may transmit the information on the waves of the received output current to the frequency determination unit (1550).

[0126] The inverter (1300) can receive direct current, convert it into alternating current, and supply it to a load. To this end, the inverter (1300) may be provided as a half-bridge type or a full-bridge type. For convenience of explanation, the inverter (1300) is described below as being provided as a full-bridge type, but the technical concept of the present specification is not limited thereto. In other words, the inverter (1300) may also be provided as a half-bridge type.

[0127] The inverter (1300) may include first to fourth switches (S1, S2, S3, S4).

[0128] Here, each of the first to fourth switches (S1, S2, S3, S4) can be turned on or off by receiving a control signal from the controller (1500). At this time, when the first and third switches (S1, S3) are turned on and the second and fourth switches (S2, S4) are turned off, a positive voltage can be applied to the load, and when the first and third switches (S1, S3) are turned off and the second and fourth switches (S2, S4) are turned on, a negative voltage can be applied to the load. In this way, the inverter (1300) can apply an AC voltage having a specific frequency by alternately applying a positive voltage and a negative voltage to the load. In this specification, for convenience of explanation, when the voltage applied to the node (1610) and the node (1710) illustrated in FIG. 2 is higher than the voltage applied to the node (1630) and the node (1730) illustrated in FIG. 2, the voltage applied to the load is described as a “positive voltage,” and when the voltage applied to the node (1610) and the node (1710) illustrated in FIG. 2 is lower than the voltage applied to the node (1630) and the node (1730) illustrated in FIG. 2, the voltage applied to the load is described as a “negative voltage.” In addition, the node (1610) illustrated in FIG. 2 is a node (1310) located between the first switch (S1) and the switch (S2) illustrated in FIG. 3, and the node (1630) illustrated in FIG. 2 is a node (1320) located between the third switch (S3) and the fourth switch (S4) illustrated in FIG. 3.

[0129] The sensor module (1400) can detect the phase (or direction and / or magnitude) of the current flowing in the load. As described in FIG. 2, the sensor module (1400) is electrically coupled to the load to obtain a current signal corresponding to the current flowing in the load, and can obtain information about the wave of the output current flowing in the load based on the obtained current signal. Here, the wave of the output current is a square waveform that senses signals related to the phase and / or direction of the output current flowing in the load (refer to the sensed output current of the inverter illustrated in FIG. 8). Hereinafter, a signal related to the phase and / or direction of the output current flowing in the load is referred to as a signal of the output current. In other words, the wave of the output current may include signals of a plurality of output currents.

[0130] Specifically, the following description will be made with reference to FIG. 4. Here, the square waveform disclosed in FIG. 4 may be signals sensed related to the phase and / or direction of the output current flowing through the load. The output current wave may be defined as a set of multiple temporally continuous output current signals. For example, the output current signal may include one rising edge and one falling edge at an interval equal to a first time width. In other words, the output current signal may increase in magnitude to +A along one rising edge, maintain +A for an interval equal to the first time width, and thereafter decrease to 0 or -B along the falling edge, and maintain 0 or -B again for an interval equal to a second time width. Here, A and B may have the same value or different values. In addition, the first time width and the second time width may have the same width or different widths.

[0131] The controller (1500) can output a wave of a first control signal corresponding to a first frequency to the inverter (1300) through a control signal output unit (1570).

[0132] The first control signal may be for appropriately turning on and / or turning off the four switches included in the inverter (1300) so that the first AC voltage having the first frequency is applied to the load, as described above. In other words, the control signal output unit (1570) may generate and output a wave of a control signal corresponding to the frequency determined by the frequency determination unit (1550) so that the AC voltage having the frequency determined by the frequency determination unit (1550) is applied to the load. The first control signal may be expressed, for example, as the control signal illustrated in FIG. 8.

[0133] Here, the wave of the control signal may mean including a plurality of control signals. Similarly to the above, referring to FIG. 4, the square waveform disclosed in FIG. 4 may be a representation of signals currently output to the inverter (1300) through the control signal output unit (1570). The wave of the control signal may be defined as a set of a plurality of temporally continuous control signals. For example, the control signal may include one rising edge and one falling edge at an interval equal to a first time width. In other words, the control signal may increase in magnitude to +A along one rising edge, maintain +A for an interval equal to the first time width, and thereafter decrease to a magnitude of 0 or -B along the falling edge, and maintain the magnitude of 0 or -B again for an interval equal to the second time width. Here, A and B may have the same value or different values. Additionally, the first time width and the second time width may be the same width or different widths.

[0134] Also, in order to facilitate understanding in the description of the control signal, the same terms as A, B, first time width, and second time width are used as in the description of the signal of the output current. However, it is obvious to those skilled in the art that A, B, first time width, and second time width in the control signal and A, B, first time width, and second time width in the signal of the output current are not necessarily the same values. In other words, A, B, first time width, and second time width are merely values ​​arbitrarily set for the convenience of description, and should not be interpreted as being limited to any specific value. In addition, A, B, first time width, and second time width for the signal of the output current and A, B, first time width, and second time width in the control signal may have different values.

[0135]

[0136] Meanwhile, in some embodiments disclosed by the present application, the points in time corresponding to each of a plurality of rising edges of the control signal may mean points in time at which a control signal for turning ON the first switch (S1) and the third switch (S3) and turning OFF the second switch (S2) and the fourth switch (S4) is output from the controller (1500), and the points in time corresponding to each of the falling edges of the control signal may mean points in time at which a control signal for turning OFF the first switch (S1) and the third switch (S3) and turning ON the second switch (S2) and the fourth switch (S4) is output from the controller (1500).

[0137] According to the above description, in the description below, the wave of the first control signal may include a plurality of first control signals, and the wave of the second control signal may include a plurality of second control signals.

[0138] Meanwhile, the frequency determination unit (1550) can assume a wave of a virtual signal that shifts the wave of the first control signal received by a predetermined amount of time. Here, assuming the wave of the virtual signal means that the wave of the virtual signal is not generated as a physical or electrical signal, nor is it output to another device or module. That is, the frequency determination unit (1550) can use the wave of the virtual signal to calculate a delay time or phase difference with the wave of the output current by implementing it in software or virtually assuming it without generating it as a physical or electrical signal.

[0139] Here, calculating a phase difference or delay time may mean that the phase difference or delay time is detected / detected. It should be noted in advance that in the description of this specification, calculating a phase difference or delay time may also be interpreted as detecting / detecting the phase difference or delay time.

[0140] However, the embodiments implemented according to the present disclosure are not necessarily limited thereto. For example, as described above, the wave of the virtual signal may be implemented in software or assumed virtually, but may also be a signal actually output as a physical or electrical signal. For example, the frequency determination unit (1550) may physically or electrically generate a wave of a virtual signal by shifting the wave of the control signal output from the control signal output unit (1570) by a predetermined time according to a circuit configured in the frequency determination unit (1550), thereby calculating a delay time or phase difference between the wave of the virtual signal generated physically or electrically and the wave of the output current.

[0141] Meanwhile, since the wave of the virtual signal is a shifted wave of the first control signal, each of the plurality of first control signals included in the wave of the first control signal can correspond to each of the plurality of virtual signals included in the wave of the virtual signal. In other words, each of the plurality of virtual signals included in the wave of the virtual signal can correspond to each of the plurality of first control signals in that order.

[0142] For example, generating a wave of a virtual signal by shifting a wave of a first control signal includes determining time points corresponding to rising edges of the wave of the virtual signal by adding or subtracting a value corresponding to a predetermined time to each of time points corresponding to rising edges of the first control signal, determining time points corresponding to falling edges of the wave of the virtual signal by adding or subtracting a value corresponding to a predetermined time to each of time points corresponding to falling edges of the wave of the virtual signal, and then generating a square wave corresponding to the determined rising edge time points and the determined falling edge time points.

[0143] Here, the predetermined time may be determined based on the time difference between the points in time at which the rising edge or falling edge of the first control signal from the controller (1500) is output to the inverter (1300) and the points in time at which the AC voltage generated by the operation of the first to fourth switches (S1, S2, S3, S4) controlled by the wave of the first control signal is expected to be output from the inverter (1300). That is, the predetermined time may be determined to be the same value as the above-described time difference, but may also be determined to be a value longer or shorter than the time difference. For example, when the predetermined time is determined to be the same value as the time difference, it may be called a complete resonance drive, when the predetermined time is longer than the time difference, it may be called an inductive drive, and when the predetermined time is shorter than the time difference, it may be called a capacitive drive.

[0144] A detailed description of these fully resonant drives, inductive drives and capacitive drives will be provided later based on Figs. 7 and 8.

[0145] Hereinafter, for convenience of explanation, the time difference between the wave of the first control signal and the wave of the (expected ideal) output voltage means the actual (or expected) time difference between the points of time of the rising edges and falling edges of the first control signal as described above and the points of time of the ideal rising edges and ideal falling edges of the AC voltage actually output through the inverter.

[0146] FIG. 5 is intended to explain the time difference between the wave of the first control signal and the wave of the output voltage. However, the components shown in FIG. 5 (e.g., the control signal output unit (1570), the buffer, the isolator, the gate driver, and / or the plurality of switches) are only examples of components constituting the controller (1500) and the inverter (1300), and are not limited thereto. In other words, at least one of the components shown in FIG. 5 may not be included, and additional components may be included. In addition, the components shown in FIG. 5 may each be configured as an individual chip or circuit, or two or more components may be configured as one chip or circuit.

[0147] Referring to FIG. 5, when the wave of the first control signal is output from the controller (1500) and applied to the plurality of switches of the inverter (1300), the DC voltage applied to the inverter (1300) according to the wave of the first control signal is output as an AC voltage through the buffer, the gate driver, and the plurality of switches described above. At this time, it takes a certain amount of time for the AC voltage to be output through the buffer, the gate driver, and the plurality of switches described above. This certain amount of time is the time difference between the time at which the wave of the first control signal from the controller (1500) is input to the inverter (1300) and the time at which the AC voltage generated by the wave of the first control signal is expected to be output from the inverter (1300), and by utilizing this time difference, the wave of the virtual signal can be assumed by shifting the wave of the first control signal. In other words, the wave of the virtual signal may be the waveform of an ideal output voltage expected when it is assumed that the output voltage from the inverter (1300) is output without any noise.

[0148] At this time, the wave of the virtual signal is used to calculate the delay time and / or phase difference with the wave of the output current, as described later. In conjunction with the above description, ultimately, the frequency determination unit (1550) assumes the wave of the virtual signal in order to calculate the delay time and / or phase difference between the wave of the output current of the inverter (1300) and the wave of the output voltage of the inverter (1300).

[0149] Meanwhile, the reason why the wave of the output voltage is not directly sensed in one embodiment of the present specification and the delay time and / or phase difference with the wave of the output current is not directly calculated is as follows.

[0150] Referring to Fig. 6, i RFThe waveform of the output current of the load indicated by is obtained in most cases as a pure sine wave (or cosine wave). Therefore, the wave for measuring the phase of the output current (i.e., the wave of the output current) through the sensor module (1400) can be obtained relatively easily in a form such as 510.

[0151] By the way, V RF In the case of the output voltage of the load indicated by , it is very difficult to accurately and reliably obtain a wave for measuring the phase of the output voltage due to the high-frequency resonance noise generated by the switching of the multiple switches included in the inverter (1300). Therefore, it is quite difficult to relatively accurately detect / detect the phase difference or delay time between the output voltage of the load and the output current of the load by directly sensing the output voltage of the load and comparing it with the output current of the load.

[0152] Additionally, if the phase difference or delay time between the output voltage of the load and the output current of the load cannot be accurately detected / detected, it may be very difficult to control the frequency of the AC voltage applied to the load by tracking the resonant frequency of the variable load.

[0153] Accordingly, in this specification, frequency tracking is performed by assuming a wave of a virtual signal that shifts the wave of a control signal that controls the operation of switches of an inverter (1300) through a controller (1500) by a predetermined time based on the time difference described in FIG. 5, and calculating the phase difference or delay time between the wave of the virtual signal and the wave of the output current of a load sensed by a sensor module (1400).

[0154] The reason why the wave of the virtual signal that is the wave of the control signal can be used instead of the output voltage of the load is that, assuming that the output voltage of the load is output in an ideal form without noise, the wave of the output voltage of the load is different from the wave of the control signal only in magnitude, and the output pattern (or phase) is the same. In other words, it is easy to predict that the wave of the output voltage of the load will be output in a form that is delayed by the time difference described in FIG. 5 while only the magnitude is changed from the wave of the control signal according to the magnitude of the DC voltage applied to the inverter (1300), and the length or pattern (or phase) of the control signals included in the wave of the control signal is maintained as is.

[0155] Therefore, since the wave of the virtual signal, which is the wave of the control signal shifted by the time difference described in Fig. 5, is different from the wave of the output voltage of the ideal load only in magnitude, and has the same pattern (or phase), there is no problem in comparing the phase difference or delay time between the output current of the load and the output voltage of the load.

[0156] Meanwhile, the time difference in FIG. 5 can be measured experimentally or inferred through the specifications of components included in the inverter (1300), but is not limited thereto, and the time difference can be determined in various ways. In addition, the time difference in FIG. 5 can be preset and can remain constant if there is no change in the inverter (1300) itself or the structure of the inverter (1300).

[0157]

[0158] The frequency determination unit (1550) can detect / detect the delay time between the wave of the virtual signal (i.e., the wave of the ideal output voltage) and the wave of the output current of the inverter (1300) in the first section during at least a portion of the first section using the clock of the processor (1510). Here, a detailed method of detecting / detecting the delay time will be described in detail later with reference to FIG. 7.

[0159] In addition, the frequency determination unit (1550) can determine the second frequency of the second AC voltage applied to the load during the second period immediately following the first period based on the first frequency of the first AC voltage to be generated by the wave of the first control signal, the detected / sensed delay time, and at least one outputtable frequency that can be determined according to the clock of the processor (1510). Here, a detailed method of determining the second frequency will be described in detail later with reference to FIGS. 7 and 11.

[0160] Here, the first section may refer to a section corresponding to the current time when the RF generator (1000) is operating according to the first frequency. In addition, the second section may refer to a time section immediately after the end of the first section, and may refer to a section corresponding to the next time when the RF generator (1000) will operate according to the second frequency after the end of the first section. Meanwhile, a third section, which is a time section immediately after the end of the second section, may also exist. The third section may refer to a section corresponding to a time when the RF generator (1000) applies an AC voltage having a third frequency to the inverter (1300) according to the embodiment described in the present disclosure after the end of the second section. Here, the third frequency is a frequency determined for the third section according to the embodiment of the present disclosure based on the second frequency. For example, the embodiment of the present disclosure may be equally applied to determine the third frequency of the third section. For example, since the method for determining the third frequency from the second frequency is the same as the method for determining the second frequency from the first frequency, determining the third frequency can be applied by replacing “first frequency” and “first AC voltage” with “second frequency” and “second AC voltage” in the embodiment of the present disclosure, respectively, and replacing “second frequency” and “second AC voltage” with “third frequency” and “third AC voltage”, respectively.

[0161] In addition, for convenience of explanation, it is assumed that the first frequency of the first AC voltage output in the first section is one of at least one outputtable frequency that can be determined using the clock of the processor (1510), but is not limited thereto.

[0162] For example, the first frequency may not be included in the at least one outputtable frequency, in which case the first frequency may also be output using multiple outputtable frequencies as described in FIG. 12. A method for generating the first frequency or the second frequency using multiple outputtable frequencies will be described in detail in FIG. 12.

[0163] Even in this case, the method for determining the second frequency output in the second section can be applied in the same manner as the embodiment disclosed in this specification, so that the second frequency can be determined, which will be apparent to those skilled in the art.

[0164] The control signal output unit (1570) can output a wave of a second control signal that controls the switches of the inverter (1300) so that a second AC voltage having a determined second frequency can be applied to the load during a second period. In addition, when the wave of the second control signal is input to the inverter (1300), the switches of the inverter (1300) are turned on and / or off, thereby generating a second AC voltage having a second frequency and applying it to the load.

[0165]

[0166] Now, referring to FIG. 7, methods for frequency control according to one embodiment of the present specification will be described. Meanwhile, the frequency control method described based on FIG. 7 can be performed under the control of a controller (1500). That is, unless otherwise specified, the following descriptions can be controlled or performed by the controller (1500) of the RF generator (1000).

[0167] Meanwhile, the configuration of the processor (1510), current detector (1530), frequency determination unit (1550), and control signal output unit (1570) included in the controller (1500) described in FIG. 3 is divided according to the function performed by each component for convenience of explanation, and is not limited to the hardware configuration. That is, each component included in the controller (1500) may be implemented in the form of software or program code, or may be implemented in the form of a circuit using various components. Accordingly, each component included in the controller (1500) may not be physically separated. In other words, each component included in the controller (1500) may be functionally separated.

[0168] Therefore, each process or each step described in FIG. 7 described below should be understood as being controlled or performed by the controller (1500) unless otherwise specified, and should not necessarily be understood as being performed by a specific, separate and distinct component within the controller (1500). Furthermore, even if described without being specifically distinguished, a person skilled in the art will be able to easily understand through the description related to FIG. 3 which component of the controller (1500) controls and performs each process or each step described in FIG. 7.

[0169] Referring to FIG. 7, the controller (1500) can output the wave of the first control signal to the inverter (1300) so that a first AC voltage having a first frequency is applied to the load during the first section (S705). In addition, the controller (1500) can assume the wave of a virtual signal that shifts the wave of the first control signal by a predetermined amount of time (S710). In this case, the predetermined time as described above is determined based on the time difference described in FIG. 5, but is not necessarily the same as the time difference.

[0170] Referring to FIG. 8, the controller (1500) can assume that the wave of the first control signal is shifted by the corresponding time difference so that the wave of the virtual signal has the same phase as the wave of the output voltage of the ideal inverter (1300) expected to be output according to the corresponding time difference, and this can be called a complete resonance driving mode. For example, referring to FIG. 8, in the complete resonance driving mode, the predetermined time can be equal to the corresponding time difference, such as in the section (1-1).

[0171] In addition, the controller (1500) may assume that the wave of the first control signal is shifted by a larger amount than the time difference so that the wave of the virtual signal follows (i.e. lags) the wave of the output voltage of the ideal inverter (1300) expected to be output according to the time difference, and this may be referred to as an inductive driving mode. For example, referring to FIG. 8, in the inductive driving mode, the predetermined time may be longer than the time difference, such as in the section (1-2).

[0172] In addition, the controller (1500) may assume that the wave of the first control signal is shifted to be smaller than the time difference so that the wave of the virtual signal is ahead (i.e., leading) of the wave of the output voltage of the ideal inverter (1300) expected to be output according to the time difference, and this may be referred to as a capacitive driving mode. For example, referring to FIG. 8, in the capacitive driving mode, the predetermined time may be shorter than the time difference, such as in the section (1-3).

[0173] The fully resonant driving mode can be used when the voltage generated by passive components (e.g., inductors and capacitors) included in the load is to be offset as precisely as possible, thereby reducing the voltage of the inductor (e.g., coil) included in the load. For example, when the load is a plasma generator for plasma generation, it can be suitable when the voltage of the antenna of the plasma generator is to be reduced by offsetting the LC voltage of the plasma source as precisely as possible, and the plasma discharge is to be maintained at the maximum power factor.

[0174] Inductive drive mode may be suitable when multiple switches included in the inverter (1300) perform soft switching and want to maintain a specific state of the load (e.g., plasma discharge).

[0175] Capacitive driving mode may be suitable when it is desired to stably maintain a specific state (e.g., plasma discharge) of a gas (e.g., NF3) that is sensitive to environmental conditions such as flow rate, power, and pressure.

[0176] In other words, the controller (1500) can select which of the three driving modes described above to operate in depending on a specific state of the load (e.g., a plasma discharge state), and shift the wave of the first control signal by a predetermined time according to the selected driving mode. That is, by determining the predetermined time to be longer, shorter, or equal to the time difference described in FIG. 5, an operation suitable for a specific state of the load (e.g., an operation suitable for maintaining a plasma discharge) can be performed.

[0177] If the RF generator (1000) operates in capacitive driving mode or inductive driving mode, it is necessary to determine how much to shift the first control signal by more or less than the time difference described in FIG. 5. This can be basically determined depending on a specific state of the load (e.g., plasma discharge state), but can preferably be selected within a range of 10 ns to 40 ns. For example, if the RF generator (1000) operates in capacitive driving mode, the controller (1500) can assume the wave of the virtual signal by shifting the wave of the first control signal by a time that is more than 10 ns to 40 ns shorter than the time difference described in FIG. 5.

[0178] For example, if the RF generator (1000) operates in an inductive driving mode, the controller (1500) can assume the wave of the virtual signal by shifting the first control signal by a time that is 10 ns or more and 15 ns or less than the time difference described in FIG. 5.

[0179] Meanwhile, the selection of which driving mode to shift the wave of the first control signal may be made by the user monitoring a specific state of the load (e.g., plasma discharge state) and inputting or setting the driving mode or a predetermined time to shift. Alternatively, the controller (1500) may adaptively determine a predetermined time to shift the wave of the first control signal by periodically or aperiodically monitoring a specific state of the load (e.g., plasma discharge state) or by determining and applying the driving mode.

[0180] Meanwhile, among the three driving modes described above, the capacitive driving mode is generally the most widely utilized. This is because operating in the capacitive driving mode is effective in maintaining a specific state of the load (e.g., plasma discharge).

[0181] Let us examine this through Fig. 9. Fig. 9(a) shows the change in resonant frequency when operating in capacitive driving mode, and Fig. 9(b) shows the change in resonant frequency when operating in inductive driving mode.

[0182] For example, if the inductive coupling between the antenna and the plasma for the plasma discharge is weakened during the plasma discharge, the resonant frequency of the antenna may decrease while the effective inductance may increase.

[0183] In this case, if the frequency tracking operation is performed according to the capacitive driving mode, as can be seen in Fig. 9(a), the resonant frequency of the antenna decreases and the magnitude of the current flowing from the RF generator (1000) to the antenna (i.e., the load) increases. This increases the power applied to the plasma, and as the inductive coupling between the antenna and the plasma becomes stronger, the resonant frequency of the antenna can increase again. Accordingly, the resonant frequency of the antenna can be restored to its original state, and a stable negative feedback can be implemented. That is, when operating in the capacitive driving mode, a stable negative feedback can be implemented when the resonant frequency of the antenna is varied, so that the plasma discharge can be stably maintained, and a stable frequency tracking operation can also be enabled.

[0184] Meanwhile, if the frequency tracking operation is performed according to the inductive driving mode, as can be seen in Fig. 9(b), the resonant frequency of the antenna decreases, and the magnitude of the current flowing from the RF generator (1000) to the antenna (i.e., the load) decreases. Accordingly, the power applied to the plasma decreases, and the inductive coupling between the antenna and the plasma weakens, further lowering the resonant frequency of the antenna. In this case, an unstable positive feedback is implemented in which the power applied to the plasma further decreases, further lowering the resonant frequency of the antenna, and thus the effect of stably maintaining the plasma discharge cannot be obtained.

[0185] For the reasons described above, it is generally preferred to implement frequency tracking operation in capacitive driving mode rather than inductive driving mode.

[0186] However, capacitive driving mode is not preferred over inductive driving mode in all cases, and inductive driving mode may be preferred depending on the state of the plasma and the application to which frequency tracking is applied.

[0187]

[0188] [Table 1] compares the discharge stabilization effect of NF3 gas when frequency tracking operation is implemented through capacitive driving mode and when frequency tracking operation is implemented through inductive driving mode.

[0189] Number Frequency Tracking Speed ​​(FTR0105 frq_change_cycle) Predetermined time and driving mode used for shifting the wave of the first control signal (FTR0108 phase_shift_lock) Plasma discharge maintenance success frequency 15 μs / cycle 90 ns (Capacitive) 50% (5 / 10) 250 μs / cycle 90 ns (Capacitive) 95% (16 / 17) 3200 μs / cycle 90 ns (Capacitive) 80% (8 / 10) 45 μs / cycle 120 ns (Inductive) 10% (1 / 10) 550 μs / cycle 120 ns (Inductive) 0% (0 / 10) 6200 μs / cycle 120 ns (Inductive) 0% (0 / 10)

[0190] [Table 1] shows that implementing the frequency tracking operation in capacitive mode is much more effective in terms of plasma discharge effect. Meanwhile, Fig. 10 shows the experimental data output for the discharge effect when NF3 gas is injected during argon (Ar) plasma discharge according to some cases of [Table 1]. Both Fig. 10(a) and Fig. 10(b) show that NF3 gas is injected about 20 ms after the start of argon (Ar) plasma discharge. Fig. 10(a) shows that NF3 is injected according to Case 4 (inductive mode) of [Table 1]. According to Fig. 10(a), an interlock occurs after the time indicated by the dotted line due to the continuously increased current, and the voltage and current do not flow and the discharge effect disappears. On the other hand, Fig. 10(b) shows that NF3 was injected according to Case 1 (capacitive mode) of [Table 1], and shows that the discharge effect is stably maintained. Referring to Fig. 10, it can be seen that the discharge effect is stably maintained in the capacitive driving mode.

[0191] Meanwhile, if the controller (1500) assumes that the wave of the virtual signal shifted by a predetermined time based on the selected driving mode from the wave of the first control signal according to S710, the controller (1500) can determine the delay time between the wave of the virtual signal and the wave of the output current of the inverter (1300) sensed in the first section (S715). Here, determining the phase difference or delay time may mean that the phase difference or delay time is detected / detected. In the following description of the specification, it is to be noted in advance that determining the phase difference or delay time may be interpreted as detecting / detecting the phase difference or delay time.

[0192] For example, referring to FIG. 8, the controller (1500) may assume a wave of a virtual signal that shifts the control signal by a predetermined time of any one of (1-1), (1-2), or (1-3) depending on the selected driving mode as described above. In addition, the controller (1500) may obtain a first counting value by counting a first time length from a rising edge of the wave of the virtual signal (i.e., (4-1), (4-2), or (4-3)) to a first falling edge that appears after the rising edge, such as the time length of (2-1), (2-2), or (2-3), based on the clock of the processor (1510).

[0193] For example, if the clock frequency of the processor (1510) is 200 MHz, the minimum time unit that can be counted with the clock is 1 / (200*10^6) = 5 ns. Therefore, if the first time length is 100 ns, the first counting value according to the first time length is 20. Similarly, if the first time length is 105 ns, the first counting value according to the first time length is 21.

[0194] Meanwhile, if the first time length is not an integer multiple of the minimum time unit, the first counting value may be determined based on the period of the pulse waves generated according to the clock. For example, if counting is performed based on the end point of the period of the pulse waves, if the first time length is 103 ns, the first counting value according to the first time length may be 20, and if the first time length is 97 ns, the first counting value according to the first time length may be 19. This may be a result that is the same as applying a floor function to the value obtained by dividing the first time length by the minimum time unit.

[0195] If counting is performed based on the starting point of the cycle of the generated pulse waves, when the first time length is 103 ns, the counting value according to the first time length may be 21, and when the first time length is 97 ns, the counting value according to the first time length may be 20. This may be the same result as applying a ceil function to the value obtained by dividing the first time length by the minimum time unit.

[0196] For convenience of explanation, the following description of the present specification will be based on counting based on the end point of the pulse wave cycle. However, this is not limited thereto. That is, since it is obvious to those skilled in the art that the embodiments of the present specification can be applied by counting based on the start point of the pulse wave cycle in the description of the present specification, it is obvious that the implementation of the embodiments described in the present specification can be easily replaced with examples that count based on the start point of the pulse wave cycle.

[0197] Referring again to FIG. 8, the controller (1500) can count the second time length from the rising edge of the wave of the virtual signal (i.e., (4-1), (4-2) or (4-3)) to the falling edge of the wave of the output current of the inverter (1300) that appears first after the rising edge, as described above, according to the clock of the processor (1510). In other words, the controller (1500) can obtain the second counting value for the second time length using the minimum time unit according to the clock of the processor (1510).

[0198] Meanwhile, in obtaining the first counting value and the second counting value, if the first time length, which serves as a reference, is determined as the length from the rising edge of the wave of the control signal to the falling edge of the wave of the virtual signal, or the second time length, which serves as the length from the rising edge of the wave of the virtual signal to the rising edge of the wave of the output current that appears following the rising edge, or from the rising edge of the wave of the control signal to the falling edge of the wave of the output current that appears following the rising edge, the following problems may occur.

[0199] First, if the second time length is determined as the length from the rising edge of the wave of the virtual signal to the rising edge of the wave of the output current that appears after the rising edge, if the inverter (1300) operates in the capacitive region, the rising edge of the wave of the output current may occur in time earlier than the rising edge of the wave of the virtual signal corresponding to the rising edge. However, in this case, if counting starts from the rising edge of the wave of the virtual signal, the controller (1500) may detect the next rising edge of the wave of the output current corresponding to the rising edge, not the rising edge, and thus, when the inverter (1300) actually operates in the capacitive region, it may be incorrectly detected that the inverter (1300) operates in the inductive region.

[0200] Meanwhile, if the first time length is determined as the length from the rising edge of the wave of the control signal to the falling edge of the wave of the virtual signal, or if the second time length is determined as the length from the rising edge of the wave of the control signal to the falling edge of the wave of the output current that appears after the rising edge, if the inverter (1300) operates in the inductive region, the wave of the output current is delayed in time compared to the wave of the virtual signal. In this case, if the degree of delay is considerably large and the falling edge of the wave of the output current occurs later in time than the second falling edge of the wave of the virtual signal, the inverter (1300) may be incorrectly detected as operating in the capacitive region when in fact it is operating in the inductive region.

[0201] Meanwhile, if the first time length is set from the rising edge (or falling edge) of the wave of the virtual signal to the next rising edge (or falling edge) that appears after the rising edge (or falling edge), and the second time length is set from the rising edge (or falling edge) of the wave of the virtual signal to the rising edge (or falling edge) of the wave of the output current that appears first after the rising edge (or falling edge), the delay time may be incorrectly detected depending on the phase difference or delay between the wave of the ideal output voltage and the wave of the output current and the degree to which the virtual signal is shifted compared to the wave of the ideal output voltage.

[0202] For example, if, as in Fig. 8, the phase of the ideal output voltage wave is ahead of the phase of the output current wave, and the first time length is set from the rising edge of the wave of the virtual signal to the next rising edge that appears after the rising edge, and the second time length is set from the rising edge of the wave of the virtual signal to the rising edge of the wave of the output current that appears first after the rising edge, the delay time may be incorrectly detected in at least one of the capacitive driving, the fully resonant driving, and the inductive driving depending on the degree of delay between the wave of the ideal output voltage and the wave of the output current. For example, taking the fully resonant driving of Fig. 8 as an example, the second time length is set from the point in time (4-1) to the rising edge of the wave of the output current that appears for the first time after (4-1), and the second counting value is calculated. However, in order for the delay time to be calculated properly, the rising edge of the wave of the output current that appears for the first time must correspond to the end point of the first time length. However, in the example described above, the rising edge of the wave of the output current that actually appears for the first time is the rising edge corresponding to the starting point of the first time length (i.e., the rising edge corresponding to (4-1)), so an error may occur in the detection of the delay time.

[0203] Similarly, even if the first time length is set from the falling edge of the wave of the virtual signal to the next falling edge that appears after the falling edge, and the second time length is set from the falling edge of the wave of the virtual signal to the falling edge of the wave of the output current that appears first after the falling edge, if the wave of the ideal output voltage is slower than the wave of the output current, the falling edge of the end point of the second time length may correspond to the falling edge corresponding to the starting point of the first time length depending on the degree of slowness, and thus an error may occur in the detection of the delay time. For the same reason as described above, it may be desirable for the controller (1500) to obtain the first counting value by counting the first time length from the rising edge of the wave of the virtual signal (i.e., (4-1), (4-2) or (4-3)) to the first falling edge that appears after the rising edge, such as the time length of (2-1), (2-2) or (2-3), according to the clock of the processor (1510). there is.

[0204] Likewise, it may be desirable for the controller (1500) to obtain a second counting value by counting a second time length from the rising edge of the wave of the virtual signal (i.e., (4-1), (4-2) or (4-3)) to the falling edge of the wave of the output current of the inverter (1300) that appears first after the rising edge, as described above, according to the clock of the processor (1510).

[0205] When the controller (1500) obtains the first counting value and the second counting value, the controller (1500) can calculate the difference between the first counting value and the second counting value to determine the delay time between the wave of the virtual signal and the wave of the output current of the inverter (1300) output in the first section (S715). For example, the controller (1500) can determine the value obtained by subtracting the first counting value and the second counting value as the delay time between the waves of the output current of the inverter (1300). At this time, since the determined delay time is the delay time between the sensed output current and the virtual signal shifted by a predetermined time according to the control signal and each mode as described above, it cannot be said to be the delay time between the actual voltage and current. However, in this specification, as already explained, the purpose is to utilize various beneficial effects arising from using a virtual signal instead of measuring the phase of the voltage, and therefore, the delay time between the voltage and the current should be understood as the delay time between the virtual signal and the current, not the delay time between the actual voltage and current, even without any special limitation or explanation of the delay time between the virtual signal and the current.

[0206] Additionally, the controller (1500) can determine the second frequency, which is the frequency of the AC voltage output by the inverter (1300) in the second section immediately following the first section, based on the corresponding delay time (S720).

[0207] For example, if the delay time is within a preset range, the controller (1500) can output a second control signal wave that is identical to the wave of the first control signal to the inverter (1300) so that the inverter (1300) outputs (i.e., applies) an AC voltage having the same frequency as the first frequency in the second section immediately following the first section. In other words, if the delay time is within a preset range (e.g., greater than or equal to the first value and less than or equal to the second value), the controller (1500) can maintain the frequency of the AC voltage without changing it in the second section immediately following the first section.

[0208] Meanwhile, if the delay time is out of a preset range (e.g., greater than or equal to the first value and less than or equal to the second value), a wave of a second control signal different from the wave of the first control signal may be output to the inverter (1300) so that the inverter (1300) outputs an AC voltage having a frequency different from the first frequency in the second section (i.e., so that it is applied to the load). For example, if the delay time is less than the first value, the controller (1500) may determine a second frequency lower than the first frequency, and output a wave of the second control signal to the inverter (1300) so that the inverter (1300) outputs an AC voltage having the second frequency in the second section (i.e., so that it is applied to the load). Additionally, when the delay time exceeds the second value, the controller (1500) can determine a second frequency higher than the first frequency and output a wave of the second control signal to the inverter (1300) so that the inverter (1300) outputs an AC voltage having the second frequency in the second section (i.e., so that it is applied to the load).

[0209] Meanwhile, the first and second values ​​can be determined based on a tolerance range. If the first value is -1 and the second value is +1, the tolerance range of the actual delay time can be -10 ns to +10 ns. If both the first and second values ​​are 0, the tolerance range of the actual delay time can be -5 ns to +5 ns.

[0210] Meanwhile, an example of the allowable error range of the actual delay time according to the first and second values ​​can be as shown in [Table 2].

[0211] Preset rangeActual delay time tolerance range(ns)First valueSecond valueError range according to first valueError range according to second value00-5+5-11-10+10-22-15+15

[0212] Meanwhile, the first value and the second value may be different or the same, and the absolute values ​​of the first value and the second value do not necessarily have to be the same. For example, if the tolerance range of the actual delay time is -5 ns to +10 ns, the first value may be 0 and the second value may be 1, and if the tolerance range of the actual delay time is -10 ns to +15 ns, the first value may be -1 and the second value may be 2.

[0213] Meanwhile, depending on the allowable error range of the actual delay time and the resulting value of the derived delay time, the first and second values ​​may be set to rational numbers rather than integers. That is, the first and second values ​​do not necessarily have to be integers and may be rational numbers including decimal points.

[0214] The above description shows that the controller (1500) calculates a delay time using a first counting value and a second counting value, and determines a second frequency using the calculated delay time. However, the controller (1500) may also calculate a delay time using a plurality of first counting values ​​and a plurality of second counting values, and determine a second frequency using the calculated delay time. In this case, the controller (1500) may calculate delay times using the difference value between each of the plurality of first counting values ​​and each of the plurality of second counting values, and determine the second frequency using the average value of the corresponding delay times.

[0215] In such cases, the first and second values ​​do not necessarily need to be integers, but may be rational numbers with decimal points, which may be determined according to the allowable error range of the actual delay time.

[0216] Meanwhile, it was mentioned in the above section that the controller (1500) can determine the second frequency using a plurality of first counting values ​​and a plurality of second counting values. An example of this will be described below.

[0217] The first and second sections described above are continuous sections in time, and the second section may be immediately following the first section. In addition, the first and second sections are cycles in which the controller (1500) determines whether to change the frequency of the AC voltage currently being output. That is, when the controller (1500) outputs the wave of the first control signal for outputting the first AC voltage having the first frequency from the starting point of the first section, it can output the wave of the second control signal for outputting the second AC voltage having the second frequency from the starting point of the second section.

[0218] At this time, the lengths of the first and second sections may be the same or different.

[0219] For example, in the first section, a wave of a first control signal including a plurality of first control signals and waves of an output current including a plurality of output current signals may be output. Accordingly, the controller (1500) may assume a wave of a virtual signal in which the wave of the first control signal in the first section is shifted by a predetermined time, and the wave of the virtual signal may include a plurality of virtual signals. Here, as described in FIG. 4, since the wave of the virtual signal is a shifted wave of the control signal, the virtual signals may increase in size to a magnitude of +A along one rising edge like the control signal, maintain +A for an interval equal to the first time width, and thereafter, decrease to a magnitude of 0 or -B along a falling edge, and maintain the magnitude of 0 or -B again for an interval equal to the second time width. Here, A and B may have the same value or different values. In addition, the first time width and the second time width may have the same width or different widths. For example, if the first time width and the second time width are the same and the frequency of the wave of the control signal is 2 MHz, the frequency of the wave of the virtual signal will also be 2 MHz, so the sum of the first time width and the second time width may be 0.5 us. In addition, each of the virtual signals included in the wave of the virtual signal may have the same first time width and the second time width, but may have different first time widths and second time widths. For example, as described below, a plurality of outputtable frequencies that can be determined using the clock of the processor (1510) to generate one frequency may be utilized, and in this case, the control signals included in the wave of the control signal may have different periods corresponding to the plurality of outputtable frequencies. For example, as shown in FIG. 12, control signals having different periods may be included in the wave of the control signal.In this case, the first time widths and the second time widths for each virtual signal or each control signal may be different from each other. Meanwhile, for example, if the length of the first section and / or the second section is 10 us, the virtual signals included in the wave of the virtual signal may be 20 in total, and thus, a total of 20 delay times may be calculated. However, as described below, among the 20 delay times, only the last N delay times may be used to determine the second frequency in the second section. For example, the controller (1500) may calculate an average value of the last N (N is a natural number) delay times among the delay times of each of the plurality of virtual signals and each of the plurality of output current signals corresponding to each of the virtual signals, and determine the second frequency based on whether the average value is between the first value and the second value described above, or is less than the first value, or is greater than the second value. At this time, the last N delay times may be integers, but may also be rational numbers including decimal points, so in this case, the first value and the second value may be set to rational numbers including decimal points rather than integers.

[0220] Meanwhile, for example, in a case where the first frequency is output using a combination of multiple output-capable frequencies as in FIG. 12, the controller (1500) can calculate an average value of the delay times of the last N (N is a natural number) among the delay times of each of the multiple virtual signals and each of the multiple output current signals corresponding to each virtual signal, regardless of the period of the control signal or the virtual signal, and determine the second frequency using the calculated average value.

[0221] In addition, the N value, which is the number of delay times for calculating the average value, can be an integer. Meanwhile, the reason why only the last N average values ​​are used instead of the average value of all delay times that can be calculated in the first section is that even if the last N average values ​​are used, if N is set sufficiently, the controller (1500) can calculate the delay time between the wave of the first control signal and the wave of the output current quite accurately. In addition, since it takes a certain amount of time for the circuit to stabilize due to the changed frequency after the start of each section, using the average value of only the delay times that can be calculated after the certain amount of time may be more advantageous in determining a frequency close to the resonant frequency of the variable load.

[0222] To summarize the above description, the controller (1500) can calculate the delay times of a plurality of first virtual signals and a plurality of output current signals in at least some sections within the first section, and determine a second frequency for the second section based on an average value of the calculated delay times, wherein at least some of the sections may be sections corresponding to the last N delay times.

[0223] However, the embodiment described in the present specification is not limited to determining the second frequency for the second section based on the average value of the calculated delay times. For example, the controller (1500) may calculate the delay times of the signals of the plurality of first virtual signals and the plurality of output currents in at least some sections within the first section, and determine the second frequency for the second section based on the mode of the calculated delay times, wherein at least some sections may be sections corresponding to the last N delay times. For example, among the calculated delay times, the delay time with the largest number of identical values ​​may be determined as the delay time in the first section, and here, the identical values ​​may be considered to be the same if they are the same up to the Xth decimal point.

[0224] Meanwhile, when the controller (1500) determines the second frequency, it may further consider at least one output-capable frequency that can be determined using the clock of the processor (1510). A method for determining the second frequency by further considering at least one output-capable frequency will be described in detail below.

[0225] When the controller (1500) determines the second frequency, it can output a wave of a second control signal that controls a second AC voltage having the second frequency to be applied to the load (i.e., output from the inverter (1300)) during the second period and apply it to the inverter (1300) (S625). Meanwhile, the controller (1500) can also determine the second frequency by considering at least one more outputtable frequency and output a wave of the second control signal corresponding thereto, and the detailed operation of the controller (1500) in such a case follows the description of FIG. 11 described below.

[0226]

[0227] Meanwhile, in the above-described description, with respect to S720 of FIG. 7, when the controller (1500) determines the second frequency, a method for determining whether the controller (1500) will determine the second frequency to be higher than the first frequency, determine the second frequency to be lower than the first frequency, or maintain the second frequency equal to the first frequency is disclosed.

[0228] Additionally, if the controller (1500) determines that the second frequency is higher than the first frequency, how much higher the second frequency will be than the first frequency, or if the controller (1500) determines that the second frequency is lower than the first frequency, how much lower the second frequency will be than the first frequency will be described in detail.

[0229] In other words, the embodiments described below describe a method for the controller (1500) to determine a gap or difference or distance between the first frequency and the second frequency in the process of S720.

[0230] The controller (1500) can use the delay time determined in step S715 to determine the second frequency. At this time, the method for obtaining the delay time can be expressed in a formula as shown in [Mathematical Formula 1] below.

[0231]

[0232] Here, td_count curr is a delay time, and "the number of 1st CLK count" is a counting value of a wave of a virtual signal according to a clock of a processor (1510) for a cycle corresponding to the frequency of an AC voltage being output in the first section, and is a first counting value which is a counting value from a rising edge of a wave of a virtual signal to a first falling edge appearing after the rising edge, and "the number of 2nd CLK count" is a second counting value which is a counting value from a rising edge of a wave of a virtual signal to a falling edge of a wave of an output current.

[0233] The controller (1500) uses [Mathematical Formula 1] to calculate td_count curr If you decide, td_count curr If it is less than the first value, the second frequency is determined to be lower than the first frequency, and td_count curr If this second value is exceeded, the second frequency can be determined to be higher than the first frequency. If td_count curr If the value is greater than or equal to the first value and less than or equal to the second value, the second frequency will be determined to be the same as the first frequency.

[0234] If the controller (1500) determines that the second frequency is higher or lower than the first frequency, the first frequency, which is the frequency of the first control signal or the first AC voltage output in the first section, and the third counting value counted using the clock of the processor (1510) can be determined using the following [Mathematical Formula 2]. Here, counting the frequency using the clock of the processor (1510) means counting the time corresponding to the period, which is the reciprocal of the frequency, according to the clock of the processor (1510), and the counting method can be applied in the same manner as described above.

[0235]

[0236]

[0237]

[0238] Here, CLK is the clock of the processor (1510), and “the number of 3rd CLK count” is the third counting value obtained by counting the first frequency using the clock of the processor (1510).

[0239] For example, if the clock of the processor (1510) is 200 MHz and the first frequency is 2 MHz, the controller (1500) can determine the third counting value as 100 since 200*10^6 / 100 = 2*10^6 = 2 MHz.

[0240] The controller (1500) can determine a frequency that can be made into a third counting value and a counting value within a certain range as a candidate frequency among a plurality of outputtable frequencies that can be output according to the clock of the processor (1510).

[0241] For example, if the controller (1500) decides to determine the second frequency to be higher than the first frequency, the candidate frequency can be determined according to [Mathematical Formula 3] below.

[0242]

[0243]

[0244] On the other hand, if it is decided that the second frequency is lower than the first frequency, the candidate frequency can be determined according to [Mathematical Formula 4] below.

[0245]

[0246]

[0247] Here, the value of k can be a natural number, or a predetermined value can be used. For example, k can be 1.

[0248] For example, let's assume that the third counting value is 100 and the clock of the processor (1510) is 200 MHz according to the example described above. If the controller (1500) determines that the second frequency is higher than the first frequency, and k = 1, the candidate frequency can be determined as 200 MHz / (100-1) = 2.02 MHz according to [Mathematical Formula 3].

[0249] On the other hand, if the controller (1500) decides to make the second frequency lower than the first frequency and k=1, the candidate frequency can be determined as 200MHz / (100+1) = 1.98MHz according to [Mathematical Formula 4].

[0250] Here, since the controller (1500) determines how much to increase or decrease the first frequency, the controller (1500) can subtract the first frequency according to [Mathematical Formula 2] from the candidate frequency according to [Mathematical Formula 3] or [Mathematical Formula 4], and define the corresponding value as the delta frequency. In other words, the delta frequency is the value obtained by subtracting the first frequency from the candidate frequency.

[0251] For example, the delta frequency can be expressed according to [Mathematical Formula 5] below.

[0252]

[0253]

[0254] As explained above, if the controller (1500) decides to increase the first frequency to determine the second frequency, the value of -k may be used, and if the controller (1500) decides to decrease the first frequency to determine the second frequency, the value of +k may be used. In addition, stands for delta frequency, f curr means the first frequency.

[0255] Meanwhile, the controller (1500) can determine a smoothing factor (m) using the delay time according to [Mathematical Formula 6] below in order to adaptively determine the second frequency according to the delay time determined in [Mathematical Formula 1].

[0256] In other words, the controller (1500) can determine a smoothing factor (m) using a delay time according to [Mathematical Formula 6] below to adaptively determine the second frequency according to the difference between the wave of the virtual signal and the wave of the output current and / or the driving mode in which the controller (1500) is operating.

[0257]

[0258]

[0259] Here, as explained earlier, td_count curr means delay time. Meanwhile, td_count max is a preset parameter value and may be a value stored in the controller (1500). For example, td_count max can be set to an integer value.

[0260] Also, td_count max The value may be changed according to the user's input or command, and may also be changed according to the judgment of the controller (1500). However, in the embodiment of this specification, td_count max Let us assume that is a preset fixed value and describe it.

[0261]

[0262] The controller (1500) can ultimately determine how much to increase or decrease the first frequency by multiplying the delta frequency according to [Mathematical Formula 5] and the smoothing factor (m) according to [Mathematical Formula 6] to determine the second frequency.

[0263] That is, the amount of frequency to be increased or decreased by the controller (1500) can be determined according to [Mathematical Formula 7].

[0264]

[0265] In other words, the controller (1500) is at the first frequency. By adding or subtracting, the second frequency can be determined.

[0266] For example, if the first frequency is 2 MHz, the delay time is 2, and the controller (1500) decides to increase the first frequency to determine the second frequency, the clock of the processor (1510) is 200 MHz. = {200MHz / (100-1)} - {200MHz / 100} = 0.02 MHz (where k=1), and m= 2 / 100 (where 100 is a fixed value), so becomes 0.02 x 0.02 = 0.0004 MHz. Therefore, the second frequency can be determined as (2 + 0.0004) = 2.0004 MHz.

[0267]

[0268] Meanwhile, if the controller (1500) uses the average value of the last N delay times among the delay times between the plurality of virtual signals and the plurality of output current signals that can be produced in the first section as the delay time for determining the second frequency, the average value is td_count curr can be used as

[0269] If the average is a rational number that includes a decimal point, the average is stored as td_count curr , or the value rounded up, down, or to the Mth decimal point is td_count curr can be used as td_count curr may be a rational number including a decimal point. However, it is not limited thereto, and td_count may be determined based on the convenience of calculation, the operating environment of the RF generator (1000), and the allowable error range between the resonant frequency of the load and the second frequency. curr An integer value rounded down or up to the first decimal place of the average value may also be used.

[0270]

[0271] Meanwhile, the controller (1500) may determine the second frequency according to the above-described description, but the second frequency may be a frequency that cannot be generated by the clock of the processor (1510). Therefore, in such a case, how the controller (1500) determines and generates the second frequency may be problematic, and this will be examined in detail.

[0272] The method for generating the second frequency described below has been mentioned in connection with step S720 of FIG. 7. That is, the method for generating the second frequency described below relates to a method for determining and generating the second frequency by considering at least one outputtable frequency in addition to the first frequency and the clock of the processor (1510) mentioned above.

[0273] Meanwhile, as described above, the third frequency output in the first frequency and the third section may also be generated according to the method described below. For example, if the first frequency is not included in at least one outputtable frequency, the controller (1500) may output the first AC voltage having the first frequency by using a plurality of outputtable frequencies close to the first frequency among the at least one outputtable frequency (e.g., the closest outputtable frequency that is larger than the first frequency and the closest outputtable frequency that is smaller than the first frequency) according to the method below.

[0274] [Table 3] below shows the output frequencies that can be output using the clock of the processor (1510) when the clock of the processor (1510) is 200 MHz.

[0275] Clock clock count of processor (1510) Voltage frequency of RF Difference from the following frequency 200,000,000603,333,33354,645200,000,000613,278,68952,882200,000,000623,225,80651,203200,000,000633,174,60349,603200,000,000643,125,00048,077200,000,000653,076,92346,620200,000,000663,030,30345,228200,000,00067 2,985,07543,898200,000,000682,941,17642,626200,000,000692,898,55141,408200,000,000702,857,14340,241200,000,000712,816,90139,124200,000,000722,777,77838,052200,000,000732,739,72637,023200,000,000742,702,70336,036

[0276] Referring to the above-described [Table 3], even if the controller (1500) determines the second frequency to be 3 MHz, the clock of the processor (1510) cannot actually generate 3 MHz. In other words, referring to [Table 3], when the clock count value is 66, a frequency of 3.03 MHz can be generated, and when the clock count value is 67, a frequency of 2.98 MHz can be generated, so it is impossible to generate a frequency of exactly 3 MHz with only a single count value.

[0277] However, since the resonant frequency of the load does not vary in consideration of the clock of the processor (1510), a method is needed to generate a frequency that is as close as possible to the resonant frequency of the load that varies with the limited clock of the processor (1510).

[0278] For example, when the quality factor of the load driven by the RF generator (1000) is high, the magnitude and phase of the output current of the inverter (1300) may change more steeply depending on the frequency. Therefore, in order to track the resonant frequency of the variable load more quickly, it is necessary to be able to output by adjusting the frequency more precisely. Meanwhile, a case where the quality factor of the load is high here may include, for example, a situation where a large amount of plasma is discharged.

[0279]

[0280] To this end, referring to FIG. 11, a method for generating a frequency that is as close as possible to the resonant frequency of the load by using the outputtable frequencies that can be output as the clock of the processor (1510) will be described. As mentioned above, the series of processes described based on FIG. 11 can be viewed as a more specific version of step S720.

[0281] Accordingly, the series of processes (S1105 to S1135) described with reference to FIG. 11 may be those performed during the processes corresponding to S720 to S725 in FIG. 7.

[0282] Referring to FIG. 11, the controller (1500) can determine the second frequency based on the first frequency and delay time according to the above-described method (S1105, S720).

[0283] The controller (1500) determines whether the second frequency is included in the outputtable frequencies that can be output according to the clock of the processor (1510) (S1110). If the determined second frequency is included in the outputtable frequencies that can be output according to the clock of the processor (1510), the controller (1500) can output a wave of a second control signal that controls a second AC voltage having the second frequency to be output by the inverter (1300) (i.e., applied to the load) during the second period as described above (S1115, S725).

[0284] If the determined second frequency is not included in the outputtable frequencies that can be output according to the clock of the processor (1510), a plurality of outputtable frequencies that are closest to the second frequency can be selected from among the outputtable frequencies (S1120). At this time, the number of outputtable frequencies that the controller (1500) selects can be determined according to a predefined setting, or the controller (1500) can select a number of outputtable frequencies that can create a frequency that is closest to the second frequency by combining a number of cases.

[0285] For example, if it is possible to generate a frequency that is closer to the second frequency and has a larger first outputtable frequency and a smaller second outputtable frequency that is closer to the second frequency and has a difference of less than a certain value, the controller (1500) can select two outputtable frequencies. If selecting four outputtable frequencies can generate a frequency closer to the second frequency than selecting two outputtable frequencies, the two largest first outputtable frequencies that are closer to the second frequency and the two smallest second outputtable frequencies that are closer to the second frequency can be selected.

[0286] However, since a frequency close to the second frequency can be generated only when an output frequency close to the second frequency and a small output frequency close to the second frequency are selected among a plurality of output frequencies, it may be preferable that the selected output frequencies be an even number.

[0287] The controller (1500) can determine the difference values ​​between each of the selected closest multiple output-capable frequencies and the second frequency (S1125). For example, if two closest multiple output-capable frequencies are selected, a first difference value between the closest and largest first output-capable frequency and the second frequency, and a second difference value between the closest and smallest second output-capable frequency and the second frequency can be determined.

[0288] The controller (1500) can determine the number of outputs of each of the closest plurality of outputtable frequencies based on the ratio of the difference values ​​(S1130). For example, the difference value between the first outputtable frequency and the second outputtable frequency or the third difference value which is the sum of the first difference value and the second difference value can be determined, and the number of outputs of each of the first outputtable frequency and the second outputtable frequency can be determined based on the ratio between (first difference value / third difference value) and (second difference value / third difference value).

[0289] The controller (1500) may output a plurality of third control signals so that each of the closest plurality of output frequencies can be output as evenly as possible during the second section according to the determined number of outputs. For example, the controller (1500) may output at least one third control signal corresponding to the first output-capable frequency and one or more third control signals corresponding to the second output-capable frequency to the inverter (1300) as evenly as possible during the second section according to the respective corresponding numbers (S1135). It is a fact obvious to those skilled in the art that if S1135 is performed, S725 will be omitted or replaced by S1135. That is, if the second frequency is not included in the plurality of output-capable frequencies, the controller (1500) may output a plurality of third control signals instead of the wave of the second control signal.

[0290] Meanwhile, when the controller (1500) outputs at least one third control signal corresponding to the first output-capable frequency and at least one third control signal corresponding to the second output-capable frequency as evenly as possible, rather than first outputting all of the third control signals corresponding to the first output-capable frequency among the closest plurality of output-capable frequencies according to the corresponding number of times and then later outputting all of the third control signals corresponding to the second output-capable frequency according to the corresponding number of times, it can be observed that an output current having an ideal frequency while approaching the second frequency is sensed. The detailed effect thereof will be described later with reference to FIG. 14.

[0291] Meanwhile, here, the meaning of outputting the third control signals corresponding to the closest multiple output possible frequencies as evenly as possible can be interpreted as one of the following definitions.

[0292] The first may mean that the output is distributed uniformly between the third control signals corresponding to each of the closest multiple outputtable frequencies.

[0293] The second may mean outputting such that the deviation between the third control signals corresponding to each of the closest multiple outputtable frequencies is maximized.

[0294] Thirdly, among the third control signals corresponding to each of the closest plurality of output-capable frequencies, two of the third control signals corresponding to the largest number of output-capable frequencies are arranged at the beginning and the end of one set, and the third control signals according to the remaining output-capable frequencies are arranged alternately in the middle positions, and the plurality of sets generated by the above-described method are controlled to be output in sequence. At this time, if the largest number of times is odd, one or more sets that can be made with the corresponding number of times are created, and the remaining third control signals corresponding to the output-capable frequencies of the corresponding number of times are arranged alternately with the third control signals according to the remaining output-capable frequencies in the middle positions.

[0295] Fourth, the difference between the averages of the distances measured by pairing two of the third control signals corresponding to each of the closest multiple output possible frequencies may be minimal. For example, if there are third control signals corresponding to four output-capable frequencies, the difference between the average distance between at least one third control signal corresponding to the first output-capable frequency and at least one third control signal corresponding to the second output-capable frequency, the average distance between at least one third control signal corresponding to the first output-capable frequency and at least one third control signal corresponding to the third output-capable frequency, the average distance between at least one third control signal corresponding to the first output-capable frequency and at least one third control signal corresponding to the fourth output-capable frequency, the average distance between at least one third control signal corresponding to the second output-capable frequency and at least one third control signal corresponding to the third output-capable frequency, and the average distance between at least one third control signal corresponding to the third output-capable frequency and at least one second control signal corresponding to the fourth output-capable frequency may be minimized.

[0296]

[0297] Now, let's look at an example of a method for finely adjusting the frequency using the frequencies outputtable by the clock of the processor (1510) according to the description of FIG. 11 described above. The following description is merely an example for understanding the explanation. Therefore, the following description should be used only to aid understanding, and the scope of the present disclosure is not limited to this example.

[0298] As shown in [Table 3], if the clock of the processor (1510) is 200 MHz and the second frequency determined by S705 to S720 is 3.0 MHz, as can be seen in [Table 3], it is difficult to precisely control the frequency because the frequency of 3.0 MHz cannot be generated regardless of the clock count value used. Therefore, in this case, the controller (1500) utilizes a table or list pre-stored in the controller (1500) as shown in [Table 3] or selects 3.03 MHz (corresponding to clock count 66) and 2.98 MHz (corresponding to clock count 67), which are frequencies that are closest to 3.0 MHz and can be generated with a 200 MHz clock, through calculation of the controller (1500).

[0299] The controller (1500) determines the first difference value = (3.03 - 3.0) = 0.03 MHz, the second difference value = (3.0 - 2.98) = 0.02 MHz, and the third difference value = (3.03-2.98) = (0.03+0.02) = 0.05 MHz. Since (first difference value / third difference value) = (0.03 / 0.05) = 0.6 and (second difference value / third difference value) = (0.02 / 0.05) = 0.4, the controller (1500) outputs at least one third control signal corresponding to a frequency of 3.03 MHz and one or more third control signals corresponding to a frequency of 2.98 MHz in a ratio of 3.03 MHz : 2.98 MHz = 2:3. Meanwhile, in order to generate a frequency closer to 3.0 MHz in more detail, the controller (1500) outputs at least one third control signal corresponding to a frequency of 3.03 MHz and one or more third control signals corresponding to a frequency of 2.98 MHz at a ratio of 2:3, but outputs them so as to be distributed as evenly as possible.

[0300] An example of outputting the third control signals corresponding to frequencies of 3.03 MHz and 2.98 MHz by distributing them as evenly as possible, as in the example described above, can be seen in Fig. 12. Since the frequency is the reciprocal of the period, 335 ns corresponds to 2.98 MHz, and 330 ns corresponds to 3.03 MHz. Referring to Fig. 12, it can be seen that at least one third control signal corresponding to a frequency of 3.03 MHz and one or more third control signals corresponding to a frequency of 2.98 MHz are output alternately, but at a ratio of 2:3.

[0301] In other words, Fig. 11 shows that the third control signals consisting of a set of {2.98 - 3.03 - 2.98 - 3.03 - 2.98} are repeatedly output during the second period.

[0302] Figure 13 shows the experimental results on the degree to which the frequency is finely adjusted when output as in Figure 12 and when it is not. Referring to Figure 13, when the 2.98 MHz frequency and the 3.03 MHz frequency are output as evenly as possible at an appropriate ratio as in Figure 13 (b), it can be seen that a frequency of 3.00 MHz is generated. However, when the 2.98 MHz frequency is output more than the appropriate ratio as in Figure 13 (a), a frequency smaller than 3.00 MHz is generated, and when the 3.03 MHz frequency is output more than the appropriate ratio as in Figure 13 (c), it can be seen that a frequency larger than 3.00 MHz is generated.

[0303] Fig. 14 is an experimental result comparing a case where the third control signals of 2.98 MHz and 3.03 MHz frequencies are output as evenly as possible at an appropriate ratio and a case where the third control signals of 2.98 MHz and 3.03 MHz frequencies are output as evenly as possible at an appropriate ratio, and a case where the third control signals of 2.98 MHz and 3.03 MHz frequencies are output as evenly as possible at an appropriate ratio, and the output current of the inverter (1300) measured can be seen to be close to an ideal waveform. However, it can be seen that the output current of the inverter (1300) measured in a case where the third control signals of 2.98 MHz and 3.03 MHz frequencies are output as evenly as possible at an appropriate ratio, does not form an ideal waveform.

[0304]

[0305] Hereinafter, in the present disclosure, an example of a structure of a control signal output unit (1570) for outputting a wave of a second control signal for controlling a second AC voltage having a second frequency to be applied to a load according to FIG. 7 and other examples of fine frequency control using this structure will be examined.

[0306] Fig. 15 shows an example of a structure of a control signal output unit (1570). Referring to Fig. 15, the control signal output unit (1570) may include a digital signal output unit (1575), a DAC (Digital to Analog Converter, 1580), a filter (1585), and a comparator (1590).

[0307] The digital signal output unit (1575) can output a bit string of a preset size according to the second frequency and / or jump step determined by the frequency determination unit (1550). For example, if the preset size is 4, the digital signal output unit (1575) can output 4 bits. In addition, the digital signal output unit (1575) can output a bit string of a preset size every time corresponding to the clock of the processor (1510). For example, if the clock of the processor (1510) is 5 ns corresponding to a frequency of 200 MHz, the digital signal output unit (1575) can output a bit string based on the jump step every 5 ns. Here, the method of determining the jump step and the method of the digital signal output unit (1575) outputting the bit string according to the jump step will be described in detail later. In addition, the digital signal output unit (1575) may be a DDS (Direct Digital Synthesizer), but is not limited thereto, and any device capable of outputting a bit string of a preset size according to the clock of the processor (1510) may be used as the digital signal output unit (1575).

[0308] Meanwhile, the digital signal output unit (1575) can map and store 2^n points and values ​​(e.g., bit strings) for each of the 2^n points. Here, the values ​​for each of the 2^n points can represent the magnitude value of the reference sinusoidal wave at the time when each point is arranged, assuming that 2^n points are arranged at equal intervals on the time axis within one period of the reference sinusoidal wave. Here, the reference sinusoidal wave can correspond to the clock frequency of the processor (1510). For example, when the clock of the processor (1510) has a frequency of 200 MHz (i.e., a period of 5 ns), the reference sinusoidal wave can be assumed to be a sinusoidal wave having a period of 5 ns. However, the reference sinusoidal wave is not necessarily limited to being a sinusoidal wave having the clock frequency of the processor (1510), and may be an arbitrarily set sinusoidal wave.

[0309] The 2^n points stored in the digital signal output unit (1575) and the values ​​mapped to each of the 2^n points will be described in more detail through Fig. 16.

[0310] Fig. 16 shows 16 points (p1 to p16) arranged at equal intervals on the time axis within one cycle of a reference sinusoidal waveform when n=4. The magnitude values ​​(i.e., BS0 to BS8) of the reference sinusoidal waveform at each point in time of the 16 equally arranged points (p1 to p16) can be mapped to each point and stored in the digital signal output unit (1575). For example, referring to Fig. 16, p1 and p9 can be stored by being mapped to the BS0 value, p2 and p8 can be stored by being mapped to the BS1 value, p3 and p7 can be stored by being mapped to the BS2 value, and the remaining points can also be stored by being mapped to their corresponding BS values. Here, BS can mean a bit sequence to be output from the digital signal output unit (1575). That is, the digital signal output unit (1575) can store each point by mapping the size value of the reference square wave corresponding to each point in the form of a bit string. However, the value mapped to each point does not necessarily have to be mapped and stored in the form of a bit string, and may be stored in another form corresponding to the bit string output by the digital signal output unit (1575). In addition, the size of the bit string output by the digital signal output unit (1575) may be n, but is not necessarily limited thereto. For example, the size of the bit string output by the digital signal output unit (1575) may be n or less. For example, the digital signal output unit (1575) may output only m MSBs (most significant bits) among the n bits of the DAC (1580).

[0311] The DAC (1580) can receive the bit string output from the digital signal output unit (1575) and generate an analog signal based on the bit string. Meanwhile, since the bit string is output at each time corresponding to the clock of the processor (1510), the DAC (1580) can also output an analog signal of the same size during the time corresponding to the clock of the processor (1510). For example, if the clock of the processor (1510) is 5 ns and the value of the bit string received from the digital signal output unit (1575) is 1, the DAC (1580) can output an analog signal having a size of 1 for 5 ns.

[0312] The filter (1585) can remove a specific frequency band from the analog signal output from the DAC (1580). For example, the filter (1585) can be a low pass filter (LPF), and can remove high frequency components from the analog signal output from the DAC (1580) and leave only low frequency components. Accordingly, the filter (1585) can make the analog signal output from the DAC (1580) into an analog signal in the form of a square wave. That is, the filter (1585) smoothes the envelope of the analog signal output from the DAC (1580). Here, the analog signal in the form of a square wave is not limited to an analog signal in the form of a perfect square wave. In other words, the analog signal in the form of a square wave can be said to be an analog signal in the form of a square wave if it is a sine or cosine signal with a smoother envelope because high frequency components are removed more than before by passing through the low pass filter.

[0313] A comparator (1590) compares the size of an analog signal in the form of a square wave output from a filter (1585) with a specific value (e.g., 0), and outputs a signal having a size of +A if the size of the analog signal is greater than the specific value, and outputs a signal having a size of 0 or -B if the size of the analog signal is less than the specific value.

[0314] The output signal output from the comparator (1590) is used as a control signal. That is, the comparator (1590) outputs a control signal or a wave of a control signal that turns on / off the switches (e.g., four switches) included in the inverter (1300).

[0315] Meanwhile, as shown in FIG. 5 and FIG. 15, the wave of the control signal output from the comparator (1590) can be input to the switches included in the inverter (1300) through the buffer.

[0316] Based on an example of the structure of the control signal output unit (1570) described through FIGS. 15 to 16, an example of generating a wave of a control signal for outputting a second AC voltage having a second frequency determined according to a frequency determination unit (1550) is examined through FIGS. 17 to 20.

[0317] Referring to FIGS. 17 to 20, the frequency determination unit (1550) determines a second frequency based on the first frequency and the delay time (S1705). At this time, the process and method for determining the second frequency can be applied in the same manner as described in S705 to S720 of FIG. 7, and therefore, a detailed description thereof will be omitted.

[0318] The frequency determination unit (1550) determines a jump step for generating a wave of the second control signal based on the determined second frequency (S1710). Here, the frequency determination unit (1550) determines the jump step according to [Mathematical Formula 8] below.

[0319]

[0320] Here, fc is the clock frequency of the processor (1510). M represents a jump step. 2^n is the number of points stored in the digital signal output unit (1575) as described above.

[0321] For example, if the frequency determination unit (1550) determines the second frequency as 50 MHz, fc is 200 MHz, and n is 4, M can be determined as 4.

[0322] Meanwhile, the digital signal output unit (1575) can output a value corresponding to at least one point according to the jump step M. At this time, the digital signal output unit (1575) can output at least one value corresponding to each clock of the processor (1510) (S1715). For example, the digital signal output unit (1575) can output a size value corresponding to each point at 4-point intervals. For example, referring to FIG. 16, the digital signal output unit (1575) can output BS0 corresponding to p1, BS4 corresponding to p5, BS0 corresponding to p9, and then BS8 corresponding to p13. After the digital signal output unit (1575) outputs BS8 corresponding to p13, it can output BS0 corresponding to p1 again using a jump step of 4. That is, the digital signal output unit (1575) can output a bit string corresponding to each point while cycling through p1 to p16 according to the determined jump step.

[0323] At this time, the digital signal output unit (1575) can output BS0 corresponding to p1, output BS4 corresponding to p5 after 5 ns, which is the clock cycle of the processor (1510), output BS0 corresponding to p9 after 5 ns again, and output BS 8 corresponding to p13 after 5 ns again.

[0324] Referring to FIG. 18, it can be seen that the digital signal output unit (1575) outputs a bit sequence (BS) corresponding to each point.

[0325] The bit string output from the digital signal output unit (1575) can be converted into an analog signal by the DAC (1580) (S1720). Here, since the digital signal output unit (1575) outputs a bit string for each clock cycle of the processor (1510), the analog signal converted by the DAC (1580) can also output an analog signal having the same value during a period corresponding to the clock cycle (e.g., 5 ns). For example, if the digital signal output unit (1575) outputs the bit string of BS4, the DAC (1580) can output an analog signal having a size corresponding to the bit string of BS4 for 5 ns. Therefore, as can be seen in FIG. 18, the envelope of the square wave of the analog signal output from the DAC (1580) is formed in a step shape, which means that the analog signal output from the DAC (1580) contains a significant amount of high-frequency components.

[0326] The analog signal output from the DAC (1580) passes through the filter (1585) and is filtered (S1725). As can be seen in Fig. 18, the analog signal passing through the filter (1585) has its high-frequency components removed, forming a smooth envelope.

[0327] The filtered analog signal is input to a comparator (1590), and the comparator (1590) can compare the magnitude of the filtered analog signal with a specific value to generate a second control signal (S1730). Referring to FIG. 18, the second control signal output from the comparator (1590) has a second frequency determined by the frequency determination unit (1550). In addition, the second control signal operates switches (e.g., four switches) included in the inverter (1300), so that a second AC voltage having a second frequency is output from the inverter (1300).

[0328] Figures 19 and 20 show that a digital signal output unit (1575) outputs a bit string according to a jump step determined from a frequency determination unit (1550), and a DAC (1580) outputs an analog signal based on the output bit string.

[0329] Referring to FIG. 19, the digital signal output unit (1575) stores 2^n points set at equal intervals within one cycle of the reference sine wave as described in FIG. 17, and the values ​​corresponding to each point. It can be seen that this storage form is expressed in the form of a digital phase wheel.

[0330] However, the values ​​corresponding to each of the 2^n points may be stored in the digital signal output unit (1575) in the form of a look-up table. For example, each of the 2^n points may be mapped to a value corresponding to each point (e.g., BS 0 to BS 8) and stored in the form of a look-up table.

[0331] Fig. 19 shows that the frequency determination unit (1550) determines the jump step to 1. In this case, the digital signal output unit (1575) outputs a bit string corresponding to each point at 1-point intervals for each clock of the processor (1510). In addition, the DAC (1580) that receives the bit string output by the digital signal output unit (1575) outputs an analog signal having a size corresponding to each bit string.

[0332] Referring to Fig. 20, the analog signals output from the DAC (1580) when the jump step is 1 and when the jump step is 2 are shown. Fig. 20(a) shows the analog signal output when the jump step is 1, and Fig. 20(b) shows the analog signal output when the jump step is 2.

[0333] Comparing Fig. 20(a) and Fig. 20(b), it can be seen that the frequency of the analog signal when the jump step is 2 is twice the frequency of the analog signal when the jump step is 1. In other words, it can be seen that the period of the analog signal when the jump step is 2 is 1 / 2 times the period of the analog signal when the jump step is 1.

[0334] By adjusting the jump step in this way, the period or frequency of the analog signal can be adjusted, and the analog signal with the adjusted period or frequency can be converted into a control signal having an adjusted frequency through a filter (1585) and a comparator (1590), and the control signal having the adjusted frequency can be applied to the switches of the inverter (1300) to output an AC voltage having an adjusted frequency.

[0335] Accordingly, referring to FIG. 19, FIG. 20 and [Mathematical Formula 8], if the jump step is 1, an analog signal having a frequency 1 / (2^n) times the clock of the processor (1510) is output from the DAC (1580). If the jump step is K, an analog signal having a frequency K / (2^n) times the clock of the processor (1510) is output from the DAC (1580).

[0336] Referring to this, it can be seen that the larger n is, the more precisely the frequency of the analog signal can be adjusted. For example, if the clock frequency of the processor (1510) is 200 MHz and n is 4, the minimum frequency of the analog signal output from the DAC (1580) is 12.5 MHz, and the frequency of the analog signal can be adjusted in units of 12.5 MHz.

[0337] On the other hand, for example, if the clock frequency of the processor (1510) is 200 MHz and n is 16, the minimum frequency of the analog signal output from the DAC (1580) is 3.052 kHz, and the frequency of the analog signal can be adjusted in units of 3.052 kHz.

[0338] That is, as the n value increases, the frequency of the analog signal output from the DAC (1580) can be adjusted more finely. In addition, the analog signal output from the DAC (1580) is converted into a second control signal through a filter (1585) and a comparator (1590). At this time, the second control signal has the same frequency as the analog signal, and the frequency of the second control signal becomes the same as the frequency of the output voltage of the inverter (1300). Therefore, as the n value increases, the frequency of the output voltage can also be adjusted more finely.

[0339] Figure 21 shows that the frequency of the processor (1510) clock is 200 MHz (i.e., the period is 5 ns), and one period of the reference sine wave is set to 2^n points to generate a frequency of 3 MHz. Here, n is 32 or more and 48 or less.

[0340] Referring to Fig. 21, in order to generate a frequency of 3 MHz, the jump step is determined as l. For example, l can be determined as 64,424,509 when n is 32, and l can be determined as 4,222,124,650,659 when n is 48. The digital signal output unit (1575) outputs a bit string corresponding to each point at l point intervals according to the clock of the processor (1510), and a second AC voltage having a frequency of 3 MHz is generated and output according to a second control signal generated through a DAC (1580), a filter (1585), and a comparator (1590).

[0341] As shown in Fig. 21, it can be seen that the frequency can be controlled more precisely by dividing the structure and reference sine wave of the control signal output unit (1570) disclosed in Fig. 15 into 2^n points, storing the values ​​corresponding to each point, and then adjusting the frequency of the sine wave using a jump step.

[0342]

[0343] The method according to the embodiment may be implemented in the form of program commands that can be executed through various computer means and recorded on a computer-readable medium. The computer-readable medium may include program commands, data files, data structures, etc., alone or in combination. The program commands recorded on the medium may be those specially designed and configured for the embodiment or may be those known and available to those skilled in the art of computer software. Examples of the computer-readable recording medium include magnetic media such as hard disks, floppy disks, and magnetic tapes, optical media such as CD-ROMs and DVDs, magneto-optical media such as floptical disks, and hardware devices specially configured to store and execute program commands, such as ROMs, RAMs, and flash memories. Examples of the program commands include not only machine language codes generated by a compiler, but also high-level language codes that can be executed by a computer using an interpreter, etc. The hardware devices described above may be configured to operate as one or more software modules to perform the operations of the embodiment, and vice versa.

[0344] Although the embodiments described above have been described by way of limited examples and drawings, those skilled in the art will appreciate that various modifications and variations can be made based on the above teachings. For example, appropriate results can still be achieved even if the described techniques are performed in a different order than described, and / or components of the described systems, structures, devices, circuits, etc. are combined or combined in a different manner than described, or are replaced or substituted with other components or equivalents.

[0345] Therefore, other implementations, other embodiments, and equivalents to the claims also fall within the scope of the claims described below.

Claims

1. In a frequency control device that controls the frequency of an AC voltage applied to a load according to the variable resonant frequency of the load, An inverter having at least two switches electrically interposed between a DC power source and terminals electrically connected to the load, and applying the AC voltage to the load through the terminals, wherein the AC voltage has a frequency determined by the operation of the at least two switches; and A controller having a processor and generating a control signal for controlling the operation of at least two switches based on a clock of the processor; The controller outputs a first control signal that controls the at least two switches so that a first AC voltage having a first frequency is applied to the load during a first period, Assume the wave of the virtual signal corresponding to the first frequency by shifting the wave of the first control signal by a predetermined amount of time, Based on the clock, the delay time between the wave of the virtual signal and the wave of the output current of the inverter in the first section is determined in at least some section within the first section, (i) determining a second frequency based on at least one outputtable frequency that can be determined using the first frequency, (ii) the delay time, and (iii) the clock; Characterized in that, during a second period immediately following the first period, a second control signal is output for controlling the at least two switches so that an AC voltage having the second frequency is applied to the load. Frequency control device.

2. In paragraph 1, The above delay time is a difference value between a first count value counted according to the clock for a first time length from a rising edge of the wave of the virtual signal to a falling edge of the wave of the virtual signal that first appears after the rising edge, and a second count value counted according to the clock for a second time length from the rising edge to a falling edge of the wave of the output current that first appears after the rising edge. Frequency control device.

3. In paragraph 1, The second frequency is increased from the first frequency when the delay time exceeds the first value, decreased from the first frequency when the delay time is less than the second value, and is the same as the first frequency when the delay time is a value between the first value and the second value, but the first value and the second value are the same or different. Frequency control device.

4. In paragraph 1, The above-determined time is equal to the time difference between the first time point at which the wave of the first control signal is input to the inverter and the second time point at which the wave of the first control signal is expected to be output from the inverter. Frequency control device.

5. In paragraph 1, The above-determined time is greater than or less than the time difference between the first time point at which the wave of the first control signal is input to the inverter and the second time point at which the wave of the first control signal is expected to be output from the inverter. Frequency control device.

6. In paragraph 1, The controller determines the second frequency based on a difference value between the first frequency and a frequency adjacent to the first frequency among the at least one outputtable frequency multiplied by a factor based on the delay time. Frequency control device.

7. In paragraph 1, The controller determines the delay time based on the average value of the last N delay times (N is a natural number) among the delay times between the wave of the virtual signal and the wave of the output current that can be obtained during the first section. Frequency control device.

8. In paragraph 1, The controller, if the second frequency is not included in the at least one outputtable frequency, Among the at least one outputtable frequency, determining the difference values ​​between each of the plurality of outputtable frequencies closest to the second frequency and the second frequency, During the second section, a plurality of third control signals corresponding to each of the plurality of outputtable frequencies are outputted instead of the second control signal according to the number of outputs of each of the plurality of outputtable frequencies determined based on the ratio between the difference values. Frequency control device.

9. In paragraph 8, The controller outputs the plurality of control signals so that the dispersion between the plurality of third control signals is uniform according to the number of outputs of each of the plurality of outputtable frequencies. Frequency control device.

10. In a frequency control method in which a frequency control device controls the frequency of an AC voltage applied to a load according to the variable resonant frequency of the load, During the first section, a first control signal is output to control that a first AC voltage having a first frequency is applied to the load; Assume a wave of a virtual signal corresponding to the first frequency by shifting the wave of the first control signal by a predetermined amount of time; Based on a clock corresponding to the frequency control device, a delay time between the wave of the virtual signal and the wave of the output current of the inverter in the first section is determined in at least some section within the first section; (i) determining a second frequency based on at least one outputtable frequency that can be determined using the first frequency, (ii) the delay time, and (iii) the clock; and During a second period immediately following the first period, a second control signal is output to control that a second AC voltage having the second frequency is applied to the load; Frequency control method.

11. In paragraph 10, The delay time is a difference value between a first count value counted according to the clock for a first time length from a rising edge of the wave of the virtual signal to a falling edge of the wave of the virtual signal that first appears after the rising edge, and a second count value counted according to the clock for a second time length from the rising edge to a falling edge of the wave of the output current that first appears after the rising edge. Frequency control method.

12. In paragraph 10, The second frequency is, If the delay time exceeds the first value, it is an increase in the first frequency, if the delay time is less than the second value, it is a decrease in the first frequency, and if the delay time is a value between the first value and the second value, it is the same as the first frequency, but the first value and the second value are the same or different. Frequency control method.

13. In paragraph 10, The above-determined time is equal to the time difference between the first time point at which the wave of the first control signal is input to the inverter and the second time point at which the wave of the first control signal is expected to be output from the inverter. Frequency control method.

14. In paragraph 10, The above-determined time is greater than or less than the time difference between the first time point at which the wave of the first control signal is input to the inverter and the second time point at which the wave of the first control signal is expected to be output from the inverter. Frequency control method.

15. In paragraph 10, Determining the above second frequency is: determining a difference value between the first frequency and a frequency adjacent to the first frequency among the at least one outputtable frequency based on a factor based on the delay time; Frequency control method.

16. In paragraph 10, Determining the above delay time is: determining based on the average value of the last N delay times (N is a natural number) among the delay times between the wave of the virtual signal and the wave of the output current that can be obtained during the first section; Frequency control method.

17. In paragraph 10, If the second frequency is not included in the at least one outputtable frequency: Determining difference values ​​between each of a plurality of outputtable frequencies closest to the second frequency and the second frequency among the at least one outputtable frequency; and During the second section, a plurality of third control signals corresponding to each of the plurality of outputtable frequencies are outputted instead of the second control signal, based on the number of outputs of each of the plurality of outputtable frequencies determined based on the ratio between the difference values; Frequency control method.

18. In paragraph 17, Outputting the plurality of control signals includes outputting the plurality of third control signals so that the dispersion between the plurality of control signals is uniform according to the number of outputs of each of the plurality of outputtable frequencies; Frequency control method.

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