Power factor correction architecture

Abstract

A circuit architecture, comprising a plurality of circuits, each circuit comprising a phase rectifying bridge, at least two inductors, each inductor connected to an inlet and outlet of the phase rectifying bridge, at least one transistor connected between outlets of each inductor, and at least two diodes, each connected to an inlet and outlet of the transistor, the plurality of circuits capable of outputting a DC voltage at an output terminal.

Description

POWER FACTOR CORRECTION ARCHITECTURETECHNICAL FIELD

[0001] The disclosure relates to an apparatus capable of power factor correction, and to a method of using said apparatus for power factor correction.BACKGROUND ART

[0002] Typical voltage source inverter based variable frequency drives (VFDs) have an AC to DC rectifier unit with a large DC bus capacitor to smooth the voltage ripple. The DC bus capacitor draws charging current only when it is discharged into a motor load. The charging current flows into the DC bus capacitor when the input rectifier is forward biased, which occurs when the instantaneous input voltage is higher than the DC voltage across the DC bus capacitor. The pulsed current drawn from the AC source is rich in harmonics, because it is discontinuous. This type of nonlinear current flow is associated with poor input power factor. The power delivery equipment is also subject to unnecessary power loss and the overall system efficiency suffers. In light of the above-mentioned problems, alternative power topologies are needed to help improve the input power factor and lower the input current distortion, thereby increasing the system’s efficiency.

[0003] Techniques, both passive and active, may be employed to improve the current waveform and reduce the overall current harmonics. The active techniques have advantages over the passive techniques, from size and performance viewpoints. However, the cost of certain type of active techniques can be higher than the cost of passive techniques.

[0004] Three phase power factor corrector circuits are known, as well as circuitry capable of rectifying a signal with a three-phase rectifying bridge. FIG. 1 shows a known circuitry configuration capable of rectifying with a three-phase rectifying bridge. The circuit illustrated in FIG. 1 comprises a three-phase rectifying bridge connected to an input capacitor and the load. This circuitry creates a high current peak in the main line and, if the line impedance is high, it can also create distortion on the voltage. Further, without any kind of power factor correction, the power factor will be very low, in the range of 0.6, and the harmonic content of the three currents of sources VI and V2 and V3 will be very high.

[0005] With a circuit having the topology of FIG. 1, at any given instant of time, three semiconductor devices are operating — either three diodes and a semiconductor switch or three diodes. This reduces power loss in the boost converter, thereby improving system efficiency. But, the DC inductor needs to be designed to handle the DC component, which can make it bulky. The AC inductors can be made smaller since the flux in the core is not unidirectional. Further, the input AC inductor also helps reduce conducted Electro Magnetic Interference (EMI) noise. But the control requires sensing the input current through all the boost inductors. This can be an involved process.

[0006] To address this problem, other three phase PFC controller architectures have been developed. Active PFC systems can be divided in two types: direct three phase systems, and phase modular systems. Phase modular systems can be further divided in Y rectifiers or Delta rectifiers. The direct three phase rectification systems can have multiple configurations. The Vienna architecture is the most common of such architectures, as shown in FIG. 2.

[0007] The illustrated configuration allows good power factor correction performances and efficiency, while using only three controlled switches and 18 discrete diodes. The success of this architecture is due to the fact that all the required components are rated 650V because they are connected between the input phase and a “virtual neutral”. The introduction of SiC allows comparable performances between 650V and 1200V devices.

[0008] One of the main drawbacks of such a configuration is the high number of discrete diodes required, and also the presence of a control algorithm that requires digital control with firmware, and such firmware requires a long time for setup and debugging of the control. The Vienna rectifier system is an unidirectional converter. It can function only in the rectifier mode, it does not work in the inverter mode, and the generation of the reactive power is strongly restricted. Usually, the Vienna rectifier is controlled on the basis of the direct current control method. However, this method lets improper control sequences appear. The application of the Vienna rectifier in the field of electric DC drives is restricted to the systems with low dynamics without regenerating braking.

[0009] In contrast with the solutions presented in the art, what are needed are solutions that use off-the-shelf, single phase power factor control controllers, that are easy to design.

[0010] FIG. 3 is a prior art electrical schematic of a phase modular power factor correction circuit. This circuit is using an autotransformer to have a “center star” point. As may be observed in the figure, the zigzag auto transformer 20 may be of conventional constructionand provides a neutral point N. As indicated, the current flowing into the zigzag neutral N is zero. The DC outputs of the three single phase boost converters 22 are connected by a DC link to a load (in this case an inverter 30). The DC link output 28-32 provides a relatively fixed DC voltage for the load (inverter 30). A DC bus capacitance formed by capacitors CDCI and CDC2 is connected across a DC link to smooth voltage ripple. The active switch controller 34 comprises three separate control integrated circuits to generate the necessary gating pulses at terminals G1 and El, G2 and E2, G3 and E3, for the three single phase boost converters 22-1, 22-2 and 22-3, respectively. The integrated circuits may be, for example, UC1854 type high power factor pre-regulators. These implement average current control operation to regulate output DC voltage. Disadvantages exhibited by this configuration are that a zig-zag auto-transformer 3xVin-> 3 Vout+N is required for every specific main line, while the three power factor circuit modules have a star connection to the auto-transformer. A neutral is as well required. Inductor currents of the three modules are summed and / averaged and the timing control of the switch is calculated using the result of the calculation. The control circuit requires the rectified AC line as input.

[0011] FIG. 4 illustrates another prior art schematic, for three phase power factor correction.

[0012] The Y and delta rectifiers shown in FIG. 4 are composed by three single stage rectifiers, that cannot be placed in parallel, because their output is referred to a different phase. To use the combined output power of the three modules a dc-dc converter has to follow the rectifier stage, for insulation purposes.

[0013] The need of a dc-dc stage to insulate the three outputs reduces the overall efficiency, increases the costs and the complexity of the circuitry, and decreases its reliability.

[0014] In light of the foregoing, there remains an ongoing need for an apparatus capable of power factor correction that comprises a lower number of components and exhibits lower complexity, while it remains reliable.DISCLOSURE OF INVENTION

[0015] The devices and methods disclosed in the present application have been conceived and developed aiming to provide solutions to the above stated objective technical needs, as it will be evidenced in the following description.

[0016] In one embodiment, the present application discloses a circuit architecture capable of power factor correction.

[0017] In another embodiment, the present application discloses a voltage source inverter circuitry.

[0018] According to an aspect of the present disclosure, a circuit architecture is provided. The circuit architecture includes a plurality of circuits. Each of the circuits comprises a phase rectifying bridge, at least two inductors, at least one transistor, and at least two diodes. Each inductor is connected to an inlet and outlet of the phase rectifying bridge. The at least one transistor is connected between outlets of each of the at least two inductors. Each of the at least two diodes is connected to an inlet and outlet of the transistor. The plurality of circuits is capable of outputting a DC voltage at an output terminal.

[0019] According to another aspect of the present disclosure, the circuit architecture is capable of three phase active power factor correction. According to a further aspect of the present disclosure, the at least two inductors have an equal impedance. According to an additional aspect of the present disclosure, the at least one transistor is a silicon carbide MOSFET transistor. According to yet another aspect of the present disclosure, the circuit architecture further comprises a direct connection to a three-phase power source via a main line. According to a still further aspect of the present disclosure, the plurality of circuits has a delta connection to the main line.

[0020] According to another aspect of the present disclosure, a voltage source inverter circuitry is provided. The voltage source inverter circuitry includes a transformer for receiving three phase AC power from an AC source, a circuit architecture comprising a plurality of circuits, an inverter for receiving DC power and converting DC power to AC power, and a link circuit. Each of the circuits in the circuit architecture comprises a phase rectifying bridge, at least two inductors, at least one transistor, and at least two diodes. Each inductor is connected to an inlet and outlet of the phase rectifying bridge. The at least one transistor is connected between outlets of each of the at least two inductors. Each of the at least two diodes is connected to an inlet and outlet of the transistor. The plurality of circuits iscapable of outputting a DC voltage at an output terminal. The link circuit is connected between each DC output and the inverter circuit and comprises a DC bus having first and second rails to provide a DC voltage, and a DC bus capacitance across the first and second rails capable of smoothing voltage ripple.

[0021] According to another aspect of the present disclosure a power factor correction circuit is provided. The power factor correction circuit comprises a plurality of single-phase boost converters, each boost converter comprising: a rectifier bridge, a first inductor connected between an input of the rectifier bridge and a first node, a second inductor connected between an output of the rectifier bridge and a second node, a transistor connected between the first node and the second node, and a first diode connected between the first node and a positive output terminal, a second diode connected between the second node and the positive output terminal, wherein the plurality of single-phase boost converters are connected in a delta configuration to receive three-phase AC power, and a controller configured to operate the transistors of the plurality of single-phase boost converters to perform power factor correction.

[0022] Other features and advantages will be apparent from a review of the entire specification, including the appended claims and drawings.BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The above and other aspects, features and advantages of the various embodiments of the devices and methods disclosed herein will become more apparent from the subsequent description thereof, presented in conjunction with the following drawings, wherein:

[0024] FIG. l is a schematic for a prior art circuitry capable of rectifying with a three-phase rectifying bridge;

[0025] FIG. 2 is a schematic for a prior art circuitry for direct rectification;

[0026] FIG. 3 is a prior art electrical schematic of a phase modular power factor correction circuit;

[0027] FIG. 4 is a schematic of the prior art circuitry for phase modular rectification and power factor correction;

[0028] FIG. 5 is an electrical schematic of a circuitry, in accordance with a first embodiment of the invention; and

[0029] FIG. 6 is a block diagram of a voltage source inverter circuitry in accordance with an embodiment of the present invention.DETAILED DESCRIPTION OF THE EMBODIMENTS OF THE INVENTION

[0030] Exemplary embodiments are described below with reference to the accompanying drawings. Unless otherwise expressly stated, in the drawings the sizes, positions, etc., of components, features, elements, etc., as well as any distances therebetween, are not necessarily to scale, and may be disproportionate and / or exaggerated for clarity.

[0031] The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should be recognized that the terms “comprises” and / or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. Unless otherwise specified, a range of values, when recited, includes both the upper and lower limits of the range, as well as any sub-ranges therebetween. Unless indicated otherwise, terms such as “first,” “second,” etc., are only used to distinguish one element from another. For example, one node could be termed a “first slave stage” and similarly, another node could be termed a “second slave stage”, or vice versa.

[0032] Unless indicated otherwise, the term “about,” “thereabout,” etc., means that amounts, sizes, formulations, parameters, and other quantities and characteristics are not and need not be exact, but may be approximate and / or larger or smaller, as desired, reflecting tolerances, conversion factors, rounding off, measurement error and the like, and other factors known to those skilled in the art.

[0033] Many of the embodiments described in the following description share common components, devices, and / or elements. Like named components and elements refer to like named elements throughout.

[0034] Thus, the same or similar named components or features may be described with reference to other drawings even if they are neither mentioned nor described in the corresponding drawing. Also, even elements that are not denoted by reference numbers may be described with reference to other drawings.

[0035] Many different forms and embodiments are possible without deviating from the spirit and teachings of this disclosure and so this disclosure should not be construed as limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will convey the scope of the disclosure to those skilled in the art.

[0036] The present application discloses various systems for power factor correction. In a particular embodiment, the circuits with an architecture disclosed herein may be configured to perform power factor correction without requiring numerous elements, and complex circuitries, which is in contrast with the requirement in prior art systems.

[0037] Circuits with a topology like disclosed herein enable direct connection to a three phase main line (360-480V universal range). The three power factor correction modules have a delta connection to the main line, and as such a neutral is not required. Each inductor current and switch time is individually calculated for each phase. Overcurrent protection is possible. The control circuit does not require the rectified AC line as input. As such the number of elements is reduced, and the size requirements for these topologies are reduced while compared with the solutions provided by the known art. Reduced overall size, complexity, development time and costs are among the advantages exhibited by the topology proposed by embodiments of the present invention, as it will be explained in detail herein.

[0038] FIG. 5 shows an electrical schematic of a circuitry, in accordance with a first embodiment of the invention. Unlike prior art power factor correction (PFC) circuitry, the power factor correction (PFC) circuitry disclosed in the present application eliminates the need for a dc-dc converter following the rectifier stage, thereby reducing system cost and complexity. Further, the power factor correction (PFC) circuitry disclosed in the present application uses off-the-shelf, single Phase PFC controllers, that are easy to design.

[0039] It is desirable to perform the power factor correction on non-linear loads to reduce the harmonic content, and as such to allow the main line voltage to remain sinusoidal. Furter, to reduce the RMS current on the main line, so there will be also a reduction in losses on the main line.

[0040] As evident from the schematics illustrated in FIG. 5, the present application proposes a circuitry comprising a small number of devices. As such, the density of elements is much lower (compared with the solutions proposed in the art) and implicitly the power consumption and the heat which emanates from this circuitry is much lower. On the otherhand, its reliability is much higher due at least to the lower number of elements. Further, the approach of FIG. 5 uses off the shelf, single phase PFC controlled s) that are easy to design.

[0041] Specifically, the circuitry 50 of FIG. 5 comprises a plurality of circuits 50.1 to 50.3, each circuit comprising: a phase rectifying bridge 502, at least two inductors 504, each inductor 504 connected to an inlet and outlet of the phase rectifying bridge 502, at least one transistor 506 connected between outlets of each of the at least two inductors 504, and at least two diodes 508, each connected to an inlet and outlet of the transistor 506, the plurality of circuits 50.1 to 50.3 capable of outputting a DC voltage at an output terminal 516. The circuit 50 is capable of three phase active power factor correction. The at least two inductors 504 have an equal impedance. The transistors 506 may be a silicon carbide MOSFET transistor. The circuit architecture of FIG. 5 also comprises a direct connection to a three phase power source via a main line. The circuits have a delta connection to the main line.

[0042] Further, the diodes 508 illustrated in FIG. 5 may be silicon carbide diodes. The illustrated three phases 50.1, 50.2 and 50.3 are the same. The working strategy of the single stage is the working strategy of a boost converter, if the MOSFET transistor 506 is closed. The two inductors 504 begin to charge and draw current. Once the MOSFET transistor 506 opens, the two inductors 504 discharge through the diodes 508. The energy stored in the two inductors 504 flows to the DC bus capacitance 514 and charges the capacitance. The DC link circuit comprises a DC bus having first and second rails (+) and (-) 510 and 512 to provide a relatively fixed DC voltage for any circuitry connected to the output terminals 516 V0+ and V0-. The DC bus capacitance 514 is formed across the first 510 and second 512 rails to smooth voltage ripple.

[0043] Therefore, to summarize, FIG. 5 illustrates a power factor correction circuit, comprising a plurality of single-phase boost converters, each boost converter comprising a rectifier bridge, a first inductor connected between an input of the rectifier bridge and a first node, a second inductor connected between an output of the rectifier bridge and a second node, a transistor connected between the first node and the second node, and a first diode connected between the first node and a positive output terminal, a second diode connected between the second node and the positive output terminal. The single-phase boost converters are connected in a delta configuration to receive three-phase AC power. The power factor correction circuit also comprises a controller configured to operate the transistors of the plurality of single-phase boost converters to perform power factor correction. The controller comprises a master stage and two slave stages, the master stage configured to calculate acurrent setpoint for itself and the two slave stages. The first and second inductors of each single-phase boost converter have equal inductance values. The power factor correction circuit also comprises a DC bus capacitance connected across the positive output terminal and a negative output terminal, wand the DC bus capacitance comprises a film capacitor.

[0044] The above-described topology is able to overcome the complexity described above in connection with the prior art devices by at least adding one diode on the source side of the switch, splitting the inductor and using an insulated gate driver to drive the three switches.

[0045] In this way the switch becomes “floating” and, when is opened, it follows the voltage superimposed by the two discharging inductors. Splitting the two inductors can also be useful to spread the heat, as these systems are used in high power converters.

[0046] Sharing the current between the three modules is realized by defining one master stage and two slaves. The output of the voltage compensator of the master stage is used as a current setpoint for the remaining two slave stages. This arrangement allows to have a circuitry that even in case of an unbalanced system maintains the currents between the phases proportional to the voltages, as if it would be a resistive load.

[0047] FIG. 6 is a block diagram of the voltage source inverter circuitry in accordance with embodiments of the present invention.

[0048] The voltage source inverter circuitry of FIG. 6 is illustrated as comprising a transformer for receiving three phase AC power from an AC source (not illustrated in the figure). Exemplarily, the current between the three modules is realized by defining one master stage and two slave stages. The power factor correction circuit may have the topology illustrated in Fig. 5 and an inverter receiving DC power and converting the received DC power to AC power. The circuitry also comprises a link circuit connected between each DC output of the PFC power stage and the inverter stage circuit, exemplarily comprising a DC bus having first and second rails to provide a DC voltage, and a DC bus capacitance across the first and second rails capable of smoothing voltage ripple.

[0049] The inverter stage converts for example 800 Volts to 18,000 Volts. As shown, the three-phase rectifying bridge known from the art, has been replaced in FIG. 6 by the power factor correction circuitry proposed by embodiments of the present invention.

[0050] The systems know from the art are able to provide sinusoidal a current, but they need software. They are more complicated. Since they have more parts, they exhibit a lower reliability.

[0051] Further, compared to the systems available in the art, the presence of an electrolytic capacitor is also eliminated. Such electrolytic capacitors are known to have issues with service life length and they are also bulky. In contrast, the solution proposed by embodiments of the present invention comprises only six diodes and a low value output film capacitor.

[0052] Described in terms of a block diagram, the system is composed of three stages that are exactly the same from the power point of view, while the control is slightly different. The block diagram comprises a master stage and two slave stages for AC current delivery. The master stage calculates a current setpoint for itself and the other two slaves. Such a configuration allows the maintenance of the power factor correction to the power factor at near to one even in case of unbalancing of the three phases.

[0053] The devices disclosed herein exhibit an improved implementation compared to direct three phase rectification, since they do not require the digital control of the full bridge totem pole configuration. Further, they exhibit reduced complexity and cost compared to the traditional phase modular design. The proposed circuitry has increased efficiency compared to the traditional phase modular design. The proposed circuitry has no need for bulky and electrolytic capacitors, and the lifetime and reliability of the circuitry is increased compared to the traditional phase modular design. Since it employs small inductors, the heat management is simplified. The solutions proposed by embodiments of the present invention exhibit reduced EMI: all the controllers are referenced to the same ground; they can be phased 120° one to each other to reduce the high voltage ripple on the bus and reduce the bus capacitance. It is also possible to introduce frequency dithering, to spread emissions. The proposed circuitry exhibits excellent power factor compared to the three-phase bridge rectifier. As far as the input voltage range: with a single device realized in accordance with embodiments of the invention it is possible to cover worldwide applications, because of extended input voltage range. Warehousing and spare parts can be reduced.

[0054] The embodiments disclosed herein are illustrative of the principles of embodiments of the invention. It will be appreciated by those skilled in the art that there are many possible modifications to be made to the specific forms of the features and components of the disclosed embodiments while keeping within the spirit of the concepts disclosed herein. Accordingly, no limitations to the specific forms of the embodiments disclosed herein should be read into the claims unless expressly recited in the claims.

[0055] Although a few embodiments have been described in detail above, other modifications are possible. For example, the logic flows depicted in the figures do not require the particular order shown, or sequential order, to achieve desirable results.

[0056] Other steps may be provided, or steps may be eliminated, from the described flows, and other components may be added to, or removed from, the described systems. Other embodiments may be within the scope of the following claims.

Claims

WHAT IS CLAIMED:

1. A circuit architecture, comprising: a plurality of circuits, each of said circuits comprising: a phase rectifying bridge; at least two inductors, each inductor connected to an inlet and outlet of the phase rectifying bridge; at least one transistor connected between outlets of each of said at least two inductors; and at least two diodes, each connected to an inlet and outlet of said transistor, said plurality of circuits capable of outputting a DC voltage at an output terminal.

2. The circuit architecture of claim 1, wherein said circuit architecture is capable of three phase active power factor correction.

3. The circuit architecture of claim 1, wherein said at least two inductors have an equal impedance.

4. The circuit architecture of claim 1, wherein said at least one transistor is a silicon carbide MOSFET transistor.

5. The circuit architecture of claim 1, further comprising a direct connection to a three- phase power source via a main line.

6. The circuit architecture of claim 5, wherein said plurality of circuits have a delta connection to said main line.

7. A voltage source inverter circuitry, comprising: a transformer for receiving three phase AC power from an AC source; a circuit architecture comprising a plurality of circuits, each of said circuits comprising: a phase rectifying bridge; at least two inductors, each inductor connected to an inlet and outlet of the phase rectifying bridge; at least one transistor connected between outlets of each of said at least two inductors; and at least two diodes, each connected to an inlet and outlet of said transistor, said plurality of circuits capable of outputting a DC voltage at an output terminal; an inverter for receiving DC power and converting DC power to AC power; and a link circuit connected between each DC output and the inverter circuit comprising a DC bus having first and second rails to provide a DC voltage, and a DC bus capacitance across the first and second rails capable of smoothing voltage ripple.

8. The voltage source inverter circuitry of claim 7, wherein said circuit architecture is capable of three phase active power factor correction.

9. The voltage source inverter circuitry of claim 7, wherein said at least two inductors have an equal impedance.

10. The voltage source inverter circuitry of claim 7, wherein said at least one transistor is a silicon carbide MOSFET transistor.

11. The voltage source inverter circuitry of claim 7, further comprising a direct connection to a three-phase power source via a main line.

12. The voltage source inverter circuitry of claim 11, wherein said plurality of circuits have a delta connection to said main line.

13. A power factor correction circuit, comprising: a plurality of single-phase boost converters, each boost converter comprising: a rectifier bridge; a first inductor connected between an input of the rectifier bridge and a first node; a second inductor connected between an output of the rectifier bridge and a second node; a transistor connected between the first node and the second node; and a first diode connected between the first node and a positive output terminal; a second diode connected between the second node and the positive output terminal; wherein the plurality of single-phase boost converters are connected in a delta configuration to receive three-phase AC power; and a controller configured to operate the transistors of the plurality of single-phase boost converters to perform power factor correction.

14. The power factor correction circuit of claim 13, wherein the controller comprises a master stage and two slave stages, the master stage configured to calculate a current setpoint for itself and the two slave stages.

15. The power factor correction circuit of claim 13, wherein the first and second inductors of each single-phase boost converter have equal inductance values.

16. The power factor correction circuit of claim 13, further comprising a DC bus capacitance connected across the positive output terminal and a negative output terminal, wherein the DC bus capacitance comprises a film capacitor.

Images