Acoustic wave resonator and transistor integrated semiconductor device and manufacturing method therefor

Abstract

The present disclosure provides an acoustic wave resonator and transistor integrated semiconductor device, comprising a transistor and an acoustic wave resonator. The transistor and the acoustic wave resonator are integrated in a semiconductor device. The transistor comprises: a support substrate; a nucleation layer and a channel layer sequentially formed on the support substrate, wherein the support substrate and the nucleation layer extend to the outside of the channel layer; a barrier layer formed on the channel layer; a source and a drain, which pass through the barrier layer to form ohmic contact with the channel layer respectively; and a gate formed on the barrier layer, wherein the gate forms Schottky contact with the barrier layer. The acoustic wave resonator comprises: an extended support substrate; an extended nucleation layer; and a piezoelectric layer located on the extended nucleation layer, wherein an air isolation area is arranged between the piezoelectric layer of the acoustic wave resonator and the transistor, so that electrical insulation is realized between the acoustic wave resonator and the transistor.

Description

Semiconductor device integrating acoustic wave resonator and transistor and manufacturing method thereof Technical Field

[0001] At least one embodiment of the present disclosure relates to a semiconductor device, and more particularly to a semiconductor device integrating an acoustic wave resonator and a transistor, and a method for manufacturing the same. Background Art

[0002] As wireless communication technology enters the 5G and 6G era, RF microsystem chips, as core components in these systems, must meet the requirements of high power density, high operating frequency, and wider bandwidth, while also being cost-effective. Third-generation semiconductors, including materials such as gallium nitride and aluminum nitride, exhibit great potential in RF chip applications due to their wide bandgap, high electromechanical coupling coefficient, large breakdown electric field, and high thermal conductivity.

[0003] Faced with the demand for RF front-end chips in the new 5G frequency band, traditional active and passive devices can no longer meet the high-performance requirements of applications.

[0004] The advantages of GaN and AlN-based devices as RF / microwave power amplifiers lie in their high power density and high cutoff frequency. Compared to silicon-based laterally diffused metal-oxide-semiconductor field-effect transistors (LDMOS) and gallium arsenide (GaAs)-based heterojunction bipolar transistors (HBTs), wide-bandgap nitride-based devices offer higher power density, meeting the requirements of next-generation wireless communication systems. Leveraging their ability to deliver high power density at high frequencies and rapidly maturing material growth and device processing technologies, AlGaN / GaN HEMTs are poised to disrupt the wireless basestation market, previously dominated by silicon-based LDMOS technology. Development trends demand high performance and cost-effective power devices, while also delivering reasonable power-added efficiency (PAE), gain, and linearity at low-voltage portable power sources such as battery packs. GaN- and AlN-based high electron mobility transistors (HEMTs) can operate at high power density and high frequencies. Furthermore, the increasing maturity of 8-inch GaN-on-Si wafers and Si-compatible processing technologies offers the potential for GaN-on-Si HEMTs to achieve high power capacity and low cost. Therefore, wide-bandgap nitride-based HEMTs are becoming key components of next-generation RF / microwave / millimeter-wave power device technologies for 5G, 6G wireless communications and other emerging applications.

[0005] Research on the collaborative design of RF power and filter components has not been widely conducted, with most studies focusing on discrete RF components. While research on discrete RF front-end components is already in-depth, the use of separate discrete components for filters and power devices in RF front-end systems not only increases the volume (area) and weight of the entire system, but also introduces additional losses and costs due to the connections and matching circuits between each component.

[0006] Summary of the Invention

[0007] In view of this, the present disclosure provides a semiconductor device integrating an acoustic wave resonator and a transistor and a manufacturing method thereof, so as to solve the problems of parasitic effects, impedance matching and other issues caused by the interconnection of discrete single devices.

[0008] As one aspect of the present disclosure, the present disclosure provides a semiconductor device integrating an acoustic wave resonator and a transistor, comprising a transistor and an acoustic wave resonator, wherein the transistor and the acoustic wave resonator are integrated in one semiconductor device; the transistor comprises: a supporting substrate; a nucleation layer formed on the supporting substrate; a channel layer formed on the nucleation layer, wherein the supporting substrate and the nucleation layer extend to the outside of the channel layer; a barrier layer formed on the channel layer, wherein the barrier layer is configured to generate a two-dimensional electron gas by polarization within the channel layer; a source and a drain, wherein the source and the drain pass through the barrier layer and respectively form an ohmic contact with the channel layer; a gate formed on the barrier layer, and the gate forms a Schottky contact with the barrier layer; the acoustic wave resonator comprises: an extended supporting substrate; an extended nucleation layer; and a piezoelectric layer located on the extended nucleation layer; wherein an air isolation region is provided between the piezoelectric layer of the acoustic wave resonator and the transistor, so that electrical insulation is achieved between the acoustic wave resonator and the transistor.

[0009] According to the semiconductor device integrating the acoustic wave resonator and the transistor provided in the above-mentioned embodiment of the present disclosure, by integrating the acoustic wave resonator and the transistor in the same structure, a semiconductor device with higher integration and smaller parasitic parameters can be obtained while reducing the device size, thereby meeting the application requirements of the 5GHz and millimeter wave frequency bands. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] FIG1 is a schematic cross-sectional view of a semiconductor device integrating an acoustic wave resonator and a transistor according to an embodiment of the present disclosure;

[0011] FIG2 is an equivalent circuit diagram of a semiconductor device integrating an acoustic wave resonator and a transistor according to an embodiment of the present disclosure;

[0012] 3A to 3E are schematic cross-sectional views of different types of acoustic wave resonators according to embodiments of the present disclosure;

[0013] FIG4 is a flow chart of a method for manufacturing a semiconductor device integrating an acoustic wave resonator and a transistor according to an embodiment of the present disclosure; and

[0014] 5A to 5J are schematic diagrams illustrating a process of manufacturing a semiconductor device integrating an acoustic wave resonator and a transistor according to an embodiment of the present disclosure.

[0015] [Description of Reference Numerals] 100 - transistor; 200 - acoustic wave resonator; 1 - supporting substrate; 2 - nucleation layer; 3 - channel layer; 4 - barrier layer; 5 - source; 6 - drain; 7 - gate; 8 - lower electrode; 9 - piezoelectric layer; 10 - upper electrode; 11 - cavity; 12 - air isolation region; 13 - passivation layer. DETAILED DESCRIPTION

[0016] To make the objectives, technical solutions, and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below with reference to specific embodiments and the accompanying drawings. However, the present disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided to make the disclosure thorough and complete and to fully convey the scope of the present disclosure to those skilled in the art. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity, and the same reference numerals represent the same elements throughout.

[0017] The terms used herein are only for describing specific embodiments and are not intended to limit the present disclosure. The terms "comprise," "include," etc. used herein indicate the presence of the features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0018] It should be noted that the most widely used RF chip integration method in today's smart devices is to integrate multiple discrete components with different functions and processes in a very compact manner on a package substrate with relatively small line width and line spacing, thereby forming a larger chip. Therefore, further integration and miniaturization of RF devices are the future development trend, especially the integration of RF filters and power devices.

[0019] At present, the mainstream RF filter technologies in the industry mainly include waveguide / cavity / dielectric filters used in base stations and surface acoustic wave filters (Surface Acoustic Wave, SAW) and film bulk acoustic wave filters (Film Bulk Acoustic Wave Resonator, FBAR or Bulk Acoustic Wave, BAW) used in terminals. Among them, the two filters used in terminals are both built based on acoustic wave resonators. Since the wavelength of the acoustic wave in the resonator is much shorter than the wavelength of the electromagnetic wave of the corresponding frequency, the size (volume) of the device is much smaller at the same operating frequency, which can better meet the requirements of wireless communication terminals. The current commercial piezoelectric material for acoustic wave resonators is mainly aluminum nitride, but as acoustic wave resonators are oriented towards 5G / 6G high-frequency and large-bandwidth applications, the electromechanical coupling coefficient (k 2) is low, making it difficult to meet the large bandwidth requirements of the filter. Researchers have disclosed scandium (Sc) doping technology, which can significantly improve the electromechanical coupling coefficient (k 2 ). At the same time, scandium-doped aluminum nitride can be used as a barrier layer for HEMT devices, which makes monolithic heterogeneous integration possible.

[0020] In view of this, the present disclosure provides a semiconductor device integrating an acoustic wave resonator and a transistor and a manufacturing method thereof, so as to solve the problems of parasitic effects caused by the interconnection of discrete single devices and impedance matching between discrete single devices, thereby obtaining an integrated device with higher integration, smaller parasitic parameters and smaller size.

[0021] FIG1 is a schematic cross-sectional view of a semiconductor device integrating an acoustic wave resonator and a transistor according to an embodiment of the present disclosure.

[0022] According to an exemplary embodiment of the present disclosure, the present disclosure provides a semiconductor device, as shown in FIG1 , including a transistor 100 and an acoustic wave resonator 200 . The transistor 100 and the acoustic wave resonator 200 are integrated into one semiconductor device.

[0023] The transistor 100 includes: a supporting substrate 1; a nucleation layer 2 formed on the supporting substrate 1; a channel layer 3 formed on the nucleation layer 2, wherein the supporting substrate 1 and the nucleation layer 2 extend to the outside of the channel layer 3; a barrier layer 4 formed on the channel layer 3, the barrier layer 4 being configured to generate a two-dimensional electron gas by polarization within the channel layer; a source 5 and a drain 6, the source 5 and the drain 6 passing through the barrier layer 4 to form an ohmic contact with the channel layer 3 respectively; and a gate 7 formed on the barrier layer 4, the gate 7 forming a Schottky contact with the barrier layer 4.

[0024] The acoustic wave resonator 200 includes: an extended supporting substrate 1; an extended nucleation layer 2; a piezoelectric layer 9 located on the extended nucleation layer 2; wherein an air isolation region 12 is provided between the piezoelectric layer 9 of the acoustic wave resonator and the transistor, so that electrical insulation is achieved between the acoustic wave resonator and the transistor.

[0025] According to an embodiment of the present disclosure, the acoustic wave resonator 200 (MEMS Resonator) may be any one of a film bulk acoustic resonator (FBAR), a Lamb wave resonator (LAMB), a surface acoustic wave resonator (SAW), and a harmonic bulk acoustic resonator (HBAR).

[0026] According to an embodiment of the present disclosure, as shown in Figure 1, the acoustic wave resonator 200 is a thin film bulk acoustic wave resonator, wherein a cavity 11 is formed between the extended nucleation layer 2 and the extended supporting substrate 1; the thin film bulk acoustic wave resonator also includes: a lower electrode 8, located between the extended nucleation layer 2 and the piezoelectric layer 9; and an upper electrode 10, located on the piezoelectric layer 9.

[0027] FIG. 2 is an equivalent circuit diagram of a semiconductor device integrating an acoustic wave resonator and a transistor according to an embodiment of the present disclosure.

[0028] As shown in Figure 2, the upper electrode 10 of the acoustic wave resonator is electrically connected to the drain 6 of the transistor via a conductive metal; the lower electrode 11 of the acoustic wave resonator is electrically connected to the gate 7 of the transistor via a conductive metal; and the source 5 of the transistor is grounded. The semiconductor device integrating the acoustic wave resonator and the transistor can be equivalent to a Pierce oscillator, which can amplify an electrical signal of a specific frequency input by the acoustic wave resonator. In other words, the upper electrode 10 of the acoustic wave resonator serves as an input port to input an electrical signal into the acoustic wave resonator, and the lower electrode 11 of the acoustic wave resonator serves as an output port to output an electrical signal of a specific frequency. The output of the acoustic wave resonator is fed to the gate 7 of the HEMT, and the electrical signal of the specific frequency is amplified at the drain 6 of the HEMT. Wherein, Cap1 represents capacitor 1, and Cap2 represents capacitor 2.

[0029] It should be noted that different connection methods between the acoustic wave resonator and the transistor can achieve different functions. The electrical connection method between the transistor and the acoustic wave resonator is selected according to actual application requirements.

[0030] According to an embodiment of the present disclosure, the upper electrode 10 of the acoustic wave resonator is electrically connected to the gate 7 of the transistor through a conductive metal.

[0031] According to an embodiment of the present disclosure, the upper electrode 10 of the acoustic wave resonator is electrically connected to the source 5 of the transistor through a conductive metal.

[0032] 3A to 3E are schematic cross-sectional views of different types of acoustic wave resonators according to embodiments of the present disclosure.

[0033] FIG3A is a schematic cross-sectional view of a thin film bulk acoustic resonator according to another embodiment of the present disclosure.

[0034] 3A , the FBAR resonator includes an extended support substrate 1 , wherein a cavity 11 penetrating the extended support substrate 1 is formed on the extended support substrate 1 , and a lower electrode 8 is formed on a side of the extended support substrate 1 away from the extended nucleation layer 2 .

[0035] According to an embodiment of the present disclosure, the material of lower electrode 8 includes at least one of the following: titanium, nickel, copper, gold, aluminum, molybdenum, platinum, titanium-gold alloy, titanium-aluminum alloy, chromium-gold alloy, chromium-aluminum alloy, or aluminum-copper alloy. The thickness of lower electrode 8 is 10 nm to 500 nm, for example, 10 nm, 100 nm, 200 nm, 400 nm, or 500 nm.

[0036] FIG3B is a schematic cross-sectional view of a Lamb wave resonator according to an embodiment of the present disclosure.

[0037] 3B , the upper electrode 10 of the LAMB resonator is an interdigitated electrode, wherein a cavity 11 penetrating the extended support substrate 1 is formed on the extended support substrate 1 , and no lower electrode is provided.

[0038] FIG3C is a schematic cross-sectional view of a Lamb wave resonator according to another embodiment of the present disclosure.

[0039] 3C , the upper electrode 10 of the LAMB resonator is an interdigitated electrode, wherein a cavity 11 penetrating the extended support substrate 1 is formed on the extended support substrate 1 , and a lower electrode 8 is provided on the side of the extended support substrate 1 away from the extended nucleation layer 2 .

[0040] FIG3D is a schematic cross-sectional view of a surface acoustic wave resonator according to an embodiment of the present disclosure.

[0041] 3D , the upper electrode 10 of the SAW resonator is an interdigital electrode, and no lower electrode is provided.

[0042] FIG3E is a schematic cross-sectional view of a harmonic bulk acoustic resonator according to an embodiment of the present disclosure.

[0043] 3E , the upper electrode 10 of the HBAR resonator is a single-layer electrode, and no lower electrode is provided.

[0044] According to an embodiment of the present disclosure, the material of the piezoelectric layer 9 is any one or more of GaN, AlN, AlGaN and AlScN.

[0045] According to an embodiment of the present disclosure, the transistor 100 is a high electron mobility transistor (HEMT).

[0046] According to an embodiment of the present disclosure, the support substrate 1 may be selected from one or more of silicon, silicon carbide, diamond, gallium nitride, and sapphire.

[0047] According to an embodiment of the present disclosure, the nucleation layer 2 is one or both of aluminum nitride and gallium nitride, and the thickness of the nucleation layer 2 is 3 nm to 1000 nm, for example, 3 nm, 10 nm, 100 nm, 500 nm, or 1000 nm.

[0048] According to an embodiment of the present disclosure, the material of the channel layer 3 includes any one of GaN, AlN, AlGaN, AlScN, InN, ScN, and YAlN. The thickness of the channel layer 3 is between 500 nm and 5 μm, for example, the thickness of the channel layer 3 can be 500 nm, 800 nm, 1 μm, 3 μm, or 5 μm.

[0049] It should be noted that a nucleation layer 2 is formed between the supporting substrate 1 and the channel layer 3 to improve the film formation quality of the channel layer 3 material.

[0050] According to the embodiments of the present disclosure, the band gap of the material of barrier layer 4 differs from the band gap of the material of channel layer 3, so that barrier layer 4 and channel layer 3 form a heterojunction, thereby forming a two-dimensional electron gas at the interface between barrier layer 4 and channel layer 3. The lattice constant of the material of barrier layer 4 differs from the lattice constant of the material of channel layer 3. Due to the lattice mismatch between barrier layer 4 and channel layer 3 in the heterojunction, piezoelectric polarization occurs in barrier layer 4, which enhances the concentration of the two-dimensional electron gas.

[0051] According to an embodiment of the present disclosure, the material of the barrier layer 4 includes any one of GaN, AlN, AlGaN, AlScN, InN, ScN, and YAlN.

[0052] Figure 4 is a flow chart of a method for manufacturing a semiconductor device integrating an acoustic wave resonator and a transistor according to an embodiment of the present disclosure. Figures 5A to 5J are schematic diagrams of a process for manufacturing a semiconductor device integrating an acoustic wave resonator and a transistor according to an embodiment of the present disclosure.

[0053] According to an exemplary embodiment of the present disclosure, the present disclosure provides a method for manufacturing a semiconductor device integrating an acoustic wave resonator and a transistor, as shown in FIG. 4 and FIG. 5A to FIG. 5J , comprising steps S01 to S07 .

[0054] In step S01 , a nitride substrate is provided. The nitride substrate includes, from bottom to top, a supporting substrate 1 , a nucleation layer 2 , a channel layer 3 , and a barrier layer 4 .

[0055] According to an embodiment of the present disclosure, a nucleation layer 2 , a channel layer 3 , and a barrier layer 4 are epitaxially grown in sequence on a supporting substrate 1 by molecular beam epitaxy (MBE) or metal organic vapor deposition (MOCVD).

[0056] In step S02 , the barrier layer 4 and the channel layer 3 are sequentially etched, so that the nitride substrate is isolated into a transistor region and an acoustic wave resonator region through the air isolation region 12 .

[0057] According to an embodiment of the present disclosure, reactive ion etching (RIE) or inductively coupled plasma etching (ICP) is used to etch the nitride substrate until the nucleation layer 2, or to etch the nitride substrate until the supporting substrate 1 to form an air isolation region 12, so that the nitride substrate is isolated into a transistor region and an acoustic wave resonance region.

[0058] In step S03 , the barrier layer 4 in the transistor region is etched to reduce the thickness of the barrier layer 4 in the transistor region.

[0059] In step S04 , a source electrode 5 and a drain electrode 6 are formed on the thinned barrier layer 4 in the transistor region, so that the source electrode 5 and the drain electrode 6 pass through the barrier layer 4 and form ohmic contacts with the channel layer 3 respectively.

[0060] According to an embodiment of the present disclosure, the process of forming the source electrode 5 and the drain electrode 6 on the thinned barrier layer 4 in the transistor region includes: forming a mask layer on the thinned barrier layer 4 in the transistor region; etching the mask layer to form source and drain electrode patterns; depositing a metal layer on the mask layer; stripping the metal layer outside the source and drain electrode patterns; and annealing the resulting device in a nitrogen atmosphere to ensure that the source electrode 5 and the drain electrode 6 form ohmic contacts with the channel layer 3.

[0061] According to an embodiment of the present disclosure, the mask layer includes one or two of photoresist, silicon oxide, and silicon nitride.

[0062] According to an embodiment of the present disclosure, the annealing temperature is 800°C to 900°C, for example, 800°C, 820°C, 850°C, 880°C, or 900°C; the annealing time is 30s to 60s, for example, 30s, 40s, 50s, 55s, or 60s.

[0063] According to an embodiment of the present disclosure, after the source electrode 5 and the drain electrode 6 are formed, the mask layer is removed by etching using a reactive ion etching method or an inductively coupled plasma method.

[0064] According to an embodiment of the present disclosure, the material of the source electrode 5 and the drain electrode 6 is titanium / aluminum / titanium / gold. The thickness of the titanium layer from bottom to top is between 10nm and 30nm, the thickness of the aluminum layer is between 80nm and 200nm, the thickness of the titanium layer is between 40nm and 60nm, and the thickness of the gold layer is between 30nm and 60nm. The material of the source electrode 5 and the drain electrode 6 can also be titanium / aluminum / nickel / gold.

[0065] In step S05 , a gate 7 is formed on the barrier layer 4 , so that the gate 7 forms a Schottky contact with the barrier layer 4 .

[0066] According to an embodiment of the present disclosure, the material of the gate 7 is nickel / gold, wherein the thickness of the nickel layer is 30 nm, and the thickness of the gold layer is 20 nm to 100 nm.

[0067] In step S06 , the barrier layer 4 and the channel layer 3 in the acoustic wave resonator region are sequentially etched to expose the extended nucleation layer 2 .

[0068] In step S07 , a piezoelectric layer 9 of the acoustic wave resonator region is formed on the extended nucleation layer 2 .

[0069] It should be noted that the thickness of the piezoelectric layer 9 is related to the operating frequency of the acoustic wave resonator. The piezoelectric layer 9 is obtained with a preset thickness to obtain an operating frequency that meets the requirements.

[0070] According to an embodiment of the present disclosure, before forming the piezoelectric layer 9 of the acoustic wave resonator region on the extended nucleation layer 2, the lower electrode 8 is formed on the extended nucleation layer 2. After forming the piezoelectric layer 9 of the acoustic wave resonator region on the extended nucleation layer 2, the upper electrode 10 is formed on the piezoelectric layer 9. A metal layer is deposited on the piezoelectric layer 9 by one or both of thermal evaporation, electron beam evaporation, or magnetron sputtering, and the metal layer is processed by lift-off technology to form the upper electrode 10 on the piezoelectric layer 9.

[0071] According to an embodiment of the present disclosure, the material of the lower electrode 8 and the upper electrode 10 includes at least one of the following: titanium, nickel, copper, gold, aluminum, molybdenum, platinum, titanium-gold alloy, titanium-aluminum alloy, chromium-gold alloy, chromium-aluminum alloy, and aluminum-copper alloy.

[0072] According to an embodiment of the present disclosure, the thickness of the lower electrode 8 and the upper electrode 10 is 10 nm to 500 nm, for example, the thickness may be 10 nm, 100 nm, 200 nm, 400 nm, or 500 nm.

[0073] According to an embodiment of the present disclosure, the acoustic wave resonator is a thin film bulk acoustic wave resonator, and the above-mentioned manufacturing method also includes: releasing the supporting substrate 1 of the acoustic wave resonator area, so that a partial area of ​​the supporting substrate 1 of the acoustic wave resonator area close to the lower electrode 8 is released to form a cavity 11 between the supporting substrate 1 and the lower electrode 8.

[0074] According to an embodiment of the present disclosure, XeF 2 gas is used to release the support substrate 1 to form a cavity 11 between the support substrate 1 and the lower electrode 8 .

[0075] According to an embodiment of the present disclosure, after forming the gate 7 of the transistor, a passivation layer 13 is deposited on the barrier layer 4 of the transistor. After forming the upper electrode 10 of the acoustic wave resonator on the piezoelectric layer 9, an electrode opening is opened in the passivation layer 13, and a conductive metal is deposited between the acoustic wave resonator and the transistor to achieve electrical connection between the acoustic wave resonator and the transistor.

[0076] It should be noted that the higher the resonant frequency of the acoustic wave resonator, the more significant the parasitic effects generated by the integrated interconnection of discrete acoustic wave resonators and discrete transistors. The semiconductor device integrating the acoustic wave resonator and transistors provided in this disclosure can better reduce parasitic effects in the 5 GHz high frequency band, thereby meeting the application requirements of the 5 GHz and millimeter wave bands.

[0077] According to the semiconductor device integrating the acoustic wave resonator and the transistor provided in the above-mentioned embodiment of the present disclosure, by integrating the acoustic wave resonator and the transistor in the same structure, a semiconductor device with higher integration and smaller parasitic parameters can be obtained while reducing the device size, thereby meeting the application requirements of the 5GHz and millimeter wave frequency bands.

[0078] According to the semiconductor device integrating the acoustic wave resonator and the transistor provided in the above embodiments of the present disclosure, the acoustic wave resonator can constitute the matching circuit of the PA (power amplifier), thereby eliminating the need for separate capacitors and inductors; the acoustic wave resonator constitutes a filter to select specific frequencies for signal amplification.

[0079] The specific embodiments of the present disclosure described above do not limit the scope of protection of the present disclosure. Any other corresponding changes and modifications made based on the technical concept of the present disclosure should be included in the scope of protection of the claims of the present disclosure.

Claims

1. A semiconductor device integrating an acoustic wave resonator and a transistor, wherein: It comprises a transistor (100) and an acoustic wave resonator (200), wherein the transistor (100) and the acoustic wave resonator (200) are integrated in one semiconductor device; The transistor (100) comprises: A supporting substrate (1); A nucleation layer (2) formed on the supporting substrate (1); A channel layer (3) formed on the nucleation layer (2), wherein the support substrate (1) and the nucleation layer (2) extend to the outside of the channel layer (3); A barrier layer (4) is formed on the channel layer (3), and the barrier layer (4) is configured to generate a two-dimensional electron gas by polarization in the channel layer; A source electrode (5) and a drain electrode (6), wherein the source electrode (5) and the drain electrode (6) pass through the barrier layer (4) and respectively form an ohmic contact with the channel layer (3); A gate (7) is formed on the barrier layer (4), and the gate (7) forms a Schottky contact with the barrier layer (4); The acoustic wave resonator (200) comprises: An extended support substrate (1); An extended nucleation layer (2); A piezoelectric layer (9) is located on the extended nucleation layer (2); An air isolation region (12) is provided between the piezoelectric layer (9) of the acoustic wave resonator and the transistor, so that electrical insulation is achieved between the acoustic wave resonator and the transistor.

2. The semiconductor device according to claim 1, wherein The acoustic wave resonator (200) is any one of a thin film bulk acoustic wave resonator, a Lamb wave resonator, a surface acoustic wave resonator and a high-order harmonic bulk acoustic wave resonator.

3. The semiconductor device according to claim 2, wherein: The acoustic wave resonator (200) is a thin film bulk acoustic wave resonator, wherein a cavity (11) is formed between the extended nucleation layer (2) and the extended support substrate (1); The film bulk acoustic wave resonator further comprises: A lower electrode (8) is located between the extended nucleation layer (2) and the piezoelectric layer (9); An upper electrode (10) is located on the piezoelectric layer (9).

4. The semiconductor device according to claim 1, wherein: The material of the nucleation layer (2) is GaN or AlN; Preferably, the material of the channel layer (3) includes any one of GaN, AlN, AlGaN, AlScN, InN, ScN and YAlN; The barrier layer (4) and the channel layer (3) form a heterojunction to form a two-dimensional electron gas at the interface between the barrier layer (4) and the channel layer (3); Preferably, the material of the barrier layer (4) includes any one of GaN, AlN, AlGaN, AlScN, InN, ScN, and YAlN.

5. The semiconductor device according to claim 3, wherein: The upper electrode (10) of the acoustic wave resonator is electrically connected to the gate (7) of the transistor via conductive metal.

6. The semiconductor device according to claim 3, wherein: The upper electrode (10) of the acoustic wave resonator is electrically connected to the source electrode (5) of the transistor via a conductive metal.

7. The semiconductor device according to claim 3, wherein: The upper electrode (10) of the acoustic wave resonator is electrically connected to the drain electrode (6) of the transistor via a conductive metal.

8. A method for manufacturing a semiconductor device according to any one of claims 1 to 7, wherein: include: Providing a nitride substrate, the nitride substrate comprising, from bottom to top, a supporting substrate (1), a nucleation layer (2), a channel layer (3), and a barrier layer (4); The barrier layer (4) and the channel layer (3) are sequentially etched so that the nitride substrate is isolated into a transistor region and an acoustic wave resonator region through an air isolation region (12); Etching the barrier layer (4) in the transistor region to reduce the thickness of the barrier layer (4) in the transistor region; A source electrode (5) and a drain electrode (6) are fabricated on the thinned barrier layer (4) in the transistor region, so that the source electrode (5) and the drain electrode (6) pass through the barrier layer (4) to form ohmic contacts with the channel layer (3) respectively; Preparing a gate electrode (7) on the barrier layer (4) so ​​that the gate electrode (7) forms a Schottky contact with the barrier layer (4); The barrier layer (4) and the channel layer (3) in the acoustic wave resonator region are sequentially etched and removed to expose the extended nucleation layer (2); A piezoelectric layer (9) of the acoustic wave resonator region is formed on the extended nucleation layer (2).

9. The method according to claim 8, wherein: The acoustic wave resonator is a thin film bulk acoustic wave resonator, and the manufacturing method further comprises: Before forming a piezoelectric layer (9) of the acoustic wave resonator region on the extended nucleation layer (2), forming a lower electrode (8) on the extended nucleation layer (2); After forming a piezoelectric layer (9) of the acoustic wave resonator region on the extended nucleation layer (2), forming an upper electrode (10) on the piezoelectric layer (9); The supporting substrate (1) of the acoustic wave resonator region is released, so that a partial area of ​​the supporting substrate (1) of the acoustic wave resonator region on one side close to the lower electrode (8) is released, so as to form a cavity (11) between the supporting substrate (1) and the lower electrode (8).

10. The method according to claim 8, wherein: After forming a gate electrode (7) on the barrier layer (4), a passivation layer (13) is deposited on the transistor; After preparing the upper electrode (10) of the acoustic wave resonator on the piezoelectric layer (9), an electrode opening is opened on the passivation layer (13), and a conductive metal is deposited between the acoustic wave resonator and the transistor, so that the acoustic wave resonator and the transistor are electrically connected.

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