Display substrate and display apparatus

Abstract

A display substrate and a display apparatus. The display substrate comprises a base (100) and pixel units (P) arranged in an array on the base (100), wherein at least one pixel unit (P) comprises a plurality of sub-pixels; the plurality of sub-pixels comprise at least one anti-peeping sub-pixel and at least one shared sub-pixel; and at least one sub-pixel comprises a pixel driving circuit and a light-emitting device, the pixel driving circuit being configured to drive the light-emitting device to emit light. Display modes of the display substrate comprise a first display mode and a second display mode, wherein the viewing angle range in the first display mode is smaller than the viewing angle range in the second display mode; in a state in which the display mode of the display substrate is the first display mode, the anti-peeping sub-pixel emits light; and in a state in which the display mode of the display substrate is the second display mode, the shared sub-pixel emits light, alternatively, the anti-peeping sub-pixel and the shared sub-pixel emit light.

Description

Display substrate and display device Technical Field

[0001] The present disclosure relates to, but is not limited to, the field of display technology, and particularly to a display substrate and a display device. Background Art

[0002] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0003] Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] In a first aspect, the present disclosure provides a display substrate, comprising: a substrate and an array of pixel units disposed on the substrate, at least one pixel unit comprising: a plurality of sub-pixels, the plurality of sub-pixels comprising: at least one anti-peep sub-pixel and at least one shared sub-pixel, at least one sub-pixel comprising: a pixel driving circuit and a light-emitting device, the pixel driving circuit being configured to drive the light-emitting device to emit light, the display modes of the display substrate comprising: a first display mode and a second display mode, the viewing angle range of the first display mode being smaller than the viewing angle range of the second display mode;

[0006] When the display mode of the display substrate is the first display mode, the anti-peeping sub-pixel emits light; when the display mode of the display substrate is the second display mode, the shared sub-pixel emits light, or the anti-peeping sub-pixel and the shared sub-pixel emit light.

[0007] In an exemplary embodiment, the plurality of sub-pixels in at least one pixel unit include: first to sixth sub-pixels;

[0008] The pixel driving circuit in the first sub-pixel to the pixel driving circuit in the sixth sub-pixel located in the same pixel unit are arranged in an array along a first direction and a second direction or arranged along the first direction, the first sub-pixel and the second sub-pixel emit a first color light, the third sub-pixel and the fourth sub-pixel emit a second color light, and the fifth sub-pixel and the sixth sub-pixel emit a third color light, and the first direction and the second direction intersect;

[0009] One of the first sub-pixel and the second sub-pixel is an anti-peeping sub-pixel, the other of the first sub-pixel and the second sub-pixel is a shared sub-pixel, one of the third sub-pixel and the fourth sub-pixel is an anti-peeping sub-pixel, the other of the third sub-pixel and the fourth sub-pixel is a shared sub-pixel, one of the fifth sub-pixel and the sixth sub-pixel is an anti-peeping sub-pixel, the other of the fifth sub-pixel and the sixth sub-pixel is a shared sub-pixel.

[0010] In an exemplary embodiment, the light emitting device includes: a first electrode, the display substrate is further provided with a pixel definition layer, and the pixel definition layer is provided with a pixel opening exposing the first electrode;

[0011] For an anti-peeping sub-pixel and a shared sub-pixel emitting light of the same color, the area of ​​the first electrode in the anti-peeping sub-pixel is equal to the area of ​​the first electrode in the shared sub-pixel, and the area of ​​the pixel opening exposing the first electrode of the anti-peeping sub-pixel is smaller than the area of ​​the pixel opening exposing the first electrode of the shared sub-pixel;

[0012] The pixel opening exposing the first electrode of the anti-peeping sub-pixel includes at least two sub-pixel openings, and the at least two sub-pixel openings are arranged along the first direction.

[0013] In an exemplary embodiment, the light emitting device includes: a first electrode;

[0014] For at least one pixel unit, the light-emitting device of the first sub-pixel, the light-emitting device of the second sub-pixel, the light-emitting device of the third sub-pixel, and the light-emitting device of the fourth sub-pixel are arranged along the second direction, the light-emitting device of the fifth sub-pixel and the light-emitting device of the sixth sub-pixel are arranged along the second direction, the light-emitting device of the third sub-pixel and the light-emitting device of the fifth sub-pixel are arranged along the first direction, and the light-emitting device of the fourth sub-pixel and the light-emitting device of the sixth sub-pixel are arranged along the first direction;

[0015] The area of ​​the first electrode of the fifth subpixel and the area of ​​the first electrode of the sixth subpixel are greater than the area of ​​the first electrode of the third subpixel and the area of ​​the first electrode of the fourth subpixel, and the area of ​​the first electrode of the third subpixel and the area of ​​the first electrode of the fourth subpixel are greater than the area of ​​the first electrode of the first subpixel and the area of ​​the first electrode of the second subpixel.

[0016] In an exemplary embodiment, the present invention further comprises: a driving structure layer, a light emitting structure layer, an encapsulation layer, and an optical structure layer sequentially stacked on the substrate, wherein the pixel driving circuit is disposed on the driving structure layer, the light emitting device is disposed on the light emitting structure layer, and the optical structure layer comprises: at least one of a light shielding structure layer and an optical device layer;

[0017] The optical device layer is located on a side of the light-shielding structure layer close to the substrate or away from the substrate.

[0018] In an exemplary embodiment, the light-shielding structure layer includes: a first light-shielding layer, a light-shielding base layer, and a second light-shielding layer, wherein the first light-shielding layer is located on a side of the light-shielding base layer close to the base, and the second light-shielding layer is located on a side of the light-shielding base layer away from the base, the first light-shielding layer includes: a plurality of first light-shielding structures, and the second light-shielding layer includes: a plurality of second light-shielding structures; the light-emitting structure layer includes: an organic light-emitting layer of a light-emitting device of at least one sub-pixel;

[0019] The orthographic projection of the first light-shielding layer on the substrate at least partially overlaps with the orthographic projection of the second light-shielding layer on the substrate. The first light-shielding structure and the second light-shielding structure are located in the anti-peeping sub-pixel area, and their orthographic projections on the substrate partially overlap with the orthographic projection of the organic light-emitting layer of at least one anti-peeping sub-pixel on the substrate. The anti-peeping sub-pixel area is the area where the anti-peeping sub-pixel is located.

[0020] In an exemplary embodiment, the optical device layer includes: an optical substrate layer and a plurality of optical devices, wherein the optical devices are located on a side of the optical substrate layer close to the substrate or a side away from the substrate, and the optical devices are configured to converge incident light; the light-emitting structure layer includes: an organic light-emitting layer of a light-emitting device of at least one sub-pixel;

[0021] The orthographic projection of the optical device on the substrate at least partially overlaps with the orthographic projection of the organic light-emitting layer of the anti-peeping sub-pixel on the substrate.

[0022] In an exemplary embodiment, the display substrate further includes a plurality of signal lines and a plurality of anode connection lines, and the pixel driving circuit is electrically connected to the plurality of signal lines and the plurality of anode connection lines, respectively.

[0023] In an exemplary embodiment, the driving structure layer includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer stacked in sequence on a substrate, and the pixel driving circuit includes: at least one transistor and at least one capacitor, the transistor includes: an active pattern, a gate electrode, a first pole and a second pole, and the capacitor includes: a first plate and a second plate.

[0024] The semiconductor layer includes at least: an active pattern of at least one transistor located in at least one sub-pixel;

[0025] The first conductive layer at least includes: at least one signal line among a plurality of signal lines, a gate electrode of at least one transistor located in at least one sub-pixel, and a first plate of at least one capacitor;

[0026] The second conductive layer at least includes: at least one signal line among the plurality of signal lines and a second plate of at least one capacitor located in at least one sub-pixel;

[0027] The third conductive layer at least includes: at least one signal line among the plurality of signal lines and a first electrode and a second electrode of at least one transistor located in at least one sub-pixel;

[0028] The fourth conductive layer includes at least: at least one signal line among a plurality of signal lines;

[0029] The fifth conductive layer includes at least one anode connecting line among a plurality of anode connecting lines.

[0030] In an exemplary embodiment, for at least one pixel unit, the pixel driving circuit of the first sub-pixel, the pixel driving circuit of the third sub-pixel and the pixel driving circuit of the fifth sub-pixel are arranged in sequence along the first direction, the pixel driving circuit of the second sub-pixel, the pixel driving circuit of the fourth sub-pixel and the pixel driving circuit of the sixth sub-pixel are arranged in sequence along the first direction, the pixel driving circuit of the first sub-pixel and the pixel driving circuit of the second sub-pixel are arranged along the second direction, the pixel driving circuit of the third sub-pixel and the pixel driving circuit of the fourth sub-pixel are arranged along the second direction, and the pixel driving circuit of the fifth sub-pixel and the pixel driving circuit of the sixth sub-pixel are arranged along the second direction.

[0031] In an exemplary embodiment, the plurality of signal lines include: 2M reset signal lines, 2M scan signal lines, 2M light emitting signal lines, 2M first initial signal lines, 2M second initial signal lines, 3N first power supply lines, and 3N data signal lines, where M is the total number of rows of pixel units, and N is the total number of columns of pixel units;

[0032] At least one signal line among the reset signal line, the scan signal line, the light emitting signal line, the first initial signal line, and the second initial signal line extends at least partially along the first direction, and at least one signal line among the first power line and the data signal line extends at least partially along the second direction, and a line width of the first power line is greater than a line width of the data signal line;

[0033] The pixel unit in the i-th row and j-th column is electrically connected to the 2i-1th scanning signal line, the 2i-th scanning signal line, the 2i-1th reset signal line, the 2i-th reset signal line, the 2i-1th light-emitting signal line, the 2i-1th first initial signal line, the 2i-th first initial signal line, the 2i-1th second initial signal line, the 2i-2th first power line, the 3j-1th first power line, the 3j-2th data signal line, the 3j-1th data signal line and the 3jth data signal line, respectively, 1≤i≤M, 1≤j≤N.

[0034] In an exemplary embodiment, for at least one pixel unit, pixel structures of pixel driving circuits of at least two sub-pixels from the first to sixth sub-pixels are at least partially identical.

[0035] In an exemplary embodiment, in the pixel unit of the i-th row and the j-th column, at least one of the first sub-pixel, the third sub-pixel, and the fifth sub-pixel is electrically connected to the 2i-1th scanning signal line, the 2i-1th light emitting signal line, the 2i-1th reset signal line, the 2i-1th first initial signal line, and the 2i-1th second initial signal line, respectively, and at least one of the second sub-pixel, the fourth sub-pixel, and the sixth sub-pixel is electrically connected to the 2i-th scanning signal line, the 2i-th light emitting signal line, the 2i-th reset signal line, the 2i-1th first initial signal line, and the 2i-1th second initial signal line, respectively. The reset signal line, the 2i-th first initial signal line and the 2i-th second initial signal line are electrically connected, at least one sub-pixel among the first sub-pixel and the second sub-pixel is also electrically connected to the 3j-2-th first power line and the 3j-2-th data signal line, respectively, at least one sub-pixel among the third sub-pixel and the fourth sub-pixel is also electrically connected to the 3j-1-th first power line and the 3j-1-th data signal line, respectively, and at least one sub-pixel among the fifth sub-pixel and the sixth sub-pixel is also electrically connected to the 3j-th first power line and the 3j-1 data signal line, respectively.

[0036] In an exemplary embodiment, orthographic projections of the first initial signal line, the second initial signal line, the reset signal line, the scan signal line, and the light emitting signal line connected to the same sub-pixel on the substrate are arranged in sequence along the second direction;

[0037] The orthographic projection of the kth data signal line on the substrate is located between the orthographic projection of the kth first power line on the substrate and the orthographic projection of the k+1th first power line on the substrate, 1≤k≤3N.

[0038] In an exemplary embodiment, the at least one transistor includes: a node reset transistor, a driving transistor, and a compensation transistor; the second electrode of the node reset transistor and the first electrode of the compensation transistor are integrally structured and electrically connected to the gate electrode of the driving transistor;

[0039] An orthographic projection of the first power line on the substrate at least partially overlaps with an orthographic projection of an integrated structure of a second electrode of a node reset transistor and a first electrode of a compensation transistor in a sub-pixel connected to the first power line on the substrate.

[0040] In an exemplary embodiment, the first power line includes: a first sub-power line and a second sub-power line connected to each other, the first sub-power line and the second sub-power line extending along the second direction, and orthographic projections of the first sub-power line and the second sub-power line on the substrate at least partially overlapping;

[0041] The light-emitting signal line is located in the first conductive layer, the first initial signal line and the second initial signal line are located in the second conductive layer, the reset signal line and the scanning signal line are located in the third conductive layer, the first sub-power line is located in the fourth conductive layer, the second sub-power line is located in the fifth conductive layer, and the data signal line is located in the fourth conductive layer or the fifth conductive layer.

[0042] In an exemplary embodiment, the plurality of signal lines include: 2M reset signal lines, 2M scan signal lines, 2M light emitting signal lines, 2M first initial signal lines, 2M second initial signal lines, 4N first power supply lines, and 6N data signal lines, where M is the total number of rows of pixel units, and N is the total number of columns of pixel units;

[0043] At least one signal line among the reset signal line, the scan signal line, the light emitting signal line, the first initial signal line, and the second initial signal line extends at least partially along the first direction, and at least one signal line among the first power line and the data signal line extends at least partially along the second direction;

[0044] The pixel unit in the i-th row and j-th column is electrically connected to the 2i-1th scan signal line, the 2i-th scan signal line, the 2i-1th reset signal line, the 2i-th reset signal line, the 2i-1th light-emitting signal line, the 2i-1th first initial signal line, the 2i-th first initial signal line, the 2i-1th second initial signal line, the 2i-2nd first power line, the 4j-1th first power line, the 4j-4th data signal line, the 6j-3th data signal line, the 6j-2th data signal line, the 6j-1th data signal line and the 6j-5th data signal line, respectively, 1≤i≤M, 1≤j≤N.

[0045] In an exemplary embodiment, for at least one pixel unit, the pixel structures of the pixel driving circuits of at least two sub-pixels among the first sub-pixel, the third sub-pixel and the fifth sub-pixel are at least partially identical, the pixel structures of the pixel driving circuits of at least two sub-pixels among the second sub-pixel, the fourth sub-pixel and the sixth sub-pixel are at least partially identical, and the pixel structure of the pixel driving circuit of the first sub-pixel is at least partially mirror-symmetrical to the pixel structure of the pixel driving circuit of the second sub-pixel.

[0046] In an exemplary embodiment, in the pixel unit at the i-th row and the j-th column, at least one of the first subpixel, the third subpixel, and the fifth subpixel is electrically connected to the 2i-1th scan signal line, the 2i-1th light emitting signal line, the 2i-1th reset signal line, the 2i-1th first initial signal line, and the 2i-1th second initial signal line, respectively, and at least one of the second subpixel, the fourth subpixel, and the sixth subpixel is electrically connected to the 2i-th scan signal line, the 2i-th light emitting signal line, the 2i-th reset signal line, the 2i-th first initial signal line, and the 2i-th second initial signal line, respectively. , the first sub-pixel is also electrically connected to the 6j-4th data signal line and the 4j-2th first power line, respectively, the second sub-pixel is also electrically connected to the 6j-5th data signal line and the 4j-3th first power line, respectively, the third sub-pixel is also electrically connected to the 6j-2th data signal line and the 4j-1th first power line, respectively, the fourth sub-pixel is also electrically connected to the 6j-3th data signal line and the 4j-2th first power line, respectively, the fifth sub-pixel is also electrically connected to the 6jth data signal line and the 4j first power line, respectively, and the sixth sub-pixel is also electrically connected to the 6j-1th data signal line and the 4j-1st first power line, respectively.

[0047] In an exemplary embodiment, an orthographic projection of a first initial signal line connected to the same sub-pixel on the substrate, a second initial signal line, a reset signal line, a scan signal line, and an orthographic projection of a light emitting signal line on the substrate are sequentially arranged along the second direction;

[0048] For at least one pixel unit, orthographic projections of two data signal lines connected to two sub-pixels arranged along the second direction on the substrate are located between orthographic projections of two first power lines connected to the two sub-pixels on the substrate.

[0049] In an exemplary embodiment, the at least one transistor includes: a node reset transistor, a driving transistor, and a compensation transistor; the second electrode of the node reset transistor and the first electrode of the compensation transistor are integrally structured and electrically connected to the gate electrode of the driving transistor; the capacitor further includes: a third electrode plate, the third electrode plate being electrically connected to the second electrode plate and being located in the fourth conductive layer;

[0050] For at least one sub-pixel, an orthographic projection of the third electrode plate on the substrate at least partially overlaps with an orthographic projection of an integrated structure of the second electrode of the node reset transistor and the first electrode of the compensation transistor on the substrate;

[0051] The orthographic projections of the third electrodes in the two sub-pixels arranged along the second direction on the substrate are located between the orthographic projections of the two data signal lines connected to the two sub-pixels arranged along the second direction on the substrate.

[0052] In an exemplary embodiment, the light emitting signal line is located in a first conductive layer, the first initial signal line and the second initial signal line are located in a second conductive layer, the reset signal line and the scan signal line are located in a third conductive layer, and the data signal line and the first power supply line are located in the fourth conductive layer.

[0053] In an exemplary embodiment, for at least one pixel unit, the pixel driving circuit of the first sub-pixel, the pixel driving circuit of the second sub-pixel, the pixel driving circuit of the third sub-pixel, the pixel driving circuit of the fourth sub-pixel, the pixel driving circuit of the fifth sub-pixel and the pixel driving circuit of the sixth sub-pixel are arranged in sequence along the first direction.

[0054] In an exemplary embodiment, the plurality of signal lines include: 2M reset signal lines, 2M scan signal lines, 2M light emitting signal lines, M first initial signal lines, M second initial signal lines, 4N first power supply lines, and 6N data signal lines, where M is the total number of rows of pixel units, and N is the total number of columns of pixel units;

[0055] At least one signal line among the reset signal line, the scan signal line, the light emitting signal line, the first initial signal line, and the second initial signal line extends at least partially along the first direction, and at least one signal line among the first power line and the data signal line extends at least partially along the second direction;

[0056] The pixel unit in the i-th row and j-th column is electrically connected to the 2i-1th scanning signal line, the 2i-th scanning signal line, the 2i-1th reset signal line, the 2i-1th reset signal line, the 2i-1th light-emitting signal line, the 2i-th light-emitting signal line, the i-th first initial signal line, the i-th second initial signal line, the 4j-3th first power line, the 4j-2th first power line, the 4j-1th first power line, the 4j-1th first power line, the 6j-5th data signal line, the 6j-4th data signal line, the 6j-3th data signal line, the 6j-2th data signal line, the 6j-1th data signal line and the 6j data signal line, respectively, 1≤i≤M, 1≤j≤N.

[0057] In an exemplary embodiment, for at least one pixel unit, pixel structures of pixel driving circuits of adjacent sub-pixels are at least partially arranged symmetrically with respect to a virtual straight line extending along the second direction.

[0058] In an exemplary embodiment, in the pixel unit of the i-th row and the j-th column, at least one of the first to sixth sub-pixels is electrically connected to the 2i-1th scan signal line, the 2i-th scan signal line, the 2i-1th reset signal line, the 2i-th reset signal line, the 2i-1th light emitting signal line, the 2i-th light emitting signal line, the ith first initial signal line, and the ith second initial signal line, respectively; the first sub-pixel is also electrically connected to the 6j-5th data signal line and the 4j-3th first power supply line, respectively; and the second The sub-pixels are also electrically connected to the 6j-4th data signal line and the 4j-2th first power line, respectively. The third sub-pixel is also electrically connected to the 6j-3th data signal line and the 4j-2th first power line, respectively. The fourth sub-pixel is also electrically connected to the 6j-2th data signal line and the 4j-1th first power line, respectively. The fifth sub-pixel is also electrically connected to the 6j-1th data signal line and the 4j-1th first power line, respectively. The sixth sub-pixel is also electrically connected to the 6jth data signal line and the 4j first power line, respectively.

[0059] In an exemplary embodiment, the at least one transistor includes: a first light emitting transistor, a second light emitting transistor, a node reset transistor, an anode reset transistor, a write transistor, a compensation transistor, and a drive transistor;

[0060] a first light-emitting transistor and a write transistor electrically connected to a first electrode of the drive transistor, respectively; a second light-emitting transistor electrically connected to a second electrode of the drive transistor and a first electrode of the light-emitting device, respectively; an anode reset transistor electrically connected to the first electrode of the light-emitting device; a compensation transistor electrically connected to a gate electrode and a second electrode of the drive transistor, respectively; and a node reset transistor electrically connected to the gate electrode of the drive transistor;

[0061] For the pixel unit in the i-th row and j-th column, the gate electrode of the first light-emitting transistor in at least one sub-pixel is electrically connected to the 2i-1th light-emitting signal line, the gate electrode of the second light-emitting transistor is electrically connected to the 2i-1th light-emitting signal line, the gate electrode of the write transistor is electrically connected to the 2i-1th scanning signal line, the gate electrode of the compensation transistor is electrically connected to the 2i-1th scanning signal line, the gate electrode of the node reset transistor is electrically connected to the 2i-1th reset signal line, and the gate electrode of the anode reset transistor is electrically connected to the 2i reset signal line.

[0062] In an exemplary embodiment, for the i-th row of pixel units, the orthographic projections of the 2i-1th light emitting signal line, the 2i-1th scan signal line, the 2i-1th scan signal line, the 2j-1th reset signal line, the i-th first initial signal line, the 2i-th light emitting signal line, the 2i-th reset signal line, and the i-th second initial signal line on the substrate are arranged sequentially along the second direction;

[0063] For at least one pixel unit, the orthographic projection of the data signal line connected to the xth subpixel and the x+1th subpixel on the substrate is located between the orthographic projections of the first power line connected to the xth subpixel and the x+1th subpixel on the substrate, and 1≤x≤6 is an odd number.

[0064] In an exemplary embodiment, the odd-numbered scan signal lines include: a first sub-scanning signal line and a second sub-scanning signal line connected to each other, the first sub-scanning signal line and the second sub-scanning signal line extending along a first direction, and orthographic projections of the first sub-scanning signal line and the second sub-scanning signal line on the substrate at least partially overlapping;

[0065] The first sub-scanning signal line is located in the first conductive layer, and the second sub-scanning signal line is located in the third conductive layer.

[0066] In an exemplary embodiment, the even-numbered reset signal lines include: a first sub-reset signal line and a second sub-reset signal line connected to each other, the first sub-reset signal line and the second sub-reset signal line extending along a first direction, and orthographic projections of the first sub-reset signal line and the second sub-reset signal line on the substrate at least partially overlapping;

[0067] The first sub-reset signal line is located in the first conductive layer, and the second sub-reset signal line is located in the third conductive layer.

[0068] In an exemplary embodiment, the light emitting signal line is located in a first conductive layer, the first initial signal line and the second initial signal line are located in a second conductive layer, the even-numbered scanning signal lines and the odd-numbered reset signal lines are located in a third conductive layer, and the data signal line and the first power supply line are located in the fourth conductive layer.

[0069] In an exemplary embodiment, the plurality of signal lines include: a plurality of first initial signal lines and a plurality of second initial signal lines, and the display substrate further includes: at least one connection line of the first initial connection line and the second initial connection line;

[0070] The first initial connection line extends along the second direction and is located between adjacent pixel units, and the first initial connection line is electrically connected to a plurality of first initial signal lines;

[0071] The second initial connection line extends along the second direction and is located between adjacent pixel units, and the second initial connection line is electrically connected to a plurality of second initial signal lines;

[0072] The first initial connection line and the second initial connection line are located in the fourth conductive layer or the fifth conductive layer.

[0073] In an exemplary embodiment, the system further includes: a first multiplexing control signal line, a second multiplexing control signal line, 6N data signal lines, 3N data power supply lines, and a data multiplexing circuit, wherein the data multiplexing circuit includes: N sub-multiplexing circuits, where N is the total number of columns of pixel units;

[0074] The nth sub-multiplexing circuit is electrically connected to three data power supply lines, a first multiplexing control signal line, a second multiplexing control signal line, and six data signal lines connected to the nth column of pixel units, and is configured to provide a signal of at least one data power supply line to at least one data signal line under the signal control of the first multiplexing control signal line and the second multiplexing control signal line; 1≤n≤N.

[0075] In an exemplary embodiment, the nth sub-multiplexing circuit includes: first to sixth multiplexing transistors;

[0076] a gate electrode of the first multiplexing transistor electrically connected to the first multiplexing control signal line, a first electrode of the first multiplexing transistor electrically connected to the data signal line connected to one of the first sub-pixel and the second sub-pixel in the n-th column of pixel units, and a second electrode of the first multiplexing transistor electrically connected to the first data power supply line of the three data power supply lines connected to the n-th multiplexing sub-circuit;

[0077] a gate electrode of the second multiplexing transistor electrically connected to the first multiplexing control signal line, a first electrode of the second multiplexing transistor electrically connected to a data signal line connected to one of the third sub-pixel and the fourth sub-pixel in the n-th column of pixel units, and a second electrode of the second multiplexing transistor electrically connected to a second data power supply line of the three data power supply lines connected to the n-th multiplexing sub-circuit;

[0078] a gate electrode of the third multiplexing transistor being electrically connected to the first multiplexing control signal line, a first electrode of the third multiplexing transistor being electrically connected to a data signal line connected to one of the fifth sub-pixel and the sixth sub-pixel in the n-th column of pixel units, and a second electrode of the third multiplexing transistor being electrically connected to a third data power supply line of the three data power supply lines connected to the n-th multiplexing sub-circuit;

[0079] a gate electrode of the fourth multiplexing transistor electrically connected to the second multiplexing control signal line, a first electrode of the fourth multiplexing transistor electrically connected to the data signal line connected to the first sub-pixel and the other sub-pixel of the second sub-pixel in the n-th column of pixel units, and a second electrode of the fourth multiplexing transistor electrically connected to the first data power supply line of the three data power supply lines connected to the n-th multiplexing sub-circuit;

[0080] a gate electrode of the fifth multiplexing transistor being electrically connected to the second multiplexing control signal line, a first electrode of the fifth multiplexing transistor being electrically connected to the data signal line connected to the third sub-pixel and the other sub-pixel of the fourth sub-pixel in the n-th column of pixel units, and a second electrode of the fifth multiplexing transistor being electrically connected to the second data power supply line of the three data power supply lines connected to the n-th multiplexing sub-circuit;

[0081] The gate electrode of the sixth multiplexing transistor is electrically connected to the second multiplexing control signal line, the first electrode of the sixth multiplexing transistor is electrically connected to the data signal line connected to the fifth sub-pixel in the n-th column pixel unit and another sub-pixel in the sixth sub-pixel, and the second electrode of the sixth multiplexing transistor is electrically connected to the third data power supply line of the three data power supply lines connected to the n-th multiplexing sub-circuit.

[0082] In a second aspect, the present disclosure further provides a display device, comprising: the above-mentioned display substrate.

[0083] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0084] Summary of the Figures

[0085] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0086] FIG1A is a schematic structural diagram of a display device;

[0087] FIG1B is a schematic diagram of an equivalent circuit of a pixel driving circuit;

[0088] FIG1C is a timing diagram of an operation of a pixel driving circuit;

[0089] FIG2 is a schematic structural diagram of a display substrate provided in an embodiment of the present disclosure;

[0090] FIG3 is a first structural diagram of a display substrate provided in an embodiment of the present disclosure;

[0091] FIG4 is a schematic diagram of a portion of the film layer in FIG3 ;

[0092] FIG5 is a second structural diagram of a display substrate provided in an embodiment of the present disclosure;

[0093] FIG6 is a schematic diagram of a portion of the film layer in FIG5 ;

[0094] FIG7 is a third structural diagram of a display substrate provided in an embodiment of the present disclosure;

[0095] FIG8 is a schematic diagram of a portion of the film layer in FIG7 ;

[0096] FIG9 is a fourth structural diagram of a display substrate provided in an embodiment of the present disclosure;

[0097] FIG10 is a schematic diagram of part of the film layer in FIG9;

[0098] FIG11A is a schematic structural diagram of a display substrate provided in an exemplary embodiment;

[0099] FIG11B is a schematic structural diagram of a display substrate provided in another exemplary embodiment;

[0100] FIG12A is a schematic diagram showing the structure of a data multiplexing circuit in a display substrate;

[0101] FIG12B is an equivalent circuit diagram of a sub-multiplexing circuit;

[0102] FIG13 is a schematic diagram showing a semiconductor layer pattern in a display substrate provided in FIG3 and FIG5 ;

[0103] FIG14 is a schematic diagram showing a pattern of a semiconductor layer in a display substrate provided in FIG7 ;

[0104] FIG15 is a schematic diagram showing a pattern of a semiconductor layer in a display substrate provided in FIG9 ;

[0105] FIG16 is a schematic diagram showing a first conductive layer pattern in a display substrate provided in FIG3 and FIG5 ;

[0106] FIG17 is a schematic diagram of the display substrate provided in FIG3 and FIG5 after a first conductive layer pattern is formed;

[0107] FIG18 is a schematic diagram showing a pattern of a first conductive layer in a display substrate provided in FIG7 ;

[0108] FIG19 is a schematic diagram of the display substrate provided in FIG7 after a first conductive layer pattern is formed;

[0109] FIG20 is a schematic diagram showing a pattern of a first conductive layer in the display substrate provided in FIG9 ;

[0110] FIG21 is a schematic diagram of the display substrate provided in FIG9 after a first conductive layer pattern is formed;

[0111] FIG22 is a schematic diagram showing a second conductive layer pattern in a display substrate provided in FIG3 and FIG5 ;

[0112] FIG23 is a schematic diagram of the display substrate provided in FIG3 and FIG5 after a second conductive layer pattern is formed;

[0113] FIG24 is a schematic diagram showing a second conductive layer pattern in the display substrate provided in FIG7 ;

[0114] FIG25 is a schematic diagram of the display substrate provided in FIG7 after a second conductive layer pattern is formed;

[0115] FIG26 is a schematic diagram showing a second conductive layer pattern in the display substrate provided in FIG9 ;

[0116] FIG27 is a schematic diagram of the display substrate provided in FIG9 after a second conductive layer pattern is formed;

[0117] FIG28 is a schematic diagram showing a third insulating layer formed on the display substrate provided in FIG3 and FIG5;

[0118] FIG29 is a schematic diagram showing a third insulating layer formed on the display substrate provided in FIG7 ;

[0119] FIG30 is a schematic diagram showing a third insulating layer formed on the display substrate provided in FIG9 ;

[0120] FIG31 is a schematic diagram showing a second conductive layer pattern in a display substrate provided in FIG3 and FIG5 ;

[0121] FIG32 is a schematic diagram of the display substrate provided in FIG3 and FIG5 after a second conductive layer pattern is formed;

[0122] FIG33 is a schematic diagram showing a second conductive layer pattern in the display substrate provided in FIG7 ;

[0123] FIG34 is a schematic diagram of the display substrate provided in FIG7 after a second conductive layer pattern is formed;

[0124] FIG35 is a schematic diagram showing a second conductive layer pattern in the display substrate provided in FIG9 ;

[0125] FIG36 is a schematic diagram of the display substrate provided in FIG9 after a second conductive layer pattern is formed;

[0126] FIG37 is a schematic diagram of the display substrate provided in FIG3 and FIG5 after a first flat layer is formed;

[0127] FIG38 is a schematic diagram of the display substrate provided in FIG7 after a first flat layer is formed;

[0128] FIG39 is a schematic diagram of the display substrate provided in FIG9 after a first flat layer is formed;

[0129] FIG40 is a schematic diagram showing a pattern of a fourth conductive layer in the display substrate provided in FIG3 ;

[0130] FIG41 is a schematic diagram of the display substrate provided in FIG3 after a fourth conductive layer pattern is formed;

[0131] FIG42 is a schematic diagram showing a pattern of a fourth conductive layer in the display substrate provided in FIG5 ;

[0132] FIG43 is a schematic diagram of the display substrate provided in FIG5 after a fourth conductive layer pattern is formed;

[0133] FIG44 is a schematic diagram showing a pattern of a fourth conductive layer in the display substrate provided in FIG7 ;

[0134] FIG45 is a schematic diagram of the display substrate provided in FIG7 after a fourth conductive layer pattern is formed;

[0135] FIG46 is a schematic diagram showing a pattern of a fourth conductive layer in the display substrate provided in FIG9 ;

[0136] FIG47 is a schematic diagram of the display substrate provided in FIG9 after a fourth conductive layer pattern is formed;

[0137] FIG48 is a schematic diagram of the display substrate provided in FIG3 after a second planarization layer is formed;

[0138] FIG49 is a schematic diagram of the display substrate provided in FIG5 after a second planarization layer is formed;

[0139] FIG50 is a schematic diagram of the display substrate provided in FIG7 after a second planarization layer is formed;

[0140] FIG51 is a schematic diagram of the display substrate provided in FIG9 after a second planarization layer is formed;

[0141] FIG52 is a schematic diagram showing a fifth conductive layer pattern in the display substrate provided in FIG3 ;

[0142] FIG53 is a schematic diagram of the display substrate provided in FIG3 after a fifth conductive layer pattern is formed;

[0143] FIG54 is a schematic diagram showing a fifth conductive layer pattern in the display substrate provided in FIG5 ;

[0144] FIG55 is a schematic diagram of the display substrate provided in FIG5 after a fifth conductive layer pattern is formed;

[0145] FIG56 is a schematic diagram showing a fifth conductive layer pattern in the display substrate provided in FIG7 ;

[0146] FIG57 is a schematic diagram of the display substrate provided in FIG7 after a fifth conductive layer pattern is formed;

[0147] FIG58 is a schematic diagram showing a pattern of a fifth conductive layer in the display substrate provided in FIG9 ;

[0148] FIG59 is a schematic diagram of the display substrate provided in FIG9 after a fifth conductive layer pattern is formed;

[0149] FIG60 is a schematic diagram of the display substrate provided in FIG3 after a third planarization layer is formed;

[0150] FIG61 is a schematic diagram of the display substrate provided in FIG5 after a third planarization layer is formed;

[0151] FIG62 is a schematic diagram of the display substrate provided in FIG7 after a third planarization layer is formed;

[0152] FIG63 is a schematic diagram of the display substrate provided in FIG9 after a third planarization layer is formed;

[0153] FIG64 is a schematic diagram showing a sixth conductive layer pattern in the display substrate provided in FIG3 and FIG5 ;

[0154] FIG65 is a schematic diagram of the display substrate provided in FIG3 after a sixth conductive layer pattern is formed;

[0155] FIG66 is a schematic diagram of the display substrate provided in FIG5 after a sixth conductive layer pattern is formed;

[0156] FIG67 is a schematic diagram showing a sixth conductive layer pattern in the display substrate provided in FIG7 ;

[0157] FIG68 is a schematic diagram of the display substrate provided in FIG7 after a sixth conductive layer pattern is formed;

[0158] FIG69 is a schematic diagram showing a sixth conductive layer pattern in the display substrate provided in FIG9 ;

[0159] FIG70 is a schematic diagram of the display substrate provided in FIG9 after a sixth conductive layer pattern is formed;

[0160] FIG71 is a schematic diagram of the display substrate provided in FIG3 after a pixel definition layer is formed;

[0161] FIG72 is a schematic diagram of the display substrate provided in FIG5 after forming a pixel definition layer;

[0162] FIG73 is a schematic diagram of the display substrate provided in FIG7 after forming a pixel definition layer;

[0163] FIG74 is a schematic diagram of the display substrate provided in FIG9 after forming a pixel definition layer.

[0164] Details

[0165] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. Unless there is a conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of some known functions and known components. The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure. Other structures can refer to the general design

[0166] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0167] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0168] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0169] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0170] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0171] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" may be interchanged.

[0172] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0173] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0174] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0175] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures using the same patterning process. The materials of these structures can be the same or different. For example, the precursor materials for forming the multiple structures arranged in the same layer can be the same, and the materials of the final structures can be the same or different.

[0176] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0177] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0178] The "integrated structure" in the embodiments of the present disclosure may refer to a structure in which two (or more) structures are formed by the same deposition process and patterned by the same composition process to be connected to each other, and their materials may be the same or different.

[0179] With the development of society and the enrichment of material conditions, while display devices provide people with many conveniences, privacy leaks are always inevitable and cannot meet the needs of users.

[0180] Figure 1A is a schematic diagram of the structure of a display device. As shown in Figure 1A, the display device may include a timing controller, a data signal driver, a scan signal driver, a light emitting signal driver, and a pixel array. The timing controller is respectively connected to the data signal driver, the scan signal driver, and the light emitting signal driver. The data signal driver is respectively connected to a plurality of data signal lines (D1 to Dn), the scan signal driver is respectively connected to a plurality of scan signal lines (S1 to Sm), and the light emitting signal driver is respectively connected to a plurality of light emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light emitting device connected to the circuit unit. The circuit unit may include a pixel driving circuit, and the pixel driving circuit may be respectively connected to the scan signal lines, the light emitting signal lines, and the data signal lines.

[0181] In an exemplary embodiment, the timing controller may provide the data signal driver with grayscale values ​​and control signals that meet the specifications of the data signal driver; may provide the scan signal driver with clock signals, scan start signals, and other signals that meet the specifications of the scan signal driver; and may provide the light signal driver with clock signals, emission stop signals, and other signals that meet the specifications of the light signal driver. The data signal driver may use the grayscale values ​​and control signals received from the timing controller to generate data voltages to be supplied to the data signal lines D1, D2, D3, ..., and Dn. For example, the data signal driver may sample grayscale values ​​using the clock signal and apply data voltages corresponding to the grayscale values ​​to the data signal lines D1 to Dn on a pixel row basis, where n may be a natural number. The scan signal driver may generate scan signals to be supplied to the scan signal lines S1, S2, S3, ..., and Sm by receiving the clock signal, scan start signals, and other signals from the timing controller. For example, the scan signal driver may sequentially supply scan signals having on-level pulses to the scan signal lines S1 to Sm. For example, the scan signal driver can be constructed in the form of a shift register and can generate a scan signal by sequentially transmitting a scan start signal provided in the form of an on-level pulse to the next level circuit under the control of a clock signal, and m can be a natural number. The light-emitting signal driver can generate an emission signal to be provided to the light-emitting signal lines E1, E2, E3, ... and Eo by receiving a clock signal, an emission stop signal, etc. from a timing controller. For example, the light-emitting signal driver can sequentially provide an emission signal with an off-level pulse to the light-emitting signal lines E1 to Eo. For example, the light-emitting signal driver can be constructed in the form of a shift register and can generate an emission signal by sequentially transmitting an emission stop signal provided in the form of an off-level pulse to the next level circuit under the control of a clock signal, and o can be a natural number.

[0182] In an exemplary embodiment, the light emitting device may be an organic electroluminescent diode (OLED) including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked.

[0183] In an exemplary embodiment, the organic light-emitting layer may include an emissive layer (EML) and any one or more of the following layers: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, one or more of the hole injection layer, hole transport layer, electron blocking layer, hole blocking layer, electron transport layer, and electron injection layer of all sub-pixels may be a common layer connected together, and the emissive layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0184] FIG1B is a schematic diagram of an equivalent circuit of a pixel driving circuit. In an exemplary embodiment, the pixel driving circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. As shown in FIG1B , the pixel driving circuit can include 7 transistors (a first transistor T1 to a seventh transistor T7), a capacitor C, and the pixel driving circuit can be connected to 7 signal segments (a data signal terminal Data, a scan signal terminal Gate, a reset signal terminal Reset, an emission signal terminal EM, a first initial signal terminal INIT1, an anode initial signal terminal INIT2, a first power supply terminal VDD, and a second power supply terminal VSS).

[0185] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, and a third node N3. The first node N1 is connected to the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the second electrode of the fifth transistor T5, respectively. The second node N2 is connected to the second electrode of the first transistor, the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the second end of the capacitor C, respectively. The third node N3 is connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6, respectively.

[0186] In an exemplary embodiment, a first terminal of the capacitor C is connected to the first power supply terminal VDD, and a second terminal of the capacitor C is connected to the second node N2 , ie, the second terminal of the capacitor C is connected to the gate electrode of the third transistor T3 .

[0187] The gate electrode of the first transistor T1 is connected to the reset signal terminal Reset, the first electrode of the first transistor T1 is connected to the first initial signal terminal INIT1, and the second electrode of the first transistor is connected to the second node N2. The first transistor T1 can be called a node reset transistor. When the on-level scanning signal is applied to the reset signal terminal Reset, the first transistor T1 transmits an initialization voltage to the gate electrode of the third transistor T3 to initialize the charge amount of the gate electrode of the third transistor T3.

[0188] The gate electrode of the second transistor T2 is connected to the scan signal terminal Gate, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3. The second transistor can be called a compensation transistor. When the on-level scan signal is applied to the scan signal terminal Gate, the second transistor T2 connects the gate electrode of the third transistor T3 to the second electrode.

[0189] The gate electrode of the third transistor T3 is connected to the second node N2, that is, the gate electrode of the third transistor T3 is connected to the second end of the capacitor C. The first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be called a driving transistor. The third transistor T3 determines the magnitude of the driving current flowing between the first power supply terminal VDD and the second power supply terminal VSS based on the potential difference between the gate electrode and the first electrode of the third transistor T3.

[0190] A gate electrode of the fourth transistor T4 is connected to the scan signal terminal Gate, a first electrode of the fourth transistor T4 is connected to the data signal terminal Data, and a second electrode of the fourth transistor T4 is connected to the first node N1. The fourth transistor T4 can be called a write transistor, etc. When a conduction-level scan signal is applied to the scan signal terminal Gate, the fourth transistor T4 inputs a data voltage at the data signal terminal Data to the pixel driving circuit.

[0191] The gate electrode of the fifth transistor T5 is connected to the light-emitting signal terminal EM, the first electrode of the fifth transistor T5 is connected to the first power supply terminal VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1. The gate electrode of the sixth transistor T6 is connected to the light-emitting signal terminal EM, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting device. The fifth transistor T5 can be referred to as a first light-emitting transistor, and the sixth transistor T6 can be referred to as a second light-emitting transistor. When an on-level light-emitting signal is applied to the light-emitting signal terminal EM, the fifth transistor T5 and the sixth transistor T6 form a drive current path between the first power supply terminal VDD and the second power supply terminal VSS, thereby causing the light-emitting device to emit light.

[0192] The gate electrode of the seventh transistor T7 is connected to the reset signal terminal Reset, the first electrode of the seventh transistor T7 is connected to the second initialization signal terminal INIT2, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light-emitting device. The seventh transistor T71 can be referred to as an anode reset transistor. When the on-level scan signal is applied to the reset signal terminal Reset, the seventh transistor T7 transmits an initialization voltage to the first electrode of the light-emitting device to initialize or release the charge accumulated in the first electrode of the light-emitting device.

[0193] In an exemplary embodiment, the second electrode of the light-emitting device is connected to the second power supply terminal VSS. The signal at the second power supply terminal VSS is a low-level signal, while the signal at the first power supply terminal VDD is a continuously high-level signal. The scan signal terminal Gate is the scan signal terminal in the pixel driving circuit of the current display row, and the reset signal terminal Reset is the scan signal terminal in the pixel driving circuit of the previous display row. The reset signal terminal Reset of the current display row is the same signal terminal as the scan signal terminal Gate in the pixel driving circuit of the previous display row. This can reduce the number of signal terminals on the display substrate and achieve a narrow bezel on the display substrate.

[0194] Transistors can be divided into N-type transistors and P-type transistors according to their characteristics. When the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltages), and the turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltages). When the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltages), and the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltages).

[0195] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be a P-type transistor or an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include P-type transistors and N-type transistors.

[0196] Figure 1C is an operating timing diagram of a pixel driving circuit. The following illustrates exemplary embodiments of the present disclosure using the operating process of the pixel driving circuit illustrated in Figure 1B . The pixel driving circuit in Figure 1B includes seven transistors (first transistor T1 to seventh transistor T7) and one capacitor C. All seven transistors are P-type transistors.

[0197] In an exemplary embodiment, the operation process of the pixel driving circuit may include:

[0198] The first phase S1 is called the reset phase. The signal at the reset signal terminal Reset is a low-level signal, while the signals at the scanning signal terminal Gate and the emission signal terminal EM are high-level signals. The low-level signal at the reset signal terminal Reset turns on the first transistor T1. The signal at the first initial signal terminal INIT1 is supplied to the second node N2, initializing (resetting) the capacitor C and clearing the existing charge in the capacitor. The seventh transistor T7 turns on, and the initial voltage at the second initial signal terminal INIT2 is supplied to the first electrode of the light-emitting device L, initializing (resetting) the first electrode of the light-emitting device L and clearing the pre-stored voltage therein, completing the initialization. The high-level signals at the scanning signal terminal Gate and the emission signal terminal EM turn on the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6. During this phase, the light-emitting device L does not emit light.

[0199] In the second phase S2, also known as the data writing phase or threshold compensation phase, the signal at the scan signal terminal Gate is a low-level signal, the signals at the reset signal terminal Reset and the luminescence signal terminal EM are high-level signals, and the data signal terminal Data outputs a data voltage. During this phase, since the second terminal of capacitor C is at a low level, the third transistor T3 is turned on. The low-level signal at the scan signal terminal Gate turns on the second transistor T2 and the fourth transistor T4. The second transistor T2 and the fourth transistor T4 are turned on, causing the data voltage output by the data signal terminal Data to be provided to the second node N2 via the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The difference between the data voltage output by the data signal terminal Data and the threshold voltage of the third transistor T3 is charged into capacitor C. The voltage at the second terminal of capacitor C (second node N2) is Vd-|Vth|, where Vd is the data voltage output by the data signal terminal Data and Vth is the threshold voltage of the third transistor T3. The signals of the reset signal terminal Reset and the emission signal terminal EM are high-level signals, so that the first transistor T1 , the fifth transistor T5 , the sixth transistor T6 and the seventh transistor T7 are turned off.

[0200] In the third phase S3, referred to as the light-emitting phase, the signal at the light-emitting signal terminal EM is a low-level signal, while the signals at the scan signal terminal Gate and the reset signal terminal Reset are high-level signals. The low-level signal at the light-emitting signal terminal EM turns on the fifth transistor T5 and the sixth transistor T6. The power supply voltage output by the first power supply terminal VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fifth transistor T5, the third transistor T3, and the sixth transistor T6, thereby driving the light-emitting device L to emit light.

[0201] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the second node N2 is Vdata-|Vth|, the driving current of the third transistor T3 is: I=K*(Vgs-Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*(Vdd-Vd) 2

[0202] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light-emitting device L, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data signal terminal Data, and Vdd is the power supply voltage output by the first power supply terminal VDD.

[0203] It can be seen from the derivation results of the above current formula that in the light-emitting stage, the driving current of the third transistor T3 is no longer affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, ensuring uniform display brightness of the display product and improving the display effect of the entire display product.

[0204] Figure 2 is a schematic structural diagram of a display substrate provided in an embodiment of the present disclosure. As shown in Figure 2, the display substrate provided in an embodiment of the present disclosure may include: a substrate and an array of pixel units P disposed on the substrate. At least one pixel unit P includes: a plurality of sub-pixels, the plurality of sub-pixels including: at least one anti-peeping sub-pixel and at least one shared sub-pixel. The at least one sub-pixel includes: a pixel driving circuit and a light-emitting device, the pixel driving circuit being configured to drive the light-emitting device to emit light. The display modes of the display substrate include: a first display mode and a second display mode, wherein the viewing angle range of the first display mode is smaller than the viewing angle range of the second display mode. When the display mode of the display substrate is the first display mode, the anti-peeping sub-pixel emits light. When the display mode of the display substrate is the second display mode, the shared sub-pixel emits light, or both the anti-peeping sub-pixel and the shared sub-pixel emit light. Figure 2 illustrates an example in which a pixel unit includes: three anti-peeping sub-pixels VP1, VP2, and VP3, and three shared sub-pixels SP1, SP2, and SP3.

[0205] In an exemplary embodiment, the first display mode may be referred to as a privacy mode, and the second display mode may be referred to as a sharing mode.

[0206] In exemplary embodiments, the substrate may be a flexible substrate, or may be a rigid substrate.

[0207] The display substrate provided by the embodiment of the present disclosure includes a substrate and pixel units arranged in an array on the substrate, at least one pixel unit includes: a plurality of sub-pixels, the plurality of sub-pixels include: at least one anti-peeping sub-pixel and at least one shared sub-pixel, at least one sub-pixel includes: a pixel driving circuit and a light-emitting device, the pixel driving circuit is configured to drive the light-emitting device to emit light, the display mode of the display substrate includes: a first display mode and a second display mode, the viewing angle range of the first display mode is smaller than the viewing angle range of the second display mode. When the display mode of the display substrate is the first display mode, the anti-peeping sub-pixel emits light, and when the display mode of the display substrate is the second display mode, the shared sub-pixel emits light, or the anti-peeping sub-pixel and the shared sub-pixel emit light. The display substrate provided by the embodiment of the present disclosure includes anti-peeping sub-pixels and shared sub-pixels through the pixel units, and controls different sub-pixels to emit light in different display modes to achieve anti-peeping display and normal display of the display substrate, thereby meeting the needs of users.

[0208] FIG3 is a schematic diagram of the structure of the display substrate provided in an embodiment of the present disclosure, FIG4 is a schematic diagram of a portion of the film layer in FIG3, FIG5 is a schematic diagram of the structure of the display substrate provided in an embodiment of the present disclosure, FIG6 is a schematic diagram of a portion of the film layer in FIG5, FIG7 is a schematic diagram of the structure of the display substrate provided in an embodiment of the present disclosure, FIG8 is a schematic diagram of a portion of the film layer in FIG7, FIG9 is a schematic diagram of the structure of the display substrate provided in an embodiment of the present disclosure, and FIG10 is a schematic diagram of a portion of the film layer in FIG9. As shown in FIG3 to FIG10, the multiple sub-pixels in at least one pixel unit include: first sub-pixel to sixth sub-pixel. FIG3 to FIG10 are described by taking the pixel unit located in the i-th row and j-th column of the display substrate as an example.

[0209] In an exemplary embodiment, as shown in Figures 3 to 10, the pixel driving circuit P1 in the first sub-pixel to the pixel driving circuit P6 in the sixth sub-pixel located in the same pixel unit are arranged in an array along the first direction D1 and the second direction D2 or arranged along the first direction D1, and the first direction D1 and the second direction D2 intersect.

[0210] In an exemplary embodiment, the first and second sub-pixels emit light of a first color, the third and fourth sub-pixels emit light of a second color, and the fifth and sixth sub-pixels emit light of a third color. In an exemplary embodiment, the first, second, and third colors are different colors, one of red, blue, and green. Figures 3 to 10 illustrate the example of a first color being green, a second color being red, and a third color being green.

[0211] As shown in Figures 3 to 10, one of the first and second sub-pixels is an anti-peeping sub-pixel, the other of the first and second sub-pixels is a shared sub-pixel, one of the third and fourth sub-pixels is an anti-peeping sub-pixel, the other of the third and fourth sub-pixels is a shared sub-pixel, one of the fifth and sixth sub-pixels is an anti-peeping sub-pixel, and the other of the fifth and sixth sub-pixels is a shared sub-pixel. Figures 3, 5, and 7 illustrate the example of the first, third, and fifth sub-pixels being anti-peeping sub-pixels and the second, fourth, and sixth sub-pixels being shared sub-pixels. Figure 9 illustrates the example of the first, third, and fifth sub-pixels being shared sub-pixels and the second, fourth, and sixth sub-pixels being anti-peeping sub-pixels.

[0212] In an exemplary embodiment, as shown in Figures 3, 5, 7, and 9, a light-emitting device includes a first electrode, and a display substrate further includes a pixel definition layer, which includes a pixel opening that exposes the first electrode. Figures 3, 5, 7, and 9 illustrate a pixel unit including first electrodes AN1 of a first subpixel to first electrodes AN6 of a sixth subpixel, and the pixel definition layer includes first pixel openings PV1 to sixth pixel openings PV6. The first pixel opening PV1 is a pixel opening that exposes the first electrode AN1 of the first subpixel, the second pixel opening PV2 is a pixel opening that exposes the first electrode AN2 of the second subpixel, the third pixel opening PV3 is a pixel opening that exposes the first electrode AN3 of the third subpixel, the fourth pixel opening PV4 is a pixel opening that exposes the first electrode AN4 of the fourth subpixel, the fifth pixel opening PV5 is a pixel opening that exposes the first electrode AN5 of the fifth subpixel, and the sixth pixel opening PV6 is a pixel opening that exposes the first electrode AN6 of the sixth subpixel.

[0213] In an exemplary embodiment, for an anti-peeping sub-pixel and a shared sub-pixel emitting light of the same color, the area of ​​the first electrode in the anti-peeping sub-pixel is equal to the area of ​​the first electrode in the shared sub-pixel, and the area of ​​the pixel opening exposing the first electrode of the anti-peeping sub-pixel is smaller than the area of ​​the pixel opening exposing the first electrode of the shared sub-pixel. Having the area of ​​the pixel opening exposing the first electrode of the anti-peeping sub-pixel smaller than the area of ​​the pixel opening exposing the first electrode of the shared sub-pixel ensures that the viewing angle range of light emitted by the anti-peeping sub-pixel is smaller, while the viewing angle range of light emitted by the shared sub-pixel is larger, thereby achieving both anti-peeping display and shared display.

[0214] For the display panels shown in Figures 3, 5, 7, and 9, the area of ​​the first electrode AN1 of the first subpixel is equal to the area of ​​the first electrode AN2 of the second subpixel, the area of ​​the first electrode AN3 of the third subpixel is equal to the area of ​​the first electrode AN4 of the fourth subpixel, and the area of ​​the first electrode AN5 of the fifth subpixel is equal to the area of ​​the first electrode AN6 of the sixth subpixel. For the display panels shown in Figures 3, 5, and 7, the area of ​​the first pixel opening PV1 is smaller than the area of ​​the second pixel opening PV2, the area of ​​the third pixel opening PV3 is smaller than the area of ​​the fourth pixel opening PV4, and the area of ​​the fifth pixel opening PV5 is smaller than the area of ​​the sixth pixel opening PV6. For the display panel shown in Figure 9, the area of ​​the first pixel opening PV1 is larger than the area of ​​the second pixel opening PV2, the area of ​​the third pixel opening PV3 is larger than the area of ​​the fourth pixel opening PV4, and the area of ​​the fifth pixel opening PV5 is larger than the area of ​​the sixth pixel opening PV6.

[0215] In an exemplary embodiment, the area of ​​the pixel opening exposing the first electrode of the anti-peeping sub-pixel is smaller than the area of ​​the pixel opening exposing the first electrode of the shared sub-pixel by making the pixel opening exposing the first electrode of the anti-peeping sub-pixel include at least two sub-pixel openings, and the at least two sub-pixel openings are arranged along the first direction D1. As shown in Figures 3, 5 and 7,

[0216] In an exemplary embodiment, as shown in Figures 3, 5, and 7, any pixel opening among the first pixel opening PV1, the third pixel opening PV3, and the fifth pixel opening PV5 includes at least two sub-pixel openings, and the at least two sub-pixel openings are arranged along the first direction D1. Figures 3, 5, and 7 illustrate this by taking the example of a pixel opening that exposes the first electrode of the anti-peep sub-pixel including two sub-pixel openings. As shown in Figure 9, any pixel opening among the second pixel opening PV2, the fourth pixel opening PV4, and the sixth pixel opening PV6 includes at least two sub-pixel openings, and the at least two sub-pixel openings are arranged along the first direction D1. Figure 9 illustrates this by taking the example of a pixel opening that exposes the first electrode of the anti-peep sub-pixel including two sub-pixel openings.

[0217] In an exemplary embodiment, as shown in Figures 3, 5, 7, and 9, for at least one pixel unit, the light-emitting devices of the first subpixel, the light-emitting devices of the second subpixel, the light-emitting devices of the third subpixel, and the light-emitting devices of the fourth subpixel are arranged in sequence along the second direction D2, the light-emitting devices of the fifth subpixel and the light-emitting devices of the sixth subpixel are arranged along the second direction D2, the light-emitting devices of the third subpixel and the light-emitting devices of the fifth subpixel are arranged along the first direction D1, and the light-emitting devices of the fourth subpixel and the light-emitting devices of the sixth subpixel are arranged along the first direction D1. The area of ​​the first electrode AN5 of the fifth subpixel and the area of ​​the first electrode AN6 of the sixth subpixel are greater than the area of ​​the first electrode AN3 of the third subpixel and the area of ​​the first electrode AN4 of the fourth subpixel, and the area of ​​the first electrode AN3 of the third subpixel and the area of ​​the first electrode AN4 of the fourth subpixel are greater than the area of ​​the first electrode AN1 of the first subpixel and the area of ​​the first electrode AN2 of the second subpixel. Figures 3, 5, and 7 illustrate the arrangement of the light-emitting device of the second sub-pixel, the light-emitting device of the first sub-pixel, the light-emitting device of the third sub-pixel, and the light-emitting device of the fourth sub-pixel in sequence along the second direction. Figure 9 illustrates the arrangement of the light-emitting device of the first sub-pixel, the light-emitting device of the second sub-pixel, the light-emitting device of the third sub-pixel, and the light-emitting device of the fourth sub-pixel in sequence along the second direction.

[0218] In an exemplary embodiment, the first electrode of the light emitting device of at least one sub-pixel may include an anode body portion AN-A and an anode connection portion AN-B connected to each other, the anode connection portion AN-B being electrically connected to a pixel driving circuit to which the light emitting device is connected.

[0219] In an exemplary embodiment, the anode body portion AN-A may be rectangular in shape, and corners of the rectangle may be chamfered in an arc shape.

[0220] In an exemplary embodiment, the anode connection portion AN-B may have a block shape.

[0221] FIG11A is a schematic diagram of the structure of a display substrate provided in an exemplary embodiment, and FIG11B is a schematic diagram of the structure of a display substrate provided in another exemplary embodiment. As shown in FIG11A and FIG11B , in an exemplary embodiment, the display substrate may further include: a driving structure layer 200, a light-emitting structure layer 300, an encapsulation layer 400, and an optical structure layer sequentially stacked on a substrate 100. The pixel driving circuit may be provided in the driving structure layer, and the light-emitting device may be provided in the light-emitting structure layer. The optical structure layer includes: at least one of a light-shielding structure layer 500 and an optical device layer 600. The optical device layer 600 is located on the side of the light-shielding structure layer 500 that is close to the substrate 100 or away from the substrate 100. FIG11A illustrates the example of the optical device layer 600 being located on the side of the light-shielding structure layer 500 that is away from the substrate 100. FIG11B illustrates the example of the optical device layer 600 being located on the side of the light-shielding structure layer 500 that is close to the substrate 100.

[0222] In an exemplary embodiment, the light-emitting structure layer may include a first electrode, a pixel definition layer, an organic light-emitting layer, and a second electrode. The first electrode is connected to the pixel driving circuit through a via, the organic light-emitting layer is connected to the first electrode, and the second electrode is connected to the organic light-emitting layer. The organic light-emitting layer emits light of corresponding colors when driven by the first electrode and the second electrode.

[0223] In an exemplary embodiment, the encapsulation structure layer may include a stacked first encapsulation layer, a second encapsulation layer, and a third encapsulation layer. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to ensure that external water vapor cannot enter the light-emitting structure layer.

[0224] In an exemplary embodiment, the display substrate may further include a touch structure layer (not shown in the figure). The touch structure layer may be located between the optical structure layer and the encapsulation layer, or may be located on a side of the optical structure layer away from the substrate.

[0225] In an exemplary embodiment, the touch structure layer may include a first touch insulation layer, a first touch metal layer, a second touch insulation layer, a second touch metal layer and a touch protection layer stacked in sequence. The first touch metal layer may include multiple bridging electrodes, and the second touch metal layer may include multiple first touch electrodes and second touch electrodes. The first touch electrode or the second touch electrode may be connected to the bridging electrode through a via.

[0226] In an exemplary embodiment, as shown in Figures 11A and 11B , the light-shielding structure layer 500 includes a first light-shielding layer 520, a light-shielding base layer 510, and a second light-shielding layer 530. The first light-shielding layer 520 is located on the side of the light-shielding base layer 510 that is closer to the substrate 100, and the second light-shielding layer 530 is located on the side of the light-shielding base layer 510 that is farther from the substrate 100. The first light-shielding layer 520 includes a plurality of first light-shielding structures 521, and the second light-shielding layer 530 includes a plurality of second light-shielding structures 531. Figures 11A and 11B illustrate the light-emitting devices L1 of the first sub-pixel to L6 of the sixth sub-pixel in a pixel unit as an example. In Figures 11A and 11B , the first, third, and fifth sub-pixels are anti-peep sub-pixels, and the second, fourth, and sixth sub-pixels are shared sub-pixels.

[0227] In an exemplary embodiment, the light emitting structure layer may include an organic light emitting layer of a light emitting device of at least one sub-pixel.

[0228] In an exemplary embodiment, as shown in Figures 11A and 11B, the orthographic projection of the first light-shielding layer 520 on the substrate 100 at least partially overlaps with the orthographic projection of the second light-shielding layer 530 on the substrate 100, the first light-shielding structure 521 and the second light-shielding structure 531 are located in the anti-peeping sub-pixel region SR, and the orthographic projections of the first light-shielding structure 521 and the second light-shielding structure 531 on the substrate 100 partially overlap with the orthographic projection of the organic light-emitting layer of at least one anti-peeping sub-pixel on the substrate. The anti-peeping sub-pixel region SR is the region where the anti-peeping sub-pixel is located.

[0229] In an exemplary embodiment, the display substrate further includes a shared sub-pixel region VR. To ensure a larger viewing angle range for shared display, the first light shielding structure 521 and the second light shielding structure 531 are not located in the shared sub-pixel region VR.

[0230] In an exemplary embodiment, as shown in Figures 11A and 11B, the optical device layer 600 includes an optical base layer 610 and a plurality of optical devices 620. The optical devices 620 are located on a side of the optical base layer 610 that is close to the substrate 100 or a side that is far from the substrate 100. The optical devices 620 are configured to converge incident light. The orthographic projections of the optical devices 620 on the substrate 100 at least partially overlap with the orthographic projections of the organic light-emitting layers of the privacy protection sub-pixels on the substrate 100.

[0231] In an exemplary embodiment, the display substrate may further include a plurality of signal lines and a plurality of anode connection lines, and the pixel driving circuit is electrically connected to the plurality of signal lines and the plurality of anode connection lines, respectively.

[0232] In an exemplary embodiment, the driving structure layer may include: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer stacked in sequence on a substrate, the pixel driving circuit includes: at least one transistor and at least one capacitor, the transistor includes: an active pattern, a gate electrode, a first pole and a second pole, and the capacitor includes: a first plate and a second plate.

[0233] In example embodiments, the semiconductor layer may include at least an active pattern of at least one transistor located in at least one sub-pixel.

[0234] In an exemplary embodiment, the first conductive layer may include at least one signal line among the plurality of signal lines, a gate electrode of at least one transistor located in at least one sub-pixel, and a first plate of at least one capacitor.

[0235] In an exemplary embodiment, the second conductive layer may include at least: at least one signal line among the plurality of signal lines and a second plate of at least one capacitor located in at least one sub-pixel.

[0236] In an exemplary embodiment, the third conductive layer may include at least one signal line among the plurality of signal lines and a first electrode and a second electrode of at least one transistor located in at least one sub-pixel.

[0237] In an exemplary embodiment, the fourth conductive layer may include at least: at least one signal line among the plurality of signal lines.

[0238] In example embodiments, the fifth conductive layer may include at least one anode connection line among the plurality of anode connection lines.

[0239] In an exemplary embodiment, as shown in Figures 3 to 8, for at least one pixel unit, the pixel driving circuit P1 of the first sub-pixel, the pixel driving circuit P3 of the third sub-pixel, and the pixel driving circuit P5 of the fifth sub-pixel are arranged in sequence along the first direction D1, the pixel driving circuit P2 of the second sub-pixel, the pixel driving circuit P4 of the fourth sub-pixel, and the pixel driving circuit P6 of the sixth sub-pixel are arranged in sequence along the first direction D1, the pixel driving circuit P1 of the first sub-pixel and the pixel driving circuit P2 of the second sub-pixel are arranged along the second direction D2, the pixel driving circuit P3 of the third sub-pixel and the pixel driving circuit P4 of the fourth sub-pixel are arranged along the second direction D2, and the pixel driving circuit P5 of the fifth sub-pixel and the pixel driving circuit P6 of the sixth sub-pixel are arranged along the second direction D2.

[0240] In an exemplary embodiment, as shown in Figures 3 to 6, in the display substrate provided in Figures 3 and 5, the plurality of signal lines include: 2M reset signal lines RL, 2M scan signal lines GL, 2M light emitting signal lines EL, 2M first initial signal lines INITL1, 2M second initial signal lines INITL2, 3N first power lines VDL and 3N data signal lines DL, where M is the total number of rows of pixel units, and N is the total number of columns of pixel units.

[0241] In an exemplary embodiment, as shown in FIG. 3 to FIG. 6 , at least one of the reset signal line RL, the scan signal line GL, the light emitting signal line EL, the first initial signal line INITL1 , and the second initial signal line INITL2 extends at least partially along the first direction D1 .

[0242] In an exemplary embodiment, as shown in FIG. 3 to FIG. 6 , at least one of the first power line VDL and the data signal line DL at least partially extends along the second direction D2 .

[0243] In an exemplary embodiment, a line width of the first power line VDL is greater than a line width of the data signal line DL.

[0244] In an exemplary embodiment, as shown in FIG4 and FIG6, the pixel unit in the i-th row and the j-th column is respectively connected to the 2i-1-th scanning signal line GL(2i-1), the 2i scanning signal line GL(2i), the 2i-1-th reset signal line RL(2i-1), the 2i reset signal line RL(2i), the 2i-1-th light emitting signal line EL(2i-1), the 2i light emitting signal line EL(2i), the 2i-1-th first initialization signal line INITL1(2i-1), and the 2i-1-th first initialization signal line INITL1(2i-1). 2i), the 2i-1th second initial signal line INITL2(2i-1), the 2ith second initial signal line INITL2(2i-1), the 3j-2th first power line VDL(3j-2), the 3j-1th first power line VDL(3j-1), the 3jth first power line VDL(3j), the 3j-2th data signal line DL(3j-2), the 3j-1th data signal line DL(3j-1) and the 3jth data signal line DL(3j) are electrically connected, 1≤i≤M, 1≤j≤N.

[0245] In an exemplary embodiment, as shown in FIG. 4 and FIG. 6 , for at least one pixel unit, pixel structures of pixel driving circuits of at least two sub-pixels from the first to sixth sub-pixels are at least partially identical.

[0246] In an exemplary embodiment, as shown in FIG4 and FIG6, in the pixel unit of the i-th row and the j-th column, at least one of the first sub-pixel, the third sub-pixel, and the fifth sub-pixel is electrically connected to the 2i-1th scanning signal line GL(2i-1), the 2i-1th light emitting signal line EL(2i-1), the 2i-1th reset signal line RL(2i-1), the 2i-1th first initial signal line INITL1(2i-1), and the 2i-1th second initial signal line INITL2(2i-1), respectively, and at least one of the second sub-pixel, the fourth sub-pixel, and the sixth sub-pixel is electrically connected to the 2i-th scanning signal line GL(2i), the 2i-th light emitting signal line EL(2i), the 2i-th reset signal line RL(2i-1), the 2i-1th first initial signal line INITL1(2i-1), and the 2i-1th second initial signal line INITL2(2i-1), respectively. The signal line RL(2i), the 2i-th first initial signal line INITL1(2i) and the 2i-th second initial signal line INITL2(2i) are electrically connected, at least one sub-pixel among the first sub-pixel and the second sub-pixel is also electrically connected to the 3j-2-th first power line VDL(3j-2) and the 3j-2-th data signal line DL(3j-2), respectively, at least one sub-pixel among the third sub-pixel and the fourth sub-pixel is also electrically connected to the 3j-1-th first power line VDL(3j-1) and the 3j-1-th data signal line DL(3j-1), respectively, and at least one sub-pixel among the fifth sub-pixel and the sixth sub-pixel is also electrically connected to the 3j-th first power line VDL(3j) and the 3j-1 data signal line DL(3j), respectively.

[0247] In an exemplary embodiment, the signals of the 2i-1th scanning signal line GL(2i-1) and the 2ith scanning signal line GL(2i) connected to the same pixel unit may be different. The signals of the 2i-1th emission signal line EL(2i-1) and the 2ith scanning signal line EL(2i) connected to the same pixel unit may be different. The signals of the 2i-1th reset signal line RL(2i-1) and the 2ith reset signal line RL(2i) connected to the same pixel unit may be different.

[0248] In an exemplary embodiment, the orthographic projections of the first initial signal line, the second initial signal line, the reset signal line, the scan signal line, and the light emitting signal line connected to the same sub-pixel on the substrate are arranged sequentially along the second direction D2. For example, as shown in Figures 4 and 6, for the first sub-pixel in the i-th row and j-th column pixel unit, the orthographic projections of the 2i-1th first initial signal line INITL1(2i-1), the 2i-1th second initial signal line INITL2(2i-1), the 2i-1th reset signal line RL(2i-1), the 2i-1th scan signal line GL(2i-1), and the 2i-1th light emitting signal line EL(2i-1) connected to the first sub-pixel on the substrate are arranged sequentially along the second direction D2.

[0249] In an exemplary embodiment, the orthographic projection of the kth data signal line on the substrate is located between the orthographic projection of the kth first power line and the orthographic projection of the k+1th first power line on the substrate, 1≤k≤3N.

[0250] In an exemplary embodiment, at least one transistor includes: a node reset transistor, a driver transistor, and a compensation transistor; the second electrode of the node reset transistor and the first electrode of the compensation transistor are integrally structured and electrically connected to the gate electrode of the driver transistor. The driver transistor and the compensation transistor; the integral structure of the second electrode of the node reset transistor and the first electrode of the compensation transistor constitutes a second node in the pixel drive circuit. The orthographic projection of a first power line VDL on the substrate at least partially overlaps with the orthographic projection of the integral structure of the second electrode of the node reset transistor and the first electrode of the compensation transistor in the sub-pixel to which the first power line is connected. That is, the first power line VDL covers the second node, ensuring that the signal at the second node is not interfered with by other signals, thereby improving the reliability of the display substrate.

[0251] In an exemplary embodiment, as shown in Figures 4 and 6, the first power line VDL includes: a first sub-power line VDL1 and a second sub-power line VDL2 connected to each other, the first sub-power line VDL1 and the second sub-power line VDL2 extend along the second direction D2, and their orthographic projections on the substrate at least partially overlap.

[0252] In an exemplary embodiment, as shown in Figures 3 to 6, the light emitting signal line EL is located in the first conductive layer, the first initial signal line INITL1 and the second initial signal line INITL2 are located in the second conductive layer, the reset signal line RL and the scan signal line GL are located in the third conductive layer, the first sub-power line VDL1 is located in the fourth conductive layer, the second sub-power line VDL2 is located in the fifth conductive layer, and the data signal line DL is located in the fourth conductive layer or the fifth conductive layer. Figures 3 and 4 illustrate the example of the data signal line DL being located in the fourth conductive layer, while Figures 5 and 6 illustrate the example of the data signal line DL being located in the fifth conductive layer.

[0253] In an exemplary embodiment, as shown in Figures 7 and 8, the plurality of signal lines may include: 2M reset signal lines RL, 2M scan signal lines GL, 2M light emitting signal lines EL, 2M first initial signal lines INITL1, 2M second initial signal lines INITL2, 4N first power lines VDL and 6N data signal lines DL, where M is the total number of rows of pixel units and N is the total number of columns of pixel units.

[0254] In an exemplary embodiment, as shown in FIG8 , at least one of the reset signal line RL, the scan signal line GL, the light emitting signal line EL, the first initial signal line INITL1, and the second initial signal line INITL2 extends at least partially along the first direction D1, and at least one of the first power line VDL and the data signal line DL extends at least partially along the second direction D2.

[0255] In an exemplary embodiment, as shown in FIG8 , the pixel unit in the i-th row and the j-th column is respectively connected to the 2i-1-th scanning signal line GL(2i-1), the 2i scanning signal line GL(2i), the 2i-1-th reset signal line RL(2i-1), the 2i reset signal line RL(2i), the 2i-1-th light emitting signal line EL(2i-1), the 2i light emitting signal line EL(2i), the 2i-1-th first initial signal line INITL1(2i-1), the 2i first initial signal line INITL1(2i), the 2i-1-th second initial signal line INITL2(2i-1), and the 2i second initial signal line INITL2(2i), the 4j-3th first power line VDL(4j-3), the 4j-2th first power line VDL(4j-2), the 4j-1th first power line VDL(4j-1), the 4jth first power line VDL(4j), the 6j-5th data signal line DL(6j-5), the 6j-4th data signal line DL(6j-4), the 6j-3th data signal line DL(6j-3), the 6j-2th data signal line DL(6j-2), the 6j-1th data signal line DL(6j-1) and the 6jth data signal line DL(6j) are electrically connected, 1≤i≤M, 1≤j≤N.

[0256] In an exemplary embodiment, as shown in FIG8 , for at least one pixel unit, the pixel structures of the pixel driving circuits of at least two sub-pixels among the first sub-pixel, the third sub-pixel, and the fifth sub-pixel are at least partially identical, the pixel structures of the pixel driving circuits of at least two sub-pixels among the second sub-pixel, the fourth sub-pixel, and the sixth sub-pixel are at least partially identical, and the pixel structure of the pixel driving circuit P1 of the first sub-pixel is at least partially mirror-symmetrical to the pixel structure of the pixel driving circuit P2 of the second sub-pixel.

[0257] In an exemplary embodiment, as shown in FIG8 , in the pixel unit of the i-th row and the j-th column, at least one sub-pixel among the first sub-pixel, the third sub-pixel, and the fifth sub-pixel is electrically connected to the 2i-1th scanning signal line GL(2i-1), the 2i-1th light emitting signal line EL(2i-1), the 2i-1th reset signal line RL(2i-1), the 2i-1th first initial signal line INITL1(2i-1), and the 2i-1th second initial signal line INITL2(2i-1), respectively, and at least one sub-pixel among the second sub-pixel, the fourth sub-pixel, and the sixth sub-pixel is electrically connected to the 2i-th scanning signal line GL(2i), the 2i-th light emitting signal line EL(2i), the 2i-th reset signal line RL(2i), the 2i-th first initial signal line INITL1(2i), and the 2i-th second initial signal line INITL2(2i), respectively. The sub-pixel is also electrically connected to the 6j-4th data signal line DL (6j-4) and the 4j-2th first power line VDL (4j-2), respectively. The second sub-pixel is also electrically connected to the 6j-5th data signal line DL (6j-5) and the 4j-3th first power line VDL (4j-3), respectively. The third sub-pixel is also electrically connected to the 6j-2nd data signal line DL (6j-2) and the 4j-1st first power line VDL (4j-1), respectively. The fourth sub-pixel is also electrically connected to the 6j-3th data signal line DL (6j-3) and the 4j-2th first power line VDL (4j-2), the fifth sub-pixel is also electrically connected to the 6j-th data signal line DL (6j) and the 4j-1st first power line VDL (4j), and the sixth sub-pixel is also electrically connected to the 6j-1th data signal line DL (6j-1) and the 4j-1th first power line VDL (4j-1).

[0258] In an exemplary embodiment, the signals of the 2i-1th scanning signal line GL(2i-1) and the 2i scanning signal line GL(2i) connected to the same pixel unit can be the same. The signals of the 2i-1th emission signal line EL(2i-1) and the 2i scanning signal line EL(2i) connected to the same pixel unit can be the same. The signals of the 2i-1th reset signal line RL(2i-1) and the 2i reset signal line RL(2i) connected to the same pixel unit can be the same.

[0259] In an exemplary embodiment, as shown in FIG8 , the orthographic projection of the first initial signal line INITL1, the second initial signal line INITL2, the reset signal line RL, the scan signal line GL, and the light emitting signal line EL connected to the same sub-pixel on the substrate are sequentially arranged along the second direction D2. For example, as shown in FIG8 , for the first sub-pixel in the i-th row and j-th column pixel unit, the orthographic projections of the 2i-1th first initial signal line INITL1(2i-1), the 2i-1th second initial signal line INITL2(2i-1), the 2i-1th reset signal line RL(2i-1), the 2i-1th scan signal line GL(2i-1), and the 2i-1th light emitting signal line EL(2i-1) connected to the first sub-pixel on the substrate are sequentially arranged along the second direction D2.

[0260] In an exemplary embodiment, as shown in FIG8 , for at least one pixel unit, the orthographic projections on the substrate of the two data signal lines DL connected to the two sub-pixels arranged along the second direction D2 are located between the orthographic projections on the substrate of the two first power lines VDL connected to the two sub-pixels. For example, for the pixel unit in the i-th row and j-th column, the orthographic projection on the substrate of the 6j-4th data signal line DL (6j-4) connected to the first sub-pixel and the orthographic projection on the substrate of the 6j-5th data signal line DL (6j-5) connected to the second sub-pixel are located between the orthographic projection on the substrate of the 4j-2th first power line VDL (4j-2) connected to the first sub-pixel and the orthographic projection on the substrate of the 4j-3th first power line VDL (4j-3) connected to the second sub-pixel.

[0261] In an exemplary embodiment, as shown in FIG8 , at least one transistor includes: a node reset transistor, a driving transistor, and a compensation transistor; the second electrode of the node reset transistor and the first electrode of the compensation transistor are an integrated structure and are electrically connected to the gate electrode of the driving transistor. The integrated structure of the second electrode of the node reset transistor and the first electrode of the compensation transistor is the second node in the pixel driving circuit.

[0262] In an exemplary embodiment, as shown in FIG8 , the capacitor further includes a third electrode plate C3. The third electrode plate C3 is electrically connected to the second electrode plate and is located in the fourth conductive layer. For at least one sub-pixel, the orthographic projection of the third electrode plate C3 on the substrate at least partially overlaps with the orthographic projection of the integrated structure of the second electrode of the node reset transistor and the first electrode of the compensation transistor on the substrate. The orthographic projection of the third electrode plate C3 on the substrate at least partially overlaps with the orthographic projection of the integrated structure of the second electrode of the node reset transistor and the first electrode of the compensation transistor on the substrate, that is, the third electrode plate C3 covers the second node, which can ensure that the signal of the second node is not interfered with by other signals, thereby improving the reliability of the display substrate.

[0263] In an exemplary embodiment, as shown in FIG8 , the orthographic projections of the third plates C3 in the two sub-pixels arranged along the second direction D2 on the substrate are located between the orthographic projections of the two data signal lines DL connected to the two sub-pixels arranged along the second direction D2 on the substrate. For example, for a pixel unit in the i-th row and j-th column, the orthographic projections of the third plates C3 in the first and second sub-pixels on the substrate are located between the orthographic projections of the 6j-4th data signal line DL (6j-4) connected to the first sub-pixel and the orthographic projections of the 6j-5th data signal line DL (6j-5) connected to the second sub-pixel on the substrate.

[0264] In an exemplary embodiment, as shown in FIG8 , the light emitting signal line EL is located in the first conductive layer, the first initial signal line INITL1 and the second initial signal line INITL2 are located in the second conductive layer, the reset signal line RL and the scan signal line GL are located in the third conductive layer, and the data signal line DL and the first power line VDL are located in the fourth conductive layer.

[0265] In an exemplary embodiment, as shown in Figures 9 and 10, for at least one pixel unit, the pixel driving circuit P1 of the first sub-pixel, the pixel driving circuit P2 of the second sub-pixel, the pixel driving circuit P3 of the third sub-pixel, the pixel driving circuit P4 of the fourth sub-pixel, the pixel driving circuit P5 of the fifth sub-pixel and the pixel driving circuit P6 of the sixth sub-pixel are arranged in sequence along the first direction D1.

[0266] In an exemplary embodiment, in the display panel provided in FIG9 , the plurality of signal lines may include: 2M reset signal lines RL, 2M scan signal lines GL, 2M light-emitting signal lines EL, M first initial signal lines INITL1, M second initial signal lines INITL2, 4N first power lines VDL, and 6N data signal lines DL, where M is the total number of rows of pixel units, and N is the total number of columns of pixel units.

[0267] In an exemplary embodiment, as shown in FIG9 , at least one of the reset signal line RL, the scan signal line GL, the light emitting signal line EL, the first initial signal line INITL1, and the second initial signal line INITL2 extends at least partially along the first direction D1, and at least one of the first power line VDL and the data signal line DL extends at least partially along the second direction D2.

[0268] In an exemplary embodiment, as shown in FIG9 , the pixel unit in the i-th row and the j-th column is respectively connected to the 2i-1-th scanning signal line GL(2i-1), the 2i-th scanning signal line GL(2i), the 2i-1-th reset signal line RL(2i-1), the 2i-th reset signal line RL(2i), the 2i-1-th light emitting signal line EL(2i-1), the 2i-th light emitting signal line EL(2i), the i-th first initial signal line INITL1(i), the i-th second initial signal line INITL2(i), the 4j-3-th first power supply line VDL(4j -3), the 4j-2th first power line VDL (4j-2), the 4j-1th first power line VDL (4j-1), the 4jth first power line VDL (4j), the 6j-5th data signal line DL (6j-5), the 6j-4th data signal line DL (6j-4), the 6j-3th data signal line DL (6j-3), the 6j-2th data signal line DL (6j-2), the 6j-1th data signal line DL (6j-1) and the 6jth data signal line DL (6j) are electrically connected, 1≤i≤M, 1≤j≤N.

[0269] In an exemplary embodiment, as shown in FIG9 , for at least one pixel unit, the pixel structures of the pixel driving circuits of adjacent sub-pixels are at least partially symmetrically arranged with respect to a virtual straight line extending along the second direction D2. For example, the pixel structure of the pixel driving circuit P1 of the first sub-pixel is symmetrically arranged with respect to the virtual straight line extending along the second direction D2, the pixel structure of the pixel driving circuit P3 of the third sub-pixel is symmetrically arranged with respect to the virtual straight line extending along the second direction D2, and the pixel structure of the pixel driving circuit P5 of the fifth sub-pixel is symmetrically arranged with respect to the virtual straight line extending along the second direction D2. The pixel structures of the pixel driving circuit P1 of the first sub-pixel, the pixel structure of the pixel driving circuit P3 of the third sub-pixel, and the pixel structure of the pixel driving circuit P5 of the sixth sub-pixel are at least partially identical, and the pixel structures of the pixel driving circuit P2 of the second sub-pixel, the pixel structure of the pixel driving circuit P4 of the fourth sub-pixel, and the pixel structure of the pixel driving circuit P6 of the sixth sub-pixel are at least partially identical.

[0270] In an exemplary embodiment, as shown in FIG9 , in the pixel unit in the i-th row and the j-th column, at least one of the first to sixth sub-pixels is electrically connected to the 2i-1-th scanning signal line GL(2i-1), the 2i-th scanning signal line GL(2i), the 2i-1-th reset signal line RL(2i-1), the 2i-th reset signal line RL(2i), the 2i-1-th light emitting signal line EL(2i-1), the 2i-th light emitting signal line EL(2i), the i-th first initial signal line INITL1(i), and the i-th second initial signal line INITL2(i), and the first sub-pixel is also electrically connected to the 6j-5-th data signal line DL(6j-5) and the 4j-3-th first power supply line VDL(4j-3), respectively. The second sub-pixel is also electrically connected to the 6j-4th data signal line DL (6j-4) and the 4j-2th first power line VDL (4j-2) respectively, the third sub-pixel is also electrically connected to the 6j-3th data signal line DL (6j-3) and the 4j-2th first power line VDL (4j-2) respectively, the fourth sub-pixel is also electrically connected to the 6j-2th data signal line DL (6j-2) and the 4j-1th first power line VDL (4j-1) respectively, the fifth sub-pixel is also electrically connected to the 6j-1th data signal line DL (6j-1) and the 4j-1th first power line VDL (4j-1) respectively, and the sixth sub-pixel is also electrically connected to the 6jth data signal line DL (6j) and the 4j-1st first power line VDL (4j) respectively.

[0271] In an exemplary embodiment, the signals of the 2i-1th scanning signal line GL(2i-1) and the 2i scanning signal line GL(2i) connected to the same pixel unit can be the same. The signals of the 2i-1th emission signal line EL(2i-1) and the 2i scanning signal line EL(2i) connected to the same pixel unit can be the same. The signals of the 2i-1th reset signal line RL(2i-1) and the 2i reset signal line RL(2i) connected to the same pixel unit can be the same.

[0272] In an exemplary embodiment, the at least one transistor includes: a first light-emitting transistor, a second light-emitting transistor, a node reset transistor, an anode reset transistor, a write transistor, a compensation transistor, and a drive transistor. The first light-emitting transistor and the write transistor are respectively electrically connected to a first electrode of the drive transistor, the second light-emitting transistor is respectively electrically connected to a second electrode of the drive transistor and a first electrode of the light-emitting device, the anode reset transistor is electrically connected to the first electrode of the light-emitting device, the compensation transistor is respectively electrically connected to a gate electrode and a second electrode of the drive transistor, and the node reset transistor is electrically connected to the gate electrode of the drive transistor. As shown in Figure 9, for the pixel unit in the i-th row and j-th column, the gate electrode of the first light-emitting transistor in at least one sub-pixel is electrically connected to the 2i-1th light-emitting signal line EL(2i-1), the gate electrode of the second light-emitting transistor is electrically connected to the 2i-th light-emitting signal line EL(2i), the gate electrode of the write transistor is electrically connected to the 2i-1th scanning signal line GL(2i-1), the gate electrode of the compensation transistor is electrically connected to the 2i-th scanning signal line GL(2i), the gate electrode of the node reset transistor is electrically connected to the 2i-1th reset signal line RL(2i-1), and the gate electrode of the anode reset transistor is electrically connected to the 2i reset signal line RL(2i).

[0273] In an exemplary embodiment, for the i-th row of pixel units, the 2i-1th light emitting signal line EL(2i-1), the 2i-1th scanning signal line GL(2i-1), the 2i-th scanning signal line GL(2i), the 2j-1th reset signal line RL(2i-1), the i-th first initial signal line INITL1(i), the 2i-th light emitting signal line EL(2i), the 2i-th reset signal line RL(2i) and the i-th second initial signal line INITL2(i) are arranged in sequence on the substrate along the second direction D2.

[0274] In an exemplary embodiment, for at least one pixel unit, the orthogonal projections of the data signal line DL connected to the xth subpixel and the x+1th subpixel on the substrate are located between the orthogonal projections of the first power line VDL connected to the xth subpixel and the x+1th subpixel on the substrate, where 1≤x≤6 and is an odd number. For example, for the jth column of pixel units, the orthogonal projection of the 6j-5th data signal line DL (6j-5) connected to the first subpixel and the orthogonal projection of the 6j-4th data signal line DL (6j-4) connected to the second subpixel on the substrate are located between the orthogonal projection of the 4j-3th first power line VDL (4j-3) connected to the first subpixel and the orthogonal projection of the 4j-2nd first power line VDL (4j-2) connected to the second subpixel on the substrate, and the orthogonal projection of the 6j-3th data signal line DL (6j-3) connected to the third subpixel and the 6j-2nd data signal line DL (6j-2) connected to the fourth subpixel on the substrate. The orthographic projection on the substrate is located between the orthographic projection of the 4j-2 first power line VDL (4j-2) connected to the third sub-pixel and the orthographic projection of the 4j-1 first power line VDL (4j-1) connected to the fourth sub-pixel on the substrate, and the orthographic projection of the 6j-1 data signal line DL (6j-1) connected to the fifth sub-pixel and the orthographic projection of the 6j data signal line DL (6j) connected to the sixth sub-pixel on the substrate are located between the orthographic projection of the 4j-1 first power line VDL (4j-1) connected to the fifth sub-pixel and the orthographic projection of the 4j first power line VDL (4j) connected to the sixth sub-pixel on the substrate.

[0275] In an exemplary embodiment, as shown in FIG10 , the odd-numbered scan signal lines GL include a first sub-scanning signal line GL1 and a second sub-scanning signal line GL2 connected to each other. The first sub-scanning signal line GL1 and the second sub-scanning signal line GL2 extend along a first direction D1, and their orthographic projections on the substrate at least partially overlap. The first sub-scanning signal line GL1 is located in the first conductive layer, and the second sub-scanning signal line GL is located in the second third conductive layer.

[0276] In an exemplary embodiment, as shown in FIG10 , the even-numbered reset signal lines RL include a first sub-reset signal line RL1 and a second sub-reset signal line RL2 that are connected to each other. The first sub-reset signal line RL1 and the second sub-reset signal line RL2 extend along a first direction D1, and their orthographic projections on the substrate at least partially overlap. The first sub-reset signal line RL1 is located in the first conductive layer, and the second sub-reset signal line RL2 is located in the third conductive layer.

[0277] In an exemplary embodiment, as shown in FIG10 , the light emitting signal line EL is located on the first conductive layer, the first initial signal line INITL1 and the second initial signal line INITL2 are located on the second conductive layer, the even-numbered scan signal lines and the odd-numbered reset signal lines are located on the third conductive layer, and the data signal line DL and the first power line VDL are located on the fourth conductive layer.

[0278] In an exemplary embodiment, the plurality of signal lines in the display substrate include: a plurality of first initial signal lines INITL1 and a plurality of second initial signal lines INITL2, and the display substrate further includes: at least one of the first initial connection line and the second initial connection line (not shown in the figure). FIG4 provides a display substrate including the first initial connection line NL

[0279] In an exemplary embodiment, the number of the first initial connection lines may be N, and the jth first initial connection line is located on a side of the jth column of pixel units close to the j+1th column of pixel units.

[0280] In an exemplary embodiment, a first initial connection line extends along the second direction D2 and is located between adjacent pixel units. The first initial connection line is electrically connected to a plurality of first initial signal lines INITL1. The first initial connection line NL may be located in the fourth conductive layer or the fifth conductive layer. FIG4 illustrates an example in which the first initial connection line may be located in the fourth conductive layer. The arrangement of the first initial connection line and the plurality of first initial signal lines can form a mesh structure, thereby ensuring display uniformity across the display substrate.

[0281] In an exemplary embodiment, the number of the second initial connection lines may be N.

[0282] In an exemplary embodiment, the second initial connection line extends along the second direction D2 and is located between adjacent pixel units. The second initial connection line is electrically connected to the plurality of second initial signal lines INITL2. The second initial connection line may be located in the fourth conductive layer or the fifth conductive layer. The second initial connection line and the plurality of second initial signal lines may form a mesh structure to ensure display uniformity across the display substrate.

[0283] In an exemplary embodiment, FIG12A is a schematic diagram of the structure of a data multiplexing circuit in a display substrate. As shown in FIG12A , for the display substrate provided in FIG7 and FIG9 , the display substrate may further include: a first multiplexing control signal line MUX1, a second multiplexing control signal line MUX2, 6N data signal lines DL, 3N data power supply lines DSL, and a data multiplexing circuit. The data multiplexing circuit includes: N sub-multiplexing circuits, where N is the total number of pixel columns. The nth sub-multiplexing circuit is electrically connected to the three data power supply lines DSL, the first multiplexing control signal line MUX1, the second multiplexing control signal line MUX2, and the six data signal lines DL connected to the nth column of pixel cells P. The sub-multiplexing circuit is configured to provide a signal from at least one data power supply line DSL to at least one data signal line DL under the control of the first multiplexing control signal line MUX1 and the second multiplexing control signal line MUX2; 1≤n≤N. The provision of the data multiplexing circuit in the present disclosure can reduce the number of signal lines connected to the display substrate's drive signals, thereby achieving a narrow bezel on the display substrate.

[0284] In an exemplary embodiment, FIG12B is an equivalent circuit diagram of a sub-multiplexing circuit. In FIG12B , DL1 is a data signal line connected to the first sub-pixel, DL2 is a data signal line connected to the second sub-pixel, DL3 is a data signal line connected to the third sub-pixel, DL4 is a data signal line connected to the fifth sub-pixel, DL5 is a data signal line connected to the fifth sub-pixel, and DL6 is a data signal line connected to the sixth sub-pixel. DSL1 is the first of three data power supply lines connected to the nth multiplexing sub-circuit, DSL2 is the second of three data power supply lines connected to the nth multiplexing sub-circuit, and DSL3 is the third of three data power supply lines connected to the nth multiplexing sub-circuit. As shown in FIG12B , the nth sub-multiplexing circuit includes first to sixth multiplexing transistors MT1 to MT6.Among them, the gate electrode of the first multiplexing transistor MT1 is electrically connected to the first multiplexing control signal line MUX1, the first electrode of the first multiplexing transistor MT1 is electrically connected to the data signal line connected to one of the first sub-pixel and the second sub-pixel in the n-th column pixel unit, and the second electrode of the first multiplexing transistor MT1 is electrically connected to the first data power supply line DSL1 of the three data power supply lines connected to the n-th multiplexing sub-circuit; the gate electrode of the second multiplexing transistor MT2 is electrically connected to the first multiplexing control signal line MUX1, and the first electrode of the second multiplexing transistor MT2 is electrically connected to the third sub-pixel and the fourth sub-pixel in the n-th column pixel unit. The data signal line connected to one of the sub-pixels in the n-th column is electrically connected, the second electrode of the second multiplexing transistor MT2 is electrically connected to the second data power supply line DSL2 of the three data power supply lines connected to the n-th multiplexing sub-circuit; the gate electrode of the third multiplexing transistor MT3 is electrically connected to the first multiplexing control signal line MUX1, the first electrode of the third multiplexing transistor MT3 is electrically connected to the data signal line connected to one of the fifth sub-pixel and the sixth sub-pixel in the n-th column pixel unit, and the second electrode of the third multiplexing transistor MT3 is electrically connected to the third data power supply line DSL3 of the three data power supply lines connected to the n-th multiplexing sub-circuit. The gate electrode of the fourth multiplexing transistor MT4 is electrically connected to the second multiplexing control signal line MUX2, the first electrode of the fourth multiplexing transistor MT4 is electrically connected to the data signal line connected to the first sub-pixel and the other sub-pixel in the n-th column pixel unit, and the second electrode of the fourth multiplexing transistor MT4 is electrically connected to the first data power supply line DSL1 of the three data power supply lines connected to the n-th multiplexing sub-circuit; the gate electrode of the fifth multiplexing transistor MT5 is electrically connected to the second multiplexing control signal line MUX2, and the first electrode of the fifth multiplexing transistor MT5 is electrically connected to the other sub-pixel in the third sub-pixel and the fourth sub-pixel in the n-th column pixel unit. The data signal line DL connected to the fifth sub-pixel and the sixth sub-pixel in the n-th column of pixel units is electrically connected, and the second electrode of the fifth multiplexing transistor MT5 is electrically connected to the second data power supply line DSL2 of the three data power supply lines connected to the n-th multiplexing sub-circuit; the gate electrode of the sixth multiplexing transistor MT6 is electrically connected to the second multiplexing control signal line MUX2, the first electrode of the sixth multiplexing transistor MT6 is electrically connected to the data signal line DL connected to the fifth sub-pixel and the other sub-pixel in the sixth sub-pixel in the n-th column of pixel units, and the second electrode of the sixth multiplexing transistor MT6 is electrically connected to the third data power supply line DSL3 of the three data power supply lines connected to the n-th multiplexing sub-circuit.Figure 12B is illustrated by an example in which the first electrode of the first multiplexing transistor MT1 is electrically connected to the data signal line DL1 connected to the first sub-pixel in the n-th column pixel unit, the first electrode of the fourth multiplexing transistor MT4 is electrically connected to the data signal line DL2 connected to the second sub-pixel in the n-th column pixel unit, the first electrode of the second multiplexing transistor MT2 is electrically connected to the data signal line DL3 connected to the third sub-pixel in the n-th column pixel unit, the first electrode of the fifth multiplexing transistor MT5 is electrically connected to the data signal line DL5 connected to the fifth sub-pixel in the n-th column pixel unit, the first electrode of the third multiplexing transistor MT3 is electrically connected to the data signal line DL3 connected to the third sub-pixel in the n-th column pixel unit, and the first electrode of the sixth multiplexing transistor MT6 is electrically connected to the data signal line DL6 connected to the sixth sub-pixel in the n-th column pixel unit. The present disclosure does not impose any limitation on this.

[0285] The following is an illustrative explanation using the preparation process of a display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials. Deposition can be performed by any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed by any one or more of spraying, spin coating, and inkjet printing; and etching can be performed by any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a thin film made by deposition, coating, or other processes on a substrate using a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer." If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0286] In an exemplary embodiment, taking a pixel unit as an example, the preparation process of the display substrate may include the following operations.

[0287] (1) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: depositing a semiconductor thin film on a substrate, patterning the semiconductor thin film through a patterning process, and forming a semiconductor layer pattern disposed on the substrate, as shown in Figures 13 to 15 , wherein Figure 13 is a schematic diagram of a semiconductor layer pattern in a display substrate provided in Figures 3 and 5 , Figure 14 is a schematic diagram of a semiconductor layer pattern in a display substrate provided in Figure 7 , and Figure 15 is a schematic diagram of a semiconductor layer pattern in a display substrate provided in Figure 9 .

[0288] In example embodiments, the semiconductor layer pattern may include at least active patterns 11 to 71 of first to seventh transistors located in at least one sub-pixel.

[0289] In an exemplary embodiment, as shown in FIG. 13 , in the display substrates provided in FIG. 3 and FIG. 5 , the structures of the first transistor active pattern 11 to the seventh transistor active pattern 71 of all sub-pixels located in the same pixel unit are at least partially the same.

[0290] In an exemplary embodiment, as shown in FIG14 , in the display substrate provided in FIG7 , the structures of the active pattern 11 of the first transistor to the active pattern 71 of the seventh transistor in the first sub-pixel, the third sub-pixel, and the fifth sub-pixel located in the same pixel unit are at least partially identical, the structures of the active pattern 11 of the first transistor to the active pattern 71 of the seventh transistor in the second sub-pixel, the fourth sub-pixel, and the sixth sub-pixel located in the same pixel unit are at least partially identical, and the structures of the active pattern 11 of the first transistor to the active pattern 71 of the seventh transistor in the first sub-pixel and the second sub-pixel located in the same pixel unit are at least partially mirrored.

[0291] In an exemplary embodiment, as shown in FIG15 , in the display substrate provided in FIG9 , the structures of the active patterns 11 of the first transistor to the active pattern 71 of the seventh transistor in adjacent sub-pixels located in the same pixel unit are at least partially symmetrically arranged along a virtual straight line extending relative to the second direction D2.

[0292] In an exemplary embodiment, as shown in Figures 13 and 14, in the display substrates provided in Figures 3, 5 and 7, the active pattern 11 of the first transistor to the active pattern 61 of the sixth transistor of at least one sub-pixel are interconnected as an integrated structure, and in the second direction D2, the active pattern 61 of the sixth transistor of the sub-pixels in this row is interconnected with the active pattern 71 of the seventh transistor of the sub-pixels in the next row.

[0293] In an exemplary embodiment, as shown in Figures 13 and 14, in the display substrate provided in Figures 3, 5 and 7, in the first direction D1, the active pattern 21 of the second transistor and the active pattern 61 of the sixth transistor can be located on the same side of the active pattern 31 of the third transistor in the present sub-pixel, the active pattern 41 of the fourth transistor and the active pattern 51 of the fifth transistor can be located on the same side of the active pattern 31 of the third transistor in the present sub-pixel, and the active pattern 21 of the second transistor and the active pattern 41 of the fourth transistor can be located on different sides of the active pattern 31 of the third transistor of the present sub-pixel. In the second direction D2, the active pattern 11 of the first transistor, the active pattern 21 of the second transistor, the active pattern 41 of the fourth transistor and the active pattern 71 of the seventh transistor in this sub-pixel can be located on the side of the active pattern 31 of the third transistor in this sub-pixel away from the next row of sub-pixels, and the active pattern 51 of the fifth transistor and the active pattern 61 of the sixth transistor in this row of sub-pixels can be located on the side of the active pattern 31 of the third transistor in this sub-pixel close to the next row of sub-pixels.

[0294] In an exemplary embodiment, as shown in Figures 13 and 14, the active pattern 11 of the first transistor may be shaped like a "bow", the active pattern 21 of the second transistor may be shaped like a "┌", the active pattern 31 of the third transistor may be shaped like an "I", the active pattern 41 of the fourth transistor and the active pattern 51 of the fifth transistor may be shaped like an "I", the active pattern 61 of the sixth transistor may be shaped like an "L", and the active pattern 71 of the seventh transistor may be shaped like an inverted "n".

[0295] In an exemplary embodiment, as shown in FIG15 , in the display substrate provided in FIG9 , the active pattern 11 of the first transistor to the active pattern 41 of the fourth transistor, the active pattern 61 of the sixth transistor, and the active pattern 71 of the seventh transistor of at least one sub-pixel are an integrated structure connected to each other, and the active pattern 51 of the fifth transistor is separately provided.

[0296] In an exemplary embodiment, as shown in FIG15 , in the display substrate provided in FIG9 , in the second direction D2, the active pattern 41 of the fourth transistor and the active pattern 51 of the fifth transistor in the sub-pixel may be located on a side of the active pattern 31 of the third transistor in the sub-pixel away from the sub-pixels in the next row, and the active pattern 11 of the first transistor, the active pattern 21 of the second transistor, the active pattern 61 of the sixth transistor, and the active pattern 71 of the seventh transistor may be located on a side of the active pattern 31 of the third transistor in the sub-pixel closer to the sub-pixels in the next row. The active pattern 11 of the first transistor and the active pattern 21 of the second transistor are arranged along the second direction D2, the active pattern 61 of the sixth transistor and the active pattern 71 of the seventh transistor are arranged along the second direction D2, and the active pattern 11 of the first transistor and the active pattern 61 of the sixth transistor are arranged along the first direction D1.

[0297] In an exemplary embodiment, as shown in FIG15 , the active pattern 11 of the first transistor, the active pattern 21 of the second transistor, the active pattern 41 of the fourth transistor, the active pattern 51 of the fifth transistor, the active pattern 61 of the sixth transistor, and the active pattern 71 of the seventh transistor may be shaped like an “I”, and the active pattern 31 of the third transistor may be shaped like an “I”.

[0298] In example embodiments, the active pattern of each transistor may include a first region, a second region, and a channel region between the first region and the second region. In exemplary embodiments, in the display substrate provided in Figures 3, 5, and 7, the second area 11-2 of the active pattern 11 of the first transistor can serve as the first area 21-1 of the active pattern 21 of the second transistor, the first area 31-1 of the active pattern 31 of the third transistor can simultaneously serve as the second area 41-2 of the active pattern 41 of the fourth transistor and the second area 51-2 of the active pattern 51 of the fifth transistor, the second area 31-2 of the active pattern 31 of the third transistor can simultaneously serve as the second area 21-2 of the active pattern 21 of the second transistor and the first area 61-1 of the active pattern 61 of the sixth transistor, the second area 61-2 of the active pattern 61 of the sixth transistor can serve as the second area 71-2 of the active pattern 71 of the seventh transistor, and the first area 11-1 of the active pattern of the first transistor, the first area 41-1 of the active pattern 41 of the fourth transistor, the first area 51-1 of the active pattern 51 of the fifth transistor, and the first area 71-1 of the active pattern of the seventh transistor can be provided separately. In the display substrate provided in Figure 9, the second area 11-2 of the active pattern 11 of the first transistor can serve as the first area 21-1 of the active pattern 21 of the second transistor, the first area 31-1 of the active pattern 31 of the third transistor can simultaneously serve as the second area 41-2 of the active pattern 41 of the fourth transistor, the second area 31-2 of the active pattern 31 of the third transistor can simultaneously serve as the second area 21-2 of the active pattern 21 of the second transistor and the first area 61-1 of the active pattern 61 of the sixth transistor, the second area 61-2 of the active pattern 61 of the sixth transistor can serve as the second area 71-2 of the active pattern 71 of the seventh transistor, and the first area 11-1 of the active pattern of the first transistor, the first area 41-1 of the active pattern 41 of the fourth transistor, the first area 51-1 and the second area 51-2 of the active pattern 51 of the fifth transistor, and the first area 71-1 of the active pattern of the seventh transistor can be set separately.

[0299] (2) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: depositing a first insulating film and a first conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the first conductive film through a patterning process to form a first insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern disposed on the first insulating layer, as shown in Figures 16 to 21, Figure 16 is a schematic diagram of the first conductive layer pattern in the display substrate provided in Figures 3 and 5, Figure 17 is a schematic diagram of the display substrate provided in Figures 3 and 5 after the first conductive layer pattern is formed, Figure 18 is a schematic diagram of the first conductive layer pattern in the display substrate provided in Figure 7, Figure 19 is a schematic diagram of the display substrate provided in Figure 7 after the first conductive layer pattern is formed, Figure 20 is a schematic diagram of the first conductive layer pattern in the display substrate provided in Figure 9, and Figure 21 is a schematic diagram of the display substrate provided in Figure 9 after the first conductive layer pattern is formed. In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0300] In an exemplary embodiment, as shown in Figures 16 to 19, in the display substrate provided in Figures 3, 5 and 7, the first conductive layer pattern includes at least: a light-emitting signal line EL, a gate electrode 12 of a first transistor to a gate electrode 72 of a seventh transistor located in at least one sub-pixel, and a first plate 24 of a capacitor.

[0301] In an exemplary embodiment, as shown in Figures 16 and 17, in the display substrates provided in Figures 3 and 5, the structures of the gate electrodes 12 of the first transistor to the gate electrode 72 of the seventh transistor and the first plate C1 of the capacitor of all sub-pixels located in the same pixel unit are at least partially the same.

[0302] In an exemplary embodiment, as shown in Figures 18 and 19, in the display substrate provided in Figure 7, the structures of the gate electrode 12 of the first transistor to the gate electrode 72 of the seventh transistor and the first plate C1 of the capacitor in the first sub-pixel, the third sub-pixel and the fifth sub-pixel located in the same pixel unit are at least partially identical, the structures of the gate electrode 12 of the first transistor to the gate electrode 72 of the seventh transistor and the first plate C1 of the capacitor in the second sub-pixel, the fourth sub-pixel and the sixth sub-pixel located in the same pixel unit are at least partially identical, and the structures of the gate electrode 12 of the first transistor to the gate electrode 72 of the seventh transistor and the first plate C1 of the capacitor in the first sub-pixel and the second sub-pixel located in the same pixel unit are at least partially mirrored.

[0303] In an exemplary embodiment, as shown in Figures 16 to 19 , in the display substrates provided in Figures 3 , 5 , and 7 , the first electrode plate C1 and the gate electrode 32 of the third transistor are integrally formed. The integral structure of the first electrode plate C1 and the gate electrode 32 of the third transistor can be rectangular, with chamfered corners. The orthographic projection of the integral structure of the first electrode plate C1 and the gate electrode 32 of the third transistor on the substrate at least partially overlaps with the orthographic projection of the active pattern of the third transistor on the substrate.

[0304] In an exemplary embodiment, as shown in Figures 16 to 19 , the light emitting signal line EL may be in the shape of a line with a main portion extending along the first direction D1. The light emitting signal line EL in this sub-pixel may be located on a side of the integrated structure of the first electrode plate C1 and the gate electrode 32 of the third transistor, closer to the next row of sub-pixels. The area where the light emitting signal line EL overlaps with the active pattern of the fifth transistor in this sub-pixel serves as the gate electrode 52 of the fifth transistor, and the area where the light emitting signal line EL overlaps with the active pattern of the sixth transistor in this sub-pixel serves as the gate electrode 62 of the sixth transistor.

[0305] In an exemplary embodiment, as shown in Figures 16 to 19, the gate electrode 12 of the first transistor and the gate electrode 72 of the seventh transistor in the same sub-pixel are an integrated structure. The integrated structure of the gate electrode 12 of the first transistor and the gate electrode 72 of the seventh transistor is in a strip shape and extends along the first direction D1.

[0306] In an exemplary embodiment, as shown in Figures 16 to 19, the gate electrode 42 of the fourth transistor and the gate electrode 22 of the second transistor in the same sub-pixel are provided separately. The gate electrode 42 of the fourth transistor is strip-shaped and extends along the first direction D1. The gate electrode 22 of the second transistor is shaped like a character "┘". The gate electrode 42 of the fourth transistor in the mth column of the same row and the gate electrode 22 of the second transistor in the m+1th column of the same row are integrally formed.

[0307] In exemplary embodiments, as shown in Figures 16 to 19, the gate electrode 12 of the first transistor includes two overlapping regions with the active pattern of the first transistor, so the first transistor may have a dual-gate structure. The gate electrode 22 of the second transistor includes two overlapping regions with the active pattern of the second transistor, so the second transistor may have a dual-gate structure.

[0308] In an exemplary embodiment, as shown in Figures 20 and 21, in the display substrate provided in Figure 9, the first conductive layer pattern includes at least: odd-numbered light-emitting signal lines EL(2i-1), even-numbered light-emitting signal lines EL(2i), first sub-scanning signal lines GL1(2i-1) of odd-numbered scan signal lines, first sub-reset signal lines RL1(2i) of even-numbered reset signal lines, gate electrodes 12 of the first transistor to the gate electrode 72 of the seventh transistor located in at least one sub-pixel, and a first plate 24 of the capacitor.

[0309] In an exemplary embodiment, as shown in Figures 20 and 21, in the display substrate provided in Figure 9, the structures of the gate electrode 12 of the first transistor to the gate electrode 72 of the seventh transistor and the first plate C1 of the capacitor in adjacent sub-pixels located in the same pixel unit are at least partially arranged symmetrically along a virtual straight line extending relative to the second direction D2.

[0310] In an exemplary embodiment, as shown in Figures 20 and 21 , in the display substrate provided in Figure 9 , the first electrode plate C1 and the gate electrode 32 of the third transistor are integrally formed. The integral structure of the first electrode plate C1 and the gate electrode 32 of the third transistor can be rectangular, with chamfered corners. The orthographic projection of the integral structure of the first electrode plate C1 and the gate electrode 32 of the third transistor on the substrate at least partially overlaps with the orthographic projection of the active pattern of the third transistor on the substrate.

[0311] In an exemplary embodiment, as shown in Figures 20 and 21, the shape of the odd-numbered light-emitting signal line EL(2i-1) can be a line whose main portion extends along the first direction D1. The odd-numbered light-emitting signal line EL(2i-1) in this sub-pixel can be located on a side of the integrated structure of the first electrode plate C1 and the gate electrode 32 of the third transistor, away from the sub-pixels in the next row. The area where the odd-numbered light-emitting signal line EL(2i-1) overlaps with the active pattern of the fifth transistor in this sub-pixel serves as the gate electrode 52 of the fifth transistor.

[0312] In an exemplary embodiment, as shown in FIG20 and FIG21 , the even-numbered light emitting signal lines EL(2i) may be in the shape of a line with a main portion extending along the first direction D1. The even-numbered light emitting signal lines EL(2i) in this sub-pixel may be located on a side of the integrated structure of the first electrode plate C1 and the gate electrode 32 of the third transistor that is closer to the next row of sub-pixels. The region where the even-numbered light emitting signal lines EL(2i) overlap with the active pattern of the sixth transistor of this sub-pixel serves as the gate electrode 62 of the sixth transistor.

[0313] In an exemplary embodiment, as shown in FIG20 and FIG21 , the shape of the first sub-scanning signal line GL1(2i-1) of the odd-numbered scan signal lines may be a line having a main portion extending along the first direction D1. The first sub-scanning signal line GL1(2i-1) of the odd-numbered scan signal lines in this subpixel may be located between the odd-numbered light-emitting signal line EL(2i-1), the integrated structure of the first electrode plate C1, and the gate electrode 32 of the third transistor. The region where the first sub-scanning signal line GL1(2i-1) of the odd-numbered scan signal lines overlaps with the active pattern of the fourth transistor of this subpixel serves as the gate electrode 42 of the fourth transistor.

[0314] In an exemplary embodiment, as shown in FIG20 and FIG21 , the shape of the first sub-reset signal line RL1(2i) of the even-numbered reset signal lines may be a line having a main portion extending along the first direction D1. The first sub-reset signal line RL1(2i) of the even-numbered reset signal lines in the present sub-pixel may be located on a side of the even-numbered light-emitting signal line EL(2i) away from the integrated structure of the first electrode plate C1 and the gate electrode 32 of the third transistor. The region where the first sub-reset signal line RL1(2i) of the even-numbered reset signal lines overlaps with the active pattern of the seventh transistor of the present sub-pixel serves as the gate electrode 72 of the seventh transistor.

[0315] In an exemplary embodiment, as shown in Figures 20 and 21, the gate electrode 12 of the first transistor and the gate electrode 22 of the second transistor in the sub-pixel are located between the integrated structure of the first electrode plate C1 and the gate electrode 32 of the third transistor in the sub-pixel and the even-numbered light-emitting signal line EL(2i) connected to the sub-pixel. The gate electrode 12 of the first transistor and the gate electrode 22 of the second transistor in the same sub-pixel are separately provided. The gate electrode 12 of the first transistor and the gate electrode 22 of the second transistor are shaped like a "[". The gate electrode 12 of the first transistor in the second sub-pixel and the gate electrode 12 of the first transistor in the third sub-pixel in the same sub-pixel are an integrated structure and are in the shape of an "I". The gate electrode 12 of the first transistor in the fourth sub-pixel and the gate electrode 12 of the first transistor in the fifth sub-pixel are an integrated structure and are in the shape of an "I". The gate electrode 22 of the second transistor in the second sub-pixel in the same sub-pixel and the gate electrode 22 of the second transistor in the third sub-pixel are an integrated structure and are in the shape of an "I". The gate electrode 22 of the second transistor in the fourth sub-pixel and the gate electrode 22 of the second transistor in the fifth sub-pixel are an integrated structure and are in the shape of an "I".

[0316] In an exemplary embodiment, as shown in Figures 20 and 21, the odd-numbered light-emitting signal lines EL(2i-1), the even-numbered light-emitting signal lines EL(2i), the first sub-scanning signal lines GL1(2i-1) of the odd-numbered scan signal lines, and the first sub-reset signal lines RL1(2i) of the even-numbered reset signal lines can be designed with equal widths, or can be designed with unequal widths, can be straight lines, or can be broken lines, which not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the signal lines. The present disclosure does not limit this.

[0317] In an exemplary embodiment, after forming the first conductive layer pattern, the first conductive layer can be used as a shield to perform conductorization on the semiconductor layer. The semiconductor layer in the area shielded by the first conductive layer forms the channel region of the first transistor to the seventh transistor, and the semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first area and the second area of ​​the first transistor T1 to the seventh active pattern are both conductorized.

[0318] (5) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: depositing a second insulating film and a second conductive film on the substrate on which the aforementioned pattern is formed, patterning the second conductive film using a patterning process to form a second insulating layer covering the substrate and a second conductive layer pattern formed on the second insulating layer, as shown in Figures 22 and 27, Figure 22 is a schematic diagram of the second conductive layer pattern in the display substrate provided in Figures 3 and 5, Figure 23 is a schematic diagram of the display substrate provided in Figures 3 and 5 after the second conductive layer pattern is formed, Figure 24 is a schematic diagram of the second conductive layer pattern in the display substrate provided in Figure 7, Figure 25 is a schematic diagram of the display substrate provided in Figure 7 after the second conductive layer pattern is formed, Figure 26 is a schematic diagram of the second conductive layer pattern in the display substrate provided in Figure 9, and Figure 27 is a schematic diagram of the display substrate provided in Figure 9 after the second conductive layer pattern is formed. In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0319] In an exemplary embodiment, as shown in Figures 22 to 27, in the display substrate provided in Figures 3, 5, 7 and 9, the second conductive layer pattern includes at least: a first initial signal line INITL1, a second initial signal line INITL2, and a first electrode plate C2 of a capacitor located in at least one sub-pixel.

[0320] In an exemplary embodiment, as shown in FIG. 22 and FIG. 23 , in the display substrates provided in FIG. 3 and FIG. 5 , the structures of the first plates C2 of the capacitors of all sub-pixels in the same pixel unit are at least partially identical.

[0321] In an exemplary embodiment, as shown in Figures 24 and 25, in the display substrate provided in Figure 7, the structures of the first plates C2 of the capacitors in the first sub-pixel, the third sub-pixel, and the fifth sub-pixel located in the same pixel unit are at least partially identical, the structures of the first plates C2 of the capacitors in the second sub-pixel, the fourth sub-pixel, and the sixth sub-pixel located in the same pixel unit are at least partially identical, and the structures of the first plates C2 of the capacitors in the first sub-pixel and the second sub-pixel located in the same pixel unit are at least partially mirrored.

[0322] In an exemplary embodiment, as shown in Figures 22 to 25, in the display substrate provided in Figures 3, 5, and 7, the second electrode C2 includes: a capacitor main body C21 and a capacitor connecting portion C22 that are connected to each other. The capacitor connecting portion C22 is located on a side of the capacitor main body C21 that is close to the second initial signal line INITL2. The outline of the capacitor main body C21 can be rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the capacitor main body C21 on the substrate at least partially overlaps with the orthographic projection of the first electrode on the substrate. An opening K2 is provided on the capacitor main body C21. The shape of the opening K2 can be rectangular and can be located in the middle of the capacitor main body C21, so that the capacitor main body C21 forms a ring structure. The opening K2 exposes the second insulating layer covering the first electrode, and the orthographic projection of the first electrode on the substrate includes the orthographic projection of the opening K2 on the substrate. An opening K1 is formed between the capacitor connection portion C22 and the capacitor body portion C21. The opening K1 can be rectangular in shape. The opening K2 exposes the second insulating layer covering the second region of the active pattern of the first transistor (also the first region of the active pattern of the second transistor). The orthographic projection of the capacitor connection portion C22 on the substrate partially overlaps with a portion of the active pattern of the first transistor. Partial structure of the capacitor connection portion C22 aligns with partial structure of the gate electrode of the second transistor.

[0323] In an exemplary embodiment, as shown in FIG. 22 to FIG. 25 , the capacitor main bodies of the second capacitors located in adjacent sub-pixels in the same row are connected to each other, which can ensure display uniformity of the display substrate.

[0324] In an exemplary embodiment, as shown in Figures 22 to 25, the shape of the first initial signal line INITL1 can be a line shape with a main portion extending along the first direction D1, and the first initial signal line INITL1 connected to the current sub-pixel can be located on the side of the first electrode C2 of the current sub-pixel away from the next row of sub-pixels.

[0325] In an exemplary embodiment, as shown in Figures 22 to 25, the shape of the second initial signal line INITL2 can be a line shape in which the main portion extends along the first direction D1, and the second initial signal line INITL2 connected to the present sub-pixel can be located between the first initial signal line INITL1 connected to the present sub-pixel and the first electrode C2 of the present sub-pixel.

[0326] In an exemplary embodiment, as shown in FIG. 26 and FIG. 27 , in the display substrate provided in FIG. 9 , the structures of the first plates C2 of the capacitors in adjacent sub-pixels in the same pixel unit are at least partially symmetrically arranged along a virtual straight line extending relative to the second direction D2 .

[0327] In an exemplary embodiment, as shown in Figures 26 and 27 , in the display substrate provided in Figure 9 , the second electrode plate C2 may have a rectangular outline, with chamfered corners. The orthographic projection of the second electrode plate C2 on the substrate at least partially overlaps the orthographic projection of the first electrode plate on the substrate. An opening K is provided on the second electrode plate C2. The opening K may be rectangular and located in the center of the second electrode plate C2, forming a ring-shaped structure. The opening K exposes the second insulating layer covering the first electrode plate, and the orthographic projection of the first electrode plate on the substrate includes the orthographic projection of the opening K on the substrate.

[0328] In an exemplary embodiment, as shown in FIG. 22 to FIG. 25 , the second capacitors of adjacent sub-pixels in the same row are connected to each other, which can ensure display uniformity of the display substrate.

[0329] In an exemplary embodiment, as shown in Figures 22 to 25, the shape of the first initial signal line INITL1 can be a line shape with a main portion extending along the first direction D1, and the first initial signal line INITL1 connected to the current sub-pixel can be located on the side of the first electrode C2 of the current sub-pixel close to the next row of sub-pixels.

[0330] In an exemplary embodiment, as shown in Figures 22 to 25, the shape of the second initial signal line INITL2 can be a line shape in which the main portion extends along the first direction D1, and the second initial signal line INITL2 connected to the present sub-pixel can be located between the first initial signal line INITL1 connected to the present sub-pixel and the first electrode C2 away from the present sub-pixel.

[0331] In an exemplary embodiment, as shown in Figures 22 to 27, the first initial signal line INITL1 and the second initial signal line INITL2 can be designed with equal width, or can be designed with unequal width, can be a straight line, or can be a broken line, which not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the signal lines, which is not limited in the present disclosure.

[0332] (4) Forming a third insulating layer pattern. In an exemplary embodiment, forming the third insulating layer pattern may include: depositing a third insulating film on the substrate on which the aforementioned pattern is formed, patterning the third insulating film using a patterning process to form a third insulating layer covering the second conductive layer, wherein a plurality of vias are provided on the third insulating layer, as shown in Figures 28 to 31 , Figure 28 is a schematic diagram of forming a third insulating layer on the display substrate provided in Figures 3 and 5 , Figure 29 is a schematic diagram of forming a third insulating layer on the display substrate provided in Figure 7 , and Figure 30 is a schematic diagram of forming a third insulating layer on the display substrate provided in Figure 9 .

[0333] In an exemplary embodiment, as shown in Figures 28 and 29, in the display substrate provided in Figures 3, 5 and 7, the multiple via holes of the third insulating layer include at least: a first via hole V1, a second via hole V2, a third via hole V3, a fourth via hole V4, a fifth via hole V5, a sixth via hole V6, a seventh via hole V7, an eighth via hole V8, a ninth via hole V9, a tenth via hole V10, an eleventh via hole V11, a twelfth via hole V12 and a thirteenth via hole V13.

[0334] In an exemplary embodiment, the orthographic projection of the first via V1 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the first transistor on the substrate, the first insulating layer and the second insulating layer within the first via V1 are etched away to expose the surface of the first area of ​​the active pattern of the first transistor, and the first via V1 is configured to connect the first electrode of the subsequently formed first transistor to the first area of ​​the active pattern of the first transistor through the via.

[0335] In an exemplary embodiment, the orthographic projection of the second via V2 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the first transistor (also the first area of ​​the active pattern of the second transistor) on the substrate, the first insulating layer and the second insulating layer in the second via V2 are etched away to expose the surface of the second area of ​​the active pattern of the first transistor (also the first area of ​​the active pattern of the second transistor), and the second via V2 is configured to connect the second electrode of the subsequently formed first transistor (also the first electrode of the second transistor) to the second area of ​​the active pattern of the first transistor (also the first area of ​​the active pattern of the second transistor) through the via.

[0336] In an exemplary embodiment, the orthographic projection of the third via V3 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the fourth transistor on the substrate, the first insulating layer and the second insulating layer in the third via V3 are etched away, exposing the surface of the first area of ​​the active pattern of the fourth transistor, and the third via V3 is configured to connect the first electrode of the subsequently formed fourth transistor to the first area of ​​the active pattern of the fourth transistor through the via.

[0337] In an exemplary embodiment, the orthographic projection of the fourth via V4 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the fifth transistor on the substrate, the first insulating layer and the second insulating layer in the fourth via V4 are etched away to expose the surface of the first area of ​​the active pattern of the fifth transistor, and the fourth via V4 is configured to connect the first electrode of the subsequently formed fifth transistor to the first area of ​​the active pattern of the fifth transistor through the via.

[0338] In an exemplary embodiment, the orthographic projection of the fifth via V5 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the sixth transistor (also the second area of ​​the active pattern of the seventh transistor) on the substrate, the first insulating layer and the second insulating layer in the fifth via V5 are etched away to expose the surface of the second area of ​​the active pattern of the sixth transistor (also the second area of ​​the active pattern of the seventh transistor), and the fifth via V5 is configured to connect the second electrode of the subsequently formed sixth transistor (also the second electrode of the seventh transistor) to the second area of ​​the active pattern of the sixth transistor (also the second area of ​​the active pattern of the seventh transistor) through the via.

[0339] In an exemplary embodiment, the orthographic projection of the sixth via V6 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the seventh transistor on the substrate, the first insulating layer and the second insulating layer in the sixth via V6 are etched away to expose the surface of the first area of ​​the active pattern of the seventh transistor, and the sixth via V6 is configured to connect the first electrode of the subsequently formed seventh transistor to the first area of ​​the active pattern of the seventh transistor through the via.

[0340] In an exemplary embodiment, the orthographic projection of the seventh via V7 on the substrate is located within the range of the orthographic projection of the gate electrode of the first transistor (also the gate electrode of the seventh transistor) on the substrate, the second insulating layer in the seventh via V7 is etched away to expose the surface of the gate electrode of the first transistor (also the gate electrode of the seventh transistor), and the seventh via V7 is configured to connect a subsequently formed reset signal line to the gate electrode of the first transistor (also the gate electrode of the seventh transistor) through the via.

[0341] In an exemplary embodiment, the orthographic projection of the eighth via V8 on the substrate is located within the range of the orthographic projection of the gate electrode of the second transistor on the substrate, the second insulating layer in the eighth via V8 is etched away to expose the surface of the gate electrode of the second transistor, and the eighth via V8 is configured to connect a subsequently formed scanning signal line to the gate electrode of the second transistor through the via.

[0342] In an exemplary embodiment, the orthographic projection of the ninth via V9 on the substrate is located within the range of the orthographic projection of the gate electrode of the third transistor (also the first plate of the capacitor) on the substrate, the second insulating layer in the ninth via V9 is etched away to expose the surface of the gate electrode of the third transistor (also the first plate of the capacitor), and the ninth via V9 is configured to connect the second electrode of the subsequently formed first transistor (also the first electrode of the second transistor) to the gate electrode of the third transistor (also the first plate of the capacitor) through the via.

[0343] In an exemplary embodiment, the orthographic projection of the tenth via hole V10 on the substrate is located within the range of the orthographic projection of the gate electrode of the fourth transistor on the substrate, the second insulating layer in the tenth via hole V10 is etched away to expose the surface of the gate electrode of the fourth transistor, and the tenth via hole V10 is configured to connect a subsequently formed scan signal line to the gate electrode of the fourth transistor through the via hole.

[0344] In an exemplary embodiment, the orthographic projection of the eleventh via V11 on the substrate is located within the range of the orthographic projection of the second plate of the capacitor on the substrate, the eleventh via V11 exposes the surface of the second plate of the capacitor, and the eleventh via V11 is configured to connect the first electrode of the subsequently formed fifth transistor to the second plate of the capacitor through the via.

[0345] In an exemplary embodiment, the orthographic projection of the twelfth via V12 on the substrate is located within the range of the orthographic projection of the first initial signal line on the substrate, the twelfth via V12 exposes the surface of the first initial signal line, and the twelfth via V12 is configured to connect the first electrode of the subsequently formed first transistor to the first initial signal line through the via.

[0346] In an exemplary embodiment, the orthographic projection of the thirteenth via V13 on the substrate is located within the range of the orthographic projection of the second initial signal line on the substrate, the thirteenth via V13 exposes the surface of the second initial signal line, and the thirteenth via V13 is configured to connect the first electrode of the subsequently formed seventh transistor to the second initial signal line through the via.

[0347] In an exemplary embodiment, in the display substrates provided in FIG. 3 , FIG. 5 and FIG. 7 , the tenth via hole V10 of the sub-pixel in the nth column and the eighth via hole V8 of the sub-pixel in the (n+1)th column in the same row are the same via hole.

[0348] In an exemplary embodiment, as shown in Figure 30, in the display substrate provided in Figure 9, the multiple via holes of the third insulating layer include at least: a first via hole H1, a second via hole H2, a third via hole H3, a fourth via hole H4, a fifth via hole H5, a sixth via hole H6, a seventh via hole H7, an eighth via hole H8, a ninth via hole H9, a tenth via hole H10, an eleventh via hole H11, a twelfth via hole H12, a thirteenth via hole H13, a fourteenth via hole H14, a fifteenth via hole H15, a sixteenth via hole H16 and a seventeenth via hole H17.

[0349] In an exemplary embodiment, the orthographic projection of the first via H1 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the first transistor on the substrate, the first insulating layer and the second insulating layer in the first via H1 are etched away to expose the surface of the first area of ​​the active pattern of the first transistor, and the first via H1 is configured to connect the first electrode of the subsequently formed first transistor to the first area of ​​the active pattern of the first transistor through the via.

[0350] In an exemplary embodiment, the orthographic projection of the second via H2 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the first transistor (also the first area of ​​the active pattern of the second transistor) on the substrate, the first insulating layer and the second insulating layer in the second via H2 are etched away to expose the surface of the second area of ​​the active pattern of the first transistor (also the first area of ​​the active pattern of the second transistor), and the second via H2 is configured to connect the second electrode of the subsequently formed first transistor (also the first electrode of the second transistor) to the second area of ​​the active pattern of the first transistor (also the first area of ​​the active pattern of the second transistor) through the via.

[0351] In an exemplary embodiment, the orthographic projection of the third via H3 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the second transistor (also the second area of ​​the active pattern of the third transistor and the first area of ​​the active pattern of the sixth transistor) on the substrate, the first insulating layer and the second insulating layer in the third via H3 are etched away, exposing the surface of the second area of ​​the active pattern of the second transistor (also the second area of ​​the active pattern of the third transistor and the first area of ​​the active pattern of the sixth transistor), and the third via H3 is configured to connect the second electrode of the subsequently formed second transistor (also the second electrode of the third transistor and the first electrode of the sixth transistor) to the second area of ​​the active pattern of the second transistor (also the second area of ​​the active pattern of the third transistor and the first area of ​​the active pattern of the sixth transistor) through the via.

[0352] In an exemplary embodiment, the orthographic projection of the fourth via H4 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the third transistor (also the second area of ​​the active pattern of the fourth transistor) on the substrate, the first insulating layer and the second insulating layer in the fourth via H4 are etched away to expose the surface of the first area of ​​the active pattern of the third transistor (also the second area of ​​the active pattern of the fourth transistor), and the fourth via H4 is configured to connect the first electrode of the subsequently formed third transistor (also the second electrode of the fourth transistor) to the first area of ​​the active pattern of the third transistor (also the second area of ​​the active pattern of the fourth transistor) through the via.

[0353] In an exemplary embodiment, the orthographic projection of the fifth via H5 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the fourth transistor on the substrate, the first insulating layer and the second insulating layer in the fifth via H5 are etched away, exposing the surface of the first area of ​​the active pattern of the fourth transistor, and the fifth via H5 is configured to connect the first electrode of the subsequently formed fourth transistor to the first area of ​​the active pattern of the fourth transistor through the via.

[0354] In an exemplary embodiment, the orthographic projection of the sixth via H6 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the fifth transistor on the substrate, the first insulating layer and the second insulating layer in the sixth via H6 are etched away to expose the surface of the first area of ​​the active pattern of the fifth transistor, and the sixth via H6 is configured to connect the first electrode of the subsequently formed fifth transistor to the first area of ​​the active pattern of the fifth transistor through the via.

[0355] In an exemplary embodiment, the orthographic projection of the seventh via H7 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the fifth transistor on the substrate, the first insulating layer and the second insulating layer in the seventh via H7 are etched away to expose the surface of the second area of ​​the active pattern of the fifth transistor, and the seventh via H7 is configured to connect the second electrode of the subsequently formed fifth transistor to the second area of ​​the active pattern of the fifth transistor through the via.

[0356] In an exemplary embodiment, the orthographic projection of the eighth via H8 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the sixth transistor (also the second area of ​​the active pattern of the seventh transistor) on the substrate, the first insulating layer and the second insulating layer in the eighth via H8 are etched away to expose the surface of the second area of ​​the active pattern of the sixth transistor (also the second area of ​​the active pattern of the seventh transistor), and the eighth via H8 is configured to connect the second electrode of the subsequently formed sixth transistor (also the second electrode of the seventh transistor) to the second area of ​​the active pattern of the sixth transistor (also the second area of ​​the active pattern of the seventh transistor) through the via.

[0357] In an exemplary embodiment, the orthographic projection of the ninth via H9 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the seventh transistor on the substrate, the first insulating layer and the second insulating layer in the ninth via H9 are etched away to expose the surface of the first area of ​​the active pattern of the seventh transistor, and the ninth via H9 is configured to connect the first electrode of the subsequently formed seventh transistor to the first area of ​​the active pattern of the seventh transistor through the via.

[0358] In an exemplary embodiment, the orthographic projection of the tenth via H10 on the substrate is located within the range of the orthographic projection of the gate electrode of the first transistor on the substrate, the second insulating layer in the tenth via H10 is etched away, exposing the surface of the gate electrode of the first transistor (which is also the gate electrode of the seventh transistor), and the tenth via H10 is configured to connect the subsequently formed odd-numbered reset signal lines to the gate electrode of the first transistor through the via.

[0359] In an exemplary embodiment, the orthographic projection of the eleventh via H11 on the substrate is located within the range of the orthographic projection of the gate electrode of the second transistor on the substrate, the second insulating layer in the eleventh via H11 is etched away to expose the surface of the gate electrode of the second transistor, and the eleventh via H11 is configured to connect the subsequently formed even-numbered scanning signal lines to the gate electrode of the second transistor through the via.

[0360] In an exemplary embodiment, the orthographic projection of the twelfth via H12 on the substrate is located within the range of the orthographic projection of the gate electrode of the third transistor (also the first plate of the capacitor) on the substrate, and the second insulating layer in the twelfth via H12 is etched away to expose the surface of the gate electrode of the third transistor (also the first plate of the capacitor). The twelfth via H12 is configured to connect a subsequently formed first connecting electrode to the gate electrode of the third transistor (also the first plate of the capacitor) through the via.

[0361] In an exemplary embodiment, the orthographic projection of the thirteenth via hole H13 on the substrate is located within the range of the orthographic projection of the first sub-scanning signal line of the odd-numbered scan signal line on the substrate, the second insulating layer in the thirteenth via hole H13 is etched away to expose the surface of the first sub-scanning signal line of the odd-numbered scan signal line, and the thirteenth via hole H13 is configured to connect the second sub-scanning signal line of the odd-numbered scan signal line formed subsequently to the first sub-scanning signal line of the odd-numbered scan signal line through the via hole.

[0362] In an exemplary embodiment, the orthographic projection of the fourteenth via H14 on the substrate is located within the range of the orthographic projection of the first sub-reset signal line of the even-numbered reset signal lines on the substrate, the second insulating layer in the fourteenth via H14 is etched away, exposing the surface of the first sub-reset signal line of the even-numbered reset signal lines, and the fourteenth via H14 is configured to connect the second sub-reset signal line of the subsequently formed even-numbered reset signal line to the first sub-reset signal line of the even-numbered reset signal lines through the via hole.

[0363] In an exemplary embodiment, the orthographic projection of the fifteenth via H15 on the substrate is located within the range of the orthographic projection of the second plate of the capacitor on the substrate, the fifteenth via H15 exposes the surface of the second plate of the capacitor, and the fifteenth via H15 is configured to connect a subsequently formed power connection line to the second plate of the capacitor through the via.

[0364] In an exemplary embodiment, the orthographic projection of the sixteenth via H16 on the substrate is located within the range of the orthographic projection of the first initial signal line on the substrate, the sixteenth via H16 exposes the surface of the first initial signal line, and the sixteenth via H16 is configured to connect the first electrode of the subsequently formed first transistor to the first initial signal line through the via.

[0365] In an exemplary embodiment, the orthographic projection of the seventeenth via H17 on the substrate is located within the range of the orthographic projection of the second initial signal line on the substrate, the seventeenth via H17 exposes the surface of the second initial signal line, and the seventeenth via H17 is configured to connect the first electrode of the subsequently formed seventh transistor to the second initial signal line through the via.

[0366] (5) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer may include: depositing a third conductive film on the substrate on which the aforementioned pattern is formed, patterning the third conductive film using a patterning process, and forming a third conductive layer disposed on the third insulating layer, as shown in Figures 31 to 36, Figure 31 is a schematic diagram of the second conductive layer pattern in the display substrate provided in Figures 3 and 5, Figure 32 is a schematic diagram of the display substrate provided in Figures 3 and 5 after the second conductive layer pattern is formed, Figure 33 is a schematic diagram of the second conductive layer pattern in the display substrate provided in Figure 7, Figure 34 is a schematic diagram of the display substrate provided in Figure 7 after the second conductive layer pattern is formed, Figure 35 is a schematic diagram of the second conductive layer pattern in the display substrate provided in Figure 9, and Figure 36 is a schematic diagram of the display substrate provided in Figure 9 after the second conductive layer pattern is formed. In an exemplary embodiment, the third conductive layer may be referred to as a first source / drain metal (SD1) layer.

[0367] In an exemplary embodiment, as shown in Figures 31 to 34, in the display substrate provided in Figures 3, 5 and 7, the third conductive layer pattern includes at least: a reset signal line RL, a scan signal line GL, and a first electrode 13 and a second electrode 14 of a first transistor located in at least one sub-pixel, a first electrode 23 of a second transistor, a first electrode 43 of a fourth transistor, a first electrode 53 of a fifth transistor, a second electrode 64 of a sixth transistor, and a first electrode 73 and a second electrode 74 of a seventh transistor.

[0368] In an exemplary embodiment, as shown in Figures 31 and 32, in the display substrates provided in Figures 3 and 5, the structures of the first electrode 13 and the second electrode 14 of the first transistor, the first electrode 23 of the second transistor, the first electrode 43 of the fourth transistor, the first electrode 53 of the fifth transistor, the second electrode 64 of the sixth transistor, and the first electrode 73 and the second electrode 74 of the seventh transistor located in the same pixel unit are at least partially identical.

[0369] In an exemplary embodiment, as shown in Figures 33 and 34, in the display substrate provided in Figure 7, the structures of the first electrode 13 and the second electrode 14 of the first transistor, the first electrode 23 of the second transistor, the first electrode 43 of the fourth transistor, the first electrode 53 of the fifth transistor, the second electrode 64 of the sixth transistor, and the first electrode 73 and the second electrode 74 of the seventh transistor in the first sub-pixel, the third sub-pixel, and the fifth sub-pixel located in the same pixel unit are at least partially the same; the structures of the first electrode 13 and the second electrode 14 of the first transistor, the first electrode 23 of the second transistor, the first electrode 43 of the fourth transistor, the first electrode 53 of the fifth transistor, the second electrode 64 of the sixth transistor, and the first electrode 73 and the second electrode 74 of the seventh transistor in the second sub-pixel, the fourth sub-pixel, and the sixth sub-pixel located in the same pixel unit are at least partially the same; and the structures of the first electrode 13 and the second electrode 14 of the first transistor, the first electrode 23 of the second transistor, the first electrode 43 of the fourth transistor, the first electrode 53 of the fifth transistor, the second electrode 64 of the sixth transistor, and the first electrode 73 and the second electrode 74 of the seventh transistor located in the same pixel unit are at least partially mirrored.

[0370] 31 to 34 , the reset signal line RL may be in the shape of a line having a main portion extending along the first direction D1. The reset signal line RL is connected to the gate electrode of the first transistor (also the gate electrode of the seventh transistor) through the seventh via hole.

[0371] 31 to 34 , the scan signal line GL may be a line having a main portion extending along the first direction D1. The scan signal line GL is connected to the gate electrode of the second transistor through the eighth via hole and to the gate electrode of the fourth transistor through the tenth via hole.

[0372] In an exemplary embodiment, as shown in Figures 31 to 34, the first electrode 13 of the first transistor is provided separately and has a strip shape extending along the first direction D1. The first electrode 13 of the first transistor is connected to the first region of the active pattern of the first transistor through a first via hole and is connected to the first initial signal line through a twelfth via hole.

[0373] In an exemplary embodiment, as shown in Figures 31 to 34, the second electrode 14 of the first transistor and the first electrode 23 of the second transistor are integrally formed and are in the shape of a strip extending along the second direction D2. The second electrode 14 of the first transistor (also the first electrode 23 of the second transistor) is connected to the second region of the active pattern of the first transistor (also the first region of the active pattern of the second transistor) through a second via, and is connected to the gate electrode of the third transistor (also the first plate of the capacitor) through a ninth via.

[0374] 31 to 34 , the first electrode 43 of the fourth transistor is separately provided and has a strip shape extending along the second direction D2 . The first electrode 43 of the fourth transistor is connected to the first region of the active pattern of the fourth transistor through a third via hole.

[0375] In an exemplary embodiment, as shown in Figures 31 to 34 , the first electrode 53 of the fifth transistor includes a first electrode connection portion 53A, a second electrode connection portion 53B, a third electrode connection portion 53C, and a fourth electrode connection portion 53D. The second electrode connection portion 53B is located on the side of the first electrode connection portion 53A closer to the scan signal line GL, while the third and fourth electrode connection portions 53C and 53D are located on the side of the first electrode connection portion 53A farther from the scan signal line GL. The second and fourth electrode connection portions 53C and 53D are located on opposite sides of the second electrode 14 of the first transistor (also the first electrode 23 of the second transistor). The first electrode connection portion 53A is electrically connected to the second, third, and fourth electrode connection portions 53B, 53C, and 53D, respectively. The first electrode connection portion 53A extends at least partially along the first direction D1, while the second, third, and fourth electrode connection portions 53B, 53C, and 53D extend at least partially along the second direction D2. The second electrode connection portion 53B of the first electrode 53 of the fifth transistor is connected to the first region of the active pattern of the fifth transistor via a fourth via. Furthermore, the first electrode connecting portion 53A of the first electrode 53 of the fifth transistor is connected to the second electrode plate of the capacitor through the eleventh via hole.

[0376] In an exemplary embodiment, the first electrode connection portions 53A of the first electrodes 53 of the fifth transistors of adjacent sub-pixels located in the same row are connected.

[0377] In an exemplary embodiment, as shown in Figures 31 to 34, the second electrode 64 of the sixth transistor and the second electrode 74 of the seventh transistor are integrally structured and are in the shape of a strip extending at least partially along the first direction D1. The second electrode 64 of the sixth transistor (also the second electrode 74 of the seventh transistor) is connected to the second region of the active pattern of the sixth transistor (also the second region of the active pattern of the seventh transistor) through a fifth via.

[0378] In an exemplary embodiment, as shown in Figures 31 to 34, the first electrode 73 of the seventh transistor is provided separately and has a strip shape extending along the first direction D1. The first electrode 73 of the seventh transistor is connected to the first region of the first region of the active pattern of the seventh transistor through a sixth via hole, and is connected to the second initial signal line through a thirteenth via hole.

[0379] In an exemplary embodiment, as shown in Figures 31 to 34, the reset signal line RL and the scan signal line GL can be designed with equal width, or can be designed with unequal width, can be straight lines, or can be broken lines, which not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the signal lines. The present disclosure does not limit this.

[0380] In an exemplary embodiment, as shown in Figures 35 and 36, in the display substrate provided in Figure 9, the third conductive layer pattern includes at least: an even-numbered scanning signal line GL(2i), a second sub-scanning signal line GL2(2i-1) of the odd-numbered scanning signal line, an odd-numbered reset signal line RL(2i-1), a second sub-reset signal line RL2(2i) of the even-numbered reset signal line, a power connection line VL, and a first electrode 13 and a second electrode 14 of a first transistor located in at least one sub-pixel, a first electrode 23 of a second transistor, a first electrode 43 of a fourth transistor, a first electrode 53 of a fifth transistor, a second electrode 64 of a sixth transistor, a first electrode 73 and a second electrode 74 of a seventh transistor, and a first connection electrode CL41.

[0381] In an exemplary embodiment, as shown in Figures 35 and 36, in the display substrate provided in Figure 9, the structures of the first electrode 13 and the second electrode 14 of the first transistor, the first electrode 23 of the second transistor, the first electrode 43 of the fourth transistor, the first electrode 53 of the fifth transistor, the second electrode 64 of the sixth transistor, and the first electrode 73 and the second electrode 74 of the seventh transistor in adjacent sub-pixels located in the same pixel unit are at least partially arranged symmetrically along a virtual straight line extending relative to the second direction D2.

[0382] In an exemplary embodiment, as shown in Figures 35 and 36, the shape of the even-numbered scan signal line GL(2i) may be a line shape whose main portion extends along the first direction D1. The even-numbered scan signal line GL(2i) is connected to the gate electrode of the second transistor through the eleventh via hole.

[0383] In an exemplary embodiment, as shown in Figures 35 and 36, the second sub-scanning signal line GL2(2i-1) of the odd-numbered scan signal lines may have a line shape in which a main portion extends along the first direction D1. The second sub-scanning signal line GL2(2i-1) of the odd-numbered scan signal lines is connected to the first sub-scanning signal line of the odd-numbered scan signal lines through the thirteenth via hole.

[0384] In an exemplary embodiment, as shown in Figures 35 and 36, the shape of the odd-numbered reset signal line RL(2i-1) may be a line shape whose main portion extends along the first direction D1. The odd-numbered reset signal line RL(2i-1) is connected to the gate electrode of the first transistor through the tenth via hole.

[0385] In an exemplary embodiment, as shown in Figures 35 and 36, the second sub-reset signal line RL2(2i) of the even-numbered reset signal lines may have a line shape in which a main portion extends along the first direction D1. The second sub-reset signal line RL2(2i) of the even-numbered reset signal lines is connected to the first sub-reset signal line of the even-numbered reset signal lines through the fourteenth via hole.

[0386] 35 and 36 , the power connection line VL may be in the shape of a line with a main portion extending along the first direction D1 . The power connection line VL is connected to the second plate of the capacitor through the fifteenth via hole.

[0387] 35 and 36 , the first connection electrode CL41 is provided separately and is in the shape of a strip extending along the second direction D2 . The first connection electrode CL41 is connected to the gate electrode of the third transistor (also the first plate of the capacitor) through the twelfth via hole.

[0388] In an exemplary embodiment, as shown in Figures 35 and 36, the first electrode 13 of the first transistor is provided separately and has a strip shape extending along the first direction D1. The first electrode 13 of the first transistor is connected to the first region of the active pattern of the first transistor through a first via hole and is connected to the first initial signal line through a sixteenth via hole.

[0389] In an exemplary embodiment, as shown in Figures 35 and 36, the second electrode 14 of the first transistor and the first electrode 23 of the second transistor are an integral structure and are block-shaped. The second electrode 14 of the first transistor (also the first electrode 23 of the second transistor) is connected to the second region of the active pattern of the first transistor (also the first region of the active pattern of the second transistor) through a second via.

[0390] In an exemplary embodiment, as shown in Figures 35 and 36, the second electrode 24 of the second transistor, the second electrode 34 of the third transistor, and the first electrode 63 of the sixth transistor are integrally formed and have a block shape. The second electrode 24 of the second transistor (also the second electrode 34 of the third transistor and the first electrode 63 of the sixth transistor) is connected to the second region of the active pattern of the second transistor (also the second region of the active pattern of the third transistor and the first region of the active pattern of the sixth transistor) through a third via.

[0391] In an exemplary embodiment, as shown in Figures 35 and 36, the first electrode 33 of the third transistor and the second electrode 44 of the fourth transistor are integrally formed and block-shaped. The first electrode 33 of the third transistor (also the second electrode 44 of the fourth transistor) is connected to the first region of the active pattern of the third transistor (also the second region of the active pattern of the fourth transistor) through a fourth via H4.

[0392] 35 and 36 , the first electrode 43 of the fourth transistor is separately provided and has a strip shape extending along the second direction D2 . The first electrode 43 of the fourth transistor is connected to the first region of the active pattern of the fourth transistor through a fifth via hole.

[0393] 35 and 36 , the first electrode 53 of the fifth transistor is separately provided and has a strip shape extending along the first direction D1 . The first electrode 53 of the fifth transistor is connected to the first region of the active pattern of the fifth transistor through a sixth via hole.

[0394] 35 and 36 , the second electrode 54 of the fifth transistor is provided separately and has a block shape. The second electrode 54 of the fifth transistor is connected to the second region of the active pattern of the fifth transistor through a seventh via hole.

[0395] In an exemplary embodiment, as shown in Figures 35 and 36, the second electrode 64 of the sixth transistor and the second electrode 74 of the seventh transistor are integrally formed and are in the shape of a strip extending at least partially along the first direction D1. The second electrode 64 of the sixth transistor (also the second electrode 74 of the seventh transistor) is connected to the second region of the active pattern of the sixth transistor (also the second region of the active pattern of the seventh transistor) through an eighth via.

[0396] In an exemplary embodiment, as shown in Figures 35 and 36, the first electrode 73 of the seventh transistor is separately provided and has a strip shape extending along the first direction D1. The first electrode 73 of the seventh transistor is connected to the first region of the first region of the active pattern of the seventh transistor through a ninth via hole and is connected to the second initial signal line through a seventeenth via hole.

[0397] In an exemplary embodiment, as shown in Figures 35 and 36, the even-numbered scanning signal lines GL(2i), the second sub-scanning signal lines GL2(2i-1) of the odd-numbered scanning signal lines, the odd-numbered reset signal lines RL(2i-1), the second sub-reset signal lines RL2(2i) of the even-numbered reset signal lines, and the power connection lines VL can be designed with equal widths, or can be designed with unequal widths, can be straight lines, or can be broken lines, which not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance between the signal lines. The present disclosure does not limit this.

[0398] (6) Forming a first flat layer pattern. In an exemplary embodiment, forming the first flat layer pattern may include: first depositing a fourth insulating film on the substrate on which the aforementioned pattern is formed, then coating the first flat film, patterning the first flat film and the fourth insulating film using a patterning process to form a fourth insulating layer covering the third conductive layer pattern and a first flat layer disposed on the fourth insulating layer, wherein the first flat layer is provided with a plurality of vias, as shown in Figures 37 to 39. Figure 37 is a schematic diagram of the display substrate provided in Figures 3 and 5 after the first flat layer is formed, Figure 38 is a schematic diagram of the display substrate provided in Figure 7 after the first flat layer is formed, and Figure 39 is a schematic diagram of the display substrate provided in Figure 9 after the first flat layer is formed.

[0399] In an exemplary embodiment, as shown in FIG. 37 , in the display substrate provided in FIG. 3 , the plurality of via holes in the first planar layer include at least fourteenth to seventeenth via holes V14 to V17 .

[0400] In an exemplary embodiment, the orthographic projection of the fourteenth via V14 on the substrate is located within the range of the orthographic projection of the first electrode of the fourth transistor on the substrate, the fourth insulating layer in the fourteenth via V14 is etched away to expose the surface of the first electrode of the fourth transistor, and the fourteenth via V14 is configured to connect the subsequently formed data signal line through the via to the first electrode of the fourth transistor.

[0401] In an exemplary embodiment, the orthographic projection of the fifteenth via V15 on the substrate is located within the range of the orthographic projection of the first electrode of the fifth transistor on the substrate, the fourth insulating layer in the fifteenth via V15 is etched away to expose the surface of the first electrode of the fourth transistor, and the fifteenth via V15 is configured to connect the first sub-power line of the subsequently formed first power line to the first electrode of the fifth transistor.

[0402] In an exemplary embodiment, the orthographic projection of the sixteenth via V16 on the substrate is located within the range of the orthographic projection of the second electrode of the sixth transistor (also the second electrode of the seventh transistor) on the substrate, the fourth insulating layer in the sixteenth via V16 is etched away to expose the surface of the second electrode of the sixth transistor (also the second electrode of the seventh transistor), and the sixteenth via V16 is configured to connect a subsequently formed connecting electrode to the second electrode of the sixth transistor (also the second electrode of the seventh transistor).

[0403] In an exemplary embodiment, the orthographic projection of the seventeenth via V17 on the substrate is located within the range of the orthographic projection of the first electrode of the first transistor in the third sub-pixel and the sixth sub-pixel in at least one pixel unit on the substrate, the fourth insulating layer in the seventeenth via V17 is etched away to expose the surface of the first electrode of the first transistor, and the seventeenth via V17 is configured to connect a subsequently formed first initial connection line to the first electrode of the first transistor.

[0404] In an exemplary embodiment, as shown in FIG. 37 , in the display substrate provided in FIG. 5 , the plurality of via holes in the first planar layer include at least fourteenth to seventeenth via holes V14 to V17 .

[0405] In an exemplary embodiment, the orthographic projection of the fourteenth via V14 on the substrate is located within the range of the orthographic projection of the first electrode of the fourth transistor on the substrate, the fourth insulating layer in the fourteenth via V14 is etched away, exposing the surface of the first electrode of the fourth transistor, and the fourteenth via V14 is configured to connect the subsequently formed second connecting electrode through the via to the first electrode of the fourth transistor.

[0406] In an exemplary embodiment, the orthographic projection of the fifteenth via V15 on the substrate is located within the range of the orthographic projection of the first electrode of the fifth transistor on the substrate, the fourth insulating layer in the fifteenth via V15 is etched away to expose the surface of the first electrode of the fourth transistor, and the fifteenth via V15 is configured to connect the first sub-power line of the subsequently formed first power line to the first electrode of the fifth transistor.

[0407] In an exemplary embodiment, the orthographic projection of the sixteenth via V16 on the substrate is located within the range of the orthographic projection of the second electrode of the sixth transistor (also the second electrode of the seventh transistor) on the substrate, the fourth insulating layer in the sixteenth via V16 is etched away to expose the surface of the second electrode of the sixth transistor (also the second electrode of the seventh transistor), and the sixteenth via V16 is configured to connect the subsequently formed first connecting electrode to the second electrode of the sixth transistor (also the second electrode of the seventh transistor).

[0408] In an exemplary embodiment, the orthographic projection of the seventeenth via V17 on the substrate is located within the range of the orthographic projection of the first electrode of the first transistor in the third sub-pixel and the sixth sub-pixel in at least one pixel unit on the substrate, the fourth insulating layer in the seventeenth via V17 is etched away to expose the surface of the first electrode of the first transistor, and the seventeenth via V17 is configured to connect a subsequently formed first initial connection line to the first electrode of the first transistor.

[0409] In an exemplary embodiment, as shown in FIG. 38 , in the display substrate provided in FIG. 7 , the plurality of via holes in the first planar layer include at least fourteenth to sixteenth via holes V14 to V16 .

[0410] In an exemplary embodiment, the orthographic projection of the fourteenth via V14 on the substrate is located within the range of the orthographic projection of the first electrode of the fourth transistor on the substrate, the fourth insulating layer in the fourteenth via V14 is etched away to expose the surface of the first electrode of the fourth transistor, and the fourteenth via V14 is configured to connect the subsequently formed data signal line through the via to the first electrode of the fourth transistor.

[0411] In an exemplary embodiment, the orthographic projection of the fifteenth via V15 on the substrate is located within the range of the orthographic projection of the first electrode of the fifth transistor on the substrate, the fourth insulating layer in the fifteenth via V15 is etched away to expose the surface of the first electrode of the fourth transistor, and the fifteenth via V15 is configured to connect the subsequently formed first power line and the third plate of the capacitor to the first electrode of the fifth transistor.

[0412] In an exemplary embodiment, the orthographic projection of the sixteenth via V16 on the substrate is located within the range of the orthographic projection of the second electrode of the sixth transistor (also the second electrode of the seventh transistor) on the substrate, the fourth insulating layer in the sixteenth via V16 is etched away to expose the surface of the second electrode of the sixth transistor (also the second electrode of the seventh transistor), and the sixteenth via V16 is configured to connect a subsequently formed connecting electrode to the second electrode of the sixth transistor (also the second electrode of the seventh transistor).

[0413] In an exemplary embodiment, as shown in FIG. 39 , in the display substrate provided in FIG. 9 , the plurality of via holes in the first planar layer include at least eighteenth to twenty-fifth via holes H18 to H25 .

[0414] In an exemplary embodiment, the orthographic projection of the eighteenth via H18 on the substrate is located within the range of the orthographic projection of the second electrode of the first transistor (also the first electrode of the second transistor) on the substrate, the fourth insulating layer in the eighteenth via H18 is etched away to expose the surface of the second electrode of the first transistor (also the first electrode of the second transistor), and the eighteenth via H18 is configured to connect the subsequently formed second connecting electrode to the second electrode of the first transistor (also the first electrode of the second transistor).

[0415] In an exemplary embodiment, the orthographic projection of the nineteenth via H19 on the substrate is located within the range of the orthographic projection of the first electrode of the third transistor (also the second electrode of the fourth transistor) on the substrate, the fourth insulating layer in the nineteenth via H19 is etched away to expose the surface of the first electrode of the third transistor (also the second electrode of the fourth transistor), and the nineteenth via H19 is configured to connect the subsequently formed third connecting electrode to the first electrode of the third transistor (also the second electrode of the fourth transistor).

[0416] In an exemplary embodiment, the orthographic projection of the twentieth via H20 on the substrate is located within the range of the orthographic projection of the first electrode of the fourth transistor on the substrate, the fourth insulating layer in the twentieth via H20 is etched away to expose the surface of the first electrode of the fourth transistor, and the twentieth via H20 is configured to connect a subsequently formed data signal line to the first electrode of the fourth transistor.

[0417] In an exemplary embodiment, the orthographic projection of the twenty-first via H21 on the substrate is located within the range of the orthographic projection of the first electrode of the fifth transistor on the substrate, the fourth insulating layer in the twenty-first via H21 is etched away, exposing the surface of the first electrode of the fifth transistor, and the twenty-first via H21 is configured to connect the subsequently formed first power line to the first electrode of the fifth transistor.

[0418] In an exemplary embodiment, the orthographic projection of the twenty-second via H22 on the substrate is located within the range of the orthographic projection of the second electrode of the fifth transistor on the substrate, the fourth insulating layer in the twenty-second via H22 is etched away to expose the surface of the second electrode of the fifth transistor, and the twenty-second via H22 is configured to connect the subsequently formed third connecting electrode to the second electrode of the fifth transistor.

[0419] In an exemplary embodiment, the orthographic projection of the twenty-third via H23 on the substrate is located within the range of the orthographic projection of the second electrode of the sixth transistor (also the second electrode of the seventh transistor) on the substrate, the fourth insulating layer in the twenty-third via H23 is etched away to expose the surface of the second electrode of the sixth transistor (also the second electrode of the seventh transistor), and the twenty-third via H23 is configured to connect the subsequently formed fourth connecting electrode to the second electrode of the sixth transistor (also the second electrode of the seventh transistor).

[0420] In an exemplary embodiment, the orthographic projection of the twenty-fourth via H24 on the substrate is located within the range of the orthographic projection of the first connecting electrode on the substrate, the fourth insulating layer in the twenty-fourth via H24 is etched away to expose the surface of the first connecting electrode, and the twenty-fourth via H24 is configured to connect the subsequently formed second connecting electrode to the first connecting electrode.

[0421] In an exemplary embodiment, the orthographic projection of the twenty-fifth via H25 on the substrate is located within the range of the orthographic projection of the power connection line on the substrate, the fourth insulating layer in the twenty-fifth via H25 is etched away to expose the surface of the power connection line, and the twenty-fifth via H25 is configured to connect the subsequently formed first power line to the power connection line.

[0422] (7) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer pattern may include: depositing a fourth conductive film on the substrate on which the aforementioned pattern is formed, patterning the fourth conductive film using a patterning process, and forming a fourth conductive layer pattern disposed on the first flat layer, as shown in Figures 40 to 47, Figure 40 is a schematic diagram of the fourth conductive layer pattern in the display substrate provided in Figure 3, Figure 41 is a schematic diagram of the display substrate provided in Figure 3 after the fourth conductive layer pattern is formed, Figure 42 is a schematic diagram of the fourth conductive layer pattern in the display substrate provided in Figure 5, Figure 43 is a schematic diagram of the display substrate provided in Figure 5 after the fourth conductive layer pattern is formed, Figure 44 is a schematic diagram of the fourth conductive layer pattern in the display substrate provided in Figure 7, Figure 45 is a schematic diagram of the display substrate provided in Figure 7 after the fourth conductive layer pattern is formed, Figure 46 is a schematic diagram of the fourth conductive layer pattern in the display substrate provided in Figure 9, and Figure 47 is a schematic diagram of the display substrate provided in Figure 9 after the fourth conductive layer pattern is formed. In an exemplary embodiment, the fourth conductive layer may be referred to as a second source / drain metal (SD2) layer.

[0423] In an exemplary embodiment, as shown in Figures 40 and 41, in the display substrate provided in Figure 3, the fourth conductive layer pattern includes at least: a first sub-power line VDL1 of the first power line, a data signal line DL, a first initial connection line NL, and a connection electrode CL located at at least one sub-pixel.

[0424] In an exemplary embodiment, as shown in FIG. 40 and FIG. 41 , the structures of the connection electrodes CL of all sub-pixels located in the same pixel unit are at least partially the same.

[0425] In an exemplary embodiment, as shown in FIG. 40 and FIG. 41 , the line width of the first sub power line VDL1 of the first power line is greater than the line width of the data signal line DL.

[0426] 40 and 41 , the first sub power line VDL1 of the first power line may be in a line shape with a main portion extending along the second direction D2. The first sub power line VDL1 of the first power line is connected to the first electrode of the fifth transistor through the fifteenth via hole.

[0427] 40 and 41 , the data signal line DL may be in the shape of a line having a main portion extending along the second direction D2 . The data signal line DL is connected to the first electrode of the fourth transistor through the fourteenth via hole.

[0428] 40 and 41 , the first preliminary connection line NL may be a line having a main portion extending along the second direction D2 . The first preliminary connection line NL is connected to the first electrode of the first transistor through the seventeenth via hole.

[0429] 40 and 41 , the connection electrode CL is in the shape of a bar extending along the second direction D2 . The connection electrode CL is connected to the second electrode of the sixth transistor (also the second electrode of the seventh transistor) through the sixteenth via hole.

[0430] In an exemplary embodiment, as shown in Figures 42 and 43, in the display substrate provided in Figure 5, the fourth conductive layer pattern includes at least: a first sub-power line VDL1 of the first power line, a first initial connection line NL, and a first connection electrode CL21 and a second connection electrode CL22 located at at least one sub-pixel.

[0431] In an exemplary embodiment, as shown in FIG. 42 and FIG. 43 , the structures of the first link electrode CL21 and the second link electrode CL22 of all sub-pixels located in the same pixel unit are at least partially identical.

[0432] In an exemplary embodiment, as shown in FIG. 42 and FIG. 43 , the line width of the first sub power line VDL1 of the first power line is greater than the line width of the data signal line DL.

[0433] 42 and 43 , the first sub power line VDL1 of the first power line may be in a line shape with a main portion extending along the second direction D2 . The first sub power line VDL1 of the first power line is connected to the first electrode of the fifth transistor through the fifteenth via hole.

[0434] 42 and 43 , the first preliminary connection line NL may be a line having a main portion extending along the second direction D2 . The first preliminary connection line NL is connected to the first electrode of the first transistor through the seventeenth via hole.

[0435] 42 and 43 , the first connection electrode CL1 is in a strip shape extending along the second direction D2 . The first connection electrode CL1 is connected to the second electrode of the sixth transistor (also the second electrode of the seventh transistor) through the sixteenth via hole.

[0436] 42 and 43 , the second connection electrode CL2 is in the shape of a bar extending along the second direction D2 . The second connection electrode CL2 is connected to the first electrode of the fourth transistor through the fourteenth via hole.

[0437] In an exemplary embodiment, as shown in FIG. 44 and FIG. 45 , in the display substrate provided in FIG. 7 , the fourth conductive layer pattern includes at least: a first power line VDL, a data signal line DL, and a third plate C3 and a connection electrode CL of a capacitor located in at least one sub-pixel.

[0438] In an exemplary embodiment, as shown in Figures 44 and 45, the structures of the third plates C3 and the connecting electrode CL of the capacitors of all sub-pixels in the same row in the same pixel unit are at least partially identical, and the structures of the third plates C3 and the connecting electrode CL of the capacitors of sub-pixels in different rows in the same pixel unit are at least partially mirrored.

[0439] 44 and 45 , the first power line VDL may be in a line shape with a main portion extending along the second direction D2 . The first power line VDL is connected to the first electrode of the fifth transistor through the fifteenth via hole.

[0440] 44 and 45 , the data signal line DL may be in the shape of a line having a main portion extending along the second direction D2 . The data signal line DL is connected to the first electrode of the fourth transistor through the fourteenth via hole.

[0441] In an exemplary embodiment, as shown in Figures 44 and 45, the outline of the third plate C3 of the capacitor can be rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the third plate C3 of the capacitor on the substrate at least partially overlaps with the orthographic projection of the first plate on the substrate, and at least partially overlaps with the orthographic projection of the second electrode of the first transistor (which is also the first electrode of the second transistor) on the substrate. The third plate C3 of the capacitor is connected to the first electrode of the fifth transistor through a fifteenth via.

[0442] 44 and 45 , the connection electrode CL is in the shape of a bar extending in the first direction D1 and is connected to the second electrode of the sixth transistor (also the second electrode of the seventh transistor) through the sixteenth via hole.

[0443] In an exemplary embodiment, as shown in Figures 46 and 47, in the display substrate provided in Figure 9, the fourth conductive layer pattern includes at least: a first power line VDL, a data signal line DL, and a second connection electrode CL2, a third connection electrode CL3 and a fourth connection electrode CL4 located at at least one sub-pixel.

[0444] In an exemplary embodiment, as shown in Figures 46 and 47, the structures of the second connection electrode CL2, the third connection electrode CL3 and the fourth connection electrode CL4 in adjacent sub-pixels located in the same pixel unit are at least partially symmetrically arranged with respect to a virtual straight line extending along the second direction D2.

[0445] In an exemplary embodiment, as shown in Figures 46 and 47, the first power line VDL may be in the shape of a line with a main portion extending along the second direction D2. The first power line VDL is connected to the first electrode of the fifth transistor through the twenty-first via hole and to the power connection line through the twenty-fifth via hole.

[0446] 46 and 47 , the data signal line DL may be in the shape of a line having a main portion extending along the second direction D2 . The data signal line DL is connected to the first electrode of the fourth transistor through the twentieth via hole.

[0447] In an exemplary embodiment, as shown in Figures 46 and 47, the second connection electrode CL42 may be in the shape of a strip extending along the second direction D2. The second connection electrode CL42 is connected to the second electrode of the first transistor (also the first electrode of the second transistor) through the eighteenth via hole and is connected to the first connection electrode through the twenty-fourth via hole.

[0448] In an exemplary embodiment, as shown in Figures 46 and 47, the third connection electrode CL43 may be in the shape of a strip extending along the second direction D2. The third connection electrode CL43 is connected to the first electrode of the third transistor (also the second electrode of the fourth transistor) through the nineteenth via hole, and is connected to the second electrode of the fifth transistor through the twenty-second via hole.

[0449] 46 and 47 , the fourth connection electrode CL44 may be in the shape of a bar extending along the second direction D2 . The fourth connection electrode CL44 is connected to the second electrode of the sixth transistor (also the second electrode of the seventh transistor) through the twenty-third via hole.

[0450] In an exemplary embodiment, as shown in Figures 44 to 47, in the display substrate provided in Figures 7 and 9, the first power line VDL and the data signal line DL can be designed with equal width, or can be designed with unequal width, can be a straight line, or can be a broken line, which not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the signal lines, which is not limited in the present disclosure.

[0451] (8) Forming a second flat layer pattern. In an exemplary embodiment, forming the second flat layer pattern may include: coating a second flat film on the substrate on which the aforementioned pattern is formed, patterning the second flat film using a patterning process to form a second flat layer covering the fourth conductive layer pattern, wherein a plurality of vias are provided on the second flat layer, as shown in Figures 48 to 51 , Figure 48 is a schematic diagram of the display substrate provided in Figure 3 after the second flat layer is formed, Figure 49 is a schematic diagram of the display substrate provided in Figure 5 after the second flat layer is formed, Figure 50 is a schematic diagram of the display substrate provided in Figure 7 after the second flat layer is formed, and Figure 51 is a schematic diagram of the display substrate provided in Figure 9 after the second flat layer is formed.

[0452] In an exemplary embodiment, as shown in FIG. 48 , in the display substrate provided in FIG. 3 , the plurality of via holes of the second planar layer include an eighteenth via hole V18 and a nineteenth via hole V19 .

[0453] In an exemplary embodiment, the orthographic projection of the eighteenth via hole V18 on the substrate is within the range of the orthographic projection of the connecting electrode on the substrate, the eighteenth via hole V18 exposes the surface of the connecting electrode, and the eighteenth via hole V18 is configured to connect a subsequently formed anode connecting line to the connecting electrode.

[0454] In an exemplary embodiment, the orthographic projection of the nineteenth via V19 on the substrate is located within the range of the orthographic projection of the first sub-power line of the first power line on the substrate, the nineteenth via V19 exposes the surface of the connecting electrode, and the nineteenth via V19 is configured to connect the subsequently formed second sub-power line of the first power line with the first sub-power line of the first power line.

[0455] In an exemplary embodiment, as shown in FIG. 49 , in the display substrate provided in FIG. 5 , the plurality of via holes of the second planar layer include: an eighteenth via hole V18 to a twentieth via hole V20 .

[0456] In an exemplary embodiment, the orthographic projection of the eighteenth via hole V18 on the substrate is located within the range of the orthographic projection of the first connection electrode on the substrate, the eighteenth via hole V18 exposes the surface of the first connection electrode, and the eighteenth via hole V18 is configured to connect the subsequently formed anode connection line to the first connection electrode.

[0457] In an exemplary embodiment, the orthographic projection of the nineteenth via V19 on the substrate is located within the range of the orthographic projection of the first sub-power line of the first power line on the substrate, the nineteenth via V19 exposes the surface of the connecting electrode, and the nineteenth via V19 is configured to connect the subsequently formed second sub-power line of the first power line with the first sub-power line of the first power line.

[0458] In an exemplary embodiment, the orthographic projection of the twentieth via hole V20 on the substrate is located within the range of the orthographic projection of the second connection electrode on the substrate, the twentieth via hole V20 exposes the surface of the second connection electrode, and the twentieth via hole V20 is configured to connect a subsequently formed data signal line to the second connection electrode.

[0459] In an exemplary embodiment, as shown in FIG. 50 , in the display substrate provided in FIG. 7 , the plurality of via holes in the second planar layer include an eighteenth via hole V18 .

[0460] In an exemplary embodiment, the orthographic projection of the eighteenth via hole V18 on the substrate is within the range of the orthographic projection of the connecting electrode on the substrate, the eighteenth via hole V18 exposes the surface of the connecting electrode, and the eighteenth via hole V18 is configured to connect a subsequently formed anode connecting line to the connecting electrode.

[0461] In an exemplary embodiment, as shown in FIG. 51 , in the display substrate provided in FIG. 9 , the plurality of via holes of the second planar layer include a twenty-sixth via hole H26 .

[0462] In an exemplary embodiment, the orthographic projection of the twenty-sixth via H26 on the substrate is located within the range of the orthographic projection of the fourth connection electrode on the substrate, the twenty-sixth via H26 exposes the surface of the fourth connection electrode, and the twenty-sixth via H26 is configured to connect the subsequently formed anode connection line to the fourth connection electrode.

[0463] (9) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming the fifth conductive layer pattern may include: depositing a fifth conductive film on the substrate on which the aforementioned pattern is formed, patterning the fifth conductive film using a patterning process, and forming a fifth conductive layer pattern disposed on the first flat layer, as shown in Figures 52 to 59, Figure 52 is a schematic diagram of the fifth conductive layer pattern in the display substrate provided in Figure 3, Figure 53 is a schematic diagram of the display substrate provided in Figure 3 after the fifth conductive layer pattern is formed, Figure 54 is a schematic diagram of the fifth conductive layer pattern in the display substrate provided in Figure 5, Figure 55 is a schematic diagram of the display substrate provided in Figure 5 after the fifth conductive layer pattern is formed, Figure 56 is a schematic diagram of the fifth conductive layer pattern in the display substrate provided in Figure 7, Figure 57 is a schematic diagram of the display substrate provided in Figure 7 after the fifth conductive layer pattern is formed, Figure 58 is a schematic diagram of the fifth conductive layer pattern in the display substrate provided in Figure 9, and Figure 59 is a schematic diagram of the display substrate provided in Figure 9 after the fifth conductive layer pattern is formed. In an exemplary embodiment, the fifth conductive layer may be referred to as a third source / drain metal (SD3) layer.

[0464] In an exemplary embodiment, as shown in FIG. 52 and FIG. 53 , in the display substrate provided in FIG. 3 , the fifth conductive layer pattern includes at least a second sub power line VDL2 of the first power line and first to sixth anode connection lines AL1 to AL6 .

[0465] 52 and 53, the second sub power line VDL2 of the first power line may be in the shape of a line having a main portion extending along the second direction D2. The second sub power line VDL2 of the first power line is connected to the first sub power line of the first power line through the nineteenth via hole.

[0466] 52 and 53 , the first anode connection line AL1 is a line extending at least partially along the second direction D2 . The first anode connection line AL1 is connected to the connection electrode of the first sub-pixel through the eighteenth via hole of the first sub-pixel.

[0467] 52 and 53 , the second anode connection line AL2 is a line extending at least partially along the second direction D2 and is connected to the connection electrode of the second sub-pixel through the eighteenth via hole of the second sub-pixel.

[0468] 52 and 53 , the third anode connection line AL3 is a line extending at least partially along the first direction D1 and is connected to the connection electrode of the third sub-pixel through the eighteenth via hole of the third sub-pixel.

[0469] 52 and 53 , the fourth anode connection line AL4 is a line extending at least partially along the first direction D1 and is connected to the connection electrode of the fourth sub-pixel through the eighteenth via hole of the fourth sub-pixel.

[0470] 52 and 53 , the fifth anode connection line AL5 is a line extending at least partially along the second direction D2 and is connected to the connection electrode of the fifth sub-pixel through the eighteenth via hole of the fifth sub-pixel.

[0471] 52 and 53 , the sixth anode connection line AL6 is a line extending at least partially along the second direction D2 and is connected to the connection electrode of the sixth sub-pixel through the eighteenth via hole of the sixth sub-pixel.

[0472] In an exemplary embodiment, as shown in FIG54 and FIG55, in the display substrate provided in FIG5, the fifth conductive layer pattern includes at least: a second sub-power line VDL2 of the first power line, a data signal line DL, a first anode connection line AL1 to a sixth anode connection line AL6

[0473] 54 and 55 , the second sub power line VDL2 of the first power line may be in the shape of a line having a main portion extending along the second direction D2. The second sub power line VDL2 of the first power line is connected to the first sub power line of the first power line through the nineteenth via hole.

[0474] In an exemplary embodiment, as shown in FIG. 54 and FIG. 55 , the line width of the second sub power line VDL2 of the first power line is greater than the line width of the data signal line DL.

[0475] 54 and 55 , the data signal line DL may have a line shape in which a main portion extends along the second direction D2. The data signal line DL is connected to the second connection electrode through the twentieth via hole.

[0476] 54 and 55 , the first anode connection line AL1 is a line extending at least partially along the second direction D2 . The first anode connection line AL1 is connected to the connection electrode of the first sub-pixel through the eighteenth via hole of the first sub-pixel.

[0477] 54 and 55 , the second anode connection line AL2 is a line extending at least partially along the second direction D2 and is connected to the connection electrode of the second sub-pixel through the eighteenth via hole of the second sub-pixel.

[0478] 54 and 55 , the third anode connection line AL3 is a line extending at least partially along the second direction D2 and is connected to the connection electrode of the third sub-pixel through the eighteenth via hole of the third sub-pixel.

[0479] 54 and 55 , the fourth anode connection line AL4 is a line extending at least partially along the second direction D2 and is connected to the connection electrode of the fourth subpixel through the eighteenth via hole of the fourth subpixel.

[0480] 54 and 55 , the fifth anode connection line AL5 is a line extending at least partially along the second direction D2 and is connected to the connection electrode of the fifth sub-pixel through the eighteenth via hole of the fifth sub-pixel.

[0481] 54 and 55 , the sixth anode connection line AL6 is a line extending at least partially along the second direction D2 and is connected to the connection electrode of the sixth sub-pixel through the eighteenth via hole of the sixth sub-pixel.

[0482] In an exemplary embodiment, as shown in FIG. 56 and FIG. 57 , in the display substrate provided in FIG. 7 , the fifth conductive layer pattern includes at least: first anode connection line AL1 to sixth anode connection line AL6

[0483] 56 and 57 , the first anode connection line AL1 is a line extending at least partially along the second direction D2 . The first anode connection line AL1 is connected to the connection electrode of the first sub-pixel through the eighteenth via hole of the first sub-pixel.

[0484] 56 and 57 , the second anode connection line AL2 is a line extending at least partially along the second direction D2 and is connected to the connection electrode of the second sub-pixel through the eighteenth via hole of the second sub-pixel.

[0485] 56 and 57 , the third anode connection line AL3 is a line extending at least partially along the first direction D1 and is connected to the connection electrode of the third sub-pixel through the eighteenth via hole of the third sub-pixel.

[0486] 56 and 57 , the fourth anode connection line AL4 is a line extending at least partially along the first direction D1 and is connected to the connection electrode of the fourth subpixel through the eighteenth via hole of the fourth subpixel.

[0487] 56 and 57 , the fifth anode connection line AL5 is a line extending at least partially along the second direction D2 and is connected to the connection electrode of the fifth subpixel through the eighteenth via hole of the fifth subpixel.

[0488] 56 and 57 , the sixth anode connection line AL6 is a line extending at least partially along the first direction D1 and is connected to the connection electrode of the sixth sub-pixel through the eighteenth via hole of the sixth sub-pixel.

[0489] In an exemplary embodiment, as shown in FIG. 58 and FIG. 59 , in the display substrate provided in FIG. 9 , the fifth conductive layer pattern includes at least: first anode connection line AL1 to sixth anode connection line AL6

[0490] 58 and 59 , the first anode connection line AL1 is a line extending at least partially along the second direction D2 . The first anode connection line AL1 is connected to the connection electrode of the first sub-pixel through the twenty-sixth via hole of the first sub-pixel.

[0491] 58 and 59 , the second anode connection line AL2 is a line extending at least partially along the second direction D2 and is connected to the connection electrode of the second sub-pixel through the twenty-sixth via hole of the second sub-pixel.

[0492] 58 and 59 , the third anode connection line AL3 is a line extending at least partially along the first direction D1 and is connected to the connection electrode of the third sub-pixel through the twenty-sixth via hole of the third sub-pixel.

[0493] 58 and 59 , the fourth anode connection line AL4 is a line extending at least partially along the second direction D2 and is connected to the connection electrode of the fourth sub-pixel through the twenty-sixth via hole of the fourth sub-pixel.

[0494] 58 and 59 , the fifth anode connection line AL5 is a line extending at least partially along the second direction D2 and is connected to the connection electrode of the fifth sub-pixel through the twenty-sixth via hole of the fifth sub-pixel.

[0495] 58 and 59 , the sixth anode connection line AL6 is a line extending at least partially along the second direction D2 and is connected to the connection electrode of the sixth sub-pixel through the twenty-sixth via hole of the sixth sub-pixel.

[0496] (10) Forming a third flat layer pattern. In an exemplary embodiment, forming the third flat layer pattern may include: coating a third flat film on the substrate on which the aforementioned pattern is formed, patterning the third flat film using a patterning process to form a third flat layer covering the fifth conductive layer pattern, wherein a plurality of vias are provided on the third flat layer, as shown in Figures 60 to 62. Figure 60 is a schematic diagram of the display substrate provided in Figure 3 after the third flat layer is formed, Figure 61 is a schematic diagram of the display substrate provided in Figure 5 after the third flat layer is formed, Figure 62 is a schematic diagram of the display substrate provided in Figure 7 after the third flat layer is formed, and Figure 63 is a schematic diagram of the display substrate provided in Figure 9 after the third flat layer is formed.

[0497] In an exemplary embodiment, as shown in FIG. 60 to FIG. 62 , in the display substrate provided in FIG. 3 , FIG. 5 and FIG. 7 , the plurality of via holes in the third planar layer include: a twenty-first via hole V21 to a twenty-sixth via hole V26 .

[0498] In an exemplary embodiment, the orthographic projection of the twenty-first via hole V21 on the substrate is located within the range of the orthographic projection of the first anode connecting line on the substrate, the twenty-first via hole V21 exposes the surface of the first anode connecting line, and the twenty-first via hole V21 is configured to connect the first electrode of the subsequently formed first sub-pixel to the first anode connecting line.

[0499] In an exemplary embodiment, the orthographic projection of the twenty-second via hole V22 on the substrate is located within the range of the orthographic projection of the second anode connecting line on the substrate, the twenty-second via hole V22 exposes the surface of the second anode connecting line, and the twenty-second via hole V22 is configured to connect the first electrode of the subsequently formed second sub-pixel to the second anode connecting line.

[0500] In an exemplary embodiment, the orthographic projection of the twenty-third via hole V23 on the substrate is located within the range of the orthographic projection of the third anode connecting line on the substrate, the twenty-third via hole V23 exposes the surface of the third anode connecting line, and the twenty-third via hole V23 is configured to connect the first electrode of the subsequently formed third sub-pixel to the third anode connecting line.

[0501] In an exemplary embodiment, the orthographic projection of the twenty-fourth via hole V24 on the substrate is located within the range of the orthographic projection of the fourth anode connecting line on the substrate, the twenty-fourth via hole V24 exposes the surface of the fourth anode connecting line, and the twenty-fourth via hole V24 is configured to connect the first electrode of the subsequently formed fourth sub-pixel to the fourth anode connecting line.

[0502] In an exemplary embodiment, the orthographic projection of the twenty-fifth via hole V25 on the substrate is located within the range of the orthographic projection of the fifth anode connecting line on the substrate, the twenty-fifth via hole V25 exposes the surface of the fifth anode connecting line, and the twenty-fifth via hole V25 is configured to connect the first electrode of the subsequently formed fifth sub-pixel to the fifth anode connecting line.

[0503] In an exemplary embodiment, the orthographic projection of the twenty-sixth via hole V26 on the substrate is located within the range of the orthographic projection of the sixth anode connecting line on the substrate, the twenty-sixth via hole V26 exposes the surface of the sixth anode connecting line, and the twenty-sixth via hole V26 is configured to connect the first electrode of the subsequently formed sixth sub-pixel to the sixth anode connecting line.

[0504] In an exemplary embodiment, as shown in FIG. 63 , in the display substrate provided in FIG. 9 , the plurality of via holes in the third planar layer include: a twenty-seventh via hole H27 to a thirty-second via hole H32 .

[0505] In an exemplary embodiment, the orthographic projection of the twenty-seventh via hole H27 on the substrate is located within the range of the orthographic projection of the first anode connecting line on the substrate, the twenty-seventh via hole H27 exposes the surface of the first anode connecting line, and the twenty-seventh via hole H27 is configured to connect the first electrode of the subsequently formed first sub-pixel to the first anode connecting line.

[0506] In an exemplary embodiment, the orthographic projection of the twenty-eighth via hole H28 on the substrate is located within the range of the orthographic projection of the second anode connecting line on the substrate, and the twenty-eighth via hole H28 exposes the surface of the second anode connecting line. The twenty-eighth via hole H28 is configured to connect the first electrode of the subsequently formed second sub-pixel to the second anode connecting line.

[0507] In an exemplary embodiment, the orthographic projection of the twenty-ninth via hole H29 on the substrate is located within the range of the orthographic projection of the third anode connecting line on the substrate, the twenty-ninth via hole H29 exposes the surface of the third anode connecting line, and the twenty-ninth via hole H29 is configured to connect the first electrode of the subsequently formed third sub-pixel to the third anode connecting line.

[0508] In an exemplary embodiment, the orthographic projection of the 30th via hole H30 on the substrate is located within the range of the orthographic projection of the fourth anode connecting line on the substrate, the 30th via hole H30 exposes the surface of the fourth anode connecting line, and the 30th via hole H30 is configured to connect the first electrode of the subsequently formed fourth sub-pixel to the fourth anode connecting line.

[0509] In an exemplary embodiment, the orthographic projection of the thirty-first via hole H31 on the substrate is located within the range of the orthographic projection of the fifth anode connecting line on the substrate, the thirty-first via hole H31 exposes the surface of the fifth anode connecting line, and the thirty-first via hole H31 is configured to connect the first electrode of the subsequently formed fifth sub-pixel to the fifth anode connecting line.

[0510] In an exemplary embodiment, the orthographic projection of the thirty-second via hole H32 on the substrate is located within the range of the orthographic projection of the sixth anode connecting line on the substrate, the thirty-second via hole H32 exposes the surface of the sixth anode connecting line, and the thirty-second via hole H32 is configured to connect the first electrode of the subsequently formed sixth sub-pixel to the sixth anode connecting line.

[0511] At this point, the drive circuit layer is completed on the substrate. In a plane parallel to the display substrate, the drive circuit layer can include multiple circuit units, each of which can include a pixel drive circuit. The pixel drive circuit is connected to a scan signal line, a reset signal line, a light signal line, a first initial signal line, a second initial signal line, a data signal line, and a first power supply line. In a plane perpendicular to the display substrate, the drive circuit layer can be disposed on the substrate.

[0512] The driving circuit layer may include a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a first planar layer, a fourth conductive layer, a second planar layer, a fifth conductive layer, and a third planar layer, sequentially disposed on a substrate. The semiconductor layer may include at least active patterns for the first through seventh transistors, the first conductive layer may include at least gate electrodes for the first through seventh transistors and a first plate of a capacitor, the second conductive layer may include at least a second plate of the capacitor, the third conductive layer may include at least first and second electrodes for a plurality of transistors, and the fifth conductive layer may include at least one anode connection electrode.

[0513] In an exemplary embodiment, the semiconductor layer can be made of various materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene, polythiophene, etc., that is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology and organic technology.

[0514] In an exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer and the fifth conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, etc.

[0515] In exemplary embodiments, the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer may be formed of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer. The first insulating layer and the second insulating layer may be referred to as a gate insulating (GI) layer, the third insulating layer and the fourth insulating layer may be referred to as an interlayer insulating (ILD) layer, and the fifth insulating layer may be referred to as a passivation (PVX) layer.

[0516] In an exemplary embodiment, the first planarization layer, the second planarization layer, and the third planarization layer may employ an organic material such as resin or the like.

[0517] In an exemplary embodiment, after the driving circuit layer is prepared, a light emitting structure layer is prepared on the driving circuit layer. The preparation process of the light emitting structure layer may include the following operations.

[0518] (11) Forming a sixth conductive layer pattern. In an exemplary embodiment, forming the sixth conductive layer pattern may include: depositing a sixth conductive film on the substrate on which the aforementioned pattern is formed, patterning the sixth conductive film using a patterning process, and forming a sixth conductive layer disposed on the third flat layer, as shown in Figures 64 to 70, Figure 64 is a schematic diagram of the sixth conductive layer pattern in the display substrate provided in Figures 3 and 5, Figure 65 is a schematic diagram of the display substrate provided in Figure 3 after the sixth conductive layer pattern is formed, Figure 66 is a schematic diagram of the display substrate provided in Figure 5 after the sixth conductive layer pattern is formed, Figure 67 is a schematic diagram of the sixth conductive layer pattern in the display substrate provided in Figure 7, Figure 68 is a schematic diagram of the display substrate provided in Figure 7 after the sixth conductive layer pattern is formed, Figure 69 is a schematic diagram of the sixth conductive layer pattern in the display substrate provided in Figure 9, and Figure 70 is a schematic diagram of the display substrate provided in Figure 9 after the sixth conductive layer pattern is formed.

[0519] In an exemplary embodiment, as shown in FIG. 64 to FIG. 70 , in the display substrate provided in FIG. 3 , FIG. 5 , FIG. 7 and FIG. 9 , the sixth conductive layer pattern may include at least: a first electrode AN1 of the first sub-pixel to a sixth electrode AN6 of the sixth sub-pixel.

[0520] In an exemplary embodiment, in the display substrate provided in FIG. 3 , FIG. 5 , and FIG. 7 , the first electrode AN1 of the first subpixel is connected to the first anode connecting line through the twenty-first via hole. The first electrode AN2 of the second subpixel is connected to the second anode connecting line through the twenty-second via hole. The first electrode AN3 of the third subpixel is connected to the third anode connecting line through the twenty-third via hole. The first electrode AN4 of the fourth subpixel is connected to the fourth anode connecting line through the twenty-fourth via hole. The first electrode AN5 of the fifth subpixel is connected to the fifth anode connecting line through the twenty-fifth via hole. The first electrode AN6 of the sixth subpixel is connected to the sixth anode connecting line through the twenty-sixth via hole.

[0521] In an exemplary embodiment, in the display substrate provided in FIG. 9 , the first electrode AN1 of the first subpixel is connected to the first anode connecting line through the twenty-seventh via hole. The first electrode AN2 of the second subpixel is connected to the second anode connecting line through the twenty-eighth via hole. The first electrode AN3 of the third subpixel is connected to the third anode connecting line through the twenty-ninth via hole. The first electrode AN4 of the fourth subpixel is connected to the fourth anode connecting line through the thirtieth via hole. The first electrode AN5 of the fifth subpixel is connected to the fifth anode connecting line through the thirty-first via hole. The first electrode AN6 of the sixth subpixel is connected to the sixth anode connecting line through the thirty-second via hole.

[0522] (12) Forming a pixel definition layer pattern. In an exemplary embodiment, forming a pixel definition layer pattern may include: coating a pixel definition film on a substrate on which the aforementioned pattern is formed, and patterning the pixel definition film using a patterning process to form a pixel definition layer. A plurality of pixel openings are provided on the pixel definition layer, as shown in Figures 71 to 74. Figure 71 is a schematic diagram of the display substrate provided in Figure 3 after forming a pixel definition layer, Figure 72 is a schematic diagram of the display substrate provided in Figure 5 after forming a pixel definition layer, Figure 73 is a schematic diagram of the display substrate provided in Figure 7 after forming a pixel definition layer, and Figure 74 is a schematic diagram of the display substrate provided in Figure 9 after forming a pixel definition layer.

[0523] In an exemplary embodiment, as shown in FIG. 71 to FIG. 74 , in the display substrate provided in FIG. 3 , FIG. 5 , FIG. 7 and FIG. 9 , the plurality of openings of the pixel definition layer include: a first pixel opening PV1 to a sixth pixel opening PV6 .

[0524] In an exemplary embodiment, as shown in Figures 71 to 74, the first pixel opening PV1 exposes the first electrode of the first subpixel, the second pixel opening PV1 exposes the first electrode of the second subpixel, the third pixel opening PV3 exposes the first electrode of the third subpixel, the fourth pixel opening PV4 exposes the first electrode of the fourth subpixel, the fifth pixel opening PV5 exposes the first electrode of the fifth subpixel, and the sixth pixel opening PV6 exposes the first electrode of the sixth subpixel.

[0525] In an exemplary embodiment, the subsequent preparation process may include: first forming an organic light-emitting layer by evaporation or inkjet printing, then forming a cathode on the organic light-emitting layer, then forming an encapsulation structure layer, and forming an optical structure layer on the encapsulation structure layer.

[0526] In an exemplary embodiment, the sixth conductive layer may be made of a metal material or a transparent conductive material. The metal material may include any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or alloys thereof. The transparent conductive material may include indium tin oxide (ITO) or indium zinc oxide (IZO). In an exemplary embodiment, the anode conductive layer may be a single-layer structure or a multi-layer composite structure, such as ITO / Al / ITO.

[0527] In an exemplary embodiment, the material of the pixel definition layer may include polyimide, acryl, polyethylene terephthalate, or the like.

[0528] In exemplary embodiments, the cathode may include any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu), and lithium (Li), or an alloy thereof.

[0529] The present disclosure further provides a display device including the aforementioned display substrate. The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system, but the embodiments of the present invention are not limited thereto.

[0530] The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures may refer to general designs.

[0531] For the sake of clarity, the thickness and size of layers or microstructures are exaggerated in the drawings used to describe the embodiments of the present disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element can be "directly on" or "under" the other element, or intervening elements may be present.

[0532] Although the embodiments disclosed in this disclosure are as described above, the contents described are merely embodiments adopted to facilitate understanding of the disclosure and are not intended to limit the disclosure. Any person skilled in the art to which the disclosure belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the disclosure. However, the scope of patent protection of the disclosure shall still be based on the scope defined by the attached claims.

Claims

1. A display substrate, comprising: A substrate and pixel units arranged in an array on the substrate, at least one pixel unit including: a plurality of sub-pixels, the plurality of sub-pixels including: at least one anti-peeping sub-pixel and at least one shared sub-pixel, at least one sub-pixel including: a pixel driving circuit and a light-emitting device, the pixel driving circuit being configured to drive the light-emitting device to emit light, the display mode of the display substrate including: a first display mode and a second display mode, the viewing angle range of the first display mode being smaller than the viewing angle range of the second display mode; In a state where the display mode of the display substrate is the first display mode, the anti-peeping sub-pixel emits light, and in a state where the display mode of the display substrate is the second display mode, the shared sub-pixel emits light, or the anti-peeping sub-pixel and the shared sub-pixel emit light.

2. The display substrate according to claim 1, wherein, The plurality of sub-pixels in at least one pixel unit include: a first sub-pixel to a sixth sub-pixel; The pixel driving circuits in the first sub-pixel to the sixth sub-pixel in the same pixel unit are arranged in an array or arranged along a first direction along a first direction and a second direction, the first sub-pixel and the second sub-pixel emit first color light, the third sub-pixel and the fourth sub-pixel emit second color light, the fifth sub-pixel and the sixth sub-pixel emit third color light, and the first direction and the second direction intersect; One of the first sub-pixel and the second sub-pixel is an anti-peeping sub-pixel, and the other of the first sub-pixel and the second sub-pixel is a shared sub-pixel. One of the third sub-pixel and the fourth sub-pixel is an anti-peeping sub-pixel, and the other of the third sub-pixel and the fourth sub-pixel is a shared sub-pixel. One of the fifth sub-pixel and the sixth sub-pixel is an anti-peeping sub-pixel, and the other of the fifth sub-pixel and the sixth sub-pixel is a shared sub-pixel.

3. The display substrate according to claim 1, wherein, The light-emitting device includes: a first electrode, and the display substrate is further provided with a pixel defining layer, and the pixel defining layer is provided with a pixel opening exposing the first electrode; For the anti-peeping sub-pixel and the shared sub-pixel that emit the same color light, the area of the first electrode in the anti-peeping sub-pixel is equal to the area of the first electrode in the shared sub-pixel, and the area of the pixel opening exposing the first electrode of the anti-peeping sub-pixel is smaller than the area of the pixel opening exposing the first electrode of the shared sub-pixel; The pixel opening exposing the first electrode of the anti-peeping sub-pixel includes: at least two sub-pixel openings, and at least two sub-pixel openings are arranged along the first direction.

4. The display substrate according to claim 2, wherein, The light-emitting device includes: a first electrode; For at least one pixel unit, the light-emitting devices of the first sub-pixel, the light-emitting devices of the second sub-pixel, the light-emitting devices of the third sub-pixel, and the light-emitting devices of the fourth sub-pixel are arranged along the second direction, the light-emitting devices of the fifth sub-pixel and the light-emitting devices of the sixth sub-pixel are arranged along the second direction, the light-emitting devices of the third sub-pixel and the light-emitting devices of the fifth sub-pixel are arranged along the first direction, and the light-emitting devices of the fourth sub-pixel and the light-emitting devices of the sixth sub-pixel are arranged along the first direction; The area of the first electrode of the fifth sub-pixel and the area of the first electrode of the sixth sub-pixel are greater than the area of the first electrode of the third sub-pixel and the area of the first electrode of the fourth sub-pixel, and the area of the first electrode of the third sub-pixel and the area of the first electrode of the fourth sub-pixel are greater than the area of the first electrode of the first sub-pixel and the area of the first electrode of the second sub-pixel.

5. The display substrate according to claim 2 further comprises: A driving structure layer, a light-emitting structure layer, a packaging layer, and an optical structure layer are sequentially stacked on the substrate. The pixel driving circuit is disposed on the driving structure layer, the light-emitting device is disposed on the light-emitting structure layer, and the optical structure layer includes at least one of a light-shielding structure layer and an optical device layer; The optical device layer is located on one side of the light-shielding structure layer close to or away from the substrate.

6. The display substrate according to claim 5, wherein, The light-shielding structure layer includes a first light-shielding layer, a light-shielding base layer, and a second light-shielding layer. The first light-shielding layer is located on the side of the light-shielding base layer close to the substrate, and the second light-shielding layer is located on the side of the light-shielding base layer away from the substrate. The first light-shielding layer includes a plurality of first light-shielding structures, and the second light-shielding layer includes a plurality of second light-shielding structures; the light-emitting structure layer includes an organic light-emitting layer of the light-emitting device of at least one sub-pixel; The orthographic projection of the first light-shielding layer on the substrate overlaps at least partially with the orthographic projection of the second light-shielding layer on the substrate. The first light-shielding structure and the second light-shielding structure are located in the anti-peeping sub-pixel region, and the orthographic projection on the substrate overlaps partially with the orthographic projection of the organic light-emitting layer of at least one anti-peeping sub-pixel on the substrate. The anti-peeping sub-pixel region is the region where the anti-peeping sub-pixel is located.

7. The display substrate according to claim 5, wherein The optical device layer includes an optical base layer and a plurality of optical devices. The optical devices are located on one side of the optical base layer close to or away from the substrate, and the optical devices are configured to converge incident light; the light-emitting structure layer includes an organic light-emitting layer of the light-emitting device of at least one sub-pixel; The orthographic projection of the optical device on the substrate overlaps at least partially with the orthographic projection of the organic light-emitting layer of the anti-peeping sub-pixel on the substrate.

8. The display substrate according to claim 5 further comprises: Multiple signal lines and multiple anode connection lines, the pixel driving circuit is electrically connected to the multiple signal lines and the multiple anode connection lines respectively. The driving structure layer includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer stacked in sequence on the substrate. The pixel driving circuit includes: at least one transistor and at least one capacitor. The transistor includes: an active pattern, a gate electrode, a first pole, and a second pole. The capacitor includes: a first plate and a second plate; The semiconductor layer at least includes: active patterns of at least one transistor located in at least one sub-pixel; The first conductive layer at least includes: at least one of the multiple signal lines, gate electrodes of at least one transistor located in at least one sub-pixel, and the first plate of at least one capacitor; The second conductive layer at least includes: at least one of the multiple signal lines and the second plate of at least one capacitor located in at least one sub-pixel; The third conductive layer at least includes: at least one of the multiple signal lines, the first pole and the second pole of at least one transistor located in at least one sub-pixel; The fourth conductive layer at least includes: at least one of the multiple signal lines; The fifth conductive layer at least includes: at least one of the multiple anode connection lines; 9. The display substrate according to claim 8, wherein, For at least one pixel unit, the pixel driving circuits of the first sub-pixel, the third sub-pixel, and the fifth sub-pixel are arranged in sequence along the first direction. The pixel driving circuits of the second sub-pixel, the fourth sub-pixel, and the sixth sub-pixel are arranged in sequence along the first direction. The pixel driving circuit of the first sub-pixel and the pixel driving circuit of the second sub-pixel are arranged along the second direction. The pixel driving circuit of the third sub-pixel and the pixel driving circuit of the fourth sub-pixel are arranged along the second direction. The pixel driving circuit of the fifth sub-pixel and the pixel driving circuit of the sixth sub-pixel are arranged along the second direction.

10. The display substrate according to claim 9, wherein, The multiple signal lines include: 2M reset signal lines, 2M scan signal lines, 2M light-emitting signal lines, 2M first initial signal lines, 2M second initial signal lines, 3N first power supply lines, and 3N data signal lines. M is the total number of rows of pixel units, and N is the total number of columns of pixel units; At least one of the reset signal lines, scan signal lines, light-emitting signal lines, first initial signal lines, and second initial signal lines extends at least partially along the first direction. At least one of the first power supply lines and data signal lines extends at least partially along the second direction, and the line width of the first power supply line is greater than the line width of the data signal line; The pixel unit at the i-th row and j-th column is electrically connected to the (2i - 1)-th scanning signal line, the 2i-th scanning signal line, the (2i - 1)-th reset signal line, the 2i-th reset signal line, the (2i - 1)-th light-emitting signal line, the 2i-th light-emitting signal line, the (2i - 1)-th first initial signal line, the 2i-th first initial signal line, the (2i - 1)-th second initial signal line, the 2i-th second initial signal line, the (3j - 2)-th first power supply line, the (3j - 1)-th first power supply line, the 3j-th first power supply line, the (3j - 2)-th data signal line, the (3j - 1)-th data signal line, and the 3j-th data signal line respectively, where 1 ≤ i ≤ M and 1 ≤ j ≤ N.

11. The display substrate according to claim 10, wherein, For at least one pixel unit, the pixel structures of at least two sub-pixels among the first sub-pixel to the sixth sub-pixel are at least partially the same.

12. The display substrate according to claim 10, wherein, In the pixel unit at the i-th row and j-th column, at least one sub-pixel among the first sub-pixel, the third sub-pixel, and the fifth sub-pixel is electrically connected to the (2i - 1)-th scanning signal line, the (2i - 1)-th light-emitting signal line, the (2i - 1)-th reset signal line, the (2i - 1)-th first initial signal line, and the (2i - 1)-th second initial signal line respectively, and at least one sub-pixel among at least one sub-pixel among the second sub-pixel, the fourth sub-pixel, and the sixth sub-pixel is electrically connected to the 2i-th scanning signal line, the 2i-th light-emitting signal line, the 2i-th reset signal line, the 2i-th first initial signal line, and the 2i-th second initial signal line respectively. At least one sub-pixel among the first sub-pixel and the second sub-pixel is also electrically connected to the (3j - 2)-th first power supply line and the (3j - 2)-th data signal line respectively. At least one sub-pixel among the third sub-pixel and the fourth sub-pixel is also electrically connected to the (3j - 1)-th first power supply line and the (3j - 1)-th data signal line respectively. At least one sub-pixel among the fifth sub-pixel and the sixth sub-pixel is also electrically connected to the 3j-th first power supply line and the 3j-th data signal line respectively.

13. The display substrate according to claim 10, wherein, The orthographic projections of the first initial signal line, the second initial signal line, the reset signal line, the scanning signal line, and the light-emitting signal line connected to the same sub-pixel are arranged in sequence along the second direction on the substrate; The orthographic projection of the k-th data signal line on the substrate is located between the orthographic projection of the k-th first power supply line on the substrate and the orthographic projection of the (k + 1)-th first power supply line on the substrate, where 1 ≤ k ≤ 3N.

14. The display substrate according to claim 10, wherein, At least one transistor includes: a node reset transistor, a driving transistor, and a compensation transistor; the second pole of the node reset transistor and the first pole of the compensation transistor are an integrated structure and are electrically connected to the gate electrode of the driving transistor; The orthographic projection of the first power supply line on the substrate and the orthographic projection of the integrated structure of the second pole of the node reset transistor and the first pole of the compensation transistor in the sub-pixel connected to the first power supply line on the substrate overlap at least partially.

15. The display substrate according to claim 10, wherein, The first power supply line includes: a first sub-power supply line and a second sub-power supply line connected to each other, the first sub-power supply line and the second sub-power supply line extend along the second direction, and their orthographic projections on the substrate overlap at least partially; The light-emitting signal line is located in the first conductive layer, the first initial signal line and the second initial signal line are located in the second conductive layer, the reset signal line and the scan signal line are located in the third conductive layer, the first sub-power line is located in the fourth conductive layer, the second sub-power line is located in the fifth conductive layer, and the data signal line is located in the fourth conductive layer or the fifth conductive layer.

16. The display substrate according to claim 9, wherein, The multiple signal lines include: 2M reset signal lines, 2M scan signal lines, 2M light-emitting signal lines, 2M first initial signal lines, 2M second initial signal lines, 4N first power lines, and 6N data signal lines, where M is the total number of rows of pixel units and N is the total number of columns of pixel units; At least one of the reset signal line, the scan signal line, the light-emitting signal line, the first initial signal line, and the second initial signal line extends at least partially along the first direction, and at least one of the first power line and the data signal line extends at least partially along the second direction; The pixel unit in the i-th row and j-th column is electrically connected to the (2i - 1)-th scan signal line, the 2i-th scan signal line, the (2i - 1)-th reset signal line, the 2i-th reset signal line, the (2i - 1)-th light-emitting signal line, the 2i-th light-emitting signal line, the (2i - 1)-th first initial signal line, the 2i-th first initial signal line, the (2i - 1)-th second initial signal line, the 2i-th second initial signal line, the (4j - 3)-th first power line, the (4j - 2)-th first power line, the (4j - 1)-th first power line, the 4j-th first power line, the (6j - 5)-th data signal line, the (6j - 4)-th data signal line, the (6j - 3)-th data signal line, the (6j - 2)-th data signal line, the (6j - 1)-th data signal line, and the 6j-th data signal line, where 1 ≤ i ≤ M and 1 ≤ j ≤ N.

17. The display substrate according to claim 16, wherein, For at least one pixel unit, the pixel structures of the pixel driving circuits of at least two of the first sub-pixel, the third sub-pixel, and the fifth sub-pixel are at least partially the same, the pixel structures of the pixel driving circuits of at least two of the second sub-pixel, the fourth sub-pixel, and the sixth sub-pixel are at least partially the same, and the pixel structure of the pixel driving circuit of the first sub-pixel and the pixel structure of the pixel driving circuit of the second sub-pixel are at least partially mirror-symmetrical.

18. The display substrate according to claim 16, wherein, In the pixel unit at the i-th row and j-th column, at least one of the first sub-pixel, the third sub-pixel, and the fifth sub-pixel is electrically connected to the (2i - 1)-th scan signal line, the (2i - 1)-th light-emitting signal line, the (2i - 1)-th reset signal line, the (2i - 1)-th first initial signal line, and the (2i - 1)-th second initial signal line respectively; at least one of the second sub-pixel, the fourth sub-pixel, and the sixth sub-pixel is electrically connected to the 2i-th scan signal line, the 2i-th light-emitting signal line, the 2i-th reset signal line, the 2i-th first initial signal line, and the 2i-th second initial signal line respectively; the first sub-pixel is further electrically connected to the (6j - 4)-th data signal line and the (4j - 2)-th first power supply line respectively; the second sub-pixel is further electrically connected to the (6j - 5)-th data signal line and the (4j - 3)-th first power supply line respectively; the third sub-pixel is further electrically connected to the (6j - 2)-th data signal line and the (4j - 1)-th first power supply line respectively; the fourth sub-pixel is further electrically connected to the (6j - 3)-th data signal line and the (4j - 2)-th first power supply line respectively; the fifth sub-pixel is further electrically connected to the 6j-th data signal line and the 4j-th first power supply line respectively; the sixth sub-pixel is further electrically connected to the (6j - 1)-th data signal line and the (4j - 1)-th first power supply line respectively.

19. The display substrate according to claim 16, wherein The positive projection of the first initial signal line, the second initial signal line, the reset signal line, the scan signal line, and the light-emitting signal line on the substrate to which the same sub-pixel is connected are arranged in sequence along the second direction; For at least one pixel unit, the positive projection of the two data signal lines connected by the two sub-pixels arranged along the second direction on the substrate is located between the positive projections of the two first power supply lines connected by the two sub-pixels on the substrate.

20. The display substrate according to claim 16, wherein, At least one transistor includes: a node reset transistor, a driving transistor, and a compensating transistor; the second pole of the node reset transistor and the first pole of the compensating transistor are an integrated structure and are electrically connected to the gate electrode of the driving transistor; the capacitor further includes: a third electrode plate, the third electrode plate is electrically connected to the second electrode plate and is located in the fourth conductive layer; For at least one sub-pixel, the positive projection of the third electrode plate on the substrate overlaps at least partially with the integrated structure of the second pole of the node reset transistor and the first pole of the compensating transistor on the substrate; The positive projection of the third electrode plates of the two sub-pixels arranged along the second direction on the substrate is located between the positive projections of the two data signal lines connected by the two sub-pixels arranged along the second direction on the substrate.

21. The display substrate according to claim 16, wherein, The light-emitting signal line is located in the first conductive layer, the first initial signal line and the second initial signal line are located in the second conductive layer, the reset signal line and the scan signal line are located in the third conductive layer, and the data signal line and the first power supply line are located in the fourth conductive layer.

22. The display substrate according to claim 8, wherein, For at least one pixel unit, the pixel driving circuits of the first sub-pixel, the pixel driving circuits of the second sub-pixel, the pixel driving circuits of the third sub-pixel, the pixel driving circuits of the fourth sub-pixel, the pixel driving circuits of the fifth sub-pixel, and the pixel driving circuits of the sixth sub-pixel are arranged in sequence along the first direction.

23. The display substrate according to claim 22, wherein, The multiple signal lines include: 2M reset signal lines, 2M scan signal lines, 2M light-emitting signal lines, M first initial signal lines, M second initial signal lines, 4N first power lines, and 6N data signal lines, where M is the total number of rows of pixel units and N is the total number of columns of pixel units; At least one of the reset signal lines, scan signal lines, light-emitting signal lines, first initial signal lines, and second initial signal lines extends at least partially along the first direction, and at least one of the first power lines and data signal lines extends at least partially along the second direction; The pixel unit in the i-th row and j-th column is electrically connected to the (2i - 1)-th scan signal line, the 2i-th scan signal line, the (2i - 1)-th reset signal line, the 2i-th reset signal line, the (2i - 1)-th light-emitting signal line, the 2i-th light-emitting signal line, the i-th first initial signal line, the i-th second initial signal line, the (4j - 3)-th first power line, the (4j - 2)-th first power line, the (4j - 1)-th first power line, the 4j-th first power line, the (6j - 5)-th data signal line, the (6j - 4)-th data signal line, the (6j - 3)-th data signal line, the (6j - 2)-th data signal line, the (6j - 1)-th data signal line, and the 6j-th data signal line, where 1 ≤ i ≤ M and 1 ≤ j ≤ N.

24. The display substrate according to claim 23, wherein, For at least one pixel unit, the pixel structures of the pixel driving circuits of adjacent sub-pixels are symmetrically arranged at least partially with respect to a virtual straight line extending along the second direction.

25. The display substrate according to claim 23, wherein, In the pixel unit in the i-th row and j-th column, at least one of the first sub-pixel to the sixth sub-pixel is electrically connected to the (2i - 1)-th scan signal line, the 2i-th scan signal line, the (2i - 1)-th reset signal line, the 2i-th reset signal line, the (2i - 1)-th light-emitting signal line, the 2i-th light-emitting signal line, the i-th first initial signal line, and the i-th second initial signal line. The first sub-pixel is further electrically connected to the (6j - 5)-th data signal line and the (4j - 3)-th first power line. The second sub-pixel is further electrically connected to the (6j - 4)-th data signal line and the (4j - 2)-th first power line. The third sub-pixel is further electrically connected to the (6j - 3)-th data signal line and the (4j - 2)-th first power line. The fourth sub-pixel is further electrically connected to the (6j - 2)-th data signal line and the (4j - 1)-th first power line. The fifth sub-pixel is further electrically connected to the (6j - 1)-th data signal line and the (4j - 1)-th first power line. The sixth sub-pixel is further electrically connected to the 6j-th data signal line and the 4j-th first power line.

26. The display substrate according to claim 23, wherein The at least one transistor includes: a first light-emitting transistor, a second light-emitting transistor, a node reset transistor, an anode reset transistor, a writing transistor, a compensation transistor, and a driving transistor; The first light-emitting transistor and the writing transistor are electrically connected to the first pole of the driving transistor respectively. The second light-emitting transistor is electrically connected to the second pole of the driving transistor and the first electrode of the light-emitting device respectively. The anode reset transistor is electrically connected to the first electrode of the light-emitting device. The compensation transistor is electrically connected to the gate electrode and the second pole of the driving transistor respectively. The node reset transistor is electrically connected to the gate electrode of the driving transistor. For the pixel unit at the i-th row and the j-th column, the gate electrode of the first light-emitting transistor in at least one sub-pixel is electrically connected to the (2i - 1)-th light-emitting signal line. The gate electrode of the second light-emitting transistor is electrically connected to the 2i-th light-emitting signal line. The gate electrode of the writing transistor is electrically connected to the (2i - 1)-th scanning signal line. The gate electrode of the compensation transistor is electrically connected to the 2i-th scanning signal line. The gate electrode of the node reset transistor is electrically connected to the (2i - 1)-th reset signal line. The gate electrode of the anode reset transistor is electrically connected to the 2i-th reset signal line.

27. The display substrate according to claim 23, wherein, For the pixel unit at the i-th row, the positive projections of the (2i - 1)-th light-emitting signal line, the (2i - 1)-th scanning signal line, the 2i-th scanning signal line, the (2j - 1)-th reset signal line, the i-th first initial signal line, the 2i-th light-emitting signal line, the 2i-th reset signal line, and the i-th second initial signal line on the substrate are arranged in sequence along the second direction. For at least one pixel unit, the positive projection of the data signal line connected to the x-th sub-pixel and the (x + 1)-th sub-pixel on the substrate is located between the positive projections of the first power supply line connected to the x-th sub-pixel and the (x + 1)-th sub-pixel on the substrate, where 1 ≤ x ≤ 6 and x is odd.

28. The display substrate according to claim 23, wherein The odd-numbered scanning signal lines include: a first sub-scanning signal line and a second sub-scanning signal line connected to each other. The first sub-scanning signal line and the second sub-scanning signal line extend along the first direction, and at least part of their positive projections on the substrate overlap. The first sub-scanning signal line is located in the first conductive layer, and the second sub-scanning signal line is located in the third conductive layer.

29. The display substrate according to claim 23, wherein The even-numbered reset signal lines include: a first sub-reset signal line and a second sub-reset signal line connected to each other. The first sub-reset signal line and the second sub-reset signal line extend along the first direction, and at least part of their positive projections on the substrate overlap. The first sub-reset signal line is located in the first conductive layer, and the second sub-reset signal line is located in the third conductive layer.

30. The display substrate according to claim 23, wherein, The light-emitting signal lines are located in the first conductive layer. The first initial signal lines and the second initial signal lines are located in the second conductive layer. The even-numbered scanning signal lines and the odd-numbered reset signal lines are located in the third conductive layer. The data signal lines and the first power supply lines are located in the fourth conductive layer.

31. The display substrate according to claim 8, wherein, The multiple signal lines include: multiple first initial signal lines and multiple second initial signal lines. The display substrate further includes: at least one connection line among the first initial connection line and the second initial connection line. The first initial connection line extends along the second direction and is located between adjacent pixel units. The first initial connection line is electrically connected to the multiple first initial signal lines. The second initial connection line extends along the second direction and is located between adjacent pixel units. The second initial connection line is electrically connected to the multiple second initial signal lines. The first initial connection line and the second initial connection line are located in the fourth conductive layer or the fifth conductive layer.

32. The display substrate according to claim 2 further comprises: A first multiplexing control signal line, a second multiplexing control signal line, 6N data signal lines, 3N data power supply lines, and a data multiplexing circuit, where the data multiplexing circuit includes: N sub-multiplexing circuits, and N is the total number of columns of pixel units; The nth sub-multiplexing circuit is respectively electrically connected to three data power supply lines, the first multiplexing control signal line, the second multiplexing control signal line, and six data signal lines connected to the nth column of pixel units, and is configured to provide the signal of at least one data power supply line to at least one data signal line under the signal control of the first multiplexing control signal line and the second multiplexing control signal line; 1 ≤ n ≤ N.

33. The display substrate according to claim 32, wherein, The nth sub-multiplexing circuit includes: a first multiplexing transistor to a sixth multiplexing transistor; The gate electrode of the first multiplexing transistor is electrically connected to the first multiplexing control signal line, the first pole of the first multiplexing transistor is electrically connected to the data signal line connected to one of the first sub-pixel and the second sub-pixel in the nth column of pixel units, and the second pole of the first multiplexing transistor is electrically connected to the first data power supply line among the three data power supply lines connected to the nth multiplexing sub-circuit; The gate electrode of the second multiplexing transistor is electrically connected to the first multiplexing control signal line, the first pole of the second multiplexing transistor is electrically connected to the data signal line connected to one of the third sub-pixel and the fourth sub-pixel in the nth column of pixel units, and the second pole of the second multiplexing transistor is electrically connected to the second data power supply line among the three data power supply lines connected to the nth multiplexing sub-circuit; The gate electrode of the third multiplexing transistor is electrically connected to the first multiplexing control signal line, the first pole of the third multiplexing transistor is electrically connected to the data signal line connected to one of the fifth sub-pixel and the sixth sub-pixel in the nth column of pixel units, and the second pole of the third multiplexing transistor is electrically connected to the third data power supply line among the three data power supply lines connected to the nth multiplexing sub-circuit; The gate electrode of the fourth multiplexing transistor is electrically connected to the second multiplexing control signal line, the first pole of the fourth multiplexing transistor is electrically connected to the data signal line connected to the other sub-pixel among the first sub-pixel and the second sub-pixel in the nth column of pixel units, and the second pole of the fourth multiplexing transistor is electrically connected to the first data power supply line among the three data power supply lines connected to the nth multiplexing sub-circuit; The gate electrode of the fifth multiplexing transistor is electrically connected to the second multiplexing control signal line, the first pole of the fifth multiplexing transistor is electrically connected to the data signal line connected to the other sub-pixel among the third sub-pixel and the fourth sub-pixel in the nth column of pixel units, and the second pole of the fifth multiplexing transistor is electrically connected to the second data power supply line among the three data power supply lines connected to the nth multiplexing sub-circuit; The gate electrode of the sixth multiplexing transistor is electrically connected to the second multiplexing control signal line. The first pole of the sixth multiplexing transistor is electrically connected to the data signal line to which the fifth sub-pixel and another sub-pixel among the sixth sub-pixels in the n-th column of pixel units are connected. The second pole of the sixth multiplexing transistor is electrically connected to the third data power supply line among the three data power supply lines to which the n-th multiplexing sub-circuit is connected.

34. A display device, comprising: The display substrate according to any one of claims 1 to 33.

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