Array substrate and display panel

Abstract

An array substrate, comprising: a substrate (10) and, arranged on the substrate (10), switch transistors (23), a first electrode (21) and a second electrode (22). In a first direction (X), gates (233) of the adjacent switching transistors (23) are connected by a first gate connection section (241) extending in the first direction (X). In a second direction (Y), each first gate connection section (241) has a first edge (2411) and a second edge (2412), and the gate (233) of each switch transistor (23) has a third edge (2421) connected to a first edge (2411) and a fourth edge (2422) connected to a second edge (2412). The orthographic projection of the second electrode (22) on the substrate (10) covers at least part of the third edges (2421) of the gates (233) of the switch transistors (23) and at least part of the fourth edges (2422) thereof.

Description

Array substrate and display panel Technical Field

[0001] This article relates to but is not limited to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] Liquid Crystal Displays (LCDs), with their compact size, low power consumption, and zero radiation, currently dominate the display market. High-Aperture Ratio Advanced Dimension Switch (HADS) LCDs, with their large aperture ratio and high transmittance, have been widely adopted in small and medium-sized products such as mobile phones and tablets.

[0003] Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] Embodiments of the present disclosure provide an array substrate and a display panel.

[0006] In one aspect, this embodiment provides an array substrate, comprising: a substrate, a switching transistor disposed on the substrate, a first electrode, and a second electrode; the switching transistor is connected to the first electrode, and the first and second electrodes have at least partially overlapping orthographic projections on the substrate. In a first direction, the gates of adjacent switching transistors are connected by a first gate connection segment extending along the first direction. In a second direction, the first gate connection segment has a first edge and a second edge, and the gate of the switching transistor has a third edge connected to the first edge of the first gate connection segment and a fourth edge connected to the second edge of the first gate connection segment. In the second direction, the maximum distance between the third edge and the fourth edge is greater than the maximum distance between the first edge and the second edge, the maximum distance between the third edge and the first edge is greater than zero, and the maximum distance between the fourth edge and the second edge is greater than zero. The orthographic projection of the second electrode on the substrate covers at least a portion of the third edge and at least a portion of the fourth edge of the gate of the switching transistor; the first direction intersects the second direction.

[0007] In some exemplary embodiments, in the second direction, a distance between an orthographic projection of the second electrode and an adjacent first gate connecting segment on the substrate is greater than zero.

[0008] In some exemplary embodiments, in the second direction, a distance between the second electrode and an adjacent first gate connecting segment on an orthographic projection of the substrate is the same as an edge coverage distance of the second electrode to the gate of the switching transistor.

[0009] In some exemplary embodiments, in the second direction, a distance between an orthographic projection of the second electrode and an adjacent first gate connecting segment on the substrate is greater than or equal to 2.0 micrometers and less than or equal to 2.5 micrometers.

[0010] In some exemplary embodiments, a length of the first gate connecting segment along the second direction ranges from 3.5 micrometers to 5.0 micrometers.

[0011] In some exemplary embodiments, the second electrode and the first gate connecting segment at least partially overlap in orthographic projection on the substrate.

[0012] In some exemplary embodiments, a length of the first gate connection segment along the second direction is a sum of twice a distance covered by the second electrode over an edge of the gate of the switching transistor and a minimum exposure size.

[0013] In some exemplary embodiments, a length of the first gate connecting segment along the second direction ranges from 7.6 micrometers to 9.4 micrometers.

[0014] In some exemplary embodiments, a distance that the second electrode covers an edge of the gate of the switching transistor is greater than or equal to 2.0 micrometers and less than or equal to 2.5 micrometers.

[0015] In some exemplary embodiments, in the second direction, a distance between a first center line of the first gate connecting segment and a second center line of the gate of the switching transistor is less than 0.1 micrometers.

[0016] In some exemplary embodiments, a first electrode of the switching transistor is connected to a data line, a second electrode of the switching transistor is connected to the first electrode, the second electrode of the switching transistor is symmetrically arranged about a third center line, and a first angle between the third center line and a first center line of the gate of the switching transistor in the second direction is in a range of 30 degrees to 60 degrees.

[0017] In some exemplary embodiments, the first electrode of the switching transistor has an orthographic projection on the substrate in a U-shape, and an opening of the U-shape faces the first electrode connected to the switching transistor.

[0018] In some exemplary embodiments, an edge of the first electrode in the second direction extends in the same direction as the first gate connecting segment, and an edge of the first electrode in the first direction extends in the same direction as the data line.

[0019] In some example embodiments, a distance between the first electrode and an adjacent first gate connecting segment is smaller than a distance between the first electrode and an adjacent data line.

[0020] In some exemplary embodiments, in a direction perpendicular to the array substrate, the array substrate includes at least: a first conductive layer, a semiconductor layer, a second conductive layer, a first transparent conductive layer, and a second transparent conductive layer disposed on the substrate. The first conductive layer includes at least: a gate electrode of the switching transistor and the first gate connecting segment; the semiconductor layer includes at least: an active layer of the switching transistor; the second conductive layer includes at least: a first electrode and a second electrode of the switching transistor; the first electrode is located in the first transparent conductive layer, and the second electrode is located in the second transparent conductive layer.

[0021] In another aspect, this embodiment provides a display panel comprising the array substrate described above, an opposing substrate, a liquid crystal layer located between the array substrate and the opposing substrate, and a plurality of support pillars, wherein the orthographic projections of the support pillars on the substrate of the array substrate overlap with the orthographic projections of the gate, active layer, first electrode, and second electrode of the switching transistor of the array substrate on the substrate.

[0022] In some exemplary embodiments, the orthographic projection of the support pillar on the substrate is located within the orthographic projection range of the gate of the switching transistor on the substrate, and the orthographic projection of the active layer of the switching transistor on the substrate is located within the orthographic projection range of the support pillar on the substrate.

[0023] In some exemplary embodiments, a distance between a center line of the support pillar in the second direction and a second center line of the gate of the switching transistor in the second direction is less than or equal to 0.1 micrometer.

[0024] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0025] Summary of the Figures

[0026] The accompanying drawings are used to provide a further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0027] FIG1 is a schematic diagram of an array substrate according to at least one embodiment of the present disclosure;

[0028] FIG2 is a partial top view of an array substrate according to at least one embodiment of the present disclosure;

[0029] FIG3 is a schematic partial cross-sectional view along the QQ' direction in FIG2;

[0030] FIG4 is a schematic diagram of the array substrate after the first conductive layer is formed in FIG2 ;

[0031] FIG5 is a schematic diagram of the array substrate after the semiconductor layer is formed in FIG2 ;

[0032] FIG6 is a schematic diagram of the array substrate after the second conductive layer is formed in FIG2 ;

[0033] FIG7 is a schematic diagram of the array substrate after the second insulating layer is formed in FIG2 ;

[0034] FIG8 is a schematic diagram of the array substrate after the first transparent conductive layer is formed in FIG2 ;

[0035] FIG9 is a schematic diagram of the second transparent conductive layer in FIG2 ;

[0036] FIG10 is another partial schematic top view of the array substrate according to at least one embodiment of the present disclosure;

[0037] FIG11 is a schematic diagram of the array substrate after the first conductive layer is formed in FIG10 ;

[0038] FIG12 is a schematic diagram of the array substrate after the second conductive layer is formed in FIG10;

[0039] FIG13 is a partial cross-sectional schematic diagram of a display panel according to at least one embodiment of the present disclosure;

[0040] FIG14 is a schematic diagram of an orthographic projection of a support column on an array substrate according to at least one embodiment of the present disclosure;

[0041] FIG15 is a schematic diagram of an orthographic projection of a black matrix on an array substrate according to at least one embodiment of the present disclosure.

[0042] Details

[0043] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a variety of different forms. A person skilled in the art can easily understand that the method and content can be transformed into one or more forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other in any way.

[0044] In the drawings, the size of one or more components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of various components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0045] In the present disclosure, ordinal numbers such as "first," "second," and "third" are provided to avoid confusion among constituent elements, and are not intended to limit the number. In the present disclosure, "plurality" refers to a number of two or more.

[0046] In this disclosure, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, it should not be understood as a limitation of this disclosure. The positional relationships of constituent elements are appropriately changed according to the direction in which the constituent elements are described. Therefore, the words and phrases are not limited to those described in the specification and can be appropriately replaced according to the circumstances.

[0047] In this disclosure, unless otherwise expressly specified or limited, the terms "mounted," "connected," "connected," and "coupled" should be interpreted broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the meanings of these terms in this disclosure based on the specific circumstances.

[0048] In this disclosure, a transistor refers to a device comprising at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain) and a source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0049] In this disclosure, to distinguish the two electrodes of a transistor other than the gate electrode, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode. The first electrode can be either a source electrode or a drain electrode, and the second electrode can be either a drain electrode or a source electrode. Furthermore, the gate electrode of the transistor is referred to as the control electrode. In cases where transistors with opposite polarity are used or where the direction of current changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, in this disclosure, the terms "source electrode" and "drain electrode" may be interchanged.

[0050] In this disclosure, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables transmission of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having one or more functions.

[0051] In this disclosure, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus includes a state where the angle is greater than 85° and less than 95°.

[0052] The terms “approximately” and “substantially” in the present disclosure do not strictly define the limits and allow for errors within the range of process and measurement errors.

[0053] The display principle of a high-aperture advanced super-dimensional field switch (HADS) type liquid crystal display is to control the liquid crystal rotation angle by controlling the voltage difference between the pixel electrode and the common electrode, thereby controlling the pixel light transmittance to achieve the target display screen. However, in the sub-pixel area, especially near the gate line, due to the high voltage difference between the signal voltage transmitted by the gate line and the voltage transmitted by the common electrode, the liquid crystal rotation in the area near the gate line is not controlled by the pixel voltage transmitted by the pixel electrode. Therefore, when the area is not blocked by the black matrix (BM) or the black matrix blocking area is small, pixel light leakage will occur, thereby affecting the contrast ratio (CR) of the display product. Among them, the contrast ratio refers to the ratio of the positive viewing angle at the brightness of L255 (i.e., the 255th grayscale) to the positive viewing angle at the brightness of L0. Moreover, if the black matrix blocks a large area of ​​the aforementioned area, although there is no risk of pixel light leakage, the pixel transmittance (TR) will be low, thereby affecting the overall display effect of the display product.

[0054] This embodiment provides an array substrate and a display panel, which can improve pixel light leakage while ensuring pixel transmittance, thereby improving the contrast of the display panel.

[0055] This embodiment provides an array substrate, comprising: a substrate, a switching transistor disposed on the substrate, a first electrode, and a second electrode. The switching transistor is connected to the first electrode, and the first and second electrodes at least partially overlap in their orthographic projections on the substrate. In a first direction, the gates of adjacent switching transistors are connected by a first gate connecting segment extending along the first direction. In a second direction, the first gate connecting segment has a first edge and a second edge, and the gate of the switching transistor has a third edge connected to the first edge and a fourth edge connected to the second edge. In the second direction, the maximum distance between the third edge and the fourth edge is greater than the maximum distance between the first edge and the second edge; the maximum distance between the third edge and the first edge is greater than zero, and the maximum distance between the fourth edge and the second edge is greater than zero. The orthographic projection of the second electrode on the substrate covers at least a portion of the third edge and at least a portion of the fourth edge of the gate of the switching transistor. The first direction intersects the second direction; for example, the first direction may be perpendicular to the second direction. In some examples, the first electrode may be a pixel electrode, and the second electrode may be a common electrode.

[0056] The array substrate provided in this embodiment, by setting the position of the first gate connection segment connected to the gates of adjacent switching transistors and covering the gate edges of the switching transistors with a second electrode, can shield the electric field near the first gate connection segment while ensuring pixel transmittance, thereby improving pixel light leakage near the gate line, thereby improving display contrast at a wide viewing angle or when black matrix coverage is insufficient, and further improving the display effect of touch display products.

[0057] In some exemplary embodiments, the distance between the second electrode and the orthographic projection of the adjacent first gate connecting segment on the substrate in the second direction may be greater than zero. In this example, the orthographic projections of the second electrode and the first gate connecting segment on the substrate may not overlap. In some examples, the distance between the second electrode and the orthographic projection of the adjacent first gate connecting segment on the substrate in the second direction may be greater than or equal to 2.0 microns and less than or equal to 2.5 microns, for example, approximately 2.3 microns. In this example, the distance between the first gate connecting segment and the edge of the second electrode is increased to reduce loading, thereby improving contrast.

[0058] In some exemplary embodiments, in the second direction, the distance between the second electrode and the orthographic projection of the adjacent first gate connection segment on the substrate can be the same as the edge coverage distance of the second electrode over the gate of the switching transistor. In some examples, the edge coverage distance of the second electrode over the gate of the switching transistor can be greater than or equal to 2.0 microns and less than or equal to 2.5 microns, for example, can be approximately 2.3 microns. In this example, by setting the edge coverage distance of the second electrode over the gate of the switching transistor, it is ensured that the second electrode can still effectively cover the edge of the gate of the switching transistor after an overlay deviation occurs, thereby achieving the effect of shielding the electric field near the first gate connection segment.

[0059] In some exemplary embodiments, the length of the first gate connection segment along the second direction may range from 3.5 microns to 5.0 microns, that is, the length of the first gate connection segment along the second direction may be greater than or equal to 3.5 microns and less than or equal to 5.0 microns. In this example, the length of the first gate connection segment along the second direction is set to ensure that the first gate connection segment and the second electrode do not overlap.

[0060] In some exemplary embodiments, the orthographic projections of the second electrode and the first gate connecting segment on the substrate may at least partially overlap. For example, the orthographic projection of the second electrode on the substrate may cover the first and second edges of the first gate connecting segment. In this example, by having the second electrode cover the edge of the first gate connecting segment, light leakage from side angles can be completely avoided, thereby improving contrast.

[0061] In some exemplary embodiments, the length of the first gate connection segment along the second direction may be the sum of twice the edge coverage distance of the second electrode to the gate of the switching transistor and the minimum exposure size. In some examples, the edge coverage distance of the second electrode to the gate of the switching transistor may be greater than or equal to 2.0 microns and less than or equal to 2.5 microns, for example, may be approximately 2.3 microns. In some examples, the length of the first gate connection segment along the second direction may range from 7.6 microns to 9.4 microns, that is, greater than or equal to 7.6 microns and less than or equal to 9.4 microns. For example, the length of the first gate connection segment along the second direction may be approximately 8.6 microns. The length of the first connection segment along the second direction set in this example can ensure that there is overlap between the first gate connection segment and the second electrode.

[0062] This embodiment also provides a display panel, comprising: an array substrate of this embodiment, an opposing substrate, a liquid crystal layer located between the array substrate and the opposing substrate, and a plurality of support pillars (PS, photo spacers). The orthographic projections of the support pillars on the substrate of the array substrate can overlap with the orthographic projections of the gate, active layer, first electrode, and second electrode of the switching transistor of the array substrate on the substrate. The display panel provided by this embodiment can ensure that the black matrix of the opposing substrate blocks the array substrate by setting the position of the support pillars, thereby achieving the effect of improving pixel light leakage while maintaining pixel transmittance.

[0063] In some exemplary embodiments, the display panel may be a liquid crystal display panel. In some examples, the display panel may be an advanced super-dimensional switch (ADS) type liquid crystal display panel, or may be a high-aperture ratio advanced super-dimensional switch (HADS) type liquid crystal display panel. This embodiment is not limited to this.

[0064] The following examples illustrate the solution of this embodiment. The following examples are described using an array substrate of the HADS type using self-capacitive touch technology as an example. In the following examples, the first electrode is a pixel electrode and the second electrode is a common electrode as an example.

[0065] Figure 1 is a schematic diagram of an array substrate according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 1 , the array substrate may include a display area AA and a border area BB located around the display area AA. The border area BB may include a first border area B1 located on one side of the display area AA and a second border area B2 located on the remaining sides of the display area AA. For example, the first border area B1 may include the bottom border of the array substrate, and the second border area B2 may include the top, left, and right borders of the array substrate.

[0066] In some examples, as shown in FIG1 , the display area AA may include: a plurality of data lines DL and a plurality of gate lines GL disposed on a substrate. The plurality of gate lines GL may extend along a first direction X and be sequentially arranged along a second direction Y different from the first direction X. The plurality of data lines DL may extend along the second direction Y and be sequentially arranged along the first direction X. The first direction X and the second direction Y may intersect; for example, the first direction X may be perpendicular to the second direction Y. The plurality of data lines DL and the plurality of gate lines GL may be located in different film layers; for example, the plurality of data lines DL may be located on a side of the plurality of gate lines GL away from the substrate.

[0067] In some examples, as shown in FIG1 , a plurality of data lines DL and a plurality of gate lines GL may intersect to form a plurality of sub-pixel areas. The area defined by the intersection of adjacent data lines DL and adjacent gate lines GL may be a sub-pixel area. A sub-pixel may be provided in a corresponding sub-pixel area. For example, the sub-pixel area may include an opening area and a non-opening area surrounding the opening area. The non-opening area may be an area blocked by the black matrix of the opposing substrate of the array substrate, and the opening area may be an area not blocked by the black matrix of the opposing substrate. For example, adjacent gate lines GL and data lines DL may both be located in the non-opening area. The array substrate of this embodiment may be used to implement a display function, and the opening area of ​​each sub-pixel area may be configured for display. The non-opening area surrounds the opening area and does not display. However, this embodiment is not limited to this. In some examples, the array substrate may be used to implement other functions.

[0068] In some examples, the display area AA may include: a plurality of pixel units disposed on a substrate. At least one pixel unit may include: three sub-pixels (e.g., a first sub-pixel, a second sub-pixel, and a third sub-pixel arranged sequentially along a first direction X). The three sub-pixels of the pixel unit may be, for example, a blue sub-pixel, a red sub-pixel, and a green sub-pixel, and the three sub-pixels may be arranged sequentially in the order of the blue sub-pixel, the green sub-pixel, and the red sub-pixel.

[0069] In some examples, as shown in FIG1 , at least one sub-pixel may include a pixel electrode 21 and a common electrode (not shown in FIG1 ), and the orthographic projections of the pixel electrode 21 and the common electrode of the sub-pixel on the substrate may at least partially overlap. The common electrodes of the multiple sub-pixels in the display area AA may be an integral structure. For example, the common electrode may be located on a side of the pixel electrode 21 away from the substrate.

[0070] In some examples, the sub-pixel may further include a switching transistor 23. The switching transistor 23 may be located adjacent to the intersection of the data line DL and the gate line GL. The switching transistor 23 may include a gate, a first electrode, and a second electrode. The gate may be electrically connected to the gate line GL, the first electrode of the switching transistor 23 may be electrically connected to the data line DL, and the second electrode may be electrically connected to the pixel electrode 21 of a sub-pixel. The switching transistor 23 may be configured to provide a data signal transmitted by the data line DL to the pixel electrode 21 of the sub-pixel under the control of the gate line GL.

[0071] Figure 2 is a partial top view of an array substrate according to at least one embodiment of the present disclosure. Figure 3 is a partial cross-sectional view along the Q-Q' direction in Figure 2. Figure 2 illustrates four switching transistors arranged in an array.

[0072] In some examples, as shown in FIG2 , within a plane parallel to the array substrate, the array substrate may include: a substrate and a plurality of switching transistors 23 disposed on the substrate, a plurality of pixel electrodes 21, a plurality of common electrodes 22, a plurality of touch signal lines 26, a plurality of data lines DL, and a plurality of gate lines GL. The plurality of switching transistors 23 may be arranged in an array along a first direction X and a second direction Y. The plurality of switching transistors 23 arranged along the first direction X may be referred to as a row of switching transistors, and the plurality of switching transistors 23 arranged along the second direction Y may be referred to as a column of switching transistors. The gates of the plurality of switching transistors 23 in the same row and the connected gate lines GL may be interconnected as an integral structure, and the first electrodes of the plurality of switching transistors 23 in the same column and the connected data lines DL may be interconnected as an integral structure.

[0073] 2 , the touch signal lines 26 may be interspersed between the data lines DL. For example, one touch signal line 26 may be disposed between two data lines DL. The touch signal lines 26 and the data lines DL may be arranged one by one along the first direction X.

[0074] In some examples, the array substrate of this example can utilize self-capacitive touch technology. The common electrodes 22 can be reused as touch electrodes. During the display phase, a common voltage is supplied to the common electrodes 23 via touch signal lines 26 to implement the display function. During the touch phase, the touch signal lines 26 transmit touch signals detected by the common electrodes 23 to implement the touch function. In some examples, multiple touch signal lines 26 can be connected to multiple touch sensing blocks in a one-to-one correspondence. Each touch sensing block can include multiple common electrodes reused as touch electrodes, for example, tens of common electrodes. The touch signal lines 26 connected to the touch sensing blocks can be connected to a driver integrated circuit that integrates display and touch functions. In this example, the common electrodes are reused as touch electrodes. During the display phase, a common voltage is applied to the common electrodes to implement the display function, and during the touch phase, a touch signal is applied to the common electrodes to implement the touch function. This eliminates the need for additional film layers for the touch electrodes, thereby saving manufacturing processes and reducing the thickness of the array substrate.

[0075] In some examples, as shown in FIG3 , in a direction perpendicular to the array substrate, the array substrate may include: a substrate 10, and a first conductive layer, a first insulating layer 101, a semiconductor layer, a second conductive layer, a second insulating layer 102, a first transparent conductive layer, a third insulating layer 103, and a second transparent conductive layer, sequentially disposed on the substrate 10. The first conductive layer may include at least a gate electrode 233 of the switching transistor 23; the semiconductor layer may include at least an active layer 230 of the switching transistor 23; the second conductive layer may include at least a first electrode 231 and a second electrode 232 of the switching transistor 23; the first transparent conductive layer may include at least a pixel electrode 21; and the second transparent conductive layer may include a common electrode 22. This example employs a bottom-gate switching transistor. The gate shields the channel region of the active layer, preventing external light from affecting the characteristics of the switching transistor. By arranging for the first and second electrodes of the switching transistor located in the second conductive layer to directly contact the active layer located in the semiconductor layer, the number of insulating film layers can be reduced, thereby lowering costs.

[0076] In some examples, the first insulating layer 101 may be an inorganic insulating layer, the second insulating layer 102 may be an organic insulating layer, and the third insulating layer 103 may be an inorganic insulating layer. However, this embodiment is not limited thereto. In other examples, the second insulating layer may be an inorganic insulating layer.

[0077] The preparation process of the array substrate is exemplified below. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials or transparent conductive materials, and includes processes such as coating organic materials, mask exposure and development for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a thin film made by deposition, coating or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern".

[0078] The phrase "A and B are arranged in the same layer" in this specification means that A and B are formed simultaneously through the same patterning process. The "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. "The orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B. The shape of A in this example refers to the shape of the orthographic projection of A on the substrate. In this example, the distance between A and B refers to the vertical distance between A and B.

[0079] The preparation process of the array substrate of this example may include the following steps.

[0080] (1-1) Provide a substrate. In some examples, substrate 10 may be a transparent substrate. For example, substrate 10 may be a rigid substrate or a flexible substrate. For example, the material of the rigid substrate may include, but is not limited to, one or more of glass and quartz; the material of the flexible substrate may include, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber. However, this embodiment is not limited to this.

[0081] (1-2) Forming a First Conductive Layer: In some examples, a first conductive film is deposited on the substrate 10 and patterned by a patterning process to form a first conductive layer disposed on the substrate 10 .

[0082] FIG4 is a schematic diagram of the array substrate after the first conductive layer is formed in FIG2 . In some examples, as shown in FIG4 , the first conductive layer may include at least a plurality of gate lines GL. Each gate line GL may include a plurality of first gate connection segments 241 extending along a first direction X, and a second gate connection segment 242 serving as the gate 233 of the switching transistor. In the first direction X, the first gate connection segments 241 and the second gate connection segments 242 may be connected at intervals. In other words, the gates 233 of adjacent switching transistors are connected via the first gate connection segments 241, and adjacent first gate connection segments may be connected via the gates 233 of the switching transistors. In this example, a portion of the gate line GL may serve as the gate 233 of the switching transistor, enabling signal transmission along the first direction X.

[0083] In some examples, the first gate connection segment 241 can be shaped substantially like a strip extending along the first direction X. The first gate connection segment 241 can have a first edge 2411 and a second edge 2412 in the second direction Y. The extension direction of the first edge 2411 can be parallel to the extension direction of the second edge 2412, for example, both being parallel to the first direction X. The maximum distance between the first edge 2411 and the second edge 2412 of the first gate connection segment 241 can be the length of the first gate connection segment 241 along the second direction Y, for example, which can be represented by a first width W1. The first width W1 can be substantially 3.5 microns to 5.0 microns, for example, approximately 3.5 microns, 4.0 microns, or 5.0 microns.

[0084] In some examples, the shape of the second gate connection segment 242 (i.e., the gate 233 of the switching transistor) can be roughly polygonal, for example, a rounded rectangle or a chamfered rectangle with inclined corners. The second gate connection segment 242 can have a third edge 2421 and a fourth edge 2422 in the second direction Y. The third edge 2421 and the fourth edge 2422 can be roughly fold lines extending along the first direction X. For example, the third edge 2421 can be bent along the second direction Y, and the fourth edge 2422 can be bent in the opposite direction of the second direction Y. The third edge 2421 of the second gate connection segment 242 is adjacent to and connected to the first edge 2411 of the first gate connection segment 241, and the fourth edge 2422 of the second gate connection segment 242 is adjacent to and connected to the second edge 2412 of the first gate connection segment 241.

[0085] In some examples, in the second direction Y, the maximum distance between the third edge 2421 of the second gate connecting segment 242 and the first edge 2411 of the first gate connecting segment 241 can be recorded as a first distance L1, and the maximum distance between the fourth edge 2422 of the second gate connecting segment 242 and the second edge 2412 of the first gate connecting segment 241 can be recorded as a second distance L2. The first distance L1 and the second distance L2 can both be greater than 0. For example, the first distance L1 can be substantially the same as the second distance L2. However, this embodiment is not limited to this.

[0086] In some examples, the maximum distance between the third edge 2421 and the fourth edge 2422 of the second gate connection segment 242 can be the maximum length of the second gate connection segment 242 along the second direction Y, which can be expressed as, for example, the second width W2. The second width W2 can be greater than the first width W1. For example, the second width W2 = the first distance L1 + the first width W1 + the second distance L2.

[0087] In some examples, the first gate connecting segment 241 may have a first centerline O1 along the second direction Y, and the second gate connecting segment 242 may have a second centerline O2 along the second direction Y. The first centerline O1 and the second centerline O2 may extend along the first direction X. For example, the first centerline O1 and the second centerline O2 may coincide, that is, the distance between the first centerline O1 and the second centerline O2 in the second direction Y is zero. However, this embodiment is not limited to this. In other examples, the distance between the first centerline O1 and the second centerline O2 in the second direction may be less than 0.1 micrometers.

[0088] In some examples, the first conductive layer can be made of a metal material, such as any one or more of molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti, etc.

[0089] (1-3) Forming a semiconductor layer. In some examples, a first insulating film and a semiconductor film are sequentially deposited on the substrate 10 forming the aforementioned structure, and the semiconductor film is patterned by a patterning process to form a first insulating layer 101 and a semiconductor layer disposed on the first insulating layer 101.

[0090] Figure 5 is a schematic diagram of the array substrate after the semiconductor layer is formed in Figure 2. In some examples, the semiconductor layer may include: an active layer 230 for multiple switching transistors 23. The orthographic projection of the active layer 230 of the switching transistor 23 onto the substrate may be located within the orthographic projection of the gate 233 onto the substrate. The shape of the active layer 230 of the switching transistor 23 may be approximately a chamfered rectangle or a polygon.

[0091] In some examples, a center line of the active layer 230 of the switch transistor 23 in the second direction Y may coincide with the first center line O1 or the second center line O2 . The center of the active layer 230 of the switch transistor 23 may substantially coincide with the center of the gate 233 .

[0092] In some examples, the active layer 230 of the switching transistor 23 may include: a first region, a second region, and a channel region located between the first region and the second region. In some examples, the semiconductor thin film may be made of one or more materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene, and polythiophene. In other words, the embodiments of the present disclosure are applicable to transistors manufactured based on oxide technology, silicon technology, and organic technology. However, this embodiment is not limited to this.

[0093] In some examples, the material of the active layer 230 may include, for example, polysilicon. The channel region may not be doped with impurities and may have semiconductor properties. The first region and the second region may be doped regions on both sides of the channel region and may be doped with impurities and thus have conductivity. The impurities may vary depending on the type of transistor (e.g., N-type or P-type). In some examples, the doped region of the active layer may be interpreted as a source electrode or a drain electrode of the transistor. The portion of the active layer between the transistors may be interpreted as wiring doped with impurities, which may be used to electrically connect the transistors.

[0094] In some examples, the first insulating layer may be any one or more of silicon oxide (SiOx, x>0), silicon nitride (SiNy, y>0), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer. However, this embodiment is not limited thereto.

[0095] (1-4) Forming a second conductive layer. In some examples, a second conductive film is deposited on the substrate 10 forming the aforementioned structure, and the second conductive film is patterned by a patterning process to form a second conductive layer.

[0096] 6 is a schematic diagram of the array substrate after the second conductive layer is formed in FIG2 . In some examples, the second conductive layer may include: a plurality of data lines DL, a plurality of touch signal lines 26 , and a plurality of second electrodes 232 of switch transistors 23 .

[0097] In some examples, the data line DL may extend generally along the second direction Y. The data line DL may include a first data connection segment 251 and a second data connection segment 252. The second data connection segment 252 may function as the first electrode 231 of the switching transistor 23. In the second direction Y, the first data connection segment 251 and the second data connection segment 252 may be connected at intervals. In other words, the first electrodes 231 of adjacent switching transistors 23 may be connected via the first data connection segment 251, and adjacent first data connection segments 251 may be connected via the first electrodes 231 of the switching transistor 23. In this example, a portion of the data line DL may function as the first electrode 231 of the switching transistor, enabling data signal transmission along the second direction Y.

[0098] In some examples, the shape of the first data connection segment 251 can be roughly a broken line extending along the second direction Y. The shape of the second data connection segment 252 (i.e., the first electrode 231 of the switching transistor 23) can be roughly U-shaped. One end of the U-shaped segment is connected to one first data connection segment 251, and the bottom of the U-shaped segment near the other end is connected to another first data connection segment 251. The opening of the U-shaped segment can face the second electrode 232 of the switching transistor 23, and one end of the second electrode 232 of the switching transistor 23 can extend into the opening of the U-shaped segment.

[0099] In some examples, the second data connection segment 252 and the active layer 230 of the switch transistor 23 may partially overlap. For example, the second data connection segment 252 may cover an edge of the active layer 230 of the switch transistor 23 away from the second electrode 232 .

[0100] In some examples, the second electrode 232 of the switching transistor 23 may be adjacent to the first data connection segment 251 in the first direction X. For example, the second electrode 232 of the switching transistor 23 may be located on a side of the first data connection segment 251 of the connected data line opposite to the first direction X. The shape of the second electrode 232 of the switching transistor 23 may be approximately fan-shaped. The second electrode 232 of the switching transistor 23 may be arranged approximately symmetrically about the third center line O3. The extension direction of the third center line O3 may intersect both the first direction X and the second direction Y. The counterclockwise angle between the third center line O3 and the first center line O1 may be denoted as a first angle a. The first angle a may range from 30 degrees to 60 degrees, i.e., greater than or equal to 30 degrees and less than or equal to 60 degrees, and may, for example, be approximately 45 degrees.

[0101] In some examples, a touch signal line 26 may be disposed between adjacent data lines DL. The extending direction of the touch signal line 26 is substantially the same as the extending direction of the data lines DL.

[0102] In some examples, the second conductive layer can be made of a metal material, such as any one or more of molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or an alloy material of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti, etc.

[0103] (1-5) Forming a second insulating layer. In some examples, a second insulating film is deposited on the substrate 10 forming the aforementioned structure, and the second insulating film is patterned by a patterning process to form a second insulating layer.

[0104] Figure 7 is a schematic diagram of the array substrate after the second insulating layer is formed in Figure 2. In some examples, the second insulating layer may have multiple first vias V1. The second insulating layer within the multiple first vias V1 may be removed, exposing a portion of the surface of the second conductive layer. The orthographic projection of a first via V1 on the substrate may be located within the orthographic projection of the second electrode 232 of the switching transistor 23 on the substrate.

[0105] In some examples, the second insulating layer may be made of an organic insulating material. However, this embodiment is not limited thereto. In other examples, the second insulating layer may be made of an inorganic insulating material.

[0106] (1-6) Forming a first transparent conductive layer. In some examples, a first transparent conductive film is deposited on the substrate 10 having the aforementioned structure, and the first transparent conductive film is patterned by a patterning process to form a first transparent conductive layer.

[0107] FIG8 is a schematic diagram of the array substrate after the first transparent conductive layer is formed in FIG2 . In some examples, as shown in FIG8 , the first transparent conductive layer may include: a plurality of pixel electrodes 21. The orthographic projection of the pixel electrode 21 on the substrate may be located within a sub-pixel region formed by the intersection of adjacent data lines DL and adjacent gate lines GL. The orthographic projection of the pixel electrode 21 on the substrate may not overlap with the orthographic projections of the data lines DL and the gate lines GL on the substrate. The orthographic projection of the pixel electrode 21 on the substrate may be roughly polygonal, for example, roughly rectangular.

[0108] In some examples, the pixel electrode 21 may have a fifth edge 211 and a sixth edge 212 in the second direction Y, and may have a seventh edge 213 and an eighth edge 214 in the first direction X. The fifth edge 211 and the sixth edge 212 may extend in a direction substantially the same as the direction of extension of the first gate connection segment 241 , for example, and may be parallel to the first direction X. The seventh edge 213 and the eighth edge 214 may extend in a direction substantially the same as the direction of extension of the first data connection segment 251 of the data line DL, for example, and may extend substantially along the second direction Y.

[0109] In some examples, the distance between the fifth edge 211 and the first edge 2411 of the adjacent first gate connecting segment 241 can be recorded as a third distance L3. The distance between the sixth edge 212 and the second edge 2412 of the adjacent first gate connecting segment 241 can be recorded as a fourth distance L4. For example, the fourth distance L4 can be greater than or equal to the third distance L3, and the third distance L3 and the fourth distance L4 can both be greater than 0.

[0110] In some examples, the distance between the seventh edge 213 and the adjacent first data connection segment 251 can be recorded as a fifth distance L5. The distance between the eighth edge 214 and the adjacent first data connection segment 241 can be recorded as a sixth distance L6. For example, the fifth distance L5 can be equal to the sixth distance L6, and the fifth distance L5 and the sixth distance L6 can both be greater than 0.

[0111] In some examples, the distance between the pixel electrode 21 and the adjacent first gate connection segment 241 can be smaller than the distance between the pixel electrode 21 and the adjacent first data connection segment 251 of the data line DL. In some examples, the third distance L3 and the fourth distance L4 can range from approximately 3.2 microns to 4.0 microns, for example, the third distance L3 or the fourth distance L4 can be approximately 3.2 microns, 3.6 microns, or 4.0 microns. In some examples, the fifth distance L5 and the sixth distance L6 can range from approximately 4.2 microns to 5.2 microns, for example, the fifth distance L5 and the sixth distance L6 can be approximately 4.2 microns, 4.7 microns, or 5.2 microns.

[0112] In some examples, the first transparent conductive layer may be made of a transparent conductive material, such as indium tin oxide (ITO), indium zinc oxide (IZO), or the like.

[0113] (1-7) Forming a third insulating layer and a second transparent conductive layer. In some examples, a third insulating film is deposited on the substrate 10 having the aforementioned structure to form the third insulating layer; subsequently, a second transparent conductive film is deposited and patterned to form the second transparent conductive layer.

[0114] FIG9 is a schematic diagram of the second transparent conductive layer in FIG2 . In some examples, as shown in FIG2 and FIG9 , the second transparent conductive layer may include at least a plurality of common electrodes 22 . For example, a plurality of common electrodes 22 adjacent along a first direction X may be interconnected as a single structure. Adjacent common electrodes along a second direction Y may be connected via a connecting electrode (not shown). The orthographic projection of the common electrode 22 on the substrate at least partially overlaps the orthographic projection of the pixel electrode 21 on the substrate.

[0115] In some examples, the common electrode 22 may have multiple slits 220. For example, one common electrode 22 may have four slits 220. The slits 220 may extend substantially along the second direction Y. For example, the extension direction of the slits 220 may be substantially the same as the extension direction of the first data connection segment 251. The four slits 220 of the common electrode 22 may extend in substantially the same direction and be arranged sequentially along the first direction X. The orthographic projection of a second slit 220 arranged along the first direction X onto the substrate may overlap with the orthographic projection of the touch signal line 26 onto the substrate. The width of the second slit 220 (e.g., the length perpendicular to the extension direction) may be greater than the widths of the remaining slits 220. This arrangement can reduce the impact of parasitic capacitance between the common electrode and the touch signal line. In this example, the multiple slits 220 extend in the same direction, forming a single-domain structure. However, this embodiment is not limited to this. In other examples, the common electrode may have slits extending in two different directions, thereby forming a dual-domain structure.

[0116] In some examples, the common electrode 22 may have a ninth edge 221 and a tenth edge 222 in the second direction Y. The extension directions of the ninth edge 221 and the tenth edge 222 may be substantially parallel to the first direction X. The ninth edge 221 may have first recessed portions 2210 that are spaced apart and recessed in the second direction Y. The tenth edge 222 may have second recessed portions 2220 that are spaced apart and recessed in the opposite direction of the second direction Y.

[0117] In some examples, the orthographic projection of the common electrode 22 on the substrate may not overlap with the orthographic projection of the adjacent first gate connecting segment 241 on the substrate. The distance between the ninth edge 221 of the common electrode 22 and the first edge 2411 of the adjacent first gate connecting segment 241 can be recorded as the seventh distance L7. The distance between the tenth edge 222 of the common electrode 22 and the second edge 2412 of the adjacent first gate connecting segment 241 can be recorded as the eighth distance L8. The seventh distance L7 and the eighth distance L8 can be greater than 0. In some examples, the seventh distance L7 and the eighth distance L8 can be the same. However, this embodiment is not limited to this. For example, the seventh distance L7 and the eighth distance L8 can be different.

[0118] In some examples, the seventh distance L7 and the eighth distance L8 may be film layer coverage deviation parameters between the first conductive layer and the second transparent conductive layer, and may be, for example, greater than or equal to 2.0 microns and less than or equal to 2.5 microns, such as approximately 2.3 microns. This example configuration ensures that the orthographic projections of the first gate connecting segment and the common electrode on the substrate do not overlap.

[0119] In some examples, the orthographic projection of the common electrode 22 on the substrate may cover a portion of the third edge 2421 and a portion of the fourth edge 2322 of the gate 233 of the switching transistor 23. For example, the edge of the first recess 2210 of the ninth edge 221 of the common electrode 22 may cover a portion of the third edge 2421 of the gate 233 of the switching transistor, and the edge of the second recess 2220 of the tenth edge 222 of the common electrode 22 may cover a portion of the fourth edge 2422 of the gate 233 of another switching transistor. The orthographic projection of the common electrode 22 on the substrate may not overlap with the orthographic projection of the active layer 230 of the switching transistor on the substrate.

[0120] In some examples, the edge coverage distance of the common electrode 22 over the gate 233 of the switching transistor 23 and the distance between the common electrode 22 and the orthographic projection of the adjacent first gate connection segment 241 on the substrate can be approximately the same. For example, the edge coverage distance of the common electrode 22 over the gate 233 of the switching transistor 23 can be a film layer coverage deviation parameter between the first conductive layer and the second transparent conductive layer, for example, greater than or equal to 2.0 microns and less than or equal to 2.5 microns, such as approximately 2.3 microns. This example ensures that even after the common electrode has a setting deviation, the common electrode can still effectively cover the gate edge of the switching transistor, thereby shielding the electric field near the first gate connection segment.

[0121] In some examples, the second transparent conductive layer may be made of a transparent conductive material, such as indium tin oxide (ITO), indium zinc oxide (IZO), and the like.

[0122] The structure and fabrication process of the array substrate in this example are merely illustrative. In some examples, the corresponding structure can be modified and patterning processes can be added or removed based on actual needs. For example, the common electrode can be a sheet-like electrode structure without slits, thereby increasing the touch electrode area and enhancing touch performance. In other examples, the common electrode can be located in the first transparent conductive layer, and the pixel electrode can be located in the second transparent conductive layer. However, this embodiment is not limited to this.

[0123] In some examples, the orthographic projection of the black matrix of the opposing substrate onto the substrate can cover the orthographic projections of the switching transistor, data line, and gate line onto the substrate, and the distance between the edge of the black matrix and the first gate connection segment can be greater than the distance between the pixel electrode and the first gate connection segment. Light effect simulations for a display panel using the array substrate of this example show that the pixel light leakage area (as shown in the dashed box area DG in Figure 2) is significantly away from the edge of the black matrix, significantly improving light leakage through the black matrix openings.

[0124] The switching transistor of this example adopts an inclined design, which can help ensure pixel transmittance. On the basis of ensuring pixel transmittance, this example increases the boundary distance between the first gate connection segment and the black matrix by adjusting the position of the first gate connection segment between the gates of adjacent switching transistors, and uses the common electrode located in the second transparent conductive layer as a shielding layer for the third edge and the fourth edge of the gate of the switching transistor, which can improve the pixel light leakage. Moreover, the load is reduced by setting the distance between the edge of the first gate connection segment and the common electrode. This example has limited impact on the gate line load and touch load of the array substrate. Although there is still a pixel light leakage area, the pixel light leakage area can be completely covered by the black matrix, which can effectively improve the display contrast. The array substrate of this example can be suitable for display products with high charging rate requirements.

[0125] Figure 10 is another partial top view of the array substrate according to at least one embodiment of the present disclosure. Figure 11 is a schematic diagram of the array substrate after forming the first conductive layer in Figure 10. Figure 12 is a schematic diagram of the array substrate after forming the second conductive layer in Figure 10.

[0126] In some examples, as shown in Figures 10 to 12, the gate line GL located in the first conductive layer may include: a plurality of first gate connection segments 241 extending along the first direction X, and a second gate connection segment 242 serving as the gate 233 of the switching transistor. The first width W1 of the first gate connection segment 241 may be the sum of twice the film layer coverage deviation parameter between the first conductive layer and the second transparent conductive layer and the minimum exposure size. For example, the minimum exposure size may be the minimum size of the second transparent conductive layer within the resolution range of the exposure machine, for example, approximately 3.6 microns to 4.4 microns, for example, approximately 4.0 microns. In some examples, the first width W1 may range from 7.6 microns to 9.4 microns, for example, approximately 7.6 microns, 8.6 microns, or 9.4 microns.

[0127] In some examples, as shown in FIG10 , the orthographic projection of the common electrode 22 on the substrate may cover the third and fourth edges of the gate 233 of the switching transistor, and may also cover the first and second edges of the first gate connection segment. The orthographic projections of the ninth and tenth edges 221 and 222 of the common electrode 22 on the substrate may overlap with the orthographic projections of the first gate connection segment and the gate of the switching transistor on the substrate.

[0128] In some examples, the edge coverage distance of the common electrode 22 on the gate of the switching transistor and the edge coverage distance of the common electrode 22 on the first gate connection segment 241 can both be film layer coverage deviation parameters between the first conductive layer and the second transparent conductive layer. For example, the edge coverage distance of the common electrode on the gate of the switching transistor and the edge coverage distance of the common electrode 22 on the first gate connection segment 241 can be greater than or equal to 2.0 microns and less than or equal to 2.5 microns, for example, can be approximately 2.3 microns. This example ensures that the common electrode can still effectively cover the edge of the gate of the switching transistor and the edge of the first gate connection segment after a coverage deviation occurs, thereby shielding the electric field near the first gate connection segment.

[0129] In some examples, for a display panel using the array substrate of this example, through light effect simulation, it can be found that pixel light leakage basically disappears, and there is no light leakage in both the covered area and the uncovered area of ​​the black matrix.

[0130] The switching transistor of this example adopts an inclined design, which can help ensure pixel transmittance. On the basis of ensuring pixel transmittance, this example increases the boundary distance between the first gate connection segment and the black matrix by adjusting the position of the first gate connection segment between the gates of adjacent switching transistors, and uses the common electrode located in the second transparent conductive layer as a shielding layer for the edge of the gate of the switching transistor and the edge of the first gate connection segment, which can completely avoid pixel light leakage and thus improve display contrast. This example may cause an increase in gate line load and touch load, which has a certain impact on power consumption and touch performance. The array substrate of this example can be suitable for display products with low charging rate requirements.

[0131] FIG13 is a partial cross-sectional schematic diagram of a display panel according to at least one embodiment of the present disclosure. In some examples, as shown in FIG13 , the display panel of this example may include: an array substrate 31, an opposing substrate 32, a liquid crystal layer 33 located between the array substrate 31 and the opposing substrate 32, and a plurality of support pillars 34. The opposing substrate 32 may include: an opposing substrate 320, a black matrix 322 disposed on the opposing substrate 320, a color filter layer (e.g., including a first filter unit 323a, a second filter unit 323b, and a third filter unit 323c), and an overcoat layer (OC) 321. Adjacent filter units may be separated by the black matrix 322.

[0132] Figure 14 is a schematic diagram of the orthographic projection of the support column on the array substrate of at least one embodiment of the present disclosure. In some examples, as shown in Figures 13 and 14, the shape of the orthographic projection of the support column 34 on the substrate can be roughly polygonal, for example, it can be a rectangle with chamfered corners. The extension direction of the long side of the support column 34 can be roughly the same as the extension direction of the first gate connection segment, such as parallel to the first direction X. The orthographic projection of the support column 34 on the substrate 10 of the array substrate 31 can overlap with the orthographic projection of the gate, active layer, first pole and second pole of the switching transistor 23 of the array substrate 31 on the substrate 10. For example, the orthographic projection of the support column 34 on the substrate 10 can be located within the orthographic projection range of the gate of the switching transistor 23 on the substrate 10, and the orthographic projection of the active layer of the switching transistor 23 on the substrate is located within the orthographic projection range of the support column 34 on the substrate 10.

[0133] In some examples, the support pillar 34 may have a fourth centerline O4 along the second direction Y, and the fourth centerline O4 may be parallel to the first direction X. The distance between the fourth centerline O4 and the second centerline O2 of the gate of the switching transistor may be denoted as a ninth distance L9. The ninth distance L9 may be less than or equal to 0.1 micrometers. For example, the fourth centerline O4 and the second centerline O2 may coincide with each other. The center of the support pillar 34 may coincide with the center of the gate of the switching transistor to ensure coverage of the support pillar 34 by the black matrix.

[0134] Figure 15 is a schematic diagram of the orthographic projection of the black matrix on the array substrate of at least one embodiment of the present disclosure. In some examples, as shown in Figure 15, the orthographic projection of the black matrix 322 on the substrate can cover the orthographic projections of the data lines DL, scan lines GL, and switching transistors on the substrate. The distance between the edge of the black matrix 322 and the first gate connection segment can be greater than the distance between the pixel electrode and the first gate connection segment. The distance between the edge of the black matrix 322 and the first data connection segment of the data line can be less than the distance between the pixel electrode and the first data connection segment. The arrangement of the black matrix in this example is conducive to ensuring pixel transmittance. The first gate connection segment of the array substrate in this example can be set at a point that divides the gate of the switching transistor along the second direction Y equally, which can increase the distance between the first gate connection segment and the edge of the black matrix, and is conducive to improving the black matrix's shielding effect on pixel light leakage. The remaining description of the array substrate in this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0135] In some examples, the display panel may be any product or component with a display function, such as a liquid crystal panel, electronic paper, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, or a navigation system. This embodiment is not limited thereto.

[0136] The drawings in this disclosure only relate to the structures involved in this disclosure, and other structures can refer to the general design. In the absence of conflict, the embodiments of the present disclosure, that is, the features in the embodiments, can be combined with each other to obtain new embodiments. It should be noted that the above-mentioned embodiments or implementation methods are merely exemplary and not restrictive. Therefore, the present disclosure is not limited to the contents shown and described in detail herein. Various modifications, replacements or omissions can be made to the form and details of the implementation without departing from the scope of this disclosure.

Claims

1. An array substrate, comprising: a substrate, a switching transistor disposed on the substrate, a first electrode, and a second electrode; the switching transistor is connected to the first electrode, and at least a part of the orthographic projections of the first electrode and the second electrode on the substrate overlap; in a first direction, the gates of adjacent switching transistors are connected by a first gate connection segment extending along the first direction; in a second direction, the first gate connection segment has a first edge and a second edge, and the gate of the switching transistor has a third edge connected to the first edge of the first gate connection segment and a fourth edge connected to the second edge of the first gate connection segment; in the second direction, the maximum distance between the third edge and the fourth edge is greater than the maximum distance between the first edge and the second edge, the maximum distance between the third edge and the first edge is greater than 0, and the maximum distance between the fourth edge and the second edge is greater than 0; the orthographic projection of the second electrode on the substrate covers at least a part of the third edge and at least a part of the fourth edge of the gate of the switching transistor; the first direction intersects with the second direction.

2. The array substrate according to claim 1, wherein in the second direction, the distance between the second electrode and the orthographic projection of an adjacent first gate connection segment on the substrate is greater than 0.

3. The array substrate according to claim 2, wherein, in the second direction, the distance between the second electrode and the orthographic projection of an adjacent first gate connection segment on the substrate is the same as the edge coverage distance of the second electrode on the gate of the switching transistor.

4. The array substrate according to claim 3, wherein, in the second direction, the distance between the second electrode and the orthographic projection of an adjacent first gate connection segment on the substrate is greater than or equal to 2.0 micrometers and less than or equal to 2.5 micrometers.

5. The array substrate according to claim 2, wherein, the length of the first gate connection segment along the second direction ranges from 3.5 micrometers to 5.0 micrometers.

6. The array substrate according to claim 1, wherein, the orthographic projection of the second electrode and the first gate connection segment on the substrate at least partially overlap.

7. The array substrate according to claim 6, wherein the length of the first gate connection segment along the second direction is the sum of twice the edge coverage distance of the second electrode on the gate of the switching transistor and the minimum exposure size.

8. The array substrate according to claim 7, wherein the length of the first gate connection segment along the second direction ranges from 7.6 micrometers to 9.4 micrometers.

9. The array substrate according to claim 7, wherein, the edge coverage distance of the second electrode on the gate of the switching transistor is greater than or equal to 2.0 micrometers and less than or equal to 2.5 micrometers.

10. The array substrate according to any one of claims 1 to 9, wherein, in the second direction, the distance between the first midline of the first gate connection segment and the second midline of the gate of the switching transistor is less than 0.1 micrometer.

11. The array substrate according to any one of claims 1 to 10, wherein, the first pole of the switching transistor is connected to a data line, and the second pole of the switching transistor is connected to the first electrode; the second pole of the switching transistor is symmetrically disposed with respect to a third midline, and the range of the first included angle between the third midline and the first midline of the gate of the switching transistor in the second direction is from 30 degrees to 60 degrees.

12. The array substrate according to claim 11, wherein, the orthographic projection of the first pole of the switching transistor on the substrate is U-shaped, and the opening of the U-shape faces the first electrode to which the switching transistor is connected.

13. The array substrate according to any one of claims 1 to 12, wherein, The extending direction of the edge of the first electrode in the second direction is the same as that of the first gate connection segment, and the extending direction of the edge in the first direction is the same as that of the data line.

14. The array substrate according to claim 13, wherein, The distance between the first electrode and the adjacent first gate connection segment is less than the distance between the first electrode and the adjacent data line.

15. The array substrate according to claim 1, wherein, In a direction perpendicular to the array substrate, the array substrate at least includes: a first conductive layer, a semiconductor layer, a second conductive layer, a first transparent conductive layer, and a second transparent conductive layer disposed on the substrate. The first conductive layer at least includes: the gate of the switching transistor and the first gate connection segment. The semiconductor layer at least includes: the active layer of the switching transistor. The second conductive layer at least includes: the first and second electrodes of the switching transistor. The first electrode is located in the first transparent conductive layer, and the second electrode is located in the second transparent conductive layer.

16. A display panel, including the array substrate according to any one of claims 1 to 15, a counter substrate, a liquid crystal layer located between the array substrate and the counter substrate, and a plurality of support pillars. The orthographic projection of the support pillar on the substrate of the array substrate overlaps with the orthographic projections of the gate, active layer, first electrode, and second electrode of the switching transistor of the array substrate on the substrate.

17. The display panel according to claim 16, wherein, The orthographic projection of the support pillar on the substrate is within the orthographic projection range of the gate of the switching transistor on the substrate, and the orthographic projection of the active layer of the switching transistor on the substrate is within the orthographic projection range of the support pillar on the substrate.

18. The display panel according to claim 16, wherein, The distance between the midline of the support pillar in the second direction and the second midline of the gate of the switching transistor in the second direction is less than or equal to 0.1 micrometer.

Images