Battery pack processing apparatus and electronic device

Abstract

The present disclosure relates to the technical field of batteries, and provides a battery pack processing apparatus and an electronic device. In the apparatus, a first chip of and a charging and discharging interface of a charging and discharging management circuit are electrically connected to each other; a pin 11 of the first chip is electrically connected to a pin 24 of a second chip of a logic control circuit; a pin 12 of the first chip is electrically connected to a pin 23 of the second chip; a positive electrode of a battery pack is electrically connected to a pin 1 of a fifth chip, and a negative electrode of the battery pack is electrically connected to a pin 11, a pin CO and a pin 9 of the fifth chip by means of a lithium battery protection circuit; a first signal output end of a battery pack communication circuit is electrically connected to a pin 13 of the second chip; a second signal output end of the battery pack communication circuit is electrically connected to a pin 14 of the second chip; the battery pack communication circuit sends a control signal to the second chip; and the second chip is used for determining, on the basis of the control signal, that the battery pack is connected in parallel or in series. Thus, the battery pack can be connected in series or in parallel, and the working efficiency of the battery pack can be improved.

Description

Battery pack processing and electronics

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure claims priority to Chinese patent application number 202311412338.3, filed with the State Intellectual Property Office of China on October 30, 2023, entitled “Processing device and electronic device for battery pack”, the entire contents of which are incorporated by reference into this disclosure. Technical Field

[0003] The present disclosure relates to the technical field of batteries, and in particular to a processing device and electronic equipment for a battery pack. Background Art

[0004] In a battery pack management system, it is often necessary to detect and control the battery status. Currently, the I2C (Inter-Integrated Circuit) communication protocol is used to implement data exchange between the battery pack and the main control device. To meet higher voltage and capacity requirements, multiple battery packs often need to be stacked and used. In the existing technology, there is a problem of relatively low battery pack utilization efficiency.

[0005] Summary of the Invention

[0006] In order to solve the above technical problems, embodiments of the present disclosure provide a processing device for a battery pack and an electronic device.

[0007] In a first aspect, an embodiment of the present disclosure provides a battery pack processing device, comprising:

[0008] Charge and discharge management circuit, logic control circuit, battery pack protection circuit and battery pack communication circuit;

[0009] The charge and discharge management circuit includes a first chip and a charge and discharge interface, and the first chip and the charge and discharge interface are electrically connected;

[0010] The logic control circuit includes a second chip;

[0011] Pin 11 of the first chip is electrically connected to pin 24 of the second chip; pin 12 of the first chip is electrically connected to pin 23 of the second chip;

[0012] The battery pack protection circuit includes a fifth chip, a lithium battery protection circuit, and a battery pack shutdown protection circuit. The positive electrode of the battery pack is electrically connected to pin 1 of the fifth chip, and the negative electrode of the battery pack is electrically connected to pins 11, CO, and 9 of the fifth chip through the lithium battery protection circuit.

[0013] The first signal output terminal of the battery pack communication circuit is electrically connected to pin 13 of the second chip; the second signal output terminal of the battery pack communication circuit is electrically connected to pin 14 of the second chip;

[0014] The battery pack communication circuit is configured to send a control signal to the second chip via the first signal output terminal and the second signal output terminal;

[0015] The second chip is used to determine whether the battery packs are connected in parallel or in series according to the control signal.

[0016] In some embodiments, the battery pack communication circuit includes a switch module, the switch module includes a twelfth field effect transistor and a thirteenth field effect transistor, and a connection point between the source of the twelfth field effect transistor and the source of the thirteenth field effect transistor is electrically connected to pin 15 of the second chip;

[0017] The second chip is used to control the switching module to be turned on or off when it is determined that the battery packs are connected in parallel or in series.

[0018] In some embodiments, the battery pack communication circuit includes a sixth chip, wherein pin 8 of the sixth chip is electrically connected to pin 16 of the second chip; and pin 1 of the sixth chip is electrically connected to pin 15 of the second chip;

[0019] The second chip is configured to send an enable signal to pin 1 of the sixth chip to start the sixth chip when determining that the battery packs are connected in parallel or in series;

[0020] The sixth chip is used to send the read output current value of the sixth chip to pin 15 of the second chip.

[0021] In some embodiments, the charge and discharge interface includes an activation module, which includes a twelfth resistor, a second field effect transistor, an eleventh resistor, a thirteenth resistor and a seventeenth capacitor. The first end of the twelfth resistor is used to connect to the power supply, the second end of the twelfth resistor is electrically connected to the base of the second field effect transistor, the emitter of the second field effect transistor is grounded, the gate of the second field effect transistor is electrically connected to the first end of the eleventh resistor and the first end of the thirteenth resistor, the second end of the thirteenth resistor is grounded, the first end of the seventeenth capacitor is electrically connected to the second end of the thirteenth resistor, and the connection point between the second end of the seventeenth capacitor and the second end of the eleventh resistor is the control end of the activation module, and the control end of the activation module is electrically connected to the output end of the charge and discharge interface.

[0022] In some embodiments, the device further includes: a voltage control circuit, the voltage control circuit including a third chip and a fourth chip, wherein a connection point between pins 3 and 5 of the fourth chip is electrically connected to pin 16 of the third chip; pin 4 of the fourth chip is electrically connected to pin 10 of the second chip; and pin 6 of the fourth chip is electrically connected to pin 11 of the second chip;

[0023] The fourth chip is used to determine whether a device is inserted into the charging and discharging interface. If a device is inserted, it sends a corresponding voltage level to the second chip.

[0024] In some embodiments, the fourth chip is also used to determine whether the charging and discharging is in a single-port state or a dual-port state. When in the single-port state, the Type C port or the USB port has a fast charging function; when in the dual-port state, the Type C port and the USB port have a standard charging function.

[0025] In some embodiments, the battery pack shutdown protection circuit includes a seventh field effect transistor, a sixty-fifth resistor and a sixty-ninth resistor, the base of the seventh field effect transistor is electrically connected to pin 14 of the fifth chip through the sixty-fifth resistor, the emitter of the seventh field effect transistor and the first end of the sixty-ninth resistor are grounded, and the connection point between the gate of the seventh field effect transistor and the second end of the sixty-ninth resistor is electrically connected to pin 2 of the second chip.

[0026] In some embodiments, the device further comprises: a Bluetooth power supply module, the Bluetooth power supply module comprising an amplifier and a Bluetooth module, the input end of the amplifier being configured to receive a battery voltage, and the output end of the amplifier being electrically connected to the Bluetooth module;

[0027] The Bluetooth power supply module is used to locate the device position.

[0028] In some embodiments, the device further includes: an illumination and sampling circuit, the illumination and sampling circuit including a seventh chip, wherein pin 6 of the seventh chip is electrically connected to pin 27 of the second chip;

[0029] The lighting and sampling circuit is used to detect whether there is a load.

[0030] In a second aspect, an embodiment of the present disclosure provides an electronic device, comprising the processing device of the battery pack provided in the first aspect.

[0031] The battery pack processing device and electronic device provided by the present disclosure include a charge and discharge management circuit comprising a first chip and a charge and discharge interface, the first chip and the charge and discharge interface being electrically connected; a logic control circuit comprising a second chip; pin 11 of the first chip being electrically connected to pin 24 of the second chip; and pin 12 of the first chip being electrically connected to pin 23 of the second chip; a battery pack protection circuit comprising a fifth chip, a lithium battery protection circuit, and a battery pack shutdown protection circuit; the positive electrode of the battery pack being electrically connected to pin 1 of the fifth chip, and the negative electrode of the battery pack being electrically connected to pins 11, CO, and 9 of the fifth chip via the lithium battery protection circuit; a first signal output terminal of the battery pack communication circuit being electrically connected to pin 13 of the second chip; and a second signal output terminal of the battery pack communication circuit being electrically connected to pin 13 of the second chip; the battery pack communication circuit being configured to send a control signal to the second chip via the first and second signal output terminals; and the second chip being configured to determine whether the battery packs are connected in parallel or in series based on the control signal. This allows for the battery packs to be connected in series or in parallel, thereby improving the operating efficiency of the battery pack. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present disclosure and should not be regarded as limiting the scope of protection of the present disclosure. Similar components are numbered similarly in each of the drawings.

[0033] FIG1 shows a schematic structural diagram of a battery pack processing device provided by an embodiment of the present disclosure;

[0034] FIG2A shows a partial structural diagram of a charge and discharge management circuit provided by an embodiment of the present disclosure;

[0035] FIG2B shows another partial structural diagram of the charge and discharge management circuit provided by an embodiment of the present disclosure;

[0036] FIG3 shows a schematic structural diagram of a logic control circuit provided by an embodiment of the present disclosure;

[0037] FIG4 shows a schematic structural diagram of a battery pack protection circuit provided by an embodiment of the present disclosure;

[0038] FIG5 shows a schematic structural diagram of a voltage control circuit provided by an embodiment of the present disclosure;

[0039] FIG6 shows a schematic structural diagram of a battery pack communication circuit provided by an embodiment of the present disclosure;

[0040] FIG7 shows another structural diagram of a battery pack communication circuit provided by an embodiment of the present disclosure;

[0041] FIG8 shows a schematic structural diagram of a Bluetooth power supply circuit provided by an embodiment of the present disclosure;

[0042] FIG9 shows a schematic structural diagram of an illumination and sampling circuit provided by an embodiment of the present disclosure.

[0043] Explanation of the main component symbols: 1-battery pack processing device; 10-charge and discharge management circuit; 101-charge and discharge interface; 20-logic control circuit; 30-battery pack protection circuit; 301-lithium battery protection circuit; 302-battery pack shutdown protection circuit; 102-activation module; 40-voltage control circuit; 50-battery pack communication circuit; 60-Bluetooth power supply module; 70-lighting and sampling circuit. DETAILED DESCRIPTION

[0044] The technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments.

[0045] The components of the embodiments of the present disclosure generally described and illustrated in the figures herein may be arranged and designed in a variety of different configurations. Therefore, the following detailed description of the embodiments of the present disclosure provided in the figures is not intended to limit the scope of the claimed disclosure, but rather merely represents selected embodiments of the present disclosure. All other embodiments derived by those skilled in the art based on the embodiments of the present disclosure without inventive effort are intended to fall within the scope of protection of the present disclosure.

[0046] Hereinafter, the terms "including", "having" and their cognates, which may be used in various embodiments of the present disclosure, are intended only to indicate specific features, numbers, steps, operations, elements, components or combinations of the foregoing items, and should not be understood as first excluding the existence of one or more other features, numbers, steps, operations, elements, components or combinations of the foregoing items or the possibility of adding one or more features, numbers, steps, operations, elements, components or combinations of the foregoing items.

[0047] Furthermore, the terms “first,” “second,” “third,” etc., are merely used for distinguishing descriptions and are not to be understood as indicating or implying relative importance.

[0048] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art to which the various embodiments of the present disclosure belong. The terms (such as those defined in generally used dictionaries) will be interpreted as having the same meaning as in the context of the relevant technical field and will not be interpreted as having an idealized meaning or an overly formal meaning unless clearly defined in the various embodiments of the present disclosure.

[0049] Example 1

[0050] An embodiment of the present disclosure provides a battery pack processing device 1, which will be described below with reference to Figures 1 to 9.

[0051] 1 to 9 , a battery pack processing device 1 includes a charge and discharge management circuit 10 , a logic control circuit 20 , a battery pack protection circuit 30 , and a battery pack communication circuit 50 .

[0052] The charge and discharge management circuit 10 includes a first chip U1 and a charge and discharge interface 101 , and the first chip U1 and the charge and discharge interface 101 are electrically connected.

[0053] The logic control circuit 20 includes a second chip U2; pin 11 of the first chip U1 is electrically connected to pin 24 of the second chip U2; and pin 12 of the first chip U1 is electrically connected to pin 23 of the second chip U2. Pin 11 of the first chip U1 is the SDA pin. Pin 12 of the first chip U1 is the SCK pin. Pin 23 of the second chip U2 is the PT21 / AIN9 pin. Pin 24 of the second chip U2 is the PT20 / AIN8 pin.

[0054] The battery pack protection circuit 30 includes a fifth chip U5, a lithium battery protection circuit 301, and a battery pack shutdown protection circuit 302. The positive electrode of the battery pack BAT1 is electrically connected to pin 1 of the fifth chip U5, and the negative electrode of the battery pack BAT1 is electrically connected to pins 11, CO, and 9 of the fifth chip U5 through the lithium battery protection circuit. Pin 1 of the fifth chip U5 is the VDD pin, pin 11 of the fifth chip U5 is the VM pin, pin CO of the fifth chip U5 is the control voltage terminal, and pin 9 of the fifth chip U5 is the DO pin.

[0055] The first signal output terminal BAT-SDA of the battery pack communication circuit 50 is electrically connected to pin 13 of the second chip U2; the second signal output terminal BAT-SCL of the battery pack communication circuit 50 is electrically connected to pin 14 of the second chip U2. Pin 13 of the second chip U2 is a PT36 / AIN6 / RX / DMC pin, and pin 14 of the second chip U2 is a PT35 / AIN5 / TX / DPC pin.

[0056] The battery pack communication circuit 50 is configured to send a control signal to the second chip U2 via the first signal output terminal and the second signal output terminal;

[0057] The second chip U2 is used to determine whether the battery packs are connected in parallel or in series according to the control signal.

[0058] The charging and discharging interface 101 includes a USB interface and a Type-C port. The Type-C port and the first chip U1 form a battery charging and discharging DC-DC converter (DCDC). The Type-C port is a standard Type-C port that can be charged and discharged.

[0059] The first chip U1 acquires the battery charge and voltage. Pins 11 and 12 of the first chip U1 are electrically connected to pins 23 and 24 of the second chip U2. Pins 11 and 12 of the first chip U1 are the SDA and SCK pins, respectively. Pins 23 and 24 of the second chip U2 are the PT21 / AIN9 and PT20 / AIN8 pins, respectively.

[0060] The second chip U2 is used to obtain voltage and current from the first chip U1, perform charge and discharge logic management, and control charge and discharge. The second chip U2 obtains the voltage and current of the battery and determines the charge and discharge power.

[0061] 2A and 2B , align the cutoff point A-1 of FIG. 2A with the cutoff point A-2 of FIG. 2B , align the cutoff point B-1 of FIG. 2A with the cutoff point B-2 of FIG. 2B , and align the cutoff point C-1 of FIG. 2A with the cutoff point C-2 of FIG. 2B to obtain a schematic diagram of the overall structure of the charge and discharge management circuit.

[0062] The charge and discharge interface 101 includes an activation module 102, which includes a twelfth resistor R12, a second field-effect transistor Q2, an eleventh resistor R11, a thirteenth resistor R13 and a seventeenth capacitor C17. The first end of the twelfth resistor R12 is used to be connected to the power supply MCU-VCC, the second end of the twelfth resistor R12 is electrically connected to the base of the second field-effect transistor Q2, the emitter of the second field-effect transistor Q2 is grounded, the gate of the second field-effect transistor Q2 is electrically connected to the first end of the eleventh resistor R11 and the first end of the thirteenth resistor R13, the second end of the thirteenth resistor R13 is grounded, the first end of the seventeenth capacitor C17 is electrically connected to the second end of the thirteenth resistor R13, and the connection point between the second end of the seventeenth capacitor C17 and the second end of the eleventh resistor R11 is the control end of the activation module 102. The control end of the activation module 102 is electrically connected to the output end of the charge and discharge interface 101.

[0063] In this embodiment, for devices with non-standard Type-C interfaces, which only have vbus and gnd, the second chip U2 is activated by the activation module 102 to realize the insertion identification of non-standard devices. In the charge and discharge management circuit formed as a whole by Figures 2A and 2B, QP1, QP2, QP3, and QP4 are power tubes for forming boost and buck. In Figure 2A, VBAT_O represents the battery voltage. When the battery voltage VBAT-O enters the charge and discharge management circuit 10, for example, when it is 9V, 15V, or 20V, the QP1 and QP4 power tubes are turned on and are in a buck state. QP1 passes through a 15uH inductor from SW2 and enters QP4 through SW1, forming a buck state. It reaches the Type-C interface from QP2, forming a buck state. LD1 / HD1 is the driving voltage provided by the first chip U1, which is high or low. High level conducts, and low level does not conduct. In FIG2B , LED1 - LED4 are power indicators, for example, indicating 25%, 50%, 75%, and 100% by the number of lights on. TVS1 - TVS4 form a surge protection circuit to prevent ESD surges.

[0064] Referring to Figure 3 , the logic control circuit 20 includes a second chip U2 and a first amplifier AU1. The second chip U2 is also connected to other chips. Pin 2 of the first amplifier AU1 is connected to the V-VBAT terminal via a third diode D3, and pin 3 of the first amplifier AU1 is connected to the MCU_VCC terminal, implementing MCU logic control. Pin 1 of the first amplifier AU1 is the GND pin, pin 2 of the first amplifier AU1 is the VIN pin, and pin 3 of the first amplifier AU1 is the OUT pin.

[0065] Referring to Figure 4 , the battery pack protection circuit 30 includes a lithium battery protection circuit 301 and a battery pack shutdown protection circuit 302. The battery pack shutdown protection circuit 302 includes a seventh field-effect transistor (FET) Q7, a sixty-fifth resistor (R65), and a sixty-ninth resistor (R69). The base of the seventh FET Q7 is electrically connected to pin 14 of the fifth chip U5 via the sixty-fifth resistor (R65). The emitter of the seventh FET Q7 and the first end of the sixty-ninth resistor (R69) are grounded. The connection point between the gate of the seventh FET Q7 and the second end of the sixty-ninth resistor (R69) is electrically connected to pin 2 of the second chip. Pin 14 of the fifth chip U5 is the RCOT pin. Pin 2 of the second chip is the PT30 / AIN0 / NTC / VREF pin.

[0066] The battery pack protection circuit 30 protects the battery, for example, protecting the battery from overvoltage, overcharge, etc.

[0067] The fifth chip U5 controls the output voltage of the Type C port and the USB port. Specifically, it controls the voltage based on the communication protocol and controls the single-port state (Type C port or USB port) or the dual-port state (Type C port and USB port).

[0068] Referring to FIG5 , the voltage control circuit 40 includes a third chip U3 and a fourth chip U4. The connection point between pins 3 and 5 of the fourth chip U4 is electrically connected to pin 16 of the third chip U3; pin 4 (LINKA1 signal) of the fourth chip U4 is electrically connected to pin 10 (LINKA_1 signal) of the second chip U2; and pin 6 (LINKB signal) of the fourth chip U4 is electrically connected to pin 11 (LINKB_1 signal) of the second chip U2. Pin 11 of the second chip U2 is a PT16 pin. Pin 16 of the third chip U3 is an FB pin. Pins 3 and 5 of the fourth chip U4 are the CMPI / SDA pin and the FB pin, respectively. Pin 4 of the fourth chip U4 is an SCL pin.

[0069] The fourth chip U4 is used to determine whether a device is inserted into the charge and discharge interface 101. If a device is inserted, it sends a corresponding voltage level to the second chip U2.

[0070] In some embodiments, the fourth chip U4 is also used to determine whether the charging and discharging is in a single-port state or a dual-port state. When in the single-port state, the Type C port or the USB port has a fast charging function; when in the dual-port state, the Type C port and the USB port have a standard charging function.

[0071] In this embodiment, the Type C port is used to charge the device or the battery pack, and is a chargeable and dischargeable interface.

[0072] The third chip U3 is a step-down IC, which is responsible for outputting power to the Type C port and the USB port. The Type C port outputs power to the mobile phone or tablet for external charging, and steps down the battery voltage before outputting it to the outside.

[0073] Referring to FIG. 6 , the battery pack communication circuit 50 includes a switch module, which includes a twelfth field-effect transistor Q12 and a thirteenth field-effect transistor Q13. The connection point between the source of the twelfth field-effect transistor Q12 and the source of the thirteenth field-effect transistor Q13 is electrically connected to pin 15 of the second chip U2. Pin 15 of the second chip U2 is the PT34 / AIN4 / RX / DMD / CC2B pin.

[0074] The second chip U2 is used to control the switching module to be turned on or off when it is determined that the battery packs are connected in parallel or in series.

[0075] As shown in Figure 6, there are four signal terminals: VBAT_OUT, BAT-SDA, BAT-SCL, and VBAT_GND. Information from the BAT-SDA and BAT-SCL terminals determines whether the battery packs are connected in parallel or in series. For example, Figures 2A and 2B form an overall charge-discharge management circuit, and in combination with Figures 3 to 6, they form an overall circuit. Figures 2A and 2B form an overall charge-discharge management circuit, and in combination with Figures 3 to 5 and 7 to 9, they form an overall circuit. Whether the battery packs are connected in parallel or in series is determined by the input signals from the BAT-SDA and BAT-SCL terminals among the VBAT_OUT, BAT-SDA, BAT-SCL, and VBAT_GND signal terminals. For example, if a battery has a capacity of 30,000 mAh, then if two are connected in parallel, the total current is 60,000 mAh.

[0076] In Figure 6, when the device is normally inserted into the four signal terminals VBAT_OUT, BAT-SDA, BAT-SCL, and VBAT_GND, the battery packs are connected in parallel. When the device is inserted into the four signal terminals VBAT_OUT, BAT-SDA, BAT-SCL, and VBAT_GND in reverse, the battery packs are connected in series. For example, when the SDA and SCL signals are 01, they are connected in parallel, and when the SDA and SCL signals are 01, they are connected in series. The SDA and SCL signals are given to the second chip U2. When the second chip U2 does not recognize the SDA and SCL signals, the switch module including the twelfth field-effect transistor Q12 and the thirteenth field-effect transistor Q13 is non-conductive. Only when the SDA and SCL signals are recognized, the twelfth field-effect transistor Q12 and the thirteenth field-effect transistor Q13 are turned on. The conduction of the twelfth field-effect transistor Q12 and the thirteenth field-effect transistor Q13 is controlled by pin 15 (PT34 / AIN4 / RX / DMD / CC2B pin) of the second chip U2. The SDA and SCL signals default to 00. By default, the twelfth and thirteenth field-effect transistors Q12 and Q13 are off. When the device is connected in the forward direction, the battery packs are connected in parallel. When the device is connected in the reverse direction, the battery packs are connected in series. When the battery packs are connected in series or in parallel, the second chip U2 outputs current and voltage normally, and the twelfth and thirteenth field-effect transistors Q12 and Q13 of the switch module are conducting.

[0077] For example, if the Type C port can only discharge for 3 hours, then after parallel connection, it can discharge for 6 hours, and the capacity becomes larger. If the voltage of the Type C port is only 10-20V and the battery voltage is 9-12.6V, then after series connection, the battery voltage is 23.2V, and the battery voltage is increased, which can drive more devices. Furthermore, after determining whether to connect in series or in parallel, when charging the battery pack, the low-voltage battery can be controlled to charge first. The second chip U2 can determine the host and slave according to the power, or determine the host or slave according to the usage status, and then the host's second chip U2 will control it.

[0078] Referring to FIG7 , the battery pack communication circuit 50 includes a sixth chip U6, wherein pin 8 of the sixth chip U6 is electrically connected to pin 16 of the second chip U2; pin 1 of the sixth chip U6 is electrically connected to pin 15 of the second chip U2. The second chip U2 is configured to send an enable signal to pin 1 of the sixth chip U6 to activate the sixth chip U6 upon determining that the battery packs are connected in parallel or in series; and the sixth chip U6 is configured to send the read output current value of the sixth chip U6 to pin 15 of the second chip U2. Pin 8 of the sixth chip U6 is the IMON pin, and pin 16 of the second chip U2 is the PT33 / AIN3 / TX / DPD / CC1B pin. Pin 1 of the sixth chip U6 is the EN pin (enable terminal), and pin 15 of the second chip U2 is the PT34 / AIN4 / RX / DMD / CC2B pin.

[0079] In Figure 7 , pin 1 of the sixth chip U6 is the enable terminal (BAT-H1 signal), which activates the sixth chip U6 and turns it on. Pin 8 (IMON pin) of the sixth chip U6 reads its own output current value BAT_I. In Figure 7 , there are BAT_SDA and BAT_SCL signal terminals. The second chip U2 determines whether the battery pack is connected in parallel or in series based on the BAT_SDA and BAT_SCL signal terminals. After the BAT_SDA and BAT_SCL signal terminals communicate with the second chip U2, the second chip U2 sends the BAT_H1 signal to the sixth chip U6 to control the activation of the sixth chip U6.

[0080] Referring to Figure 8 , a Bluetooth power supply module 60 includes an amplifier AU2 and a Bluetooth module BT1. The input of the amplifier AU2 is used to receive the battery voltage VBAT_O, and the output of the amplifier AU2 is electrically connected to the Bluetooth module BT1. Pin 1 of the amplifier AU2 is a GND pin, pin 2 of the amplifier AU2 is an input (VIN pin), and pin 3 of the amplifier AU2 is an output (OUT pin).

[0081] The Bluetooth power supply module 60 is used to locate the device, which can be a mobile phone or tablet waiting to be charged.

[0082] In this embodiment, the Bluetooth power supply module 60 can sense Bluetooth devices within a certain sensing range and locate the relevant devices.

[0083] Referring to FIG9 , as shown in FIG9 , the lighting and sampling circuit 70 includes a seventh chip U7 , wherein pin 6 of the seventh chip U7 is electrically connected to pin 27 of the second chip U2 . Pin 6 of the seventh chip U7 is an OUT pin, and pin 27 of the second chip U2 is a PT24 / AIN12 / DMB pin.

[0084] The lighting and sampling circuit 70 is used to detect whether there is a load.

[0085] In this embodiment, the lighting and sampling circuit 70 can be used as a flashlight for illumination. Pin 6 (OUT pin) of the seventh chip U7 of the lighting and sampling circuit 70 is electrically connected to pin 27 (PT24 / AIN12 / DMB pin) of the second chip U2. The circuit detects the current Qi-I at pin 6 of the seventh chip U7 to determine whether a load is present. Based on whether a load is present, the circuit determines whether the indicator light should be illuminated.

[0086] In this embodiment, the first chip U1 , the second chip U2 , the third chip U3 , the fourth chip U4 , the fifth chip U5 , the sixth chip U6 , and the seventh chip U7 are chips with corresponding pins and can implement corresponding functions.

[0087] The battery pack processing device 1 provided by the present disclosure above, the charge and discharge management circuit 10 includes a first chip and a charge and discharge interface 101, the first chip and the charge and discharge interface 101 are electrically connected; the logic control circuit 20 includes a second chip; pin 11 of the first chip is electrically connected to pin 24 of the second chip; pin 12 of the first chip is electrically connected to pin 23 of the second chip; the battery pack protection circuit 30 includes a fifth chip, a lithium battery protection circuit 301, and a battery pack shutdown protection circuit 302, the positive pole of the battery pack is electrically connected to pin 1 of the fifth chip, and the negative pole of the battery pack is electrically connected to pin 11, pin CO, and pin 9 of the fifth chip through the lithium battery protection circuit; the first signal output end of the battery pack communication circuit 50 is electrically connected to pin 13 of the second chip; the second signal output end of the battery pack communication circuit 50 is electrically connected to pin 13 of the second chip; the battery pack communication circuit 50 is used to send a control signal to the second chip through the first signal output end and the second signal output end; the second chip is used to determine whether the battery pack is connected in parallel or in series according to the control signal. The battery packs can be connected in series or in parallel to improve the working efficiency of the battery packs.

[0088] Example 2

[0089] In addition, an embodiment of the present disclosure provides an electronic device, including the processing device of the battery pack provided in embodiment 1.

[0090] It should be noted that the electronic device provided in this embodiment includes the battery pack processing device 1 provided in the embodiment, which can implement the processing process of the battery pack processing device 1 in embodiment 1 and achieve the corresponding effect of the battery pack processing device 1 in embodiment 1. To avoid repetition, it will not be described here.

[0091] The embodiments of the present disclosure are described above in conjunction with the accompanying drawings, but the present disclosure is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present disclosure, ordinary technicians in this field can also make many forms without departing from the scope of protection of the purpose of the present disclosure and the claims, all of which are protected by the present disclosure. Industrial Applicability

[0092] The present disclosure provides a battery pack processing device and electronic device, belonging to the field of battery technology. In the device, a first chip of a charge and discharge management circuit is electrically connected to a charge and discharge interface; pin 11 of the first chip is electrically connected to pin 24 of a second chip of a logic control circuit; pin 12 of the first chip is electrically connected to pin 23 of the second chip; the positive electrode of the battery pack is electrically connected to pin 1 of a fifth chip, and the negative electrode of the battery pack is electrically connected to pins 11, CO, and 9 of the fifth chip via a lithium battery protection circuit; a first signal output terminal of a battery pack communication circuit is electrically connected to pin 13 of the second chip; a second signal output terminal of the battery pack communication circuit is electrically connected to pin 14 of the second chip; the battery pack communication circuit sends a control signal to the second chip; and the second chip is configured to determine whether the battery packs are connected in parallel or in series based on the control signal. This allows the battery packs to be connected in series or in parallel, thereby improving the operating efficiency of the battery pack.

[0093] Furthermore, it is understood that the processing device and electronic devices of the battery pack of the present disclosure are reproducible and can be used in a variety of industrial applications. For example, the processing device and electronic devices of the battery pack of the present disclosure can be used in the field of battery technology.

Claims

1. A battery pack processing device, characterized in that: include: Charge and discharge management circuit, logic control circuit, battery pack protection circuit and battery pack communication circuit; The charge and discharge management circuit includes a first chip and a charge and discharge interface, and the first chip is electrically connected to the charge and discharge interface; The logic control circuit includes a second chip; Pin 11 of the first chip is electrically connected to pin 24 of the second chip; pin 12 of the first chip is electrically connected to pin 23 of the second chip; The battery pack protection circuit includes a fifth chip, a lithium battery protection circuit, and a battery pack shutdown protection circuit. The positive electrode of the battery pack is electrically connected to pin 1 of the fifth chip, and the negative electrode of the battery pack is electrically connected to pins 11, CO, and 9 of the fifth chip through the lithium battery protection circuit. The first signal output terminal of the battery pack communication circuit is electrically connected to the 13th pin of the second chip; the second signal output terminal of the battery pack communication circuit is electrically connected to the 14th pin of the second chip; The battery pack communication circuit is used to send a control signal to the second chip through the first signal output terminal and the second signal output terminal; The second chip is used to determine whether the battery packs are connected in parallel or in series according to the control signal.

2. The battery pack processing device according to claim 1, characterized in that: The battery pack communication circuit includes a switch module, the switch module includes a twelfth field effect tube and a thirteenth field effect tube, and the connection point of the source of the twelfth field effect tube and the source of the thirteenth field effect tube is electrically connected to the 15th pin of the second chip; The second chip is used to control the switching module to be turned on or off when it is determined that the battery packs are connected in parallel or in series.

3. The battery pack processing device according to claim 1, characterized in that: The battery pack communication circuit includes a sixth chip, wherein the 8th pin of the sixth chip is electrically connected to the 16th pin of the second chip; the 1st pin of the sixth chip is electrically connected to the 15th pin of the second chip; The second chip is used to send an enable signal to pin 1 of the sixth chip to start the sixth chip when it is determined that the battery packs are connected in parallel or in series; The sixth chip is used to send the read output current value of the sixth chip to pin 15 of the second chip.

4. The battery pack processing device according to claim 1, characterized in that: The charge and discharge interface includes an activation module, which includes a twelfth resistor, a second field effect transistor, an eleventh resistor, a thirteenth resistor and a seventeenth capacitor. The first end of the twelfth resistor is used to connect to the power supply, the second end of the twelfth resistor is electrically connected to the base of the second field effect transistor, the emitter of the second field effect transistor is grounded, the gate of the second field effect transistor is electrically connected to the first end of the eleventh resistor and the first end of the thirteenth resistor, the second end of the thirteenth resistor is grounded, the first end of the seventeenth capacitor is electrically connected to the second end of the thirteenth resistor, the connection point between the second end of the seventeenth capacitor and the second end of the eleventh resistor is the control end of the activation module, and the control end of the activation module is electrically connected to the output end of the charge and discharge interface.

5. The battery pack processing device according to claim 4, characterized in that: Also includes: A voltage control circuit, the voltage control circuit comprising a third chip and a fourth chip, wherein a connection point between pins 3 and 5 of the fourth chip is electrically connected to pin 16 of the third chip; pin 4 of the fourth chip is electrically connected to pin 10 of the second chip; and pin 6 of the fourth chip is electrically connected to pin 11 of the second chip; The fourth chip is used to determine whether a device is inserted into the charging and discharging interface, and if a device is inserted, send a corresponding level to the second chip.

6. The battery pack processing device according to claim 5, characterized in that: The fourth chip is also used to determine whether the charging and discharging is in a single-port state or a dual-port state. When in the single-port state, the Type C port or the USB port has a fast charging function; when in the dual-port state, the Type C port and the USB port have a standard charging function.

7. The battery pack processing device according to claim 1, characterized in that: The battery pack shutdown protection circuit includes a seventh field effect transistor, a sixty-fifth resistor and a sixty-ninth resistor. The base of the seventh field effect transistor is electrically connected to pin 14 of the fifth chip through the sixty-fifth resistor, the emitter of the seventh field effect transistor and the first end of the sixty-ninth resistor are grounded, and the connection point between the gate of the seventh field effect transistor and the second end of the sixty-ninth resistor is electrically connected to pin 2 of the second chip.

8. The battery pack processing device according to claim 1, characterized in that: Also includes: A Bluetooth power supply module, the Bluetooth power supply module comprises an amplifier and a Bluetooth module, the input end of the amplifier is used to receive a battery voltage, and the output end of the amplifier is electrically connected to the Bluetooth module; The Bluetooth power supply module is used to locate the device.

9. The battery pack processing device according to claim 8, characterized in that: Also includes: An illumination and sampling circuit, the illumination and sampling circuit comprising a seventh chip, wherein pin 6 of the seventh chip is electrically connected to pin 27 of the second chip; The lighting and sampling circuit is used to detect whether there is a load.

10. An electronic device, characterized in that: A processing device comprising the battery pack according to any one of claims 1 to 9.

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