Manufacturing method for storage device, and storage device

Abstract

Disclosed in the present invention are a manufacturing method for a storage device, and a storage device. The manufacturing method comprises: providing a semiconductor substrate comprising a base and a plurality of gate structures, wherein some of the plurality of gate structures are located in a storage region, a source and a drain are respectively arranged in the base at two sides of each gate structure in a first direction, and the storage region comprises a source lead-out region; and covering the semiconductor substrate with a first interlayer dielectric layer, and forming source contact window structures in the first interlayer dielectric layer, wherein each source contact window structure extends in a second direction, and is connected to a plurality of sources in the same row in the second direction, the source contact window structures in the source lead-out region each comprise a source connection structure and a source contact structure which are stacked, and the cross-sectional area of the source contact structure is greater than that of the source connection structure. Therefore, in the present application, expansion of the cross-sectional area of the upper portions of the source contact window structures in the source lead-out region can effectively increase the process margin of structural contact, and reduce the corresponding contact resistance, thereby improving the performance of a semiconductor device.

Description

Method for manufacturing a memory device and memory device

[0001]

Cross-reference

[0002] This application claims priority to Chinese patent application No. CN202311456945.X filed on November 1, 2023, the entire contents of which are incorporated herein by reference.

Technical field

[0003] The present invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a memory device and the memory device. [Background Technology]

[0004] In the application process of integrated circuits, the performance of various devices will be affected by the spacing between each layer of material, especially memory devices, because the spacing between each layer of material affects the metal wiring of the device.

[0005] During actual operation, the researchers of this application discovered that in current semiconductor device manufacturing schemes, especially in the manufacture of memory devices, the back-end process of the gate structure formed requires high metal wiring accuracy. If alignment of the via hole and the contact hole is required, the process margin of the contact between the via hole and the contact hole will become smaller, and the contact area between the via hole and the contact hole will be reduced due to the overlay problem, thereby increasing the corresponding contact resistance and affecting the performance of the semiconductor device.

[0006] [Summary of the invention]

[0007] According to various embodiments of the present application, a method for manufacturing a memory device and a memory device are provided.

[0008] The present application provides a method for manufacturing a semiconductor device, comprising: providing a semiconductor substrate, the semiconductor substrate comprising a substrate and a plurality of gate structures, a portion of the plurality of gate structures being located in a storage region, a source and a drain being respectively arranged in the substrate on both sides of each gate structure in a first direction; wherein the storage region comprises a source lead-out region; covering the semiconductor substrate with a first interlayer dielectric layer, and forming a source contact window structure in the first interlayer dielectric layer, each of the source contact window structures extending along a second direction and connected to a plurality of the source electrodes in the same row in the second direction, wherein the source contact window structure in the source lead-out region comprises a source connection structure and a source contact structure stacked in sequence, and the cross-sectional area of ​​the source contact structure is larger than the cross-sectional area of ​​the source connection structure.

[0009] On the other hand, the present application provides a storage device comprising a substrate, multiple gate structures, a first interlayer dielectric layer and multiple source contact window structures; wherein, a portion of the multiple gate structures is located in a storage area, each of the gate structures is provided with a drain and a source on both sides in a first direction, respectively, and the storage area includes a source lead-out area; the first interlayer dielectric layer covers the substrate, the gate structures, the drain and the source; multiple source contact window structures are located in the first interlayer dielectric layer, each of the source contact window structures extends along a second direction and is connected to multiple sources in the same row in the second direction, the source contact window structure comprises a source connection structure and a source contact structure stacked in sequence, and the cross-sectional area of ​​the source contact structure is larger than the cross-sectional area of ​​the source connection structure.

[0010] The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will become apparent from the description, drawings, and claims.

Brief Description of the Drawings

[0011] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without inventive efforts. Among them:

[0012] FIG1 is a schematic flow chart of an embodiment of a method for manufacturing a memory device in the present application;

[0013] 2a-2b are schematic structural diagrams of a first direction and a second direction of an embodiment of forming a first dielectric layer and a second dielectric layer on a substrate in the present application;

[0014] 3a-3b are schematic structural diagrams of the second direction and the first direction of an embodiment of providing a second groove in the substrate according to the present application;

[0015] 4a-4b are schematic diagrams of the second direction and the first direction of an embodiment of forming a shallow trench isolation structure in the present application;

[0016] 5a-5b are schematic structural diagrams of the second direction and the first direction of an embodiment of forming a second well region in the present application;

[0017] 6a-6b are schematic structural diagrams of a second direction and a first direction of an embodiment of forming a hard mask layer in the present application;

[0018] 7a-7b are schematic structural diagrams of the second direction and the first direction of an embodiment of a first groove provided in the present application;

[0019] 8a-8b are schematic diagrams of the structure in the second direction and the first direction of an embodiment of filling the first gate material in this application;

[0020] 9a-9b are schematic diagrams of the second direction and first direction structures of an embodiment of forming a contact window in the present application;

[0021] 10a-10b are schematic diagrams of the structure in the second direction and the first direction of an embodiment of filling the second gate material in this application;

[0022] 11a-11b are schematic diagrams of the structure in the second direction and the first direction of an embodiment of forming a half floating gate in the present application;

[0023] 12a-12b are schematic structural diagrams of the second direction and the first direction of an embodiment of forming a first isolation portion in the present application;

[0024] 13a-13b are schematic structural diagrams of the second direction and the first direction of another embodiment of the present application in which the shallow trench isolation structure is further lowered to form a first isolation portion;

[0025] 14a-14b are schematic structural diagrams of the second direction and the first direction of an embodiment of forming an inter-gate dielectric layer in the present application;

[0026] 15a-15b are schematic diagrams of the structure in the second direction and the first direction of an embodiment of covering the third gate material (first gate layer) in the present application;

[0027] 16a-16b are schematic diagrams of structures in the second direction and the first direction of an embodiment of forming a control gate in the present application;

[0028] 17a-17b are schematic diagrams of the second direction and the first direction of the structure of an embodiment of forming the second insulating layer in the present application;

[0029] 18a-18b are schematic diagrams of the structure in the second direction and the first direction of an embodiment of removing the hard mask layer in the present application;

[0030] 19a-19b are schematic diagrams of the structure in the second direction and the first direction of an embodiment of forming an isolation retaining wall in the present application;

[0031] FIG20 is a top view of an embodiment of forming a first interlayer dielectric layer on a memory device in the present application;

[0032] 21a-21b are schematic diagrams of the structure in the first direction and the Y3 direction of an embodiment of forming a first interlayer dielectric layer in the present application;

[0033] FIG22 is a top view of an embodiment of forming a second interlayer dielectric layer on a memory device;

[0034] 23a, 23c and 23d are schematic diagrams of the structures in the Y1 direction, Y2 direction and Y3 direction of an embodiment of forming the second interlayer dielectric layer in the present application;

[0035] FIG24 is a schematic top view of an embodiment of forming a first metal layer on a memory device;

[0036] 25a, 25b and 25c are schematic diagrams of structures in the Y1 direction, Y2 direction and Y3 direction of an embodiment of forming a first metal layer in the present application;

[0037] 26 is a top view of an embodiment of forming a third interlayer dielectric layer and a second metal layer on a memory device;

[0038] 27a, 27b and 27c are schematic diagrams of the structures in the Y1 direction, Y2 direction and Y3 direction of an embodiment of forming a third interlayer dielectric layer and a second metal layer in the present application.

[0039] In the accompanying drawings, a substrate 100, a second groove 101, a shallow trench isolation structure 102, a first groove 103, a first groove section 1031, a second groove section 1032, a vacant area 1033, a first insulating layer 104, a gate insulating layer 1041, a first gate material 105, a first gate 1051, a second gate material 106, a second gate 1061, a first well region 110, a second well region 120, a first dielectric layer 200, a metal silicide layer 210, a second dielectric layer 300, a hard mask layer 400, a filling layer 410, a protective layer 420, an inter-gate dielectric layer 500, and a third gate material 600 (the first dielectric layer 200). a gate layer), a control gate 610, an idle area 620, a second insulating layer 700, an isolation barrier 800, a first interlayer dielectric layer ILD1, a source contact window structure CT, a source connection structure CT1, a source contact structure CT2, a second interlayer dielectric layer ILD2, a first lead-out structure v1, a source lead-out structure v11, a drain lead-out structure v12, a first control gate lead-out structure v13, a first metal layer m1, a source line m11, a bit line m12, a control gate contact m13, a third interlayer dielectric layer ILD3, a second lead-out structure v2, a second control gate lead-out structure v21, a second metal layer m2, and a word line m21. [Specific implementation method]

[0040] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0041] In the current memory device manufacturing process, especially the manufacturing of memory devices, in the manufacturing of the buried gate structure formed by the semi-floating gate, the metal wiring accuracy is required to be high in its back-end process. If the through hole (via hole) and the contact hole (contact) need to be aligned, the process margin of the contact between the through hole (via hole) and the contact hole (contact) will become smaller. Due to the overlay problem, the contact area between the through hole and the contact hole will be reduced, and the corresponding contact resistance will increase, affecting the performance of the semiconductor device.

[0042] Therefore, a method for manufacturing a memory device is provided, in which the upper cross-sectional area of ​​the source contact window structure corresponding to the source electrode in the source lead-out region is enlarged, which can effectively increase the process margin of the contact between the via hole and the trench contact, reduce the corresponding contact resistance, and improve the performance of the semiconductor device.

[0043] Please refer to FIG. 1 , which is a flow chart of an embodiment of a method for manufacturing a memory device in the present application.

[0044] As shown in FIG1 , the method for manufacturing a memory device of the present application includes:

[0045] S11. Provide a semiconductor substrate, the semiconductor substrate including a substrate and multiple gate structures, a portion of the multiple gate structures is located in a storage area, and each gate structure is respectively provided with a source and a drain on the substrate on both sides in a first direction, wherein the storage area includes a source lead-out area.

[0046] The substrate may be any suitable base material known in the art, for example, at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbon (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI).

[0047] In some embodiments, the operation flow of step S11 is as follows:

[0048] Providing a semiconductor substrate includes: providing a substrate, and forming a hard mask layer on the substrate;

[0049] In some embodiments, the operation of forming a hard mask layer on a substrate is as follows:

[0050] 2a and 2b, which are schematic structural diagrams of the second direction and the first direction of an embodiment of forming a first dielectric layer and a second dielectric layer on a substrate in the present application.

[0051] The second direction is the wordline extension direction (WL), which is also the X direction, and the X direction is the row direction; the first direction is the bitline extension direction (BL), which is also the Y direction, and the Y direction is the column direction; that is, the first direction and the second direction are perpendicular to each other in the same horizontal plane.

[0052] As shown in FIG2a , a substrate 100 is provided in the second direction, and a first dielectric layer 200 and a second dielectric layer 300 are sequentially formed on the substrate 100 ; as shown in FIG2b , a first dielectric layer 200 and a second dielectric layer 300 are sequentially formed on the substrate 100 in the first direction.

[0053] In some embodiments, the first dielectric layer 200 may be an oxide layer, such as a silicon oxide layer, and the second dielectric layer 300 may be a nitride layer, such as a silicon nitride layer.

[0054] In some embodiments, a shallow trench isolation structure may be further provided in the substrate, as described below.

[0055] 3a and 3b , which are schematic structural diagrams of the second direction and the first direction of an embodiment of providing a second groove in the substrate in the present application.

[0056] As shown in Figure 3a, in the second direction, a second groove 101 is opened from the second dielectric layer 300 to the substrate 100. As shown in Figure 3b, in the first direction, the structure of Figure 2b is maintained.

[0057] In some embodiments, the plurality of second grooves 101 are sequentially spaced apart along the second direction (X direction), and the bottom of the second groove is higher than the bottom of the substrate 100 , that is, the second groove 101 extends to a portion of the substrate 100 .

[0058] Then, an isolation material is filled in the second groove to form a shallow trench isolation structure; and ion implantation is performed to form a first well region in the substrate.

[0059] 4a and 4b, which are schematic structural diagrams of the second direction and the first direction of an embodiment of forming a shallow trench isolation structure in the present application.

[0060] As shown in Figure 4a, in the second direction, an isolation material is filled in the second groove 101 to form a shallow trench isolation structure 102, and then ion implantation is performed on the substrate 100 to form a first well region 110 in the substrate 100; wherein the shallow trench isolation structure 102 penetrates into the first well region 110, and the bottom of the shallow trench isolation structure 102 is higher than the bottom of the first well region 110 and lower than the top of the first well region 110; as shown in Figure 4b, in the first direction, ion implantation is performed on the substrate 100 to form a first well region 110 in the substrate 100.

[0061] In some embodiments, the lowest point of the first well region 110 is higher than the lowest point of the substrate 100 , and the highest point of the first well region 110 is lower than the highest point of the substrate 100 , that is, the first well region 110 is located in the substrate 100 .

[0062] In some embodiments, the shallow trench isolation structure 102 is partially disposed within the substrate 100 and partially protrudes from the substrate 100 to define a plurality of active areas (AA) in the substrate. The shallow trench isolation structure 102 extends along a first direction and is spaced apart in a second direction.

[0063] After forming the shallow trench isolation structure 102, the second dielectric layer 300 is removed, exposing a portion of the shallow trench isolation structure 102. Ion implantation is performed again on the substrate 100 to form a second well region 120 on a side of the substrate 100 adjacent to the first dielectric layer 200. The doping type of the second well region 120 is different from that of the first well region 110.

[0064] 5a and 5b , which are schematic structural diagrams of the second direction and the first direction of an embodiment of forming the second well region in the present application.

[0065] As shown in Figure 5a, in the second direction, the second dielectric layer 300 is removed to expose part of the shallow trench isolation structure 102, and ion implantation is performed on the substrate 100 using the first dielectric layer 200 as a barrier layer to form a second well region 120 on the side of the substrate 100 close to the first dielectric layer 200; as shown in Figure 5b, in the first direction, the second dielectric layer 300 is removed to expose the first dielectric layer 200, and ion implantation is performed on the substrate 100 using the first dielectric layer 200 as a barrier layer to form a second well region 120 on the side of the substrate 100 close to the first dielectric layer 200, wherein the second well region 120 is above the first well region 110.

[0066] In some embodiments, the doping types of the first well region 110 and the second well region 120 are different, that is, the doping types of the first well region 110 and the second well region 120 are opposite; for example, if the first well region 110 is an N-type doped well region, then the second well region 120 is a P-type doped well region; conversely, if the first well region 110 is a P-type doped well region, then the second well region is an N-type doped well region.

[0067] Next, a filling cover layer is formed on the first dielectric layer, with the first dielectric layer and the filling cover layer serving as a hard mask layer 400. The filling cover layer fills between two adjacent shallow trench isolation structures 102 and covers the shallow trench isolation structures 102, and can be a multi-layer structure or a single-layer structure. In the case of a multi-layer structure, the filling cover layer can include a filling layer 410 and a protective layer 420. In this case, the filling layer 410 is formed on the first dielectric layer 200, wherein the filling layer 410 fills between two adjacent shallow trench isolation structures 102; and the protective layer 420 is formed on the filling layer 410 and the shallow trench isolation structures 102. Alternatively, the filling cover layer is a single-layer structure, such as a silicon nitride layer, which fills between the two shallow trench isolation structures 102 and is formed on the shallow trench isolation structures 102. In this case, the first dielectric layer 200 also serves as part of the hard mask layer 400.

[0068] 6 a and 6 b , which are schematic structural diagrams of the second direction and the first direction of forming a hard mask layer in an embodiment of the present application.

[0069] As shown in FIG6a, in the second direction, a filling layer 410 is formed on the first dielectric layer 200. The filling layer 410 fills between two adjacent shallow trench isolation structures 102, and then a protective layer 420 is formed on the filling layer 410 and the shallow trench isolation structures 102. The filling layer 410 and the protective layer 420 constitute a filling cover layer, and the first dielectric layer 200, the filling layer 410, and the protective layer 420 serve as a hard mask layer 400. As shown in FIG6b, in the first direction, a filling layer 410 is formed on the first dielectric layer 200, and then a protective layer 420 is formed on the filling layer 410.

[0070] In some embodiments, the filling layer 410 may be a polycrystalline material filling layer, such as polysilicon, and the protective layer 420 may be an ON structure composed of a nitride layer and an oxide layer, such as an ON structure protective layer composed of a silicon nitride layer and a silicon oxide layer.

[0071] Then, multiple first grooves are opened in the active area of ​​the substrate 100 from the hard mask layer 400, with some of the first grooves located in the storage area and others in the lead-out area. The first grooves in the substrate are defined as base grooves, as shown in Figures 7a and 7b.

[0072] Please refer to FIG. 7 a and FIG. 7 b , which are schematic structural diagrams of the second direction and the first direction of an embodiment of providing a first groove in the present application.

[0073] As shown in Figure 7a, in the second direction, part of the hard mask layer 400 on the shallow trench isolation structure 102 between two adjacent first grooves 103 is removed to expose part of the shallow trench isolation structure 102, and then a first groove 103 is opened in the active area between the shallow trench isolation structures 102; as shown in Figure 7b, in the first direction, a plurality of first grooves 103 are opened from the hard mask layer 400 to the active area of ​​the substrate 100 at intervals; wherein, in the second direction, the first grooves 103 are separated by the shallow trench isolation structure 102, and a plurality of first grooves 103 are arranged at intervals in the first direction.

[0074] In some embodiments, the first groove 103 sequentially penetrates the protective layer 420, the filling layer 410, the first dielectric layer 200 and the second well region 120, that is, penetrates the hard mask layer 400 and the second well region 120, that is, the bottom of the first groove 103 contacts the first well region 110, so that the first well region 110 is exposed through the first groove 103.

[0075] Then, a gate structure is formed in the substrate groove.

[0076] The storage area can be divided into a drain lead-out area and a source lead-out area.

[0077] In some embodiments, the gate structure in the storage region includes a semi-floating gate and a control gate, while the gate structure in the lead-out region includes a semi-floating gate and a lead-out line. The semi-floating gate is formed at the bottom of a substrate groove, the control gate in the storage region fills the substrate groove, and the control gate in the storage region is located within the substrate. At least a portion of the lead-out line in the lead-out region is located on the substrate 100. Because a portion of the first groove is located in the storage region and another portion is located in the lead-out region, the gate structure including the control gate is located in the storage region, and the gate structure including the lead-out line is located in the lead-out region.

[0078] Then, a gate insulating layer and a semi-floating gate are formed at the bottom of the substrate groove, a part of the semi-floating gate is in contact with the substrate, and the other part is isolated from the substrate by the gate insulating layer.

[0079] Specifically, the manufacturing process of the semi-floating gate is as follows:

[0080] Please refer to FIG. 8 a and FIG. 8 b , which are schematic structural diagrams of the second direction and the first direction of an embodiment of filling the first gate material in the present application.

[0081] As shown in Figure 8a, in the second direction, a first insulating layer 104 is formed on the inner wall of the base groove. The first insulating layer 104 can be formed on the exposed substrate by a thermal oxidation process, and the first gate material 105 is filled in the first groove 103, so that the first gate material 105 covers the first groove 103; as shown in Figure 8b, in the first direction, a first insulating layer 104 is formed on the inner wall of the base groove, and the first gate material 105 is filled in the first groove 103, so that the first gate material 105 is flush with the hard mask layer 400, that is, flush with the protective layer 420.

[0082] In some embodiments, the first gate material 105 may be a polycrystalline material, such as polysilicon. After filling the first gate material 105 , the first gate material 105 is chemically mechanically polished so that the first gate material 105 is flush with the protection layer 420 .

[0083] In some embodiments, when forming the first insulating layer 104 on the inner wall of the first groove 103 and filling the first groove 103 with the first gate material 105 , the first gate material 105 also covers the shallow trench isolation structure 102 , see FIG. 8 a .

[0084] Next, a portion of the first gate material 105 and a corresponding portion of the first insulating layer 104 in the first groove 103 are removed to form a contact window; wherein at least a portion of the first insulating layer in the first groove section is removed.

[0085] Please refer to FIG. 9 a and FIG. 9 b , which are schematic structural diagrams of the second direction and the first direction of an embodiment of forming a contact window in the present application.

[0086] As shown in Figure 9b, in the first direction, part of the first gate material 105 and the corresponding part of the first insulating layer 104 in the first groove 103 are removed, and part of the first gate material 105 and part of the first insulating layer 104 in the first groove section 1031 in the base groove are removed to form a contact window with the substrate 100; as shown in Figure 9a, in the second direction, the structure shown in Figure 8a is maintained; wherein, the removal method can be photolithography processing or etching processing.

[0087] Among them, the base groove includes a first groove section 1031 and a second groove section 1032, and the second groove section 1032 is above the first groove section 1031, that is, the first groove section 1031 is the bottom part of the first groove 103, the first groove section 1031 is used to place the semi-floating gate, and the second groove section 1032 is used to place the control gate, or place part of the lead wire.

[0088] Then, the second gate material 106 is filled in the idle area of ​​the first groove 103 , that is, the second gate material 106 is formed above the contact window; wherein the second gate material 106 in the first groove section 1031 contacts the substrate 100 through the contact window.

[0089] Please refer to FIG. 10 a and FIG. 10 b , which are schematic structural diagrams of the second direction and the first direction of an embodiment of filling the second gate material in the present application.

[0090] As shown in Figure 10a, in the second direction, the structure shown in Figure 9a is maintained; as shown in Figure 10b, in the first direction, after removing part of the first gate material 105 and the corresponding part of the first insulating layer 104 in the first groove 103, an idle area of ​​the first groove 103 is formed, and the second gate material 106 is filled in the idle area of ​​the first groove 103, that is, the second gate material 106 is formed above the contact window, and chemical mechanical polishing is performed after filling to make the surface after filling smooth; and because at least part of the first insulating layer 104 in the first groove section 1031 is removed to form a contact window, the second gate material 106 in the first groove section 1031 can contact the substrate 100 through the contact window, such as contacting the second well region 120, that is, part of the semi-floating gate is in contact with the substrate 100 through the contact window, and the other part is isolated from the substrate 100 by the first insulating layer 104.

[0091] In some embodiments, the second gate material 106 may be formed by an epitaxial or deposition process. In one embodiment, the second gate material 106 is formed by an epitaxial process so that at least the contact portion between the second gate material 106 and the substrate 100 is a single crystal material.

[0092] After filling the second gate material 106 , a first gate 1051 , a second gate 1061 and a gate insulating layer are formed, that is, a semi-floating gate is formed.

[0093] Please refer to FIG. 11 a and FIG. 11 b , which are schematic structural diagrams of the second direction and the first direction of an embodiment of forming a half-floating gate in the present application.

[0094] As shown in FIG11b, in the first direction, a portion of the first gate material 105, the second gate material 106, and the first insulating layer 104 in the first groove 103 are removed, and the first gate material 105, the second gate material 106, and the first insulating layer 104 in the first groove section 1031 are retained. The first gate material 105 in the retained first groove section 1031 serves as the first gate 1051, the second gate material 106 in the retained first groove section 1031 serves as the second gate 1061, and the first insulating layer 104 in the retained first groove section 1031 serves as the gate insulating layer 1041. The first gate 1051 and the second gate 1061 cooperate to form a semi-floating gate, wherein a portion of the semi-floating gate contacts the substrate 100 through a contact window, and the other portion is isolated from the substrate 100 by the gate insulating layer 1041. The bottom of the base groove where the first gate 1051, the second gate 1061, and the gate insulating layer 1041 remain is the first groove section 1031.

[0095] In some embodiments, when performing the step of removing a portion of the first gate material 105, the second gate material 106 and the first insulating layer 104 in the first groove 103, the portion of the first gate material 105 covering the shallow trench isolation structure 102 is also removed at the same time, thereby continuing to expose a portion of the shallow trench isolation structure 102.

[0096] As shown in FIG. 11 a , in the second direction, the portion of the first gate material 105 covering the shallow trench isolation structure 102 is removed simultaneously, so that the shallow trench isolation structure 102 continues to be exposed.

[0097] In another embodiment, the manufacturing process of the half-floating gate is as follows:

[0098] A first insulating layer 104 is formed on the inner wall of the base groove, and a sacrificial material is formed on the first insulating layer 104, so that the sacrificial material fills the first groove 103; part of the sacrificial material and the corresponding first insulating layer 104 are removed to form a contact window on the side wall of the first groove section 1031 of the base groove; the sacrificial material is removed and the gate material is filled; part of the gate material and the corresponding first insulating layer 104 in the first groove 103 are removed to form a semi-floating gate and a gate insulating layer in the first groove section 1031.

[0099] Among them, the gate material remaining in the first groove section 1031 is a semi-floating gate, and the first insulating layer remaining in the first groove section 1031 is a gate insulating layer. A part of the semi-floating gate contacts the substrate through the contact window, and the other part is isolated from the substrate by the gate insulating layer.

[0100] The sacrificial material is made of, for example, a silicon-rich composite material or other suitable dielectric materials.

[0101] Next, the height of the shallow trench isolation structure is lowered to form a first isolation portion.

[0102] Please refer to FIG. 12 a and FIG. 12 b , which are schematic structural diagrams of the second direction and the first direction of an embodiment of forming the first isolation portion in the present application.

[0103] As shown in FIG12a , in the second direction, based on FIG11a , the exposed portion of the shallow trench isolation structure 102 is removed, that is, the height of the shallow trench isolation structure 102 is lowered so that the height of the shallow trench isolation structure 102 is not higher than the height of the half-floating gate to form a first isolation portion; as shown in FIG12b , in the first direction, the structure shown in FIG11b can be maintained.

[0104] In some embodiments, when the height of the shallow trench isolation structure 102 is reduced to form the first isolation portion, the remaining shallow trench isolation structure 102 may be flush with the half-floating gate to serve as the first isolation portion.

[0105] 13a and 13b, FIG13a is a schematic diagram of the second direction structure of another embodiment of the present application in which the shallow trench isolation structure is further lowered to form the first isolation portion; FIG13b is a schematic diagram of the first direction structure of another embodiment of the present application in which the shallow trench isolation structure is further lowered to form the first isolation portion.

[0106] As shown in FIG13a , in the second direction, based on FIG12a , a portion of the shallow trench isolation structure 102 is removed so that the height of the shallow trench isolation structure 102 is lower than the height of the half-floating gate, and the remaining portion of the shallow trench isolation structure 102 is used as the first isolation portion; as shown in FIG13b , in the first direction, the protective layer 420 can be removed.

[0107] The removal process here may be performed by first wet etching and then dry etching.

[0108] Furthermore, the manufacturing process of the control gate of the storage area and the lead-out line of the lead-out area is as follows:

[0109] An inter-gate dielectric layer is formed, wherein the inter-gate dielectric layer at least covers half of the floating gate.

[0110] 14a and 14b, which are schematic structural diagrams of the second direction and the first direction of an embodiment of forming an inter-gate dielectric layer in the present application.

[0111] As shown in FIG14a , in the second direction, based on FIG13a , an inter-gate dielectric layer 500 is formed so that the inter-gate dielectric layer 500 covers the first isolation portion and the semi-floating gate in the first groove segment 1031 , forming a tooth-like structure, thereby increasing the coupling area between the semi-floating gate and the control gate; as shown in FIG14b , in the first direction, an inter-gate dielectric layer 500 is formed so that the inter-gate dielectric layer 500 covers the first groove 103 portion above the semi-floating gate composed of the first gate 1051 and the second gate 1061 , and covers the residual hard mask layer 400 on the area between the two adjacent first grooves 103 .

[0112] Then, the third gate material is covered on the inter-gate dielectric layer, that is, the first gate layer is covered on the inter-gate dielectric layer 500, and excess third gate material is removed until it is flush with the highest point of the first groove, that is, the third gate material is flush with the highest point of the first groove.

[0113] Please refer to FIG. 15 a and FIG. 15 b , which are schematic structural diagrams of the second direction and the first direction of an embodiment of covering the third gate material in the present application.

[0114] As shown in Figure 15a, in the second direction, based on Figure 14a, a third gate material 600 is covered on the inter-gate dielectric layer 500, where the third gate material is also the first gate layer, and excess third gate material 600 is removed so that the third gate material 600 is flush with the highest point of the first groove 103; as shown in Figure 15b, in the first direction, based on Figure 14b, a third gate material 600 is covered on the inter-gate dielectric layer 500, and excess third gate material 600 is removed so that the third gate material 600 is flush with the highest point of the first groove 103.

[0115] Then, the control gate of the memory region and the lead-out line of the lead-out region are formed.

[0116] Please refer to FIG. 16 a and FIG. 16 b , which are schematic structural diagrams of the second direction and the first direction of forming a control gate in an embodiment of the present application.

[0117] As shown in FIG16b, in the first direction, based on FIG15b, a portion of the third gate material 600 in the first groove 103 of the storage region is removed to form a vacant region 1033, so that the remaining third gate material 600 is no higher than the highest point of the base groove. The remaining third gate material 600 serves as the control gate 610, that is, the remaining first gate layer in the base groove of the storage region serves as the control gate of the memory cell. As shown in FIG16a, in the second direction, a portion of the third gate material 600 above the first groove 103 of the storage region is removed to form a vacant region 620.

[0118] To more fully illustrate the device structure, the left side of the dashed line in Figure 16b shows a cross-sectional view of the device with a vacant region 1033 formed in the first direction, which is a cross-sectional view taken along the Y1 direction of the memory region in Figure 20 below. The right side of the dashed line in Figure 16b shows a cross-sectional view of the device with the third gate material 600 retained in the first recess 103 in the first direction, with the retained third gate material 600 serving as the lead-out line for the memory cell control gate in the lead-out region, which is a cross-sectional view taken along the Y2 direction of the lead-out region in Figure 20 below. As shown to the left of the dashed line in Figure 16b, the third gate material 600 above the substrate recess in the memory region is removed to form a control gate 610. As shown in Figure 16a, when viewed from the second direction, a vacant region 620 is formed.

[0119] Next, a second insulating layer 700 is formed on the remaining third gate material in the vacant area 1033 of the first groove 103 and on the first isolation portion.

[0120] Please refer to FIG. 17 a and FIG. 17 b , which are schematic structural diagrams of the second direction and the first direction of an embodiment of forming the second insulating layer in the present application.

[0121] As shown in FIG17a , in the second direction, based on FIG16a , a second insulating layer 700 is formed in the idle area 620 of the third gate material 600 ; as shown in FIG17b , in the first direction, based on FIG16b , a second insulating layer 700 is formed in the idle area 1033 of the first groove 103 , and chemical mechanical polishing is performed to make the surface flat. The material of the second insulating layer 700 is, for example, silicon oxide.

[0122] In some embodiments, in a first direction (such as the Y2 direction of Figure 20 below), the third gate material 600 in the first groove 103 of the lead-out region is completely retained; wherein, the third gate material 600 retained in the first groove 103 of the lead-out region serves as a connection point of the control gate in the memory cell, for realizing the connection between the control gate 610 of the memory cell and the outside world; that is, the third gate material 600 in the first groove 103 of the retained lead-out region serves as a lead-out line of the control gate of the memory cell, and the lead-out line connects the control gates 610 of multiple memory cells in the same row.

[0123] In some embodiments, in the second direction, at least one first groove in the lead-out area of ​​every preset number of first grooves is shielded, and a portion of the third gate material 600 in the first groove 103 of the lead-out area is retained, wherein, in the second direction, the third gate material 600 retained in the first grooves of the same row serves as a connection point for all control gates in the memory cells of the row, and is used to realize the connection between the control gate 610 in the memory cells of the same row and the outside world; a lead-out line of the control gate can be made at a fixed distance BL, such as every 32 columns BL, that is, a lead-out line corresponding to the lead-out area, so that the control gate 610 is connected to the outside world through the lead-out line.

[0124] In addition, the process also includes removing all hard mask layers on the memory device, wherein the second isolation portion is a portion of the shallow trench isolation structure 102 other than the exposed first isolation portion.

[0125] 18a and 18b, which are schematic structural diagrams of the second direction and the first direction of removing the hard mask layer in one embodiment of the present application.

[0126] As shown in FIG18a , in the second direction, the first insulating layer 104 and the hard mask layer 400 on the second isolation part of the shallow trench isolation structure in the second type of area in the first direction are removed. FIG18a is a cross-sectional view of the second type of area in the second direction, that is, there is no first insulating layer 104 and hard mask layer 400 on the first isolation part; as shown in FIG18b , in the first direction, the first insulating layer 104 and the hard mask layer 400 in the area between two adjacent substrate grooves and on the second isolation part of the shallow trench isolation structure 102 in the second direction are removed.

[0127] In some embodiments, in the first direction, the first isolation portions and the second isolation portions are alternately arranged.

[0128] Form an isolation retaining wall.

[0129] Please refer to FIG. 19 a and FIG. 19 b , which are schematic structural diagrams of the second direction and the first direction of an embodiment of forming an isolation retaining wall in the present application.

[0130] As shown in Figure 19a, in the second direction, the structure is as shown in Figure 18a; as shown in Figure 19b, in the first direction, isolation walls 800 are formed on both sides of the second insulating layer 700 and / or the third gate material 600 remaining on the substrate groove, that is, isolation walls 800 are formed on both sides of the second insulating layer 700 remaining on the substrate groove in the storage area, as shown on the left side of the dotted line in Figure 19b; isolation walls 800 are formed on both sides of the third gate material 600 on the substrate groove in the lead-out area, that is, isolation walls 800 are formed on both sides of the lead-out line on the substrate groove in the lead-out area, as shown on the right side of the dotted line in Figure 19b.

[0131] In some embodiments, in a first direction, ion implantation is performed in the substrate on both sides of the first groove 103 to form a source and a drain, respectively. The source and the drain are then led out through a subsequently formed source contact window structure and a drain lead-out structure.

[0132] In some embodiments, the first dielectric layer 200 is removed, and a metal silicide layer 210 is formed on the source region corresponding to the source, the drain region corresponding to the drain, and the third gate material.

[0133] At this point, the semiconductor substrate is formed.

[0134] S12. Covering a first interlayer dielectric layer on the semiconductor substrate, and forming a source contact window structure in the first interlayer dielectric layer, each source contact window structure extends along the second direction and is connected to multiple source electrodes in the same row in the second direction, wherein the source contact window structure in the source lead-out area includes a source connection structure and a source contact structure stacked in sequence, and the cross-sectional area of ​​the source contact structure is larger than the cross-sectional area of ​​the source connection structure.

[0135] Next, a first interlayer dielectric layer is covered on the semiconductor substrate.

[0136] Referring to Figures 20, 21a and 21b, Figure 20 is a top view of an embodiment of forming a first interlayer dielectric layer on a memory device in the present application; Figure 21a is a schematic diagram of the first direction Y1 and Y2 structures of an embodiment of forming a first interlayer dielectric layer in the present application; Figure 21b is a schematic diagram of the Y3 direction structure of an embodiment of forming a first interlayer dielectric layer in the present application.

[0137] As shown in Figure 20, in the first direction, it can be divided into three types of regions, among which Y1 is the first type of region in the first direction, that is, the drain lead-out region, and the left side of the dotted line of the aforementioned xb figure is a cross-sectional view of the first type of region in the first direction; Y2 is the second type of region in the first direction, that is, the lead-out region, and the right side of the dotted line of the aforementioned xb figure is a cross-sectional view of the second type of region in the first direction; Y3 is the third type of region in the first direction, that is, the source lead-out region; in the second direction, it can be divided into three types of regions, among which X1 is the first type of region in the second direction, and the second isolation part is located in the first type of region X1 in the second direction; X2 is the second type of region in the second direction, and the first isolation part is located in the second type of region X2 in the second direction, and the aforementioned xa figures are all cross-sectional views of the second type of region in the second direction; X3 is the third type of region in the second direction, corresponding to the strip-shaped source contact window structure.

[0138] Then, as shown in Figures 20 and 21a, in the first direction, a first interlayer dielectric layer ILD1 is covered on the semiconductor substrate, and the first interlayer dielectric layer ILD1 is etched and filled to form a source contact window structure CT in the first interlayer dielectric layer, and each source contact window structure CT extends along the second direction to form a strip-shaped source contact window structure, and is connected to multiple sources in the same row in the second direction; wherein, the left side of the dotted line in Figure 21a is a cross-sectional view in the Y1 direction, and the right side of the dotted line in Figure 21a is a cross-sectional view in the Y2 direction; as shown in Figure 21b, the source contact window structure in the source lead-out area includes a lower source connection structure CT1 and an upper source contact structure CT2, the source connection structure CT1 is connected to the source, and the cross-sectional area of ​​the source contact structure CT2 is larger than the cross-sectional area of ​​the source connection structure CT1, so that the subsequently formed source lead-out structure is convenient for connecting with the source contact structure.

[0139] In one embodiment, a trench contact region may be formed in the first interlayer dielectric layer ILD1 by photolithography and etching, and then a conductive material (e.g., tungsten (W)) may be deposited in the trench contact region and chemical mechanical polishing may be performed to form a source contact window structure, thereby connecting the sources of the memory cells in the same row to form a common source.

[0140] In one embodiment, the first interlayer dielectric layer ILD1 is etched, and the isolation barrier 800 is used as an etch stop layer in the source lead-out region to form a trench contact region that is wider at the top and narrower at the bottom in the source lead-out region, and then a source contact window structure including a lower source connection structure CT1 and an upper source contact structure CT2 is formed in the source lead-out region. The source connection structure CT1 is in contact with the isolation barrier 800, and the source connection structure CT1 and the source contact structure CT2 are formed as one piece.

[0141] In some embodiments, the source connection structure CT1 and the isolation retaining wall 800 may be adjacent, that is, the source connection structure CT1 and the isolation retaining wall 800 are arranged non-contact, as shown in Figure 21b; in this case, a groove of the same width as a whole is first formed, and then the upper part of the groove is widened, and then the source connection structure CT1 is formed in the lower part of the groove in the source lead-out area, and the source contact structure CT2 is formed in the upper part, that is, the source contact structure CT2 is formed on the source connection structure CT1, that is, the cross-sectional area of ​​the source contact structure CT2 is larger than the cross-sectional area of ​​the source connection structure CT1, so as to form a source contact window structure.

[0142] In one embodiment, a barrier layer 900 (eg, silicon nitride (SIN)) is deposited on the source contact window structure, and the barrier layer 900 on the source contact structure CT2 is retained by photolithography and etching.

[0143] In another embodiment, a trench contact region can be formed in the first interlayer dielectric layer ILD1 by photolithography and etching. After a conductive material (such as tungsten (W)) is deposited in the trench contact region, the conductive material is etched back to form a source contact window structure. The etch-back depth can be 400A-600A (angstroms). For example, if the etch-back depth is 500A, a barrier layer 900 (such as silicon nitride (SIN)) is deposited and chemical mechanical polishing is performed on the barrier layer 900 to retain the barrier layer 900 on the source contact structure CT2.

[0144] Next, a second interlayer dielectric layer is covered on the first interlayer dielectric layer.

[0145] Referring to Figures 22, 23a, 23b and 23c, Figure 22 is a top view of an embodiment of forming a second interlayer dielectric layer on a memory device; Figures 23a, 23b and 23c are structural schematic diagrams of the Y1 direction, Y2 direction and Y3 direction of an embodiment of forming a second interlayer dielectric layer in the present application.

[0146] A second interlayer dielectric layer ILD2 is covered on the first interlayer dielectric layer ILD1, and a first lead-out structure v1 is formed in the second interlayer dielectric layer ILD2 and / or the first interlayer dielectric layer ILD1, wherein the first lead-out structure v1 includes a source lead-out structure v11, a drain lead-out structure v12 and a first control gate lead-out structure v13.

[0147] As shown in FIG22 , the drain lead-out structure v12 is located on the drain of the drain lead-out region, the source lead-out structure v11 is located on the source contact structure CT2 of the source of the source lead-out region, and the first control gate lead-out structure v13 is located on the lead-out line of the lead-out region.

[0148] The source lead-out structure v11, the drain lead-out structure v12, and the first control gate lead-out structure v13 are formed simultaneously. By adjusting the etching process to form through-holes of varying depths, the barrier layer 900 has a lower etching rate than the first interlayer dielectric layer ILD1 and the second interlayer dielectric layer ILD2, allowing for the simultaneous formation of through-holes for the source lead-out structure v11, the drain lead-out structure v12, and the first control gate lead-out structure v13. The through-holes for the source lead-out structure v11, the drain lead-out structure v12, and the first control gate lead-out structure v13 expose the source contact window structure of the source lead-out region, the drain electrode of the drain lead-out region, and the lead-out line of the lead-out region, respectively. Conductive material is then filled into these through-holes to form the source lead-out structure v11, the drain lead-out structure v12, and the first control gate lead-out structure v13.

[0149] As shown in Figure 23a, in the Y1 direction, in the drain lead-out area, a drain lead-out structure v12 is formed in the first interlayer dielectric layer ILD1 and the second interlayer dielectric layer ILD2 on the substrate on one side of the first groove, and a source contact window structure CT is formed in the first interlayer dielectric layer ILD1 on the substrate on the other side; that is, the drain lead-out structure v12 on the drain extends from the second interlayer dielectric layer ILD2 to the first interlayer dielectric layer ILD1 and is connected to the corresponding drain, wherein each source contact window structure CT extends along the second direction and is connected to multiple sources in the same row in the second direction, and the source contact window structure CT is a strip structure; a drain lead-out structure v12 is formed in the second interlayer dielectric layer ILD2, and each drain lead-out structure v12 is connected to a corresponding drain, so that the drain is led out by the drain lead-out structure v12.

[0150] As shown in Figure 23b, in the Y2 direction, in the lead-out area, a first control gate lead-out structure v13 is formed in the second interlayer dielectric layer ILD2, and the first control gate lead-out structure v13 extends into the first interlayer dielectric layer ILD1. Each first control gate lead-out structure v13 is connected to a lead-out line shared by the control gates of multiple storage cells in the same row, that is, the first control gate lead-out structure v13 is connected to the third gate material 600 (first gate layer) of the first groove, so that the lead-out line corresponding to the control gate is led out by the first control gate lead-out structure v13.

[0151] As shown in Figure 23c, in the Y3 direction, in the source lead-out region, an active contact window structure CT is formed in the first interlayer dielectric layer ILD1 on the source electrode, and the source contact window structure CT extends along the second direction to form a strip-shaped source contact window structure, connecting multiple source electrodes in the same row in the second direction. The source contact window structure CT in the source lead-out region includes a lower source connection structure CT1 and an upper source contact structure CT2, and the cross-sectional area of ​​the source contact structure CT2 is larger than the cross-sectional area of ​​the source connection structure CT1; an active lead-out structure v11 is formed in the second interlayer dielectric layer ILD2 in the source lead-out region, each source lead-out structure v11 is connected to a corresponding source contact window structure CT, that is, the source lead-out structure v11 penetrates the barrier layer and is connected to the source contact structure CT2, and one source contact window structure CT corresponds to the source contact structure CT2 in one source lead-out region, so that the source electrode is led out by the source lead-out structure v11, wherein the cross-sectional area of ​​the source lead-out structure v11 can be smaller than the cross-sectional area of ​​the source contact structure CT2.

[0152] In some embodiments, a source lead structure v11 may be provided at a fixed distance BL, such as every 32 columns BL, so that the source electrode is connected to the outside world through the source lead structure v11 .

[0153] Next, a patterned first metal layer m1 is formed on the second interlayer dielectric layer, wherein the first metal layer includes a source line m11 , a bit line m12 , and a control gate contact m13 .

[0154] Referring to Figures 24, 25a, 25b and 25c, Figure 24 is a top view schematic diagram of an embodiment of forming a first metal layer on a memory device; Figures 25a, 25b and 25c are structural schematic diagrams of the Y1 direction, Y2 direction and Y3 direction of an embodiment of forming the first metal layer in the present application.

[0155] As shown in Figures 24 and 25a, in the drain lead-out area, a first metal layer m1, namely, a bit line m12, is formed on the second interlayer dielectric layer ILD2. The bit line m12 extends along the first direction, and multiple bit lines m12 are spaced apart in the second direction, corresponding to drains of different columns respectively. The bit line m12 connects multiple drain lead-out structures v12 in the same column in the first direction.

[0156] As shown in Figures 24 and 25b, in the lead-out area, a first metal layer m1, that is, a control gate contact m13, is formed on the second interlayer dielectric layer ILD2, that is, a control gate contact m13 is formed on the first control gate lead-out structure v13, so that the control gate contact m13 is connected to the lead-out line of the control gate through the first control gate lead-out structure v13, that is, connected to the third gate material 600 (first gate layer) in the lead-out area; wherein, the cross-sectional area of ​​the control gate contact m13 can be larger than the cross-sectional area of ​​the first control gate lead-out structure v13, so that the first control gate lead-out structure v13 can effectively connect the upper and lower related structures.

[0157] As shown in Figures 24 and 25c, in the source lead-out area, a first metal layer m1, that is, a source line m11, is formed on the source lead-out structure v11 of the second interlayer dielectric layer ILD2. The source line m11 extends along a first direction, wherein the source line m11 is connected to the source contact window structure CT through the source lead-out structure v11, that is, the source is connected, and the source line m11 connects multiple source lead-out structures v11 in the same column.

[0158] Then, a third interlayer dielectric layer ILD3 is covered on the first metal layer m1, and a second lead-out structure v2 is formed in the third interlayer dielectric layer, wherein the second lead-out structure v2 includes a second control gate lead-out structure v21; and a patterned second metal layer m2 is formed on the third interlayer dielectric layer ILD3, wherein the second metal layer m2 includes word lines m21, each word line m21 extends along the second direction and connects at least one control gate contact m13 in the same row in the second direction.

[0159] Referring to Figures 26, 27a, 27b and 27c, Figure 26 is a top view of an embodiment of forming a third interlayer dielectric layer and a second metal layer on a memory device; Figure 27a is a Y1 direction structural schematic diagram of an embodiment of forming a third interlayer dielectric layer and a second metal layer in the present application; Figure 27b is a Y2 direction structural schematic diagram of an embodiment of forming a third interlayer dielectric layer and a second metal layer in the present application; Figure 27c is a Y3 direction structural schematic diagram of an embodiment of forming a third interlayer dielectric layer and a second metal layer in the present application.

[0160] As shown in Figures 26 and 27a, in the drain lead-out area, a third interlayer dielectric layer ILD3 is formed on the first metal layer m1, and a patterned second metal layer m2, i.e., a word line m21, is formed on the third interlayer dielectric layer ILD3, wherein the word line m21 is located on the gate structure and extends along the second direction.

[0161] As shown in Figures 26 and 27b, in the lead-out area, a third interlayer dielectric layer ILD3 is formed on the first metal layer m1, and a patterned second metal layer m2, that is, the word line m21, is formed on the third interlayer dielectric layer ILD3. A second lead-out structure v2 is also formed in the third interlayer dielectric layer ILD3, and the first metal layer m1 and the second metal layer m2 are connected through the second control gate lead-out structure v21 in the second lead-out structure v2, that is, the control gate contact m13 is connected to the word line m21 through the second control gate lead-out structure v21.

[0162] In some embodiments, the word line m21 extends along the second direction and may connect at least one second control gate lead-out structure v21 in the same row.

[0163] As shown in Figures 26 and 27c, in the Y3 direction, in the source lead-out area, a third interlayer dielectric layer ILD3 is formed on the first metal layer m1, and a patterned second metal layer m2, i.e., a word line m21, is formed on the third interlayer dielectric layer ILD3, wherein the word line m21 is located on the gate structure and extends along the second direction.

[0164] In this embodiment, the upper cross-sectional area of ​​the source contact window structure corresponding to the source electrode in the source lead-out region is enlarged, which can effectively increase the process margin of the contact between the through hole (via hole) and the trench contact (trench contact), avoid the connection process of the through hole (via hole) and the contact hole (contact hole), increase the corresponding process margin, reduce the corresponding contact resistance, and improve the performance of the semiconductor device.

[0165] The present application also includes a storage device, including a substrate, multiple gate structures, a first interlayer dielectric layer and multiple source contact window structures; wherein, a portion of the multiple gate structures is located in a storage area, and each gate structure is respectively provided with a drain and a source on both sides in a first direction, and the storage area includes a source lead-out area; the first interlayer dielectric layer covers the substrate, the gate structure, the drain and the source; multiple source contact window structures are located in the first interlayer dielectric layer, each source contact window structure extends along a second direction and is connected to multiple sources in the same row in the second direction, wherein the source contact window structure includes a source connection structure and a source contact structure stacked in sequence, and the cross-sectional area of ​​the source contact structure is larger than the cross-sectional area of ​​the source connection structure.

[0166] Another portion of the plurality of gate structures is located in the lead-out region, the gate structure of the storage region is located in the substrate, and at least a portion of the gate structure of the lead-out region is located on the substrate.

[0167] In some embodiments, the gate structure includes a semi-floating gate, which is located at the bottom of a base groove of a substrate, with a portion of the semi-floating gate in contact with the substrate and the other portion isolated from the substrate by a gate insulating layer, wherein the gate structure of the storage area also includes a control gate, which is located on the semi-floating gate and isolated from the semi-floating gate by an inter-gate dielectric layer; the gate structure of the lead-out area also includes a lead-out line, at least a portion of the lead-out line is located on the substrate and serves as a lead-out line of the control gate of the storage cell, and the lead-out line connects the control gates of multiple storage cells in the same row.

[0168] In some embodiments, in the second direction, at least one corresponding lead wire is provided for every predetermined number of control gates, and the lead wire serves as a connection point for connecting multiple control gates in the same row with the outside world.

[0169] In one embodiment of the present application, the memory device further includes: a second interlayer dielectric layer, a plurality of source lead-out structures and a first metal layer; wherein the second interlayer dielectric layer covers the first interlayer dielectric layer; the plurality of source lead-out structures are located in the second interlayer dielectric layer in the source lead-out area, and each source lead-out structure is connected to a corresponding source contact window structure; the first metal layer is located on the second interlayer dielectric layer, and the source line in the first metal layer is connected to the plurality of source lead-out structures in the same column in the source lead-out area.

[0170] In one embodiment of the present application, a barrier layer is further included, which is located on the source contact structure, wherein the source lead-out structure penetrates the barrier layer and is connected to the source contact window structure.

[0171] In one embodiment of the present application, the storage area also includes a drain lead-out area; the storage device also includes: multiple drain lead-out structures and multiple bit lines; wherein the multiple drain lead-out structures are located in the second interlayer dielectric layer and the first interlayer dielectric layer of the drain lead-out area of ​​the storage area, and each drain lead-out structure is respectively connected to a corresponding drain electrode; the first metal layer also includes multiple bit lines located in the drain lead-out area, each bit line extending along the first direction and connecting multiple drain lead-out structures in the same column in the first direction.

[0172] In one embodiment of the present application, it also includes: multiple first control gate lead-out structures and multiple control gate contacts; wherein the multiple first control gate lead-out structures are located in the second interlayer dielectric layer and the first interlayer dielectric layer in the lead-out area, and each first control gate lead-out structure is connected to the lead-out line shared by the control gates of multiple storage cells in the same row in the lead-out area; the first metal layer also includes multiple control gate contacts located in the lead-out area, and each control gate contact is connected to a first control gate lead-out structure.

[0173] In one embodiment of the present application, it also includes: a third interlayer dielectric layer, multiple second control gate lead-out structures, and a second metal layer; wherein the third interlayer dielectric layer covers the first metal layer; multiple second control gate lead-out structures are located in the third interlayer dielectric layer in the lead-out area, and each second control gate lead-out structure is respectively connected to a corresponding control gate contact; the second metal layer is located on the third interlayer dielectric layer, and the word lines in the second metal layer extend along the second direction, and each word line is connected to the control gate contacts in the same row in the second direction through the second control gate lead-out structure.

[0174] In this embodiment, the source contact window structure corresponding to the source electrode in the source lead-out region is set to an upper source contact structure and a lower source connection structure, and the cross-sectional area of ​​the source contact structure is set to be larger than the cross-sectional area of ​​the source connection structure, which can effectively increase the process margin of the contact between the through hole (via hole) and the trench contact (trench contact), avoid the connection process of the through hole (via hole) and the contact hole (contact hole), increase the corresponding process margin, reduce the corresponding contact resistance, and improve the performance of the semiconductor device.

[0175] The above description is only an embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made by using the contents of the description and drawings of the present invention, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A method for manufacturing a memory device, characterized in that: include: A semiconductor substrate is provided, the semiconductor substrate comprising a substrate and a plurality of gate structures, a portion of the plurality of gate structures is located in a storage region, and a source and a drain are respectively arranged in the substrate on both sides of each gate structure in a first direction; wherein the storage region comprises a source lead-out region; A first interlayer dielectric layer is covered on the semiconductor substrate, and a source contact window structure is formed in the first interlayer dielectric layer, each of the source contact window structures extends along a second direction and is connected to a plurality of source electrodes in the same row in the second direction, wherein the source contact window structure in the source lead-out region includes a source connection structure and a source contact structure stacked in sequence, and a cross-sectional area of ​​the source contact structure is larger than a cross-sectional area of ​​the source connection structure.

2. The method according to claim 1, characterized in that Another portion of the plurality of gate structures is located in a lead-out region, wherein the gate structure in the storage region is located in the substrate, and at least a portion of the gate structure in the lead-out region is located on the substrate.

3. The method according to claim 2, characterized in that The semiconductor substrate is provided, comprising: providing a substrate, and forming a hard mask layer on the substrate; Opening a plurality of first grooves in the active area of ​​the substrate from the hard mask layer, wherein a portion of the plurality of first grooves is located in the storage area and another portion is located in the lead-out area, wherein a portion of the first groove in the substrate is defined as a base groove; forming a gate insulating layer and a semi-floating gate at the bottom of the substrate groove, wherein a portion of the semi-floating gate contacts the substrate, and another portion of the semi-floating gate is isolated from the substrate by the gate insulating layer; An inter-gate dielectric layer and a first gate layer are respectively formed in the multiple first grooves, a portion of the first gate layer in the first groove of the storage area is removed to form a control gate of the storage unit, and the first gate layer in the first groove of the lead-out area is retained as a lead-out line of the control gate of the storage unit, and the lead-out line connects the control gates of multiple storage units in the same row, wherein the semi-floating gate and the control gate in the storage area cooperate to form the gate structure of the storage area, and the semi-floating gate and the lead-out line in the lead-out area cooperate to form the gate structure of the lead-out area.

4. The method according to claim 3, characterized in that In the second direction, at least one of the first grooves in the lead-out area of ​​every preset number of the first grooves is shielded, and a portion of the first gate layer in the first groove in the lead-out area is retained, wherein, in the second direction, the first gate layer retained in the first grooves of the same row serves as a connection point for all control gates in the storage unit of the row, and is used to realize the connection between the control gates in the storage area of ​​the same row and the outside world.

5. The method according to claim 1, characterized in that The method of covering the semiconductor substrate with a first interlayer dielectric layer and forming a source contact window structure in the first interlayer dielectric layer comprises: Etching the first interlayer dielectric layer to form a strip-shaped trench contact region on the source electrode, and forming a trench contact region that is wide at the top and narrow at the bottom in the source lead-out region; A conductive material is filled in the trench contact region to form the source contact window structure, wherein the source connection structure is formed at a lower portion of the trench contact region in the source lead-out region, and the source contact structure is formed at an upper portion of the trench contact region in the source lead-out region.

6. The method according to claim 5, characterized in that Isolation walls are formed on both sides of the gate structure of the storage area; The step of forming a trench contact region that is wide at the top and narrow at the bottom in the source lead-out region comprises: The first interlayer dielectric layer is etched, wherein the isolation barrier corresponding to the source lead-out region is used as an etching stop layer to form a trench contact region that is wide at the top and narrow at the bottom.

7. The method according to claim 1, characterized in that A second interlayer dielectric layer is covered on the first interlayer dielectric layer, and a first lead-out structure is formed in the second interlayer dielectric layer and / or the first interlayer dielectric layer, wherein the first lead-out structure includes a source lead-out structure, the source lead-out structure is located in the source lead-out region, each source lead-out structure corresponds to a source contact window structure, and is connected to the corresponding source contact window structure in the source lead-out region; A patterned first metal layer is formed on the second interlayer dielectric layer, wherein the first metal layer includes a source line, the source line is located in the source lead-out region, the source line extends along the first direction, and is connected to the plurality of source lead-out structures in the same column. connect.

8. The method according to claim 1, characterized in that forming a barrier layer on the source contact structure, covering the first interlayer dielectric layer with a second interlayer dielectric layer, and forming a first lead-out structure in the second interlayer dielectric layer and / or the first interlayer dielectric layer; The first lead-out structure includes a source lead-out structure, a drain lead-out structure and a first control gate lead-out structure; Wherein, the source lead-out structure, the drain lead-out structure and the first control gate lead-out structure are formed synchronously.

9. The method according to claim 7, characterized in that: The storage area also includes a drain lead-out area; The first lead-out structure further includes a drain lead-out structure located in the drain lead-out region, and each of the drain lead-out structures is respectively connected to a corresponding drain electrode; The first metal layer further includes a bit line located in the drain lead-out region, each of the bit lines extending along the first direction to connect a plurality of drain lead-out structures in the same column in the first direction.

10. The method according to claim 7, characterized in that Another portion of the plurality of gate structures is located in the lead-out region; The first lead-out structure further includes a first control gate lead-out structure located in the lead-out region, each of the first control gate lead-out structures being connected to a lead-out line shared by a plurality of memory cells in the same row; The first metal layer further includes control gate contacts located in the lead-out region, and each of the control gate contacts is respectively connected to one of the first control gate lead-out structures.

11. The method according to claim 10, characterized in that A third interlayer dielectric layer is covered on the first metal layer, and a second lead-out structure is formed in the third interlayer dielectric layer, wherein the second lead-out structure includes a second control gate lead-out structure located in the lead-out region, and each of the second control gate lead-out structures is connected to a corresponding control gate contact; A patterned second metal layer is formed on the third interlayer dielectric layer, wherein the second metal layer includes word lines, each of which extends along the second direction and connects the control gate contacts in the same row in the second direction.

12. A storage device, characterized in that: include: substrate; A plurality of gate structures, a portion of which is located in a storage area, each of which is provided with a drain and a source on both sides in a first direction, wherein the storage area includes a source lead-out area; A first interlayer dielectric layer, covering the substrate, the gate structure, the drain and the source; A plurality of source contact window structures are located in the first interlayer dielectric layer, each of the source contact window structures extends along a second direction and is connected to a plurality of the source electrodes in the same row in the second direction, wherein the source contact window structure comprises a source connection structure and a source contact structure stacked in sequence, and a cross-sectional area of ​​the source contact structure is greater than a cross-sectional area of ​​the source connection structure.

13. The memory device according to claim 12, wherein: Another portion of the plurality of gate structures is located in a lead-out region, wherein the gate structure in the storage region is located in the substrate, and at least a portion of the gate structure in the lead-out region is located on the substrate.

14. The memory device according to claim 13, wherein: The gate structure comprises: A semi-floating gate is located at the bottom of the base groove of the substrate, a part of the semi-floating gate is in contact with the substrate, and another part is isolated from the substrate by a gate insulating layer; Wherein, the gate structure of the storage area further includes a control gate, the control gate is located on the semi-floating gate and is isolated from the semi-floating gate by an inter-gate dielectric layer; The gate structure of the lead-out region further includes a lead-out line, at least a portion of which is located on the substrate and serves as a lead-out line of a control gate of a memory cell, and the lead-out line connects the control gates of a plurality of memory cells in the same row.

15. The memory device according to claim 14, wherein: In the second direction, at least one corresponding lead wire is provided for every preset number of control grids, and the lead wire is used as a connection point to realize the connection between a plurality of control grids in the same row and the outside world.

16. The memory device according to claim 12, wherein: The storage device further comprises: a second interlayer dielectric layer, covering the first interlayer dielectric layer; A plurality of source lead-out structures are located in the second interlayer dielectric layer, and each of the source lead-out structures is connected to a corresponding source contact window structure; The first metal layer is located on the second interlayer dielectric layer, and the source line in the first metal layer is connected to a plurality of the source lead-out structures in the same column in the source lead-out region.

17. The memory device according to claim 16, wherein: Also includes: A barrier layer is located on the source contact structure, wherein the source lead-out structure penetrates the barrier layer and is connected to the source contact window structure.

18. The memory device according to claim 16, wherein: The storage area also includes a drain lead-out area; The storage device further comprises: A plurality of drain lead-out structures, located in the second interlayer dielectric layer and the first interlayer dielectric layer in the drain lead-out region, each of the drain lead-out structures correspondingly connected to one of the drain electrodes; The first metal layer further includes a plurality of bit lines located in the drain lead-out region, each of the bit lines extending along the first direction and connecting a plurality of drain lead-out structures in the same column in the first direction.

19. The memory device according to claim 16, wherein: Also includes: A plurality of first control gate lead-out structures are located in the second interlayer dielectric layer and the first interlayer dielectric layer, and each of the first control gate lead-out structures is connected to a lead-out line shared by a plurality of memory cell control gates in the same row in the lead-out region; The first metal layer further includes a plurality of control gate contacts located in the lead-out region, and each of the control gate contacts is respectively connected to one of the first control gate lead-out structures.

20. The memory device according to claim 19, wherein: Also includes: A third interlayer dielectric layer covering the first metal layer; A plurality of second control gate lead-out structures, located in the third interlayer dielectric layer in the lead-out region, each of the second control gate lead-out structures correspondingly connected to one of the control gate contacts; The second metal layer is located on the third interlayer dielectric layer. The word lines in the second metal layer extend along the second direction. Each of the word lines is connected to the control gate contacts in the same row in the second direction through the second control gate lead-out structure.

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