Memory compatibility system and method, and electronic device

Abstract

Disclosed are a memory compatibility system and method, and an electronic device. The memory compatibility system comprises: a current memory, the current memory being any type of target memory, various types of target memories having the same number of pins, the pins comprising distinguishing pins, and the distinguishing pins being the pins of the various types of target memories that are located at the same position and have different configuration information; a power manager configured to determine the type of the current memory, determine a power supply demand of the current memory on the basis of the type, and output a power supply voltage to the current memory on the basis of the power supply demand; and a baseband processor configured to determine the type of the current memory, determine the current configuration information of the distinguishing pin of the current memory on the basis of the type, and on the basis of the current configuration information, process a signal interacting with the current memory.

Description

Memory compatible system, method and electronic device

[0001] Citation of Related Applications

[0002] This disclosure claims all rights and interests in the Chinese invention patent application with application number 2023114605530 filed with the State Intellectual Property Office of the People's Republic of China on November 3, 2023, entitled "A Memory-Compatible System, Method and Electronic Device", and incorporates the entire contents thereof into this disclosure by reference.

[0003] field

[0004] The present disclosure relates generally to the field of communications, and more particularly to memory compatible systems, methods, and electronic devices.

[0005] background

[0006] Communication devices serve as the connecting link in the IoT industry, powering the interconnectedness of everything. With the increasing adoption of 5G high-bandwidth, high-speed modules, customer product applications are becoming increasingly widespread. However, different products require different memory module capacity configurations. For example, for 5G cellular modules used in the CPE market, operators who need to install multiple apps will require a memory module with a capacity of 32GB (NAND) + 2GB (LPDDR4x). For products that don't require app installation, a memory module with a capacity of 1GB (NAND) + 1GB (LPDDR4x) can meet customer product requirements, thereby reducing module costs.

[0007] Due to space limitations, communication devices often use MCP (Multiple Chip Package) devices as memory modules. For MCP devices on the market, small-capacity memory is designed with nMCP (NAND + LPDDR), where SLC NAND devices are used for NAND, and large-capacity memory is designed with eMCP (eMMC + LPDDR) because the controller in the eMMC can more effectively manage NAND devices. Taking the current products using dual-channel LPDDR4x eMCP and nMCP memory as an example, communication devices that need to be compatible with eMCP and nMCP usually adopt a common PCB design, that is, resistor jumpers are used on the same PCB to achieve compatibility with eMCP and nMCP. However, since NAND and eMMC share 12 signal lines, 24 jumper resistors need to be added, and 12 PCB traces need to be added. This is simply not possible on current high-density 5G communication devices. Even if it can be achieved, it will bring serious PCB EMC problems.

[0008] Overview

[0009] In one aspect, the present disclosure provides a memory compatible system comprising:

[0010] Current memory; the current memory is any type of target memory, each type of the target memory has the same number of pins, the pins include distinguishing pins, and the distinguishing pins are the pins of the target memory of each type that are in the same position and have different configuration information;

[0011] a power manager configured to determine a category of the current memory, determine a power supply requirement of the current memory according to the category, and output a power supply voltage to the current memory according to the power supply requirement; and

[0012] The baseband processor is configured to determine the category of the current memory, determine the current configuration information of the distinguishing pins of the current memory according to the category, and process the signal interacting with the current memory according to the current configuration information.

[0013] In some embodiments, the power manager is further configured to output a configuration signal according to the category of the current memory; and

[0014] The baseband processor is configured to determine the type of the current memory according to the configuration signal.

[0015] In certain embodiments, the power manager includes an enable pin, the enable pin being selectively connected to a classification resistor to adjust a current level of the enable pin, the current level being configured to indicate the current memory classification;

[0016] The power manager is configured to output a configuration signal according to a current level of the enable pin.

[0017] In certain embodiments, the classification resistor is a jumper resistor.

[0018] In some embodiments, the power manager includes a plurality of power output pins, each of the power output pins is connected to a power pin of the current memory, and each of the power output pins outputs a different power supply voltage;

[0019] The power manager is configured to determine the category of the current memory, determine a target power supply pin among all the power supply output pins according to the category, control the target power supply pin to output a power supply voltage, and control the power supply output pins other than the target power supply pin to not output a power supply voltage.

[0020] In certain embodiments, the memory-compatible system further comprises:

[0021] The voltage stabilizing capacitor connected to the current memory is configured to adjust the output voltage of the core voltage regulator when the current memory is provided with the core voltage regulator.

[0022] In certain embodiments, the baseband processor includes a selection switch component and multiple interfaces, each of the interfaces includes configuration information of the distinguishing pins of the corresponding target memory, each first end of the selection switch component is connected to each of the interfaces in a one-to-one correspondence, and the second end of the selection switch component is connected to the current memory. The selection switch component is configured to connect the interface corresponding to the category to the current memory according to the category.

[0023] In certain embodiments, the selector switch assembly includes a plurality of single-pole, multi-throw switches.

[0024] On the other hand, the present disclosure also provides an electronic device including the memory-compatible system described in the present disclosure.

[0025] In another aspect, the present disclosure further provides a memory compatibility method, which is applied to the memory compatibility system described in the present disclosure. The memory compatibility method includes:

[0026] determining, by a power manager, a category of a current memory, determining a power supply requirement of the current memory according to the category, and outputting a power supply voltage to the current memory according to the power supply requirement;

[0027] Determining, by a baseband processor, a category of the current memory, determining current configuration information of the distinguishing pins of the current memory according to the category, and processing signals interacting with the current memory according to the current configuration information;

[0028] The current memory is any type of target memory, and each type of target memory has the same number of pins. The pins include distinguishing pins, and the distinguishing pins are pins in the same position and with different configuration information for each type of target memory.

[0029] In certain embodiments, the memory compatibility system disclosed herein pre-stores configuration information for the distinguishing pins corresponding to each target memory in the baseband processor. After determining the current memory, the system processes the signals transmitted between the system and the current memory according to the configuration information for the distinguishing pins corresponding to the current memory, and outputs the power supply voltage required by the current memory to the current memory through the power supply management device. This eliminates the need to set jumper resistors for each shared signal line, does not increase the PCB area or the complexity of device and PCB routing, and does not affect the EMC performance of the PCB. This standardizes the PCBs of module products and significantly reduces R&D investment and product certification costs. The present disclosure also provides a memory compatibility method and electronic device that have the same beneficial effects as the aforementioned memory compatibility system.

[0030] BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the embodiments of the present disclosure, the following will briefly introduce the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0032] FIG1 is a schematic structural diagram of a memory compatibility system provided by an embodiment of the present disclosure;

[0033] FIG2 is a schematic diagram showing a comparison of pinMaps for 254-pin nMCP and eMCP devices provided in one embodiment of the present disclosure;

[0034] FIG3 is a schematic structural diagram of another memory compatibility system provided by an embodiment of the present disclosure; and

[0035] FIG4 is a schematic diagram of the structure of a baseband processor provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0036] The core of this disclosure is to provide a memory-compatible system, method, and electronic device that can standardize the PCBs of module products without increasing the PCB area and the complexity of device and PCB routing, without affecting the EMC performance of the PCB, and greatly reducing R&D investment and product certification costs.

[0037] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present disclosure without making any creative efforts shall fall within the scope of protection of the present disclosure.

[0038] Please refer to FIG1 , which is a schematic diagram of the structure of a memory compatibility system provided by an embodiment of the present disclosure. The memory compatibility system includes:

[0039] Current memory 1; current memory 1 is any type of target memory, each type of target memory has the same number of pins, and the pins include distinguishing pins, which are pins in the same position of each type of target memory but with different configuration information;

[0040] The power manager 2 is configured to determine the category of the current memory 1, determine the power supply requirement of the current memory 1 according to the category, and output a power supply voltage to the current memory 1 according to the power supply requirement; and

[0041] The baseband processor 3 is configured to determine the category of the current memory 1, determine the current configuration information of the distinguishing pins of the current memory 1 according to the category, and process the signal interacting with the current memory 1 according to the current configuration information.

[0042] It is understood that the communication device can adapt to multiple types of target memories, each type of target memory has the same number of pins, and each type of memory has distinguishing pins. The distinguishing pins are pins that are located in the same position but have different configuration information for each type of target memory. The baseband processor 3 is provided with pin configuration modes corresponding to the various types of target memories adapted by the communication device. Each pin configuration mode includes configuration information for each distinguishing pin of its corresponding memory. The configuration information is the definition of the pin. After determining the type of current memory 1 currently configured by the communication device, the baseband processor 3 determines the pin configuration mode of the current memory 1 and then processes the signals transmitted between itself and the current memory 1 according to the configuration information of each distinguishing pin in the pin configuration mode. The current memory 1 is the memory currently configured by the communication device. In this embodiment, the baseband processor 3 can be specifically implemented by a baseband chip, and the power manager 2 can be specifically implemented by a PMU (Power Management Unit) chip.

[0043] In some implementation schemes, the correspondence between the category of each memory and the pin configuration mode may be pre-stored. After the current memory 1 is determined, the pin configuration mode may be determined based on the category of the current memory 1 and the correspondence.

[0044] In some implementation schemes, different memories may have different power supply requirements due to different internal devices. After determining the category of the current memory 1, the power manager 2 outputs the power supply voltage required by the current memory 1, supplies power to the current memory 1, and ensures the normal operation of the current memory 1.

[0045] In certain embodiments, the target memory includes 254-pin nMCP memory and eMCP memory as an example for illustration, wherein both nMCP memory and eMCP memory use 254-pin standard JEDEC packages with the same size, number of pins, and ball size spacing. Referring to FIG2 , FIG2 is a pinMap comparison of 254-pin nMCP memory and eMCP memory, wherein the middle black border portion is a comparison of NAND and eMMC pins. The default is the NAND pin definition, and the slash " / " is the eMMC definition. It can be concluded that in addition to the difference in the NAND and eMMC pin definitions, the external LPDDR4x definition only has 4 pins of chip2's CKE2 (clock enable) and CS2 (chip select). And since the nMCP device only has dual-channel LPDDR4x, these 4-pin circuit designs can be kept NC, as shown in Table 1 for details.

[0046] Table 1. The first difference between nMCP and eMCP pins

[0047] There are significant differences in the pinouts of NAND and eMMC in the black border, as shown in Table 2.

[0048] Table 2. Second difference pin table between nMCP and eMCP

[0049] It can be understood that the pins in Table 1 and Table 2 are the distinguishing pins. In some embodiments, the baseband processor 3 only stores the configuration information of the distinguishing pins in Table 2 corresponding to the multiplexing of the baseband processor 3.

[0050] It can be seen that in this embodiment, the configuration information of the distinguishing pins corresponding to each target memory is pre-stored in the baseband processor 3. After determining the current memory 1, the signal transmitted between itself and the current memory 1 is processed according to the configuration information of the distinguishing pins corresponding to the current memory 1, and the power supply voltage required by the current memory 1 is output to the current memory 1 through the power supply management device. There is no need to set jumper resistors for each common signal line, and the PCB area and the complexity of the device and PCB routing are not increased. The EMC performance of the PCB is not affected, so the PCB of the module product is normalized, which greatly reduces the R&D investment and product certification costs.

[0051] In some embodiments, the power manager 2 is further configured to output a configuration signal according to the category of the current memory 1;

[0052] The baseband processor 3 is configured to determine the category of the current memory 1 according to the configuration signal.

[0053] In some embodiments, the power manager 2 includes an enable pin, the enable pin being selectively connected to a classification resistor to adjust a current level of the enable pin, the current level being configured to indicate a current category of the memory 1;

[0054] The power manager 2 is configured to output a configuration signal according to the current level of the enable pin.

[0055] In certain embodiments, the classification resistor is a jumper resistor.

[0056] Please refer to FIG. 3 , which is a schematic diagram of the structure of another memory-compatible system provided in another embodiment. The power manager 2 includes an enable pin eMMC_PWR_EN and a configuration pin NAND_eMMC_CTRL. The enable pin is configured to output a configuration signal to the input control pin NAND# / eMMC of the baseband processor 3. The internal port of the enable pin is connected to the first resistor module, and the external port of the enable pin is connected to the second resistor module. The enable pin can default to a first level, i.e., the level of the enable pin is configured by the first resistor module. When the enable pin is at the first level, the configuration pin of the power manager 2 outputs a configuration signal corresponding to the first level. Assuming that the first level corresponds to the first memory, upon receiving the configuration signal corresponding to the first level, the baseband processor 3 performs subsequent processing according to the pin configuration mode of the first memory. When the second resistor module is activated, the level of the enable pin is configured to a second level, and the configuration pin of the power manager 2 outputs a configuration signal corresponding to the second level. Assuming that the second level corresponds to the second memory, upon receiving the configuration signal corresponding to the second level, the baseband processor 3 performs subsequent processing according to the pin configuration mode of the second memory.

[0057] In certain embodiments, taking the case where the first memory is an eMCP memory including a controller, the second memory is an nMCP memory, the first level is a high level, and the second level is a low level as an example, the enable pin is pulled up to a high level of 1.8V by a 10K resistor in the first resistor module by default, and is pulled to a low level through a classified resistor connected to a 1K resistor in an external second resistor module. When the enable pin is high, the configuration pin outputs a high level, and the baseband processor 3 is configured as an eMMC interface. When the enable pin is pulled low, the configuration pin outputs a low level, and the baseband processor 3 is configured as a NAND interface.

[0058] In certain embodiments, the second resistance module includes a classification resistor R, which can be a jumper resistor. When the communication device is replaced by an nMCP memory with an eMCP memory, it is only necessary to remove the jumper resistor R to achieve a compatible design of the eMCP memory and the nMCP memory without changing other circuits. It can be understood that when the second resistance module includes a jumper resistor R, the enable pin is at a low level, and the configuration pin outputs a low-level configuration signal. The baseband processor 3 is configured as a NAND interface and is compatible with the nMCP memory. If the jumper resistor in the second resistance module is removed, the enable pin is pulled to a high level, and the configuration pin outputs a high-level configuration signal. The baseband processor 3 is configured as an eMMC interface and is compatible with the eMCP memory.

[0059] In some embodiments, the second resistor module may also include a classification resistor and a switch, one end of the classification resistor and the switch being connected in series is grounded, and the other end is connected to the enable pin. By setting the switch to be on or off, the classification resistor is controlled to be connected or disconnected to the enable pin.

[0060] In some embodiments, the power manager 2 includes a plurality of power output pins, each of which is connected to a power pin of the current memory 1, and each power output pin outputs a different power supply voltage;

[0061] The power manager 2 is configured to determine the category of the current memory 1, determine the target power supply pin among all power supply output pins according to the category, control the target power supply pin to output the power supply voltage, and control the power supply output pins of non-target power supply pins not to output the power supply voltage.

[0062] In this embodiment, the target memory includes nMCP memory and eMCP memory as an example for explanation. The power manager 2 can provide two power supplies for NAND / eMMC. The power manager 22 includes a power supply output pin VOUT1 and a power supply output pin VOUT2. VOUT1 outputs 1.8V to the VCC / VCCQM pin of the current memory 1 to supply the NAND and eMMC controllers. It is turned on by default. VOUT2 is enabled by the enable pin. When the enable pin is high, VOUT2 outputs 3V power supply voltage to the VCCM pin of the current memory 1 to power the eMMC. When the enable pin is pulled low, VOUT2 is turned off and no output is made.

[0063] In certain embodiments, the memory-compatible system further comprises:

[0064] The voltage stabilizing capacitor connected to the current memory 1 is configured to regulate the output voltage of the core voltage regulator when the current memory 1 is provided with a core voltage regulator.

[0065] In certain embodiments, the current memory 1 includes an NC / VDDIM pin, to which an external voltage-stabilizing capacitor is connected, and is configured to provide a voltage-stabilizing capacitor to the core regulator inside the eMCP to stabilize the output voltage of the core regulator to a regulated value, thereby achieving seamless compatibility between memories using nMCP and memories using eMCP on the communication module.

[0066] In certain embodiments, the baseband processor 3 includes a selection switch component and multiple interfaces, each interface includes configuration information of the distinguishing pins of its corresponding target memory, each first end of the selection switch component is connected to each interface one-to-one, the second end of the selection switch component is connected to the current memory 1, and the selection switch component is configured to connect the interface corresponding to the category according to the category.

[0067] In certain embodiments, the selector switch assembly includes a plurality of single-pole, multi-throw switches.

[0068] 4 is a schematic diagram of the structure of a baseband processor 3 provided in another embodiment of the present disclosure, and the target memory includes an nMCP memory and an eMCP memory as an example for explanation. The NAND / eMMC in the baseband processor 3 The AUX module is provided with an eMMC interface corresponding to the eMCP memory and a NAND interface corresponding to the nMCP memory. The eMMC interface includes configuration information of each distinguishing pin of the eMCP memory, and the NAND interface includes configuration information of each distinguishing pin of the nMCP memory. The selection switch component includes multiple single-pole multi-throw switches, and the number of single-pole multi-throw switches is determined by the number of distinguishing pins in each interface. For example, in Figure 4, both interfaces include 15 distinguishing pins, and the selection switch component includes 15 single-pole double-throw switches. It is assumed that each distinguishing pin of the eMMC interface is connected to the first end of the single-pole double-throw switch in a one-to-one correspondence, and each distinguishing pin of the NAND interface is connected to the second end of the single-pole double-throw switch in a one-to-one correspondence, and the third end of the single-pole double-throw switch is connected to the current memory 1. The selection switch component adjusts the first end of each single-pole double-throw switch to connect to the third end, or the second end to the third end according to the category of the current memory 1, so that the eMMC interface and the current memory 1 can be selectively connected, or the NAND interface and the current memory 1 can be selectively connected. In Figure 4, NAND# / eMMC is the control pin of a multi-way single-pole double-throw switch. By default, NAND# / eMMC is high, and the external common signal switches to the NAND signal, at which point an external NAND device is connected. When NAND# / eMMC is pulled low, the external common signal switches to the eMMC signal, at which point an external eMMC device is connected. This disclosure integrates the NAND / eMMC switching circuit into the baseband, achieving a compatible design for NAND and eMMC devices without increasing PCB area.

[0069] In summary, the present disclosure achieves seamless compatibility between nMCP memory and eMCP memory on wireless communication modules through the NAND / eMMC AUX pin multiplexing design inside the above chip, combined with the power enable design of the external PMU and the external voltage-stabilizing capacitor design of the VDDIM pin of the nMCP / eMCP device. When changing from eMCP memory to nMCP memory, it is only necessary to remove the classification resistors in the second resistor module to achieve the compatible design of the device without the need for other circuit changes. The present disclosure does not increase the PCB area, does not increase the complexity of the device and PCB routing, does not affect the EMC performance of the PCB, and normalizes the PCB of the module product, greatly reducing the R&D investment and product certification costs.

[0070] On the other hand, the present disclosure also provides an electronic device including the memory-compatible system described in the present disclosure.

[0071] For an introduction to the electronic device provided by the present disclosure, please refer to the above embodiments, and the present disclosure will not go into details here.

[0072] The electronic device provided by the present disclosure has the same beneficial effects as the above-mentioned memory-compatible system.

[0073] In another aspect, the present disclosure further provides a memory compatibility method, which is applied to the memory compatibility system described in the present disclosure. The memory compatibility method includes:

[0074] Determine the type of the current memory through the power manager, determine the power supply requirement of the current memory according to the type, and output the power supply voltage to the current memory according to the power supply requirement;

[0075] Determine the category of the current memory through the baseband processor, determine the current configuration information of the distinguishing pins of the current memory according to the category, and process the signal interacting with the current memory according to the current configuration information;

[0076] The current memory is any type of target memory. The number of pins of each type of target memory is the same. The pins include distinguishing pins. The distinguishing pins are pins of each type of target memory that are in the same position but have different configuration information.

[0077] For an introduction to the memory compatibility method provided by the present disclosure, please refer to the above embodiments, and the present disclosure will not elaborate on them here.

[0078] The memory compatibility method provided by the present disclosure has the same beneficial effects as the above-mentioned memory compatibility system.

[0079] It should also be noted that, in this specification, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element.

[0080] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present disclosure. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure is not limited to the embodiments shown herein, but is intended to be embodied in the widest possible manner consistent with the principles and novel features disclosed herein.

Claims

1. A memory compatible system comprising: Current memory; The current memory is any type of target memory, each type of the target memory has the same number of pins, and the pins include distinguishing pins, and the distinguishing pins are the pins of each type of the target memory that are in the same position and have different configuration information; A power manager is configured to determine a category of the current memory, determine a power supply requirement of the current memory according to the category, and output a power supply voltage to the current memory according to the power supply requirement; as well as The baseband processor is configured to determine the category of the current memory, determine the current configuration information of the distinguishing pins of the current memory according to the category, and process the signal interacting with the current memory according to the current configuration information.

2. The memory compatible system according to claim 1, wherein: The power manager is further configured to output a configuration signal according to the category of the current memory; as well as The baseband processor is configured to determine the category of the current memory according to the configuration signal.

3. The memory compatible system according to claim 1 or 2, wherein: The power manager includes an enable pin, the enable pin is selectively connected to a classification resistor to adjust a current level of the enable pin, the current level is configured to indicate the category of the current memory; The power manager is configured to output a configuration signal according to a current level of the enable pin.

4. The memory compatible system according to claim 3, wherein: The classified resistor is a jumper resistor.

5. The memory compatible system according to any one of claims 1 to 4, wherein: The power manager comprises a plurality of power supply output pins, each of which is connected to a power supply pin of the current memory, and each of which outputs a different power supply voltage; The power manager is configured to determine the category of the current memory, determine a target power pin among all the power output pins according to the category, control the target power pin to output a power voltage, and control the power output pins other than the target power pin to not output a power voltage.

6. The memory compatible system according to any one of claims 1 to 5, further comprising: The voltage stabilizing capacitor connected to the current memory is configured to adjust the output voltage of the core voltage regulator when the current memory is provided with a core voltage regulator.

7. The memory compatible system according to any one of claims 1 to 6, wherein: The baseband processor includes a selection switch component and multiple interfaces, each of the interfaces includes configuration information of the distinguishing pins of the corresponding target memory, each first end of the selection switch component is connected to each interface one-to-one, and the second end of the selection switch component is connected to the current memory. The selection switch component is configured to connect the interface corresponding to the category to the current memory according to the category.

8. The memory compatible system according to claim 7, wherein: The selector switch assembly includes a plurality of single-pole multi-throw switches.

9. Electronic equipment comprising the memory compatible system according to any one of claims 1 to 8.

10. A memory compatibility method, applied to the memory compatibility system according to any one of claims 1 to 8, the memory compatibility method comprising: Determine the category of the current memory through the power manager, determine the power supply requirement of the current memory according to the category, and output the power supply voltage to the current memory according to the power supply requirement; Determine the category of the current memory by the baseband processor, and determine current configuration information of the distinguishing pins of the current memory, and processing the signal interacting with the current memory according to the current configuration information, The current memory is any type of target memory, each type of the target memory has the same number of pins, and the pins include distinguishing pins, which are pins in the same position and with different configuration information for each type of the target memory.

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