Pixel driving circuit and driving method therefor, and display substrate and display

Abstract

A pixel driving circuit and a driving method therefor, a display substrate, and a display. The pixel driving circuit comprises: a reset sensing sub-circuit, a driving sub-circuit, a node control sub-circuit and a light-emitting control sub-circuit, wherein the driving sub-circuit is configured to provide a driving signal to a third node under the control of a signal of a first node and a signal of a second node; the reset sensing sub-circuit is configured to provide, under the control of a signal of a reset signal end and a signal of a sensing control signal end, to the third node a reference signal provided by a control signal end, or to the control signal end the signal of the first node or a signal of the third node; the node control sub-circuit is configured to provide a signal of a data signal end to the first node under the control of a signal of a scanning signal end, and to store a voltage difference between the signal of the first node and a signal of a first power source end; and the light-emitting control sub-circuit is configured to provide the signal of the first power source end to the second node under the control of a signal of a light-emitting control signal end.

Description

Pixel driving circuit and driving method thereof, display substrate and display device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on October 31, 2023, with application number 202311437743.0 and invention name “Pixel driving circuit and driving method thereof, display substrate and display device”, the contents of which should be understood as incorporated into this application by reference. Technical Field

[0002] The present disclosure relates to, but is not limited to, the field of display technology, and in particular to a pixel driving circuit and a driving method thereof, a display substrate, and a display device. Background Art

[0003] Organic Light Emitting Diodes (OLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, and extremely high response speeds. With the continuous development of display technology, flexible displays using OLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become the mainstream products in the current display field.

[0004] Currently, the concept of full-screen mobile phones has attracted widespread attention in the mobile phone market and is also the future development direction of mobile phones. In such full-screen mobile phones, the camera can be hidden so that the front viewing area is almost entirely screen, thus providing users with a better display effect.

[0005] Summary of the Invention

[0006] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0007] In a first aspect, the present disclosure provides a pixel driving circuit configured to drive a light-emitting device to emit light, comprising: a reset sensing subcircuit, a driving subcircuit, a node control subcircuit, and a light-emitting control subcircuit;

[0008] The driving sub-circuit is electrically connected to the first node, the second node and the third node respectively, and is configured to provide a driving signal to the third node under the control of the signals of the first node and the second node;

[0009] The reset sensing sub-circuit is electrically connected to the sensing control signal terminal, the reset signal terminal, the control signal terminal, the first node, and the third node, respectively, and is configured to provide the reference signal provided by the control signal terminal to the third node, or provide the signal of the first node or the third node to the control signal terminal, under the control of the signals of the reset signal terminal and the sensing control signal terminal;

[0010] The node control subcircuit is electrically connected to the scan signal terminal, the data signal terminal, the first node, and the first power supply terminal, respectively, and is configured to provide the signal of the data signal terminal to the first node under the control of the signal of the scan signal terminal, and store the voltage difference between the signal of the first node and the signal of the first power supply terminal;

[0011] The light emitting control subcircuit is electrically connected to the light emitting control signal terminal, the first power terminal and the second node respectively, and is configured to provide the signal of the first power terminal to the second node under the control of the signal of the light emitting control signal terminal;

[0012] The light emitting device is electrically connected to the third node and the second power supply terminal respectively.

[0013] In an exemplary embodiment, the reset sensing subcircuit includes: a first sensing subcircuit and a second sensing subcircuit;

[0014] The first sensing sub-circuit is electrically connected to the reset signal terminal, the control signal terminal, and the third node, respectively, and is configured to provide the reference signal provided by the control signal terminal to the third node, or provide the signal of the third node to the control signal terminal, under the control of the signal of the reset signal terminal;

[0015] The second sensing sub-circuit is electrically connected to the sensing control signal terminal, the control signal terminal and the first node respectively, and is configured to provide the signal of the first node to the control signal terminal under the control of the signal of the sensing control signal terminal.

[0016] In an exemplary embodiment, the first sensing sub-circuit includes: a first transistor, and the second sensing sub-circuit includes: a second transistor;

[0017] The gate electrode of the first transistor is electrically connected to the reset signal terminal, the first electrode of the first transistor is electrically connected to the control signal terminal, and the second electrode of the first transistor is electrically connected to the third node;

[0018] A gate electrode of the second transistor is electrically connected to the sensing control signal terminal, a first electrode of the second transistor is connected to the control signal terminal, and a second electrode of the second transistor is electrically connected to the first node.

[0019] In an exemplary embodiment, the reset sensing subcircuit includes: a first transistor and a second transistor, the driving subcircuit includes: a third transistor, the node control subcircuit includes: a fourth transistor and a capacitor, the capacitor includes: a first plate and a second plate, and the light emitting control subcircuit includes: a fifth transistor;

[0020] The gate electrode of the first transistor is electrically connected to the reset signal terminal, the first electrode of the first transistor is electrically connected to the control signal terminal, and the second electrode of the first transistor is electrically connected to the third node;

[0021] The gate electrode of the second transistor is electrically connected to the sensing control signal terminal, the first electrode of the second transistor is connected to the control signal terminal, and the second electrode of the second transistor is electrically connected to the first node;

[0022] The gate electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node;

[0023] The gate electrode of the fourth transistor is electrically connected to the scan signal terminal, the first electrode of the fourth transistor is electrically connected to the data signal terminal, and the second electrode of the fourth transistor is electrically connected to the first node;

[0024] The gate electrode of the fifth transistor is electrically connected to the light emitting control signal terminal, the first electrode of the fifth transistor is connected to the first power supply terminal, and the second electrode of the fifth transistor is electrically connected to the second node;

[0025] The first plate of the capacitor is connected to the first node, and the second plate of the capacitor is electrically connected to the first power supply terminal.

[0026] In an exemplary embodiment, the first transistor, the second transistor, and the fourth transistor are N-type transistors, and the third transistor and the fifth transistor are P-type transistors.

[0027] In a second aspect, the present disclosure further provides a driving method for a pixel driving circuit, configured to drive the above-mentioned pixel driving circuit, wherein the pixel driving circuit is provided in a display substrate, and the operation process of the display substrate includes: a display phase and a non-display phase;

[0028] In the display stage and the non-display stage, the driving method of the pixel driving circuit includes:

[0029] The driving sub-circuit provides a driving signal to the third node under the control of the signals of the first node and the second node;

[0030] The reset sensing sub-circuit provides the reference signal provided by the control signal terminal to the third node, or provides the signal of the first node or the third node to the control signal terminal under the control of the signals of the reset signal terminal and the sensing control signal terminal;

[0031] The node control subcircuit provides the signal of the data signal terminal to the first node under the control of the signal of the scan signal terminal, and stores the voltage difference between the signal of the first node and the signal of the first power terminal;

[0032] The light emitting control sub-circuit provides the signal of the first power supply terminal to the second node under the control of the signal of the light emitting control signal terminal.

[0033] In an exemplary embodiment, the display phase includes: a first reset phase, a first data writing phase, and a light emitting phase;

[0034] The signal of the sensing control signal end in the display phase is an invalid level signal, the signal of the reset signal end in the first reset phase is an effective level signal, and the signal in the first data writing phase and the light emitting phase is an invalid level signal, the signal of the scanning signal end in the first data writing phase is an effective level signal, and the signal in the first reset phase and the light emitting phase is an invalid level signal, the signal of the light emitting control signal end in the light emitting phase is an effective level signal, and the signal in the first reset phase and the first data writing phase is an invalid level signal;

[0035] In the display stage, the driving method of the pixel driving circuit includes:

[0036] In the first reset phase, the reset sensing sub-circuit provides the reference signal provided by the control signal terminal to the third node under the control of the signal of the reset signal terminal;

[0037] In the first data writing phase, the node control subcircuit provides the signal of the data signal terminal to the first node under the control of the signal of the scan signal terminal, and stores the voltage difference between the signal of the first node and the signal of the first power terminal;

[0038] In the light-emitting stage, the light-emitting control subcircuit provides the signal of the first power supply end to the second node under the control of the signal of the light-emitting control signal end, and the driving subcircuit provides the driving signal to the third node under the control of the signals of the first node and the second node.

[0039] In an exemplary embodiment, the non-display phase includes: a first sensing phase, the first sensing phase occurring before the display phase, the first sensing phase including: a second reset phase, a second data writing phase, and a first sampling phase;

[0040] The signal of the sensing control signal end in the first sensing stage is an invalid level signal, the signal of the reset signal end in the second reset stage and the first sampling stage is a valid level signal, and the signal in the second data writing stage is an invalid level signal, the signal of the scanning signal end in the second data writing stage is a valid level signal, and the signal in the second reset stage and the first sampling stage is an invalid level signal, the signal of the light emitting control signal end in the first sampling stage is a valid level signal, and the signal in the second reset stage and the second data writing stage is an invalid level signal.

[0041] In the first sensing stage, the driving method of the pixel driving circuit includes:

[0042] In the second reset phase, the reset sensing sub-circuit provides the reference signal provided by the control signal terminal to the third node under the control of the signal of the reset signal terminal;

[0043] In the second data writing phase, the node control subcircuit provides the signal of the data signal terminal to the first node under the control of the signal of the scan signal terminal, and stores the voltage difference between the signal of the first node and the signal of the first power terminal;

[0044] In the first sampling phase, the light-emitting control subcircuit provides the signal of the first power supply terminal to the second node under the control of the signal of the light-emitting control signal terminal, the driving subcircuit provides the driving signal to the third node under the control of the signals of the first node and the second node, and the reset sensing subcircuit provides the signal of the third node to the control signal terminal under the control of the signal of the reset signal terminal.

[0045] In an exemplary embodiment, the display substrate further includes: an integrated circuit electrically connected to the pixel driving circuit;

[0046] The integrated circuit obtains the signal of the third node, processes the signal of the third node, and provides the processed signal of the third node to the pixel driving circuit to compensate for the brightness of the light emitting device.

[0047] In an exemplary embodiment, the non-display phase includes: a second sensing phase, the second sensing phase occurs before the display phase, the second sensing phase includes: a third reset phase, a third data writing phase, and a second sampling phase;

[0048] The signal of the reset signal terminal in the third reset phase is a valid level signal, and the signal of the reset signal terminal in the third data writing phase and the second sampling phase is an invalid level signal. The signal of the scan signal terminal in the third data writing phase is a valid level signal, and the signal of the scan signal terminal in the third data writing phase is an invalid level signal. The signal of the light emitting control signal terminal in the second sampling phase is a valid level signal, and the signal of the light emitting control signal terminal in the third reset phase and the third data writing phase is an invalid level signal. The signal of the sensing control signal terminal in the second sampling phase is a valid level signal, and the signal of the sensing control signal terminal in the third reset phase and the third data writing phase is an invalid level signal.

[0049] In the second sensing stage, the driving method of the pixel driving circuit includes:

[0050] In the third reset phase, the reset sensing sub-circuit provides the reference signal provided by the control signal terminal to the third node under the control of the signal from the reset signal terminal;

[0051] In the third data writing phase, the node control subcircuit provides the signal of the data signal terminal to the first node under the control of the signal of the scan signal terminal, and stores the voltage difference between the signal of the first node and the signal of the first power terminal;

[0052] In the second sampling phase, the light-emitting control subcircuit provides the signal of the first power supply terminal to the second node under the control of the signal of the light-emitting control signal terminal, the driving subcircuit provides the driving signal to the third node under the control of the signals of the first node and the second node, and the reset sensing subcircuit provides the signal of the first node to the control signal terminal under the control of the signal of the sensing control signal terminal.

[0053] In an exemplary embodiment, the display substrate further includes: an integrated circuit electrically connected to the pixel driving circuit;

[0054] The integrated circuit obtains the signal of the first node, processes the signal of the first node, and provides the processed signal of the first node to the pixel driving circuit to compensate for the threshold voltage of the driving transistor in the pixel driving circuit.

[0055] In a third aspect, the present disclosure further provides a display substrate, comprising: a base, the base comprising: a display area and a non-display area surrounding the display area, the display area comprising: a first display area and a second display area, the second display area being located on at least one side of the first display area;

[0056] The first display area includes: a plurality of first sub-pixels, the second display area includes: a plurality of second sub-pixels, and at least one of the first sub-pixels and the second sub-pixels includes: the pixel driving circuit according to any one of claims 1 to 5.

[0057] In an exemplary embodiment, the pixel driving circuit includes: at least one P-type transistor and at least one N-type transistor;

[0058] An orthographic projection of the at least one P-type transistor on the substrate at least partially overlaps with an orthographic projection of the at least one N-type transistor on the substrate.

[0059] In an exemplary embodiment, the transistor includes an active pattern, and an orthographic projection of the active pattern of the at least one N-type transistor on the substrate at least partially overlaps with an orthographic projection of the active pattern of the at least one P-type transistor on the substrate.

[0060] In an exemplary embodiment, an orthographic projection of the active pattern of the at least one N-type transistor on the substrate is located within an orthographic projection of the active pattern of the at least one P-type transistor on the substrate.

[0061] In an exemplary embodiment, the display area further includes: at least one first power line;

[0062] The orthographic projection of the first power line on the substrate at least partially overlaps with the orthographic projection of the active pattern of the at least one P-type transistor on the substrate, and the orthographic projection of the first power line on the substrate at least partially overlaps with the orthographic projection of the active pattern of the at least one N-type transistor on the substrate;

[0063] The active pattern of the at least one P-type transistor is located on a side of the first power line close to the substrate, and the active pattern of the at least one N-type transistor is located on a side of the first power line away from the substrate.

[0064] In an exemplary embodiment, the display area further includes: pixel units arranged in an array, at least one light emitting control signal line, at least one reset signal line, at least one scanning signal line, at least one sensing control signal line, at least one data signal line, at least one control signal line, and at least one first power supply line, at least one pixel unit including: at least one sub-pixel arranged along the first direction;

[0065] The at least one pixel unit is electrically connected to the light emitting control signal line, the reset signal line, the scanning signal line, the sensing control signal line, N data signal lines, N control signal lines and N first power lines, respectively, where N is the number of sub-pixels in a pixel unit.

[0066] In an exemplary embodiment, pixel structures of adjacent sub-pixels among the plurality of sub-pixels arranged along the first direction are at least partially symmetrically arranged with respect to a virtual straight line extending along a second direction, and the first direction and the second direction intersect.

[0067] In an exemplary embodiment, the display area further includes: at least one data signal line and at least one control signal line, the data signal line and the control signal line at least partially extending along the second direction;

[0068] The data signal line is electrically connected to the data signal terminal connected to the pixel driving circuit, and the control signal line is electrically connected to the control signal terminal connected to the pixel driving circuit;

[0069] The data signal lines connecting adjacent sub-pixels among the multiple sub-pixels arranged along the first direction are symmetrically arranged relative to the center line of the adjacent sub-pixels, and the control signal lines connecting adjacent sub-pixels among the multiple sub-pixels arranged along the first direction are symmetrically arranged relative to the center line of the adjacent sub-pixels.

[0070] In an exemplary embodiment, the display area further includes: at least one first power line; the first power line at least partially extending along the second direction;

[0071] The first power line is electrically connected to the first power end connected to the pixel driving circuit, adjacent first power lines are electrically connected, and the first power lines connected to adjacent sub-pixels in a plurality of sub-pixels arranged along the first direction are symmetrically arranged relative to the center line of the adjacent sub-pixels.

[0072] In an exemplary embodiment, the first power line includes: a first connecting line, a second connecting line, and a plurality of connecting blocks, the first connecting line and the second connecting line are arranged along a first direction and extend along a second direction, the connecting block is provided between the first connecting line and the second connecting line, and the pixel driving circuit includes: a capacitor, the capacitor including: a first electrode plate and a second electrode plate;

[0073] The orthographic projection of the connecting block on the substrate at least partially overlaps with the orthographic projection of the first electrode plate on the substrate, and the multiple connecting blocks located between the first connecting line and the second connecting line are arranged along the second direction and are spaced apart, and a closed area is formed between adjacent connecting blocks arranged along the second direction and adjacent first connecting lines and second connecting lines.

[0074] In an exemplary embodiment, the display area further includes: at least one light emitting control signal line, at least one reset signal line, at least one scan signal line, and at least one sensing control signal line, wherein at least one of the light emitting control signal line, the reset signal line, the scan signal line, and the sensing control signal line extends at least partially along the first direction;

[0075] The light emitting control signal line is electrically connected to the light emitting control signal terminal connected to the pixel driving circuit, the reset signal line is electrically connected to the reset signal terminal connected to the pixel driving circuit, the scanning signal line is electrically connected to the scanning signal terminal connected to the pixel driving circuit, and the sensing control signal line is electrically connected to the sensing control signal terminal connected to the pixel driving circuit;

[0076] The orthographic projections of the light emitting control signal line, the scanning signal line, the sensing control signal line, and the reset signal line connected to at least one sub-pixel on the substrate are arranged in sequence along the second direction;

[0077] The light emitting control signal line is provided in a different layer from at least one of the reset signal line, the scanning signal line, and the sensing control signal line.

[0078] In an exemplary embodiment, the present invention further includes: a driving structure layer provided on the substrate, the driving structure layer being provided with an anode connection line, a light emitting control signal line, a reset signal line, a scanning signal line, a sensing control signal line, a first power line, a data signal line, a control signal line, and the pixel driving circuit, the driving structure layer at least comprising: a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, and a fourth conductive layer stacked in sequence in a direction away from the substrate, the pixel driving circuit comprising: at least one P-type transistor, at least one N-type transistor, and a capacitor, the transistor comprising: an active pattern, a gate electrode, a first electrode, and a second electrode, the capacitor comprising: a first electrode plate and a second electrode plate;

[0079] The first semiconductor layer includes at least: the active pattern of the at least one P-type transistor located in at least one sub-pixel;

[0080] The first conductive layer at least includes: the light emitting control signal line, the gate electrode of the at least one P-type transistor located in at least one sub-pixel, and the first plate of the capacitor;

[0081] The second conductive layer at least includes: the first power line, the second plate of the capacitor located in at least one sub-pixel, and the first and second electrodes of the at least one P-type transistor;

[0082] The second semiconductor layer includes at least: an active pattern of the at least one N-type transistor located in at least one sub-pixel;

[0083] The third conductive layer at least includes: the reset signal line, the scan signal line, the sensing control signal line, and the gate electrode, the first electrode, and the second electrode of the at least one N-type transistor located in at least one sub-pixel;

[0084] The fourth conductive layer at least includes: the data signal line, the control signal line, and the anode connection line located in at least one sub-pixel.

[0085] In an exemplary embodiment, at least a portion of at least one of the data signal line and the control signal line is a transparent conductive signal line.

[0086] In an exemplary embodiment, the present invention further includes: a light emitting structure layer located on a side of the driving structure layer away from the substrate, the light emitting structure layer including: a fifth conductive layer and a pixel definition layer sequentially stacked on the substrate, the fifth conductive layer including at least: a first electrode of the light emitting device, the pixel definition layer being provided with a plurality of pixel openings, the pixel openings including: a first pixel opening, a second pixel opening, and a third pixel opening;

[0087] The light emitting device comprises: a first light emitting device, a second light emitting device and a third light emitting device, wherein the first light emitting device, the second light emitting device and the third light emitting device emit light of different colors;

[0088] The first pixel opening exposes the first electrode of the first light emitting device, the second pixel opening exposes the first electrode of the second light emitting device, and the third pixel opening exposes the first electrode of the third light emitting device;

[0089] The area of ​​the first pixel opening located in the first display area is smaller than the area of ​​the first pixel opening located in the second display area, the area of ​​the second pixel opening located in the first display area is smaller than the area of ​​the second pixel opening located in the second display area, and the area of ​​the third pixel opening located in the first display area is smaller than the area of ​​the third pixel opening located in the second display area.

[0090] In an exemplary embodiment, the light transmittance of the first display area is greater than the light transmittance of the second display area, and the sub-pixel density of the first display area is less than or equal to the sub-pixel density of the second display area.

[0091] In a fourth aspect, the present disclosure further provides a display device comprising the above-mentioned display substrate and a light-sensitive sensor;

[0092] The orthographic projection of the photosensor on the substrate at least partially overlaps with the first display area.

[0093] Summary of the Figures

[0094] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0095] FIG1 is a schematic structural diagram of a pixel driving circuit provided by an embodiment of the present disclosure;

[0096] FIG2A is a schematic structural diagram of a pixel driving circuit provided in an exemplary embodiment;

[0097] FIG2B is an equivalent circuit diagram of the first inductive sub-circuit and the second inductive sub-circuit;

[0098] FIG3 is an equivalent circuit diagram of a pixel driving circuit;

[0099] FIG4A is a timing diagram of the operation of the pixel driving circuit provided in FIG3 during the display phase;

[0100] FIG4B is a timing diagram of the operation of the pixel driving circuit provided in FIG3 in the first sensing phase;

[0101] FIG4C is an operation timing diagram of the pixel driving circuit provided in FIG3 during the second sensing phase;

[0102] FIG5A is a schematic structural diagram of a display substrate;

[0103] FIG5B is a partial schematic diagram of the first display area in FIG5A ;

[0104] FIG5C is a partial schematic diagram of the second display area in FIG5A ;

[0105] FIG6A is a schematic diagram 1 of a portion of film layers in a display substrate provided in FIG5B and FIG5C ;

[0106] FIG6B is a second schematic diagram of a portion of the film layer in the display substrate provided in FIG5B and FIG5C ;

[0107] FIG7 is a schematic diagram of a pattern of a first semiconductor layer;

[0108] FIG8 is a schematic diagram of a first conductive layer pattern;

[0109] FIG9 is a schematic diagram after forming a first conductive layer pattern;

[0110] FIG10 is a schematic diagram after forming a second insulating layer;

[0111] FIG11 is a schematic diagram of a second conductive layer pattern;

[0112] FIG12 is a schematic diagram after forming a second conductive layer pattern;

[0113] FIG13 is a schematic diagram after forming a third insulating layer;

[0114] FIG14 is a schematic diagram of a second semiconductor layer pattern;

[0115] FIG15 is a schematic diagram after forming a second semiconductor layer pattern;

[0116] FIG16 is a schematic diagram after forming a fourth insulating layer;

[0117] FIG17 is a schematic diagram of a pattern of a third conductive layer;

[0118] FIG18 is a schematic diagram after forming a third conductive layer pattern;

[0119] FIG19 is a schematic diagram after forming a first planar layer;

[0120] FIG20 is a schematic diagram of a fourth conductive layer pattern;

[0121] FIG21 is a schematic diagram after forming a fourth conductive layer pattern;

[0122] FIG22 is a schematic diagram after forming a second planar layer;

[0123] FIG23 is a schematic diagram of a fifth conductive layer pattern;

[0124] FIG24 is a schematic diagram after forming a fifth conductive layer pattern;

[0125] FIG25 is a schematic diagram after forming a pixel definition layer;

[0126] FIG26 is a cross-sectional view of a display device.

[0127] Details

[0128] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. Unless there is a conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of some known functions and known components. The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure. Other structures can refer to the general design

[0129] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to this. For example, the width-to-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixel units in the display substrate and the number of sub-pixels in each pixel unit are not limited to the numbers shown in the figures. The figures described in this disclosure are only structural schematics, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the figures.

[0130] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0131] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0132] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0133] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0134] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" may be interchanged.

[0135] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0136] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0137] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0138] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures using the same patterning process. The materials of these structures can be the same or different. For example, the precursor materials for forming the multiple structures arranged in the same layer can be the same, and the materials of the final structures can be the same or different.

[0139] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0140] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0141] Full-screen display products include: a translucent display area and a normal display area. In order to ensure the transmittance of the translucent display area of ​​the full-screen display product, the pixel circuits and pixel openings located in the translucent display area are compressed, which not only results in poor display effects of the display product, but also reduces the lifespan of the display product.

[0142] FIG1 is a schematic diagram of the structure of a pixel driving circuit provided by an embodiment of the present disclosure. As shown in FIG1 , the pixel driving circuit provided by an embodiment of the present disclosure is configured to drive the light-emitting device to emit light, and may include: a reset sensing subcircuit, a driving subcircuit, a node control subcircuit, and a light-emitting control subcircuit. The driving subcircuit is electrically connected to the first node N1, the second node N2, and the third node N3, respectively, and is configured to provide a driving signal to the third node N3 under the control of the signals of the first node N1 and the second node N2; the reset sensing subcircuit is electrically connected to the sensing control signal terminal SW-SENSE, the reset signal terminal Reset, the control signal terminal CON, the first node N1, and the third node N3, respectively, and is configured to provide the reference signal provided by the control signal terminal CON to the third node N3 under the control of the signals of the reset signal terminal Reset and the sensing control signal terminal SW-SENSE, or to provide the signal of the first node N1 or the third node N3 to the control signal terminal CON. signal; a node control sub-circuit, electrically connected to the scan signal terminal Gate, the data signal terminal Data, the first node N1 and the first power supply terminal VDD, respectively, and configured to provide the signal of the data signal terminal Data to the first node N1 under the control of the signal of the scan signal terminal Gate, and store the voltage difference between the signal of the first node N1 and the signal of the first power supply terminal VDD; a light-emitting control sub-circuit, electrically connected to the light-emitting control signal terminal EM, the first power supply terminal VDD and the second node N2, respectively, and configured to provide the signal of the first power supply terminal VDD to the second node N2 under the control of the signal of the light-emitting control signal terminal EM; a light-emitting device, electrically connected to the third node N3 and the second power supply terminal VSS, respectively.

[0143] In an exemplary embodiment, the light emitting device may include a stacked first electrode (anode), an organic light emitting layer, and a second electrode (cathode). Exemplarily, the anode of the light emitting device is electrically connected to the third node N3, and the cathode of the light emitting device is electrically connected to the second power supply terminal VSS.

[0144] In an exemplary embodiment, the light-emitting device may include a current-driven device, and a current-driven light-emitting diode may be used, such as a micro light-emitting diode (Micro LED), a mini light-emitting diode (Mini LED), an organic light-emitting diode (OLED), or a quantum dot light-emitting diode (QLED). A typical size (e.g., length) of a Micro LED may be less than 100 μm, for example, 10 μm to 50 μm. A typical size (e.g., length) of a Mini LED may be approximately 100 μm to 300 μm, for example, 120 μm to 260 μm.

[0145] In an exemplary embodiment, the organic light-emitting layer may include a stacked hole injection layer (HIL), a hole transport layer (HTL), an electron block layer (EBL), an emitting layer (EML), a hole block layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, the hole injection layers of all sub-pixels may be a common layer connected together, the electron injection layers of all sub-pixels may be a common layer connected together, the hole transport layers of all sub-pixels may be a common layer connected together, the electron transport layers of all sub-pixels may be a common layer connected together, and the hole blocking layers of all sub-pixels may be a common layer connected together. The light-emitting layers of adjacent sub-pixels may have a small overlap or may be isolated, and the electron blocking layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0146] In an exemplary embodiment, the first power supply terminal VDD continuously provides a high-level signal, and the signal of the first power supply terminal VDD is a DC signal.

[0147] In an exemplary embodiment, the second power supply terminal VSS continuously provides a low-level signal, and the signal of the second power supply terminal VSS is a DC signal.

[0148] In an exemplary embodiment, the reference signal is a low-level signal and a DC signal. Exemplarily, the voltage of the reference signal may be 0V.

[0149] In an exemplary embodiment, the reset sensing sub-circuit provided by the present disclosure can provide a signal of the first node N1 or the third node N3 to the control signal terminal CON, so that the integrated circuit connected to the control signal terminal can obtain a signal of at least one of the first node N1 and the third node N3, obtain a threshold voltage of the driving transistor based on the signal of the first node, and perform external compensation on the pixel driving circuit based on the threshold voltage, and obtain a compensation voltage based on the signal of the third node and a device aging model, and perform external compensation on the pixel driving circuit based on the compensation voltage.

[0150] In an exemplary embodiment, the difference between the voltage value of the signal at the first power supply terminal VDD and the voltage value of the signal at the first node is equal to the threshold voltage of the threshold transistor. The device aging model is a data processing model stored in the display device where the pixel driving circuit is located.

[0151] In an exemplary embodiment, externally compensating the pixel driving circuit according to the threshold voltage may include adjusting a signal at a data signal terminal according to the threshold voltage, thereby externally compensating the pixel driving circuit.

[0152] In an exemplary embodiment, externally compensating the pixel driving circuit according to the compensation voltage may include adjusting a signal at the data signal terminal according to the compensation voltage, thereby externally compensating the pixel driving circuit.

[0153] The pixel driving circuit provided by the embodiment of the present disclosure is configured to drive the light-emitting device to emit light, and includes: a reset sensing subcircuit, a driving subcircuit, a node control subcircuit and a light-emitting control subcircuit; wherein the driving subcircuit is electrically connected to the first node, the second node and the third node respectively, and is configured to provide a driving signal to the third node under the control of the signals of the first node and the second node; the reset sensing subcircuit is electrically connected to the sensing control signal terminal, the reset signal terminal, the control signal terminal, the first node and the third node respectively, and is configured to provide a reference signal provided by the control signal terminal to the third node under the control of the signals of the reset signal terminal and the sensing control signal terminal. The present invention relates to a reset sensing subcircuit of the present invention, wherein the reset sensing subcircuit is electrically connected to the scanning signal terminal, the data signal terminal, the first node and the first power supply terminal, and is configured to provide the signal of the data signal terminal to the first node under the control of the signal of the scanning signal terminal, and store the voltage difference between the signal of the first node and the signal of the first power supply terminal; the light emitting control subcircuit is electrically connected to the light emitting control signal terminal, the first power supply terminal and the second node, and is configured to provide the signal of the first power supply terminal to the second node under the control of the signal of the light emitting control signal terminal; the light emitting device is electrically connected to the third node and the second power supply terminal. The control signal terminal in the reset sensing subcircuit of the present invention can not only provide a reference signal, but also obtain the parameters of the pixel driving circuit (such as the first node and the third node) to compensate the pixel driving circuit, which can reduce the number of devices in the pixel driving circuit, reduce the area occupied by the pixel driving circuit, and ensure that the pixel driving circuit is not affected by the threshold voltage, thereby avoiding the pixel driving circuit from being compressed in the full-screen display product, improving the display effect of the display product, and improving the display life of the display product.

[0154] In an exemplary embodiment, FIG2A is a schematic diagram of the structure of a pixel driving circuit provided in an exemplary embodiment. As shown in FIG2A , the reset sensing subcircuit in the pixel driving circuit may include: a first sensing subcircuit and a second sensing subcircuit. The first sensing subcircuit is electrically connected to the reset signal terminal Reset, the control signal terminal CON, and the third node N3, respectively, and is configured to provide a reference signal provided by the control signal terminal CON to the third node N3 or provide a signal from the third node N3 to the control signal terminal CON under the control of a signal from the reset signal terminal Reset. The second sensing subcircuit is electrically connected to the sensing control signal terminal SW-SENSE, the control signal terminal CON, and the first node N1, respectively, and is configured to provide a signal from the first node N1 to the control signal terminal CON under the control of a signal from the sensing control signal terminal SW-SENSE.

[0155] In an exemplary embodiment, the first sensing sub-circuit may obtain a signal at the third node, ie, the anode voltage of the light-emitting device, and thus may perform external compensation on the pixel driving circuit.

[0156] In an exemplary embodiment, the second sensing sub-circuit may obtain a signal of the first node, and thus may perform external compensation on the pixel driving circuit.

[0157] In an exemplary embodiment, Figure 2B is an equivalent circuit diagram of a first sensing sub-circuit and a second sensing sub-circuit. As shown in Figure 2B, the first sensing sub-circuit may include a first transistor T1, and the second sensing sub-circuit may include a second transistor T2. The gate electrode of the first transistor T1 is electrically connected to the reset signal terminal Reset, the first electrode of the first transistor T1 is electrically connected to the control signal terminal CON, and the second electrode of the first transistor T1 is electrically connected to the third node N3. The gate electrode of the second transistor T2 is electrically connected to the sensing control signal terminal SW-SENSE, the first electrode of the second transistor T2 is electrically connected to the control signal terminal CON, and the second electrode of the second transistor T2 is electrically connected to the first node N1.

[0158] FIG2B only shows an exemplary structure of the first inductive sub-circuit and the second inductive sub-circuit. Those skilled in the art will readily appreciate that the implementation of the first inductive sub-circuit and the second inductive sub-circuit is not limited thereto.

[0159] In an exemplary embodiment, FIG3 is an equivalent circuit diagram of a pixel driving circuit. As shown in FIG3 , the reset sensing subcircuit in the pixel driving circuit includes: a first transistor T1 and a second transistor T2, the driving subcircuit includes: a third transistor T3, the node control subcircuit includes: a fourth transistor T4 and a capacitor C, the capacitor C includes: a first plate and a second plate, and the light emitting control subcircuit includes: a fifth transistor T5. Among them, the gate electrode of the first transistor T1 is electrically connected to the reset signal terminal Reset, the first electrode of the first transistor T1 is electrically connected to the control signal terminal CON, and the second electrode of the first transistor T1 is electrically connected to the third node N3; the gate electrode of the second transistor T2 is electrically connected to the sensing control signal terminal SW-SENSE, the first electrode of the second transistor T2 is connected to the control signal terminal CON, and the second electrode of the second transistor T2 is electrically connected to the first node N1; the gate electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the third transistor T3 is electrically connected to the first node N1. A second electrode of the transistor T3 is electrically connected to the third node N3; a gate electrode of the fourth transistor T4 is electrically connected to the scan signal terminal Gate, a first electrode of the fourth transistor T4 is electrically connected to the data signal terminal Data, and a second electrode of the fourth transistor T4 is electrically connected to the first node N1; a gate electrode of the fifth transistor T5 is electrically connected to the light emitting control signal terminal EM, a first electrode of the fifth transistor T5 is connected to the first power supply terminal VDD, and a second electrode of the fifth transistor T5 is electrically connected to the second node N2; a first plate of the capacitor C is connected to the first node N1, and a second plate of the capacitor C is electrically connected to the first power supply terminal VDD.

[0160] Transistors can be divided into N-type transistors and P-type transistors according to their characteristics. When the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltages), and the turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltages). When the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltages), and the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltages).

[0161] In an exemplary embodiment, the first transistor T1, the second transistor T2, and the fourth transistor T4 are N-type transistors and are metal oxide transistors. In an exemplary embodiment, the N-type transistors may be oxide thin film transistors. The active pattern of the oxide thin film transistors uses an oxide semiconductor (Oxide). Oxide thin film transistors have advantages such as low leakage current.

[0162] In an exemplary embodiment, the third transistor T3 and the fifth transistor T5 are P-type transistors. In an exemplary embodiment, the P-type transistors may be low-temperature polysilicon transistors.

[0163] In an exemplary embodiment, the first transistor T1 , the second transistor T2 , and the fourth transistor T4 are N-type transistors, which can reduce leakage currents at the first node and the third node and improve the reliability of the pixel driving circuit.

[0164] In an exemplary embodiment, the pixel driving circuit may be disposed in a display substrate. The operation process of the display substrate includes a display phase and a non-display phase. The operation process of the pixel driving circuit in the non-display phase includes a first sensing phase and a second sensing phase. The first sensing phase and the second sensing phase occur before the display phase.

[0165] In an exemplary embodiment, the first sensing phase and the second sensing phase may occur simultaneously.

[0166] In an exemplary embodiment, the operation of the pixel driving circuit during the display phase includes: a first reset phase, a first data writing phase, and a light-emitting phase. The control signal terminal provides a reference signal during the display phase, and the signal at the sensing control signal terminal is an inactive signal during the display phase. The reset signal terminal provides an active signal during the first reset phase, and an inactive signal during the first data writing phase and the light-emitting phase. The scan signal terminal provides an active signal during the first data writing phase, and an inactive signal during the first reset phase and the light-emitting phase. The light-emitting control signal terminal provides an active signal during the light-emitting phase, and an inactive signal during the first reset phase and the first data writing phase.

[0167] In an exemplary embodiment, the operation of the pixel driving circuit during the first sensing phase includes: a second reset phase, a second data writing phase, and a first sampling phase. The control signal terminal provides a reference signal during the second reset phase and the second data writing phase, and obtains a signal at the third node during the first sampling phase. The signal at the sensing control signal terminal during the first sensing phase is an inactive signal. The signal at the reset signal terminal during the second reset phase and the first sampling phase is an active signal, and during the second data writing phase is an inactive signal. The signal at the scanning signal terminal during the second data writing phase is an active signal, and during the second reset phase and the first sampling phase is an inactive signal. The signal at the light emission control signal terminal during the first sampling phase is an active signal, and during the second reset phase and the second data writing phase is an inactive signal.

[0168] In an exemplary embodiment, the operation process of the pixel driving circuit in the second sensing phase includes: a third reset phase, a third data writing phase, and a second sampling phase. The control signal terminal provides a reference signal during the third reset phase and the third data writing phase, and obtains a signal at the first node during the second sampling phase. The signal at the reset signal terminal is a valid level signal during the third reset phase, and an invalid level signal during the third data writing phase and the second sampling phase. The signal at the scanning signal terminal is a valid level signal during the third data writing phase, and an invalid level signal during the third reset phase and the second sampling phase. The signal at the light-emitting control signal terminal is a valid level signal during the second sampling phase, and an invalid level signal during the third reset phase and the third data writing phase. The signal at the sensing control signal terminal is a valid level signal during the second sampling phase, and an invalid level signal during the third reset phase and the third data writing phase.

[0169] In an exemplary embodiment, the first sensing phase and the second sensing phase may occur simultaneously, which means that the first sampling phase and the second sampling phase occur simultaneously, ie, the pixel driving circuit acquires signals of the first node and the third node.

[0170] FIG4A is a timing diagram illustrating the operation of the pixel driving circuit in the display phase provided in FIG3 . The following describes exemplary embodiments of the present disclosure using the operation of the pixel driving circuit in the display phase as illustrated in FIG3 . The pixel driving circuit in FIG3 includes five transistors (a first transistor T1 to a fifth transistor T5) and a capacitor (capacitor C). The first transistor T1, the second transistor T2, and the fourth transistor T4 are N-type transistors, and the third transistor T3 and the fifth transistor T5 are P-type transistors.

[0171] In an exemplary embodiment, the operation process of the pixel driving circuit provided in FIG3 during the display phase may include:

[0172] In the first phase A1, referred to as the first reset phase, the signals at the reset signal terminal Reset and the light-emitting control signal terminal EM are high-level signals, the signals at the sensing control signal terminal SW-SENSE and the scanning signal terminal Gate are low-level signals, and the control signal terminal CON provides a reference signal, where Vref is the voltage value of the reference signal. The signal at the reset signal terminal Reset is high-level, turning on the first transistor T1. The reference signal at the control signal terminal CON is written to the third node N3, initializing the third node N3, i.e., the anode of the light-emitting device L, and clearing the existing charge at the third node N3. The signal at the light-emitting control signal terminal EM is high-level, the signals at the sensing control signal terminal SW-SENSE and the scanning signal terminal Gate are low-level signals, and the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned off. During this phase, the light-emitting device L does not emit light.

[0173] In the second phase A2, the first data writing phase, the signals at the scan signal terminal Gate and the emission control signal terminal EM are high-level signals, the signals at the sensing control signal terminal SW-SENSE and the reset signal terminal Reset are low-level signals, the control signal terminal CON provides a reference signal, and the data signal terminal Data outputs a data voltage. The signal at the scan signal terminal Gate is high-level, the fourth transistor T4 is turned on, and the data voltage at the data signal terminal Data is written to the first node N1. The signal at the emission control signal terminal EM is high-level, the signals at the sensing control signal terminal SW-SENSE and the reset signal terminal Reset are low-level signals, and the first transistor T1, the second transistor T2, and the fifth transistor T5 are turned off. During this phase, the light-emitting device L does not emit light.

[0174] In the third phase A3, i.e., the light-emitting phase, the signals at the scanning signal terminal Gate, the light-emitting control signal terminal EM, the sensing control signal terminal SW-SENSE, and the reset signal terminal Reset are low-level signals, and the control signal terminal CON provides a reference signal. The signal at the light-emitting control signal terminal EM is low-level, and the fifth transistor T5 is turned on. The power supply voltage output by the first power supply terminal VDD provides a driving voltage to the anode of the light-emitting device L through the turned-on fifth transistor T5 and the third transistor T3, driving the light-emitting device L to emit light. The signals at the scanning signal terminal Gate, the sensing control signal terminal SW-SENSE, and the reset signal terminal Reset are low-level signals, and the first transistor T1, the second transistor T2, and the fourth transistor T4 are turned off. In this phase, the light-emitting device L emits light.

[0175] FIG4B is a timing diagram illustrating the operation of the pixel driving circuit shown in FIG3 during the first sensing phase. The following illustrates exemplary embodiments of the present disclosure using the operation of the pixel driving circuit shown in FIG3 during the first sensing phase. The pixel driving circuit in FIG3 includes five transistors (a first transistor T1 to a fifth transistor T5) and a capacitor (capacitor C). The first transistor T1, the second transistor T2, and the fourth transistor T4 are N-type transistors, and the third transistor T3 and the fifth transistor T5 are P-type transistors.

[0176] In an exemplary embodiment, the operation process of the pixel driving circuit provided in FIG3 in the first sensing phase may include:

[0177] The first phase B1, referred to as the second reset phase, is characterized by high-level signals at the reset signal terminal Reset and the emission control signal terminal EM, low-level signals at the sensing control signal terminal SW-SENSE and the scanning signal terminal Gate, and a reference signal provided by the control signal terminal CON, where Vref is the voltage of the reference signal. The reset signal terminal Reset is high, turning on the first transistor T1. The reference signal at the control signal terminal CON is written to the third node N3, initializing the third node N3, i.e., the anode of the light-emitting device L, and clearing the existing charge on the third node N3. The emission control signal terminal EM is high, the sensing control signal terminal SW-SENSE and the scanning signal terminal Gate are low, and the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned off.

[0178] In the second phase B2, the second data writing phase, the signals at the scan signal terminal Gate and the emission control signal terminal EM are high-level signals, the signals at the sensing control signal terminal SW-SENSE and the reset signal terminal Reset are low-level signals, the control signal terminal CON provides a reference signal, and the data signal terminal Data outputs a data voltage. The signal at the scan signal terminal Gate is high-level, the fourth transistor T4 is turned on, and the data voltage at the data signal terminal Data is written to the first node N1. The signal at the emission control signal terminal EM is high-level, the signals at the sensing control signal terminal SW-SENSE and the reset signal terminal Reset are low-level signals, and the first transistor T1, the second transistor T2, and the fifth transistor T5 are turned off.

[0179] In the third stage B3, i.e., the first sampling stage, the signal of the reset signal terminal Reset is a high-level signal, the signals of the scanning signal terminal Gate, the light-emitting control signal terminal EM, and the sensing control signal terminal SW-SENSE are low-level signals, the signal of the reset signal terminal Reset is a high-level signal, the first transistor T1 is turned on, the signal of the light-emitting control signal terminal EM is a low-level signal, the fifth transistor T5 is turned on, the power supply voltage output by the first power supply terminal VDD provides a driving voltage to the anode of the light-emitting device L through the turned-on fifth transistor T5 and the third transistor T3, the control signal terminal CON obtains the signal of the third node N3 and samples the signal of the third node N3, the signals of the scanning signal terminal Gate and the sensing control signal terminal SW-SENSE are low-level signals, and the second transistor T2 and the fourth transistor T4 are turned off.

[0180] FIG4C is a timing diagram illustrating the operation of the pixel driving circuit in the second sensing phase provided in FIG3 . The following describes exemplary embodiments of the present disclosure using the operation of the pixel driving circuit in the second sensing phase as illustrated in FIG3 . The pixel driving circuit in FIG3 includes five transistors (a first transistor T1 to a fifth transistor T5) and a capacitor (capacitor C). The first transistor T1, the second transistor T2, and the fourth transistor T4 are N-type transistors, and the third transistor T3 and the fifth transistor T5 are P-type transistors.

[0181] In an exemplary embodiment, the operation process of the pixel driving circuit provided in FIG3 in the second sensing phase may include:

[0182] The first phase C1, referred to as the third reset phase, is characterized by high-level signals at the reset signal terminal Reset and the emission control signal terminal EM, low-level signals at the sensing control signal terminal SW-SENSE and the scanning signal terminal Gate, and a reference signal provided by the control signal terminal CON, where Vref is the voltage of the reference signal. The reset signal terminal Reset is high, turning on the first transistor T1. The reference signal at the control signal terminal CON is written to the third node N3, initializing the third node N3, i.e., the anode of the light-emitting device L, and clearing the existing charge on the third node N3. The emission control signal terminal EM is high, the sensing control signal terminal SW-SENSE and the scanning signal terminal Gate are low, and the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned off.

[0183] In the second phase C2, the third data writing phase, the signals at the scan signal terminal Gate and the emission control signal terminal EM are high-level signals, the signals at the sensing control signal terminal SW-SENSE and the reset signal terminal Reset are low-level signals, the control signal terminal CON provides a reference signal, and the data signal terminal Data outputs a data voltage. The signal at the scan signal terminal Gate is high-level, the fourth transistor T4 is turned on, and the data voltage at the data signal terminal Data is written to the first node N1. The signal at the emission control signal terminal EM is high-level, the signals at the sensing control signal terminal SW-SENSE and the reset signal terminal Reset are low-level signals, and the first transistor T1, the second transistor T2, and the fifth transistor T5 are turned off.

[0184] In the third stage C3, i.e., the second sampling stage, the signal of the sensing control signal terminal SW-SENSE is a high-level signal, the signals of the scanning signal terminal Gate, the light-emitting control signal terminal EM, and the reset signal terminal Reset are low-level signals, the signal of the sensing control signal terminal SW-SENSE is a high-level signal, the second transistor T2 is turned on, the control signal terminal CON obtains the signal of the first node N1 and samples the signal of the first node N1, the signal of the light-emitting control signal terminal EM is a low-level signal, the fifth transistor T5 is turned on, and the power supply voltage output by the first power supply terminal VDD provides a driving voltage to the anode of the light-emitting device L through the turned-on fifth transistor T5 and the third transistor T3. The signals of the scanning signal terminal Gate and the reset signal terminal Reset are low-level signals, and the first transistor T1 and the fourth transistor T4 are turned off.

[0185] The present disclosure also provides a driving method for a pixel driving circuit, which is configured to drive the pixel driving circuit provided by any of the aforementioned embodiments. The pixel driving circuit is provided in a display substrate, and the operation process of the display substrate includes: a display phase and a non-display phase;

[0186] In the display phase and the non-display phase, the driving method of the pixel driving circuit includes:

[0187] The driving subcircuit provides a driving signal to the third node under the control of the signals of the first node and the second node;

[0188] The reset sensing subcircuit provides the reference signal provided by the control signal terminal to the third node, or provides the signal of the first node or the third node to the control signal terminal under the control of the signals of the reset signal terminal and the sensing control signal terminal;

[0189] The node control subcircuit provides the signal of the data signal terminal to the first node under the control of the signal of the scan signal terminal, and stores the voltage difference between the signal of the first node and the signal of the first power terminal;

[0190] The light emitting control sub-circuit provides the signal of the first power supply terminal to the second node under the control of the signal of the light emitting control signal terminal.

[0191] In an exemplary embodiment, the display phase includes: a first reset phase, a first data writing phase, and a light emitting phase; the pixel driving circuit in the display phase, the driving method of the pixel driving circuit may include the following steps:

[0192] In the first reset phase, the reset sensing sub-circuit provides the reference signal provided by the control signal terminal to the third node under the control of the signal of the reset signal terminal;

[0193] In the first data writing phase, the node control subcircuit provides the signal of the data signal terminal to the first node under the control of the signal of the scan signal terminal, and stores the voltage difference between the signal of the first node and the signal of the first power terminal;

[0194] In the light-emitting stage, the light-emitting control subcircuit provides the signal of the first power supply end to the second node under the control of the signal of the light-emitting control signal end, and the driving subcircuit provides the driving signal to the third node under the control of the signals of the first node and the second node.

[0195] In an exemplary embodiment, the non-display phase includes a first sensing phase, which occurs before the display phase. The first sensing phase includes a second reset phase, a second data writing phase, and a first sampling phase.

[0196] In an exemplary embodiment, the pixel driving circuit is in a first sensing phase, and a driving method of the pixel driving circuit may include the following steps:

[0197] In the second reset phase, the reset sensing sub-circuit provides the reference signal provided by the control signal terminal to the third node under the control of the signal from the reset signal terminal;

[0198] In the second data writing phase, the node control subcircuit provides the signal of the data signal terminal to the first node under the control of the signal of the scan signal terminal, and stores the voltage difference between the signal of the first node and the signal of the first power terminal;

[0199] In the first sampling phase, the light-emitting control subcircuit provides the signal of the first power supply terminal to the second node under the control of the signal of the light-emitting control signal terminal, the driving subcircuit provides the driving signal to the third node under the control of the signals of the first node and the second node, and the reset sensing subcircuit provides the signal of the third node to the control signal terminal under the control of the signal of the reset signal terminal.

[0200] In an exemplary embodiment, the display substrate further includes an integrated circuit electrically connected to the pixel driving circuit. The integrated circuit receives a signal from the third node, processes the signal from the third node, and provides the processed signal from the third node to the pixel driving circuit to compensate for the brightness of the light-emitting device. The display substrate provided by this disclosure can provide external compensation for the pixel driving circuit, thereby improving the reliability and display quality of the display substrate.

[0201] In an exemplary embodiment, the non-display phase includes a second sensing phase, which occurs before the display phase. The second sensing phase includes a third reset phase, a third data writing phase, and a second sampling phase.

[0202] In an exemplary embodiment, the pixel driving circuit is in the second sensing phase, and a driving method of the pixel driving circuit may include the following steps:

[0203] In the third reset phase, the reset sensing sub-circuit provides the reference signal provided by the control signal terminal to the third node under the control of the signal from the reset signal terminal;

[0204] In the third data writing phase, the node control subcircuit provides the signal of the data signal terminal to the first node under the control of the signal of the scan signal terminal, and stores the voltage difference between the signal of the first node and the signal of the first power terminal;

[0205] In the second sampling phase, the light-emitting control subcircuit provides the signal of the first power supply terminal to the second node under the control of the signal of the light-emitting control signal terminal, the driving subcircuit provides the driving signal to the third node under the control of the signals of the first node and the second node, and the reset sensing subcircuit provides the signal of the first node to the control signal terminal under the control of the signal of the sensing control signal terminal.

[0206] In an exemplary embodiment, an integrated circuit captures a signal from a first node, processes the signal from the first node, and provides the processed signal from the first node to a pixel driver circuit to compensate for the threshold voltage of a driver transistor in the pixel driver circuit. The display substrate provided by the present disclosure can externally compensate the pixel driver circuit, thereby improving the reliability and display quality of the display substrate. For example, the display substrate includes multiple sub-pixels, at least one of which includes a pixel driver circuit. The integrated circuit can capture the signal from the first node of the pixel driver circuit in at least one sub-pixel.

[0207] Figure 5A is a schematic diagram of the structure of the display substrate, Figure 5B is a partial schematic diagram of the first display area in Figure 5A, and Figure 5C is a partial schematic diagram of the second display area in Figure 5A. As shown in Figures 5A to 5C, the embodiment of the present disclosure also provides a display substrate, including a substrate, the substrate including a display area AA and a non-display area BB, the display area AA including: a first display area A1 and a second display area A2, the second display area A2 is located on at least one side of the first display area A1. The first display area A1 includes: a plurality of first sub-pixels, the second display area A2 includes: a plurality of second sub-pixels, and at least one sub-pixel among the first sub-pixel and the second sub-pixel includes: a pixel driving circuit and a light-emitting device. Among them, the pixel driving circuit in the first sub-pixel is the pixel driving circuit provided in any of the aforementioned embodiments, and the implementation effect and implementation principle will not be repeated here. Figures 5B and 5C are illustrated by taking two rows and six columns of sub-pixels as an example.

[0208] In an exemplary embodiment, the pixel driving circuit in the second sub-pixel may be the pixel driving circuit provided by any of the aforementioned embodiments.

[0209] In an exemplary embodiment, as shown in FIG5A , the pixel driving circuit 11 in the first sub-pixel is electrically connected to the light emitting device 13 in the first sub-pixel, and the pixel driving circuit 12 in the second sub-pixel is electrically connected to the light emitting device 14 in the second sub-pixel.

[0210] In an exemplary embodiment, the display area may be in the shape of a rounded polygon or a circle. When the display area is in the shape of a rounded polygon, the display area may further include a straight display border. FIG5A illustrates an example of a display area in the shape of a rounded rectangle.

[0211] In an exemplary embodiment, the light transmittance of the first display area A1 may be greater than the light transmittance of the second display area A2. The first display area A1 may be a light-transmitting display area, and the second display area A2 may be a normal display area. The light-transmitting display area may display or transmit light.

[0212] In an exemplary embodiment, the shape of the first display area, within a plane parallel to the display substrate, may be any one or more of the following: rectangular, polygonal, circular, and elliptical. FIG5A illustrates a circular shape as an example. For example, when the first display area is circular, the diameter of the circle may be approximately 3 mm to 5 mm. For another example, when the first display area is rectangular, the side length of the rectangle may be approximately 3 mm to 5 mm.

[0213] In an exemplary embodiment, in a plane parallel to the display substrate, the shape of the first display area A1 may be any one or more of the following: a rectangle, a polygon, a circle, and an ellipse.

[0214] In an exemplary embodiment, the second display area A2 may surround or semi-surround the first display area A1. When the second display area A2 surrounds the first display area A1, the first display area A1 is located in the middle of the second display area A2. When the second display area A2 semi-surrounds the first display area A1, the first display area A1 is positioned at the top edge, i.e., along the edge of the second display area A2.

[0215] In an exemplary embodiment, the area of ​​the first display area A1 may be larger than the area of ​​the second display area A2, or the area of ​​the first display area A1 may be equal to the area of ​​the second display area A2, or the area of ​​the first display area A1 may be smaller than the area of ​​the second display area A2. Figure 5A is illustrated by taking the example that the area of ​​the first display area is smaller than the area of ​​the second display area.

[0216] In an exemplary embodiment, the display substrate may include a plurality of pixel units arranged regularly on a plane parallel to the display substrate. Each pixel unit may include three sub-pixels, four sub-pixels, or a plurality of sub-pixels. When the pixel unit includes three sub-pixels, the three sub-pixels include a first sub-pixel that emits a first color light, a second sub-pixel that emits a second color light, and a third sub-pixel that emits a third color light. When the pixel unit includes four sub-pixels, the four sub-pixels include a first sub-pixel that emits a first color light, a second sub-pixel that emits a second color light, a third sub-pixel that emits a third color light, and a fourth sub-pixel that emits a fourth color light.

[0217] In an exemplary embodiment, the pixel unit may include a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B.

[0218] In an exemplary embodiment, when a pixel unit includes three sub-pixels, the three rectangular sub-pixels may be arranged in parallel in a horizontal direction, or may be arranged in parallel in a vertical direction.

[0219] In an exemplary embodiment, when a pixel unit includes four sub-pixels, the four sub-pixels included in the pixel unit can have various shapes and be arranged in various ways. The four sub-pixels can have a rectangular shape and be arranged in parallel, from left to right: R sub-pixel, G sub-pixel, B sub-pixel, and G sub-pixel. Alternatively, the four sub-pixels can have a pentagonal shape and a hexagonal shape, respectively, and be arranged in parallel, with two pentagonal G sub-pixels located in the middle of the pixel unit and hexagonal R sub-pixels and hexagonal B sub-pixels located on either side of the G sub-pixel.

[0220] In an exemplary embodiment, the sub-pixel density of the first display area A1 is equal to the sub-pixel density of the second display area A2, and the resolution of the first display area is equal to the resolution of the second display area. Among them, resolution (Pixels Per Inch, abbreviated as PPI) refers to the number of sub-pixels per unit area, which can be called sub-pixel density. The higher the PPI value, the higher the density at which the picture is displayed, and the richer the details of the picture. That is. In the present disclosure, by adopting a pixel driving circuit that occupies a smaller area, it is possible to avoid compressing the pixel driving circuit in the first display area in a full-screen display product, and to improve the display effect of the display substrate. The sub-pixel density of the first display area A1 being equal to the sub-pixel density of the second display area A2 can ensure the display uniformity of the display substrate and improve the display effect of the display substrate.

[0221] In an exemplary embodiment, the sub-pixel density of the first display area A1 may be greater than the sub-pixel density of the second display area A2, and the resolution of the first display area is greater than the resolution of the second display area; alternatively, the sub-pixel density of the first display area A1 may be less than the sub-pixel density of the second display area A2, and the resolution of the first display area is less than the resolution of the second display area.

[0222] In an exemplary embodiment, as shown in Figures 5B and 5C, pixel structures of adjacent sub-pixels in a plurality of sub-pixels arranged along a first direction D1 are at least partially symmetrically arranged with respect to a virtual line extending along a second direction D2, and the first direction D1 and the second direction D2 intersect. In an exemplary embodiment, the first direction D1 and the second direction D2 may be perpendicular. The first direction D1 may be a row direction, and the second direction D2 may be a column direction.

[0223] In an exemplary embodiment, the light-emitting device includes a first light-emitting device, a second light-emitting device, and a third light-emitting device. The light-emitting device includes a first electrode. The first light-emitting device, the second light-emitting device, and the third light-emitting device emit light of different colors. Figures 5B and 5C illustrate an example in which the first light-emitting device emits red light, the second light-emitting device emits blue light, and the third light-emitting device emits green light.

[0224] In an exemplary embodiment, the area of ​​the first electrode AN1-1 of the first light-emitting device located in the first display area A1 may be smaller than the area of ​​the first electrode AN1-2 of the first light-emitting device located in the second display area A2, or the area of ​​the first electrode AN1-1 of the first light-emitting device located in the first display area A1 may be equal to the area of ​​the first electrode AN1-2 of the first light-emitting device located in the second display area A2, or the area of ​​the first electrode AN1-1 of the first light-emitting device located in the first display area A1 may be larger than the area of ​​the first electrode AN1-2 of the first light-emitting device located in the second display area A2.

[0225] In an exemplary embodiment, the area of ​​the first electrode AN2-1 of the second light-emitting device located in the first display area A1 may be smaller than the area of ​​the first electrode AN2-2 of the second light-emitting device located in the second display area A2, or the area of ​​the first electrode AN2-1 of the second light-emitting device located in the first display area A1 may be equal to the area of ​​the first electrode AN2-2 of the second light-emitting device located in the second display area A2, or the area of ​​the first electrode AN2-1 of the second light-emitting device located in the first display area A1 may be larger than the area of ​​the first electrode AN2-2 of the second light-emitting device located in the second display area A2.

[0226] In an exemplary embodiment, the area of ​​the first electrode AN3-1 of the third light-emitting device located in the first display area A1 may be smaller than the area of ​​the first electrode AN2-2 of the third light-emitting device located in the second display area A2, or the area of ​​the first electrode AN3-1 of the third light-emitting device located in the first display area A1 may be equal to the area of ​​the first electrode AN2-2 of the third light-emitting device located in the second display area A2, or the area of ​​the first electrode AN3-1 of the third light-emitting device located in the first display area A1 may be larger than the area of ​​the first electrode AN2-2 of the third light-emitting device located in the second display area A2.

[0227] In an exemplary embodiment, the first electrode may employ a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0228] In an exemplary embodiment, Figure 6A is a schematic diagram (I) of a portion of the film layers in the display substrate provided in Figures 5B and 5C, and Figure 6B is a schematic diagram (II) of a portion of the film layers in the display substrate provided in Figures 5B and 5C. As shown in Figures 6A and 6B, the pixel driving circuit includes at least one P-type transistor and at least one N-type transistor, with the orthographic projection of the at least one P-type transistor on the substrate at least partially overlapping with the orthographic projection of the at least one N-type transistor on the substrate. The at least one P-type transistor includes a third transistor T3 and a fifth transistor T5, and the at least one N-type transistor includes a first transistor T1, a second transistor T2, and a fourth transistor T4.

[0229] In an exemplary embodiment, as shown in FIG6B , the transistor includes an active pattern. The orthographic projection of the active pattern of at least one P-type transistor on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one N-type transistor on the substrate. Exemplarily, the orthographic projection of the active pattern of at least one N-type transistor on the substrate is located within the orthographic projection of the active pattern of at least one P-type transistor on the substrate. The active pattern of at least one N-type transistor in FIG6B includes an active pattern 11 of a first transistor, an active pattern 21 of a second transistor, and an active pattern 41 of a fourth transistor, and the active pattern of at least one P-type transistor includes an active pattern 31 of a third transistor and an active pattern 51 of a fifth transistor. In the present disclosure, at least a portion of the orthographic projection of at least a portion of the active pattern of at least one P-type transistor on the substrate overlaps with the orthographic projection of at least a portion of the active pattern of at least one N-type transistor on the substrate, which can reduce and further compress the area of ​​the pixel driving circuit, increase light transmittance, and ensure that the active pattern of the N-type transistor is disposed on a flat structure, thereby improving the reliability of the display substrate.

[0230] In an exemplary embodiment, as shown in FIG6B , the display area may further include at least one first power line VDDL disposed within the display area. The orthographic projection of the first power line VDDL on the substrate at least partially overlaps with the orthographic projection of at least a portion of at least one P-type transistor on the substrate, and the orthographic projection of the first power line VDDL on the substrate at least partially overlaps with the orthographic projection of at least a portion of at least one N-type transistor on the substrate. The first power line VDDL in the present disclosure separates the P-type transistor from the N-type transistor. Because the signal of the first power line VDDL is a constant voltage signal, the first power line in the present disclosure can prevent interference between the signals of the P-type transistor and the N-type transistor.

[0231] In an exemplary embodiment, as shown in FIG. 6B , the active pattern of at least one P-type transistor may be located on a side of the first power line VDDL close to the substrate, and the active pattern of at least one N-type transistor may be located on a side of the first power line VDDL far from the substrate.

[0232] In an exemplary embodiment, as shown in FIG6A , the display area includes: pixel elements PE arranged in an array, at least one emission control signal line EL, at least one reset signal line RL, at least one scan signal line GL, at least one sensing control signal line SL, at least one data signal line DL, at least one control signal line CONL, and at least one first power supply line VDDL. At least one pixel element includes at least one sub-pixel arranged along a first direction. FIG6A illustrates two rows and two columns of pixel elements as an example.

[0233] In an exemplary embodiment, at least one pixel unit is electrically connected to the light emitting control signal line EL, the reset signal line RL, the scanning signal line GL, the sensing control signal line SL, N data signal lines DL, N control signal lines CONL and N first power lines VDDL, respectively, where N is the number of sub-pixels in one pixel unit.

[0234] In an exemplary embodiment, as shown in FIG6A , the display area may include at least one data signal line DL and at least one control signal line CONL, the data signal line DL and the control signal line CONL extending at least partially along the second direction D2, wherein the data signal line DL is electrically connected to a data signal terminal connected to the pixel driving circuit, and the control signal line CONL is electrically connected to a control signal terminal connected to the pixel driving circuit.

[0235] In an exemplary embodiment, as shown in FIG6A , the data signal lines DL connected to adjacent sub-pixels among the plurality of sub-pixels arranged along the first direction D1 are symmetrically arranged with respect to a center line O of the adjacent sub-pixels, and the control signal lines CONL connected to adjacent sub-pixels among the plurality of sub-pixels arranged along the first direction D1 are symmetrically arranged with respect to the center line O of the adjacent sub-pixels.

[0236] In an exemplary embodiment, at least a portion of either the data signal line DL or the control signal line CONL is a transparent conductive signal line. This can further increase the pixel aperture, facilitating under-screen camera performance without compromising display quality.

[0237] In an exemplary embodiment, as shown in FIG6A and FIG6B , the display substrate may include at least one first power line VDDL; the first power line VDDL at least partially extending along the second direction D2. The first power line VDDL is electrically connected to a first power terminal connected to the pixel driving circuit, adjacent first power lines VDDL are electrically connected, and the first power lines VDDL connected to adjacent sub-pixels among a plurality of sub-pixels arranged along the first direction D1 are symmetrically arranged with respect to a center line O of the adjacent sub-pixels.

[0238] In an exemplary embodiment, as shown in FIG6B , a first power line VDDL includes a first connection line VL1, a second connection line VL2, and a plurality of connection blocks CL. The first connection line VL1 and the second connection line VL2 are arranged along a first direction D1 and extend along a second direction D2. The connection blocks CL are disposed between the first connection line VL1 and the second connection line VL2. The pixel driving circuit includes a capacitor, which includes a first plate C1 and a second plate C2. The orthographic projection of the connection block CL on the substrate at least partially overlaps with the orthographic projection of the first plate C1 on the substrate, i.e., the connection block CL serves as the second plate C2 of the capacitor. The plurality of connection blocks CL are arranged along the second direction D2 and are spaced apart. Adjacent connection blocks CL arranged along the second direction D2 form a closed region with adjacent first connection lines VL1 and second connection lines VL2.

[0239] In an exemplary embodiment, the closed area may be a light-transmitting area.

[0240] In an exemplary embodiment, as shown in FIG6A , the display area may further include: at least one light-emitting control signal line EL, at least one reset signal line RL, at least one scan signal line GL, and at least one sensing control signal line SL, wherein at least one of the light-emitting control signal line EL, the reset signal line RL, the scan signal line GL, and the sensing control signal line SL extends at least partially along the first direction D1, wherein the light-emitting control signal line EL is electrically connected to a light-emitting control signal terminal connected to the pixel driving circuit, the reset signal line RL is electrically connected to a reset signal terminal connected to the pixel driving circuit, the scan signal line GL is electrically connected to a scan signal terminal connected to the pixel driving circuit, and the sensing control signal line SL is electrically connected to a sensing control signal terminal connected to the pixel driving circuit.

[0241] In an exemplary embodiment, as shown in FIG. 6A , the light emission control signal line EL is disposed in a different layer from at least one of the reset signal line RL, the scan signal line GL, and the sensing control signal line SL.

[0242] In an exemplary embodiment, as shown in FIG6A , the orthographic projections of the emission control signal line EL, the scan signal line GL, the sensing control signal line SL, and the reset signal line RL connected to at least one sub-pixel on the substrate are arranged sequentially along the second direction;

[0243] In an exemplary embodiment, the display substrate further includes a driving structure layer disposed on the base, the driving structure layer being provided with a light-emitting control signal line, a reset signal line, a scan signal line, a sensing control signal line, a first power line, a data signal line, a control signal line, and a pixel driving circuit. The driving structure layer includes at least a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, and a fourth conductive layer stacked sequentially away from the base. The pixel driving circuit includes at least one P-type transistor, at least one N-type transistor, and a capacitor. The transistor includes an active pattern, a gate electrode, a first electrode, and a second electrode. The capacitor includes a first plate and a second plate. The at least one P-type transistor may include the third transistor and the fifth transistor in FIG. 3 , and the at least one N-type transistor may include the first transistor, the second transistor, and the fourth transistor in FIG. 3 .

[0244] The first semiconductor layer includes at least an active pattern of at least one P-type transistor located in at least one sub-pixel.

[0245] The first conductive layer at least includes: a light emitting control signal line, a gate electrode of at least one P-type transistor located in at least one sub-pixel, and a first plate of a capacitor.

[0246] The second conductive layer at least includes: a first power line, a second plate of a capacitor located in at least one sub-pixel, and a first electrode and a second electrode of at least one P-type transistor.

[0247] The second semiconductor layer includes at least an active pattern of at least one N-type transistor located in at least one sub-pixel.

[0248] The third conductive layer at least includes: a reset signal line, a scan signal line, a sensing control signal line, and a gate electrode, a first electrode, and a second electrode of at least one N-type transistor located in at least one sub-pixel.

[0249] The fourth conductive layer at least includes: a data signal line, a control signal line, and an anode connection line located in at least one sub-pixel.

[0250] In an exemplary embodiment, the anode connection line includes a transparent wire. Exemplarily, the transparent wire may be made of indium tin oxide (ITO) or indium zinc oxide (IZO).

[0251] In an exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. The rigid substrate may include, but is not limited to, one or more of glass and quartz, and the flexible substrate may include, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers.

[0252] In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The first and second flexible material layers may be made of polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The first and second inorganic material layers may be made of silicon nitride (SiNx) or silicon oxide (SiOx) to improve the substrate's resistance to water and oxygen. The semiconductor layer may be made of amorphous silicon (a-Si).

[0253] The display substrate disclosed herein uses four conductive layers and two semiconductor layers to implement a pixel driving circuit including P-type transistors and N-type transistors, simplifying the film layer structure of the display substrate. This not only saves the space occupied by the pixel driving circuit to the maximum extent, but also helps to improve the aperture ratio of the light-transmitting display area.

[0254] In an exemplary embodiment, the driving structure layer may further include: a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a first planar layer, and a second planar layer. The first insulating layer is located between the first semiconductor layer and the first conductive layer, the second insulating layer is located between the first conductive layer and the second conductive layer, the third insulating layer is located between the second conductive layer and the second semiconductor layer, the fourth insulating layer is located between the second semiconductor layer and the third conductive layer, the first planar layer is located between the third conductive layer and the fourth conductive layer, and the second planar layer is located on a side of the fourth conductive layer away from the substrate.

[0255] In an exemplary embodiment, the display substrate may further include a light-emitting structure layer located on a side of the drive structure layer away from the substrate. The light-emitting structure layer includes a fifth conductive layer and a pixel definition layer sequentially stacked on the substrate. The fifth conductive layer includes at least a first electrode. The pixel definition layer is provided with a plurality of pixel openings, including a first pixel opening, a second pixel opening, and a third pixel opening. The first pixel opening exposes the first electrode of the first light-emitting device, the second pixel opening exposes the first electrode of the second light-emitting device, and the third pixel opening exposes the first electrode of the third light-emitting device.

[0256] As shown in Figures 5B and 5C, the area of ​​the first pixel opening PV1-1 located in the first display area A1 is smaller than the area of ​​the first pixel opening PV1-2 located in the second display area A2, the area of ​​the second pixel opening PV2-1 located in the first display area A1 is smaller than the area of ​​the second pixel opening PV2-2 located in the second display area A2, and the area of ​​the third pixel opening PV3-2 located in the first display area A1 is smaller than the area of ​​the third pixel opening PV3-2 located in the second display area A2.

[0257] The display substrate provided by the embodiment of the present disclosure can be applicable to application scenarios such as front-facing camera photography and mobile gaming of high-frequency terminal devices.

[0258] The following is an illustrative explanation using the preparation process of a display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials. Deposition can be performed by any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed by any one or more of spraying, spin coating, and inkjet printing; and etching can be performed by any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a thin film made by deposition, coating, or other processes on a substrate using a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer." If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0259] In an exemplary embodiment, taking 12 sub-pixels (2 sub-pixel rows and 6 sub-pixel columns) located in the first display area as an example, the preparation process of the display substrate may include the following operations.

[0260] (1) Forming a first semiconductor layer pattern. In an exemplary embodiment, forming the first semiconductor layer pattern may include: depositing a first semiconductor thin film on a substrate, and patterning the first semiconductor thin film through a patterning process to form a first semiconductor layer pattern covering the substrate, as shown in FIG7 , which is a schematic diagram of the first semiconductor layer pattern.

[0261] In an exemplary embodiment, as shown in FIG. 7 , the first semiconductor layer pattern may include at least an active pattern 31 of a third transistor and an active pattern 51 of a fifth transistor located in at least one sub-pixel.

[0262] In an exemplary embodiment, the active pattern 31 of the third transistor and the active pattern 51 of the fifth transistor located in the same sub-pixel are connected to each other as an integral structure.

[0263] In an exemplary embodiment, the integrated structure of the third transistor active pattern 31 and the fifth transistor active pattern 51 of adjacent sub-pixels located in the same row is symmetrical with respect to a center line O of the adjacent sub-pixels extending along the second direction D2 .

[0264] In an exemplary embodiment, in the first direction D1, the active pattern 31 of the third transistor of the i-th column sub-pixel is located on a side of the active pattern 51 of the fifth transistor of the i-th column sub-pixel that is closer to the adjacent column sub-pixel. In the second direction D2, the active pattern 31 of the third transistor of the j-th row sub-pixel is located on a side of the active pattern 51 of the fifth transistor of the j-th row sub-pixel that is closer to the j+1-th row sub-pixel.

[0265] In example embodiments, the active pattern 51 of the fifth transistor may have an “I” shape.

[0266] In an exemplary embodiment, the active pattern 31 of the third transistor includes a first active connection portion 31A, a second active connection portion 31B, and a third active connection portion 31C. The first active connection portion 31A and the third active connection portion 31C are located on a side of the second active connection portion 31B that is closer to the active pattern 51 of the fifth transistor. The first active connection portion 31A is connected to the active pattern 51 of the fifth transistor and the second active connection portion 31B, respectively, and the third active connection portion 31C is connected to the second active connection portion 31B.

[0267] In an exemplary embodiment, the first active connection portion 31A may be shaped like an inverted Ω, the second active connection portion 31B may be shaped like an I, and the third active connection portion 31C may be shaped like a straight line.

[0268] In an exemplary embodiment, the active pattern of each transistor may include a first region, a second region, and a channel region located between the first region and the second region. In an exemplary embodiment, the first region 31-1 of the active pattern 31 of the third transistor may serve as the second region 51-2 of the active pattern 51 of the fifth transistor, and the second region 31-2 of the active pattern 31 of the third transistor and the first region 51-1 of the active pattern 51 of the fifth transistor may be separately provided.

[0269] (2) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: sequentially depositing a first insulating film and a first conductive film on the substrate having the aforementioned pattern formed thereon, patterning the first conductive film through a patterning process to form a first insulating layer covering the first semiconductor layer pattern and a first conductive layer pattern disposed on the first insulating layer, as shown in FIG8 and FIG9 , FIG8 is a schematic diagram of the first conductive layer pattern, and FIG9 is a schematic diagram after forming the first conductive layer pattern. In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0270] In an exemplary embodiment, as shown in FIG8 and FIG9, the first conductive layer pattern includes at least: the light emission control signal line EL and the gate electrode 32 of the third transistor, the gate electrode 52 of the fifth transistor and the first plate C1 of the capacitor located in at least one sub-pixel.

[0271] In an exemplary embodiment, the light emission control signal line EL may be in the shape of a line with a main portion extending along the first direction D1. The light emission control signal line EL in the j-th row of sub-pixels may be located on a side of the first plate C1 of the capacitor of the j-th row of sub-pixels that is away from the j+1-th row of sub-pixels. The region where the light emission control signal line EL overlaps with the active pattern of the fifth transistor serves as the gate electrode of the fifth transistor T5.

[0272] In an exemplary embodiment, the gate electrode 32 of the third transistor and the first plate C1 of the capacitor located in the same sub-pixel are integrally formed. The integral structure of the gate electrode 32 of the third transistor and the first plate C1 of the capacitor may be rectangular, and the corners of the rectangle may be chamfered. The orthographic projection of the integral structure of the gate electrode 32 of the third transistor and the first plate C1 of the capacitor on the substrate at least partially overlaps with the orthographic projection of the first active connection portion in the active pattern of the third transistor on the substrate.

[0273] In an exemplary embodiment, the integrated structure of the gate electrodes 32 of the third transistors and the first plates C1 of the capacitors of adjacent sub-pixels located in the same row is symmetrical with respect to a center line O extending along the second direction D2 of the adjacent sub-pixels.

[0274] In an exemplary embodiment, after forming the first conductive layer pattern, the first conductive layer can be used as a shield to perform conductorization on the first semiconductor layer. The first semiconductor layer in the area shielded by the first conductive layer forms the channel region of the third transistor T3 and the fifth transistor T5, and the first semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first area and the second area of ​​the third transistor T3 and the fifth transistor T5 are both conductorized, and the first area 31-1 of the active pattern 31 of the third transistor (also the second area 51-2 of the active pattern 51 of the fifth transistor) can serve as the first electrode 33 of the third transistor (also the second electrode 54 of the fifth transistor).

[0275] (3) Forming a second insulating layer pattern. In an exemplary embodiment, forming the second insulating layer pattern may include: depositing a second insulating film on the substrate on which the aforementioned pattern is formed, patterning the second insulating film using a patterning process to form a second insulating layer covering the first conductive layer, wherein the second insulating layer is provided with a plurality of vias, as shown in FIG10 , which is a schematic diagram after the second insulating layer is formed.

[0276] In an exemplary embodiment, as shown in FIG. 10 , the plurality of via holes include at least a first via hole V1 and a second via hole V2 located at at least one sub-pixel.

[0277] In an exemplary embodiment, the orthographic projection of the first via V1 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the third transistor on the substrate, the first insulating layer in the first via V1 is etched away, exposing the surface of the second area of ​​the active pattern of the third transistor, and the first via V1 is configured to connect the second electrode of the subsequently formed third transistor to the second area of ​​the active pattern of the third transistor through the via.

[0278] In an exemplary embodiment, the orthographic projection of the second via V2 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the fifth transistor on the substrate, the first insulating layer in the second via V2 is etched away, exposing the surface of the first area of ​​the active pattern of the fifth transistor, and the second via V2 is configured to connect a subsequently formed first power line to the first area of ​​the active pattern of the fifth transistor through the via.

[0279] (4) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: depositing a second conductive film on the substrate on which the aforementioned pattern is formed, patterning the second conductive film using a patterning process, and forming a second conductive layer pattern on the second insulating layer, as shown in Figures 11 and 12, where Figure 11 is a schematic diagram of the second conductive layer pattern, and Figure 12 is a schematic diagram after the second conductive layer pattern is formed.

[0280] In an exemplary embodiment, the second conductive layer pattern includes at least a first power line VDDL, a second electrode 34 of a third transistor, a first electrode 53 of a fifth transistor, and a second plate C2 of a capacitor in at least one sub-pixel.

[0281] In an exemplary embodiment, the first power lines VDDL connected to adjacent sub-pixels among the plurality of sub-pixels arranged along the first direction D1 are symmetrically arranged with respect to a center line O of the adjacent sub-pixels. The second electrodes 34 of the third transistors of adjacent sub-pixels located in the same row are symmetrically arranged with respect to a virtual straight line O extending along the second direction between the adjacent sub-pixels.

[0282] In an exemplary embodiment, adjacent first power lines VDDL are electrically connected. The first power lines VDDL at least partially extend along the second direction D2.

[0283] In an exemplary embodiment, as shown in FIG11 , a first power line VDDL includes a first connection line VL1, a second connection line VL2, and a plurality of connection blocks CL. The first connection line VL1 and the second connection line VL2 are arranged along a first direction D1 and extend along a second direction D2. The connection blocks CL are disposed between the first connection line VL1 and the second connection line VL2. The pixel driving circuit includes a capacitor, which includes a first plate C1 and a second plate C2. The orthographic projection of the connection block CL on the substrate at least partially overlaps with the orthographic projection of the first plate C1 on the substrate, meaning that the connection block CL serves as the second plate C2 of the capacitor. The plurality of connection blocks CL between the first connection line VL1 and the second connection line VL2 are arranged along the second direction D2 and spaced apart. For the same first power line VDDL, adjacent connection blocks CL form a closed region with the first connection line VL1 and the second connection line VL2.

[0284] In an exemplary embodiment, the overlapping area between the first power line VDDL and the second via is reused as the first electrode of the fifth transistor. The connection block CL is reused as the second plate C2 of the capacitor, and its orthographic projection on the substrate at least partially overlaps with the orthographic projection of the first plate of the capacitor on the substrate.

[0285] In an exemplary embodiment, the outline of the connection block CL can be rectangular. An opening K is provided on the connection block CL. The opening K can be rectangular in shape and can be located in the middle of the connection block CL, so that the connection block CL forms a ring structure. The opening K exposes the second insulating layer covering the first electrode plate, and the orthographic projection of the first electrode plate on the substrate includes the orthographic projection of the opening K on the substrate. In an exemplary embodiment, the opening K is configured to accommodate a fourth via hole formed subsequently. The fourth via hole is located within the opening K and exposes the first electrode plate 24, so that the second electrode of the fourth transistor formed subsequently (which is also the second electrode of the second transistor) is connected to the first electrode plate.

[0286] In an exemplary embodiment, the second electrode 34 of the third transistor is provided separately and may be rectangular in shape, which is not limited in the present disclosure. The second electrode 34 of the third transistor may be located in a closed area.

[0287] In an exemplary embodiment, the first power line VDDL is electrically connected to the second region of the active pattern of the fifth transistor through the second via hole. The second electrode 34 of the third transistor is electrically connected to the second region of the active pattern of the third transistor through the first via hole.

[0288] In an exemplary embodiment, since adjacent first power lines VDDL are electrically connected to each other, by forming all the first power lines into an integrated structure connected to each other, it can be ensured that the second plates of multiple capacitors in all sub-pixel rows have the same potential, which is beneficial to improving the uniformity of the display substrate, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

[0289] (5) Forming a third insulating layer pattern. In an exemplary embodiment, forming the third insulating layer pattern may include: depositing a third insulating film on the substrate having the aforementioned pattern formed thereon, patterning the third insulating film using a patterning process to form a third insulating layer covering the second conductive layer, wherein the third insulating layer is provided with a plurality of vias, as shown in FIG13 . FIG13 is a schematic diagram after forming the third insulating layer.

[0290] In an exemplary embodiment, as shown in FIG. 13 , the via holes on the third insulating layer include at least a third via hole V3 located in at least one sub-pixel.

[0291] In an exemplary embodiment, the orthographic projection of the third via V3 on the substrate is located within the range of the orthographic projection of the second electrode of the third transistor on the substrate, the third via V3 exposes the surface of the second electrode of the third transistor, and the third via V3 is configured to connect the second area of ​​the active pattern of the subsequently formed first transistor to the second electrode of the third transistor through the via.

[0292] (6) Forming a second semiconductor layer pattern. In an exemplary embodiment, forming the second semiconductor layer pattern may include: depositing a second semiconductor thin film on the substrate on which the aforementioned pattern is formed, and patterning the second semiconductor thin film through a patterning process to form a second semiconductor layer pattern covering the third insulating layer, as shown in Figures 14 and 15 , where Figure 14 is a schematic diagram of the second semiconductor layer pattern, and Figure 15 is a schematic diagram after the second semiconductor layer pattern is formed.

[0293] In exemplary embodiments, as shown in FIG. 14 and FIG. 15 , the second semiconductor layer pattern may include at least a first transistor active pattern 11 , a second transistor active pattern 21 , and a fourth transistor active pattern 41 located in at least one sub-pixel.

[0294] In an exemplary embodiment, the active pattern 11 of the first transistor and the active pattern 21 of the second transistor located in the same sub-pixel are connected to each other as an integral structure, while the active pattern 41 of the fourth transistor may be provided separately.

[0295] In an exemplary embodiment, the first transistor active pattern 11 , the second transistor active pattern 21 , and the fourth transistor active pattern 41 of adjacent sub-pixels located in the same row are symmetrical with respect to a center line O extending along the second direction D2 of the adjacent sub-pixels.

[0296] In an exemplary embodiment, in the first direction D1, the integrated structure of the active pattern 11 of the first transistor and the active pattern 21 of the second transistor of the i-th column sub-pixel is located on a side of the active pattern 41 of the fourth transistor of the i-th column sub-pixel that is close to the sub-pixel in the adjacent column. In the second direction D2, the integrated structure of the active pattern 11 of the first transistor and the active pattern 21 of the j-th row sub-pixel is located on a side of the active pattern 41 of the fourth transistor of the j-th row sub-pixel that is close to the sub-pixel in the j+1-th row.

[0297] In an exemplary embodiment, the active pattern 21 of the second transistor and the active pattern 41 of the fourth transistor may have an I-shape. The active pattern 11 of the first transistor may have a straight-line shape.

[0298] In an exemplary embodiment, the active pattern of each transistor may include a first region, a second region, and a channel region located between the first region and the second region. In an exemplary embodiment, the first region 11-1 of the active pattern 11 of the first transistor may serve as the first region 21-1 of the active pattern 21 of the second transistor, and the second region 11-2 of the active pattern 11 of the first transistor, the second region 21-2 of the active pattern 21 of the second transistor, and the first region 41-1 and the second region 41-2 of the active pattern 41 of the fourth transistor may be separately provided.

[0299] In an exemplary embodiment, orthographic projections of the first transistor active pattern 11 , the second transistor active pattern 21 , and the fourth transistor active pattern 41 on the substrate at least partially overlap with an orthographic projection of the first power line VDDL on the substrate.

[0300] In an exemplary embodiment, the second region 11 - 2 of the active pattern 11 of the first transistor is connected to the second electrode of the third transistor through a third via hole.

[0301] (7) Forming a fourth insulating layer pattern. In an exemplary embodiment, forming the fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate having the aforementioned pattern formed thereon, patterning the fourth insulating film using a patterning process to form a fourth insulating layer covering the second semiconductor layer, wherein the fourth insulating layer is provided with a plurality of vias, as shown in FIG16 . FIG16 is a schematic diagram after forming the fourth insulating layer.

[0302] In an exemplary embodiment, as shown in FIG. 16 , the via holes on the fourth insulating layer include at least a fourth via hole V4 , a fifth via hole V5 , a sixth via hole V6 , a seventh via hole V7 , an eighth via hole V8 , and a ninth via hole V9 located in at least one sub-pixel.

[0303] In an exemplary embodiment, the orthographic projection of the fourth via V4 on the substrate is located within the range of the orthographic projection of the gate electrode of the third transistor (also the first plate of the capacitor) on the substrate, the second insulating layer, the third insulating layer and the fourth insulating layer within the fourth via V4 are etched, and the surface of the second electrode of the third transistor is exposed, and the fourth via V4 is configured to connect the second electrode of the subsequently formed second transistor (also the second electrode of the fourth transistor) to the gate electrode of the third transistor (also the first plate of the capacitor) through the via.

[0304] In an exemplary embodiment, the orthographic projection of the fifth via V5 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the first transistor (also the first area of ​​the active pattern of the second transistor) on the substrate, and the fifth via V5 exposes the surface of the first area of ​​the active pattern of the first transistor (also the first area of ​​the active pattern of the second transistor). The fifth via V5 is configured to connect the first electrode of the subsequently formed first transistor (also the first electrode of the second transistor) to the first area of ​​the active pattern of the first transistor (also the first area of ​​the active pattern of the second transistor) through the via.

[0305] In an exemplary embodiment, the orthographic projection of the sixth via V6 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the first transistor on the substrate, the sixth via V6 exposes the surface of the second area of ​​the active pattern of the first transistor, and the sixth via V6 is configured to connect the second electrode of the subsequently formed first transistor T1 to the second area of ​​the active pattern of the first transistor through the via.

[0306] In an exemplary embodiment, the orthographic projection of the seventh via V7 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the second transistor on the substrate, and the surface of the second area of ​​the active pattern of the second transistor is exposed by the seventh via V7. The seventh via V7 is configured to connect the second electrode of the subsequently formed second transistor (which is also the second electrode of the fourth transistor) to the second area of ​​the active pattern of the second transistor through the via.

[0307] In an exemplary embodiment, the orthographic projection of the eighth via V8 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the fourth transistor on the substrate, the eighth via V8 exposes the surface of the first area of ​​the active pattern of the fourth transistor, and the eighth via V8 is configured to connect the first electrode of the subsequently formed fourth transistor to the first area of ​​the active pattern of the fourth transistor through the via.

[0308] In an exemplary embodiment, the orthographic projection of the ninth via V9 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the fourth transistor on the substrate, the ninth via V9 exposes the surface of the second area of ​​the active pattern of the fourth transistor, and the ninth via V9 is configured to connect the second electrode of the subsequently formed second transistor (which is also the second electrode of the fourth transistor) to the second area of ​​the active pattern of the fourth transistor through the via.

[0309] (8) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer may include: depositing a third conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the third conductive film using a patterning process to form a third conductive layer disposed on the fourth insulating layer, as shown in FIG17 and FIG18 . FIG17 is a schematic diagram of the third conductive layer pattern, and FIG18 is a schematic diagram after the third conductive layer pattern is formed.

[0310] In an exemplary embodiment, as shown in Figures 17 and 18, the third conductive layer pattern includes at least: a scanning signal line GL, a sensing control signal line SL, a reset signal line RL, and the gate electrode 12, the first electrode 13 and the second electrode 14 of the first transistor located in at least one sub-pixel, the gate electrode 22, the first electrode 23 and the second electrode 24 of the second transistor, and the gate electrode 42, the first electrode 43 and the second electrode 44 of the fourth transistor.

[0311] In an exemplary embodiment, the scan signal line connected to the j-th row of sub-pixels is located on a side of the sensing control signal line SL connected to the j-th row of sub-pixels close to the j-1-th row of sub-pixels, and the reset signal line RL connected to the j-th row of sub-pixels is located on a side of the sensing control signal line SL connected to the j-th row of sub-pixels close to the j+1-th row of sub-pixels.

[0312] In an exemplary embodiment, the scan signal line GL may be in the shape of a line with a main portion extending along the first direction D1 , and an area where the scan signal line GL overlaps with the active pattern of the fourth transistor of the sub-pixel serves as the gate electrode 42 of the fourth transistor.

[0313] In an exemplary embodiment, the sensing control signal line SL may be in the shape of a line with a main portion extending along the first direction D1. The area where the sensing control signal line SL overlaps with the active pattern of the second transistor of the sub-pixel serves as the gate electrode 22 of the second transistor.

[0314] In an exemplary embodiment, the reset signal line RL may be in the shape of a line with a main portion extending along the first direction D1. The area where the reset signal line RL overlaps with the active pattern of the first transistor of the sub-pixel serves as the gate electrode 12 of the first transistor.

[0315] In an exemplary embodiment, the first electrodes 13 and 14 of the first transistor, the first electrodes 23 and 24 of the second transistor, and the first electrodes 43 and 44 of the fourth transistor located in adjacent sub-pixels in the same row are symmetrically arranged with respect to a center line O extending along the second direction D2 of the adjacent sub-pixels.

[0316] In an exemplary embodiment, the first electrode 13 of the first transistor and the first electrode 23 of the second transistor are an integrated structure. The integrated structure of the first electrode 13 of the first transistor and the first electrode 23 of the second transistor is block-shaped and connected to the first area of ​​the active pattern of the first transistor (which is also the first area of ​​the active pattern of the second transistor) through a fifth via.

[0317] In an exemplary embodiment, the second electrode 14 of the first transistor is provided separately. The second electrode 14 of the first transistor is in a block shape and is connected to the second region of the active pattern of the first transistor through a sixth via hole.

[0318] In an exemplary embodiment, the second electrode 24 of the second transistor and the second electrode 44 of the fourth transistor are integrally formed. The integral structure of the second electrode 24 of the second transistor and the second electrode 44 of the fourth transistor is strip-shaped and extends along a first direction D1. The integral structure of the second electrode 24 of the second transistor and the second electrode 44 of the fourth transistor is connected to the gate electrode of the third transistor (which is also the first plate of the capacitor) via a fourth via, connected to the second region of the active pattern of the second transistor via a seventh via, and connected to the first region of the active pattern of the fourth transistor via an eighth via.

[0319] In an exemplary embodiment, the first electrode 43 of the fourth transistor is separately provided. The first electrode 43 of the fourth transistor is in a block shape and is connected to the second region of the active pattern of the fourth transistor through a ninth via hole.

[0320] In an exemplary embodiment, the second electrode 14 of the first transistor is connected to the second electrode of the third transistor through the second electrode of the active pattern of the first transistor.

[0321] In an exemplary embodiment, the scanning signal line GL, the sensing control signal line SL, and the reset signal line RL can be designed with equal width, or can be designed with unequal width, can be straight lines, or can be broken lines, which not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the signal lines. The present disclosure does not limit this.

[0322] (9) Forming a first planar layer pattern. In an exemplary embodiment, forming the first planar layer pattern may include: coating a first planar film on the substrate on which the aforementioned pattern is formed, patterning the first planar film using a patterning process to form a first planar layer covering the third conductive layer pattern, wherein a plurality of vias are provided on the first planar layer, as shown in FIG. 19 , which is a schematic diagram after the first planar layer is formed.

[0323] In an exemplary embodiment, as shown in FIG. 19 , the plurality of via holes include at least a tenth via hole V10 , an eleventh via hole V11 , and a twelfth via hole V12 located in at least one sub-pixel.

[0324] In an exemplary embodiment, the orthographic projection of the tenth via V10 on the substrate is located within the range of the orthographic projection of the first electrode of the first transistor (also the first electrode of the second transistor) on the substrate, the tenth via V10 exposes the surface of the first electrode of the first transistor (also the first electrode of the second transistor), and the tenth via V10 is configured to connect a subsequently formed control signal line through the via to the first electrode of the first transistor (also the first electrode of the second transistor).

[0325] In an exemplary embodiment, the orthographic projection of the eleventh via V11 on the substrate is located within the range of the orthographic projection of the second electrode of the first transistor on the substrate, the eleventh via V11 exposes the surface of the second electrode of the first transistor, and the eleventh via V11 is configured to connect a subsequently formed anode connection line to the second electrode of the first transistor through the via.

[0326] In an exemplary embodiment, the orthographic projection of the twelfth via V12 on the substrate is located within the range of the orthographic projection of the first electrode of the fourth transistor on the substrate, the twelfth via V12 exposes the surface of the first electrode of the fourth transistor, and the twelfth via V12 is configured to connect a subsequently formed data signal line to the first electrode of the fourth transistor through the via.

[0327] (10) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer may include: depositing a fourth conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the fourth conductive film using a patterning process to form a fourth conductive layer disposed on the first flat layer, as shown in FIG20 and FIG21 , where FIG20 is a schematic diagram of the fourth conductive layer pattern, and FIG21 is a schematic diagram after the fourth conductive layer pattern is formed.

[0328] In an exemplary embodiment, as shown in FIG. 20 and FIG. 21 , the fourth conductive layer pattern includes at least a data signal line DL, a control signal line CONL, and an anode connection line AL located in at least one sub-pixel.

[0329] In an exemplary embodiment, the anode connection line AL may be in the shape of a strip having a main portion extending along the second direction D2. The anode connection line AL is connected to the second electrode of the first transistor through an eleventh via hole. The anode connection line AL is configured to be connected to a subsequently formed anode. Because the second electrode of the first transistor is also connected to the second electrode of the third transistor, the subsequently formed anode can be connected to the second electrodes of the first and third transistors.

[0330] In an exemplary embodiment, the data signal lines DL connected to adjacent sub-pixels in the same row are symmetrically arranged with respect to a center line O extending along the second direction D2 between the adjacent sub-pixels. The control signal lines CONL connected to adjacent sub-pixels in the same row are symmetrically arranged with respect to a center line O extending along the second direction D2 between the adjacent sub-pixels.

[0331] In an exemplary embodiment, the data signal line DL may be in a zigzag shape with a main portion extending along the second direction D1 . The data signal line DL is connected to the first electrode of the fourth transistor through the twelfth via hole.

[0332] In an exemplary embodiment, the control signal line CONL may be shaped like a zigzag line with a main portion extending along the second direction D1. The control signal line CONL is connected to the first electrode of the first transistor (also the first electrode of the second transistor) through a tenth via hole.

[0333] (11) Forming a second planar layer pattern. In an exemplary embodiment, forming the second planar layer pattern may include: coating a second planar film on the substrate on which the aforementioned pattern is formed, patterning the second planar film using a patterning process to form a second planar layer covering the fourth conductive layer pattern, wherein a plurality of vias are provided on the second planar layer, as shown in FIG22 , which is a schematic diagram after the second planar layer is formed.

[0334] In an exemplary embodiment, as shown in FIG. 22 , the plurality of via holes includes at least a thirteenth via hole V13 located in at least one sub-pixel.

[0335] In an exemplary embodiment, the orthographic projection of the thirteenth via hole V13 on the substrate is located within the range of the orthographic projection of the anode connecting line on the substrate, the thirteenth via hole V13 exposes the surface of the anode connecting line, and the thirteenth via hole V13 is configured to connect the first electrode of the subsequently formed light-emitting device to the anode connecting line through the via hole.

[0336] At this point, the drive circuit layer is completed on the substrate. In a plane parallel to the display substrate, the drive circuit layer can include multiple circuit units, each of which can include a pixel drive circuit. The pixel drive circuit is connected to scan signal lines, light emission control signal lines, sensing control signal lines, reset signal lines, first power lines, data signal lines, and control signal lines. In a plane perpendicular to the display substrate, the drive circuit layer can be disposed on the substrate, which can include a stacked first flexible layer, a barrier layer, and a second flexible layer.

[0337] The driving circuit layer may include a first semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a second semiconductor layer, a fourth insulating layer, a third conductive layer, a first planar layer, a fourth conductive layer and a second planar layer arranged in sequence on the substrate.

[0338] In example embodiments, the first semiconductor layer may be an amorphous silicon layer or a polycrystalline silicon layer.

[0339] In an exemplary embodiment, the second semiconductor layer may be a metal oxide layer. The metal oxide layer may be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium, and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium, and tin, an oxide containing indium and zinc, an oxide containing silicon, indium, and tin, or an oxide containing indium or gallium and zinc. The metal oxide layer may be a single layer, a double layer, or a multilayer.

[0340] In an exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, etc.

[0341] In an exemplary embodiment, the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer and the fifth insulating layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and can be a single layer, a multilayer or a composite layer.

[0342] In an exemplary embodiment, the first planarization layer and the second planarization layer may be made of an organic material such as resin.

[0343] In an exemplary embodiment, after the driving circuit layer is prepared, a light emitting structure layer is prepared on the driving circuit layer. The preparation process of the light emitting structure layer may include the following operations.

[0344] (12) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming the fifth conductive layer pattern may include: depositing a fifth conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the fifth conductive film using a patterning process to form a fifth conductive layer disposed on the second flat layer, as shown in FIG23 and FIG24 , where FIG23 is a schematic diagram of the fifth conductive layer pattern, and FIG24 is a schematic diagram after the fifth conductive layer pattern is formed.

[0345] In an exemplary embodiment, as shown in FIG. 23 and FIG. 24 , the fifth conductive layer pattern includes at least a plurality of first electrodes.

[0346] In an exemplary embodiment, the fifth conductive layer has a single-layer structure, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or may have a multi-layer composite structure, such as ITO / Ag / ITO.

[0347] In an exemplary embodiment, the plurality of first electrodes may include a first anode AN1 for a light emitting device emitting a first color light, a second anode AN2 for a light emitting device emitting a second color light, and a third anode AN3 for a light emitting device emitting a third color.

[0348] In an exemplary embodiment, the first anode AN1 and the second anode AN2 are alternately arranged along the first direction D1. The plurality of third anodes AN3 are alternately arranged along the first direction D1. A virtual straight line extending in the second direction D2 and passing through the center of the third anode AN3 is located between a virtual straight line extending in the second direction D2 and passing through the center of the first anode AN1 and the virtual straight line extending in the second direction D2 and passing through the center of the second anode AN2.

[0349] In an exemplary embodiment, the first electrode of the light emitting device is connected to the anode connection line through the thirteenth via hole.

[0350] In an exemplary embodiment, the first electrode may include an anode body portion and an anode connection portion connected to each other, the anode connection portion being connected to the anode connection line through the thirteenth via hole. The anode body portion may be rectangular, and the corners of the rectangle may be chamfered in an arc shape.

[0351] (13) Forming a pixel definition layer pattern. In an exemplary embodiment, forming the pixel definition layer pattern may include: coating a pixel definition film on the substrate on which the aforementioned pattern is formed, patterning the pixel definition film using a patterning process to form a pixel definition layer, wherein a pixel opening PV is provided on the pixel definition layer of each sub-pixel, and the pixel definition film within the pixel opening PV is removed to expose the first electrode of the sub-pixel, as shown in FIG25 , which is a schematic diagram after the pixel definition layer is formed.

[0352] In an exemplary embodiment, an orthographic projection of the pixel opening on the substrate does not overlap with an orthographic projection of the thirteenth via hole on the substrate.

[0353] In an exemplary embodiment, the subsequent preparation process may include: first forming an organic light-emitting layer by an evaporation or inkjet printing process, then forming a cathode on the organic light-emitting layer, and then forming an encapsulation structure layer. The encapsulation structure layer may include a stacked first encapsulation layer, a second encapsulation layer, and a third encapsulation layer. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to ensure that external water vapor cannot enter the light-emitting structure layer.

[0354] Figure 26 is a cross-sectional view of a display device. The present disclosure also provides a display device. As shown in Figure 26, the display device provided by the present disclosure includes: a display substrate 10 and a light sensor 20. The orthographic projection of the light sensor 20 on the substrate at least partially overlaps with the first display area A1. Ambient light can enter the light sensor through the first display area.

[0355] In an exemplary embodiment, the display device may be any product or component with a display function, such as an organic light-emitting diode (OLED) display device, an active-matrix organic light-emitting diode (AMOLED) display device, a mobile phone, a tablet computer, a flexible display device, a television, and a monitor.

[0356] The display substrate may be the display substrate provided by any of the aforementioned embodiments, and the implementation principle and effect are similar, which will not be described in detail here.

[0357] In an exemplary embodiment, the area of ​​the orthographic projection of the light sensor on the substrate may be smaller than or equal to the area of ​​the inscribed circle of the first display area. That is, the size of the area where the light sensor is located may be smaller than or equal to the size of the inscribed circle of the first display area. For example, the size of the area where the light sensor is located may be equal to the size of the inscribed circle of the first display area. That is, the shape of the area where the light sensor is located may be circular. Accordingly, the area where the light sensor is located may also be referred to as a light-transmitting hole.

[0358] In an exemplary embodiment, the photosensor may include at least one of a camera module (e.g., a front camera module), a 3D structured light module (e.g., a 3D structured light sensor), a time-of-flight 3D imaging module (e.g., a time-of-flight sensor), an infrared sensing module (e.g., an infrared sensing sensor), etc.

[0359] In an exemplary embodiment, the front-facing camera module is typically activated when a user takes a selfie or makes a video call, and the display area of ​​the display device displays the image obtained from the selfie for the user to view. The front-facing camera module includes, for example, a lens, an image sensor, and an image processing chip. The optical image of the scene generated by the lens is projected onto the surface of the image sensor (image sensors include CCD and CMOS), where it is converted into an electrical signal. The image processing chip then converts the analog-to-digital signal into a digital image signal, which is then processed and output on the display screen.

[0360] The drawings in this disclosure only relate to the structures involved in the embodiments of this disclosure, and other structures may refer to general designs.

[0361] For the sake of clarity, the thickness and size of layers or microstructures are exaggerated in the drawings used to describe the embodiments of the present disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element can be "directly on" or "under" the other element, or intervening elements may be present.

[0362] Although the embodiments disclosed in this disclosure are as described above, the contents described are merely embodiments adopted to facilitate understanding of the disclosure and are not intended to limit the disclosure. Any person skilled in the art to which the disclosure belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the disclosure. However, the scope of patent protection of the disclosure shall still be based on the scope defined by the attached claims.

Claims

1. A pixel driving circuit, configured to drive a light-emitting device to emit light, comprising: a reset sensing subcircuit, a driving subcircuit, a node control subcircuit and a light-emitting control subcircuit; The driving subcircuit is electrically connected to the first node, the second node and the third node respectively, and is configured to provide a driving signal to the third node under the control of the signals of the first node and the second node; The reset sensing sub-circuit is electrically connected to the sensing control signal terminal, the reset signal terminal, the control signal terminal, the first node and the third node respectively, and is configured to provide the reference signal provided by the control signal terminal to the third node, or provide the signal of the first node or the third node to the control signal terminal under the control of the signals of the reset signal terminal and the sensing control signal terminal; The node control subcircuit is electrically connected to the scan signal terminal, the data signal terminal, the first node and the first power supply terminal respectively, and is configured to provide the signal of the data signal terminal to the first node under the control of the signal of the scan signal terminal, and store the voltage difference between the signal of the first node and the signal of the first power supply terminal; The light emitting control subcircuit is electrically connected to the light emitting control signal terminal, the first power supply terminal and the second node respectively, and is configured to provide the signal of the first power supply terminal to the second node under the control of the signal of the light emitting control signal terminal; The light emitting device is electrically connected to the third node and the second power supply terminal respectively.

2. The pixel driving circuit according to claim 1, wherein: The reset induction subcircuit comprises: a first induction subcircuit and a second induction subcircuit; The first sensing sub-circuit is electrically connected to the reset signal terminal, the control signal terminal and the third node respectively, and is configured to provide the reference signal provided by the control signal terminal to the third node, or provide the signal of the third node to the control signal terminal, under the control of the signal of the reset signal terminal; The second sensing sub-circuit is electrically connected to the sensing control signal terminal, the control signal terminal and the first node respectively, and is configured to provide the signal of the first node to the control signal terminal under the control of the signal of the sensing control signal terminal.

3. The pixel driving circuit according to claim 2, wherein: The first sensing subcircuit includes: a first transistor, and the second sensing subcircuit includes: a second transistor; The gate electrode of the first transistor is electrically connected to the reset signal terminal, the first electrode of the first transistor is electrically connected to the control signal terminal, and the second electrode of the first transistor is electrically connected to the third node; A gate electrode of the second transistor is electrically connected to the sensing control signal terminal, a first electrode of the second transistor is connected to the control signal terminal, and a second electrode of the second transistor is electrically connected to the first node.

4. The pixel driving circuit according to claim 1, wherein: The reset sensing subcircuit includes: a first transistor and a second transistor, the driving subcircuit includes: a third transistor, the node control subcircuit includes: a fourth transistor and a capacitor, the capacitor includes: a first plate and a second plate, and the light emitting control subcircuit includes: a fifth transistor; The gate electrode of the first transistor is electrically connected to the reset signal terminal, the first electrode of the first transistor is electrically connected to the control signal terminal, and the second electrode of the first transistor is electrically connected to the third node; The gate electrode of the second transistor is electrically connected to the sensing control signal terminal, the first electrode of the second transistor is connected to the control signal terminal, and the second electrode of the second transistor is electrically connected to the first node; The gate electrode of the third transistor is electrically connected to the first node, and the first electrode of the third transistor is electrically connected to the first node. The second node is electrically connected to the second electrode of the third transistor, and the second electrode of the third transistor is electrically connected to the third node; The gate electrode of the fourth transistor is electrically connected to the scan signal terminal, the first electrode of the fourth transistor is electrically connected to the data signal terminal, and the second electrode of the fourth transistor is electrically connected to the first node; The gate electrode of the fifth transistor is electrically connected to the light emitting control signal terminal, the first electrode of the fifth transistor is connected to the first power supply terminal, and the second electrode of the fifth transistor is electrically connected to the second node; The first plate of the capacitor is connected to the first node, and the second plate of the capacitor is electrically connected to the first power supply terminal.

5. The pixel driving circuit according to claim 4, wherein: The first transistor, the second transistor and the fourth transistor are N-type transistors, and the third transistor and the fifth transistor are P-type transistors.

6. A driving method of a pixel driving circuit, configured to drive the pixel driving circuit according to any one of claims 1 to 5, wherein the pixel driving circuit is arranged in a display substrate, and a working process of the display substrate comprises: display phase and non-display phase; In the display stage and the non-display stage, the driving method of the pixel driving circuit includes: The driving subcircuit provides a driving signal to the third node under the control of the signals of the first node and the second node; The reset sensing subcircuit provides the reference signal provided by the control signal terminal to the third node, or provides the signal of the first node or the third node to the control signal terminal, under the control of the signals of the reset signal terminal and the sensing control signal terminal; The node control subcircuit provides the signal of the data signal terminal to the first node under the control of the signal of the scan signal terminal, and stores the voltage difference between the signal of the first node and the signal of the first power terminal; The light emitting control subcircuit provides the signal of the first power supply terminal to the second node under the control of the signal of the light emitting control signal terminal.

7. The method according to claim 6, wherein: The display stage includes: a first reset stage, a first data writing stage and a light emitting stage; The signal of the sensing control signal end in the display stage is an invalid level signal, the signal of the reset signal end in the first reset stage is a valid level signal, and the signal in the first data writing stage and the light emitting stage is an invalid level signal, the signal of the scanning signal end in the first data writing stage is a valid level signal, and the signal in the first reset stage and the light emitting stage is an invalid level signal, the signal of the light emitting control signal end in the light emitting stage is a valid level signal, and the signal in the first reset stage and the first data writing stage is an invalid level signal; In the display stage, the driving method of the pixel driving circuit includes: In the first reset phase, the reset sensing subcircuit provides the reference signal provided by the control signal terminal to the third node under the control of the signal at the reset signal terminal; In the first data writing phase, the node control subcircuit provides the signal of the data signal terminal to the first node under the control of the signal of the scan signal terminal, and stores the voltage difference between the signal of the first node and the signal of the first power terminal; In the light-emitting stage, the light-emitting control subcircuit provides the signal of the first power supply end to the second node under the control of the signal of the light-emitting control signal end, and the driving subcircuit provides the driving signal to the third node under the control of the signals of the first node and the second node.

8. The method according to claim 6, wherein: The non-display stage includes: a first sensing stage, the first sensing stage occurs before the display stage, and the first sensing stage includes: a second reset stage, a second data writing stage and a first sampling stage; The signal of the sensing control signal end in the first sensing stage is an invalid level signal, the signal of the reset signal end in the second reset stage and the first sampling stage is a valid level signal, and the signal in the second data writing stage is an invalid level signal, the signal of the scanning signal end in the second data writing stage is a valid level signal, and the signal in the second reset stage and the first sampling stage is an invalid level signal, the signal of the light emitting control signal end in the first sampling stage is a valid level signal, and the signal in the second reset stage and the second data writing stage is an invalid level signal; In the first sensing stage, the driving method of the pixel driving circuit includes: In the second reset phase, the reset sensing subcircuit provides the reference signal provided by the control signal terminal to the third node under the control of the signal at the reset signal terminal; In the second data writing phase, the node control subcircuit provides the signal of the data signal terminal to the first node under the control of the signal of the scan signal terminal, and stores the voltage difference between the signal of the first node and the signal of the first power terminal; In the first sampling stage, the light-emitting control subcircuit provides the signal of the first power supply terminal to the second node under the control of the signal of the light-emitting control signal terminal, the driving subcircuit provides the driving signal to the third node under the control of the signals of the first node and the second node, and the reset sensing subcircuit provides the signal of the third node to the control signal terminal under the control of the signal of the reset signal terminal.

9. The method according to claim 8, wherein: The display substrate further comprises: an integrated circuit electrically connected to the pixel driving circuit; The integrated circuit acquires the signal of the third node, processes the signal of the third node, and provides the processed signal of the third node to the pixel driving circuit to compensate for the brightness of the light emitting device.

10. The method according to claim 6, wherein: The non-display stage includes: a second sensing stage, the second sensing stage occurs before the display stage, and the second sensing stage includes: a third reset stage, a third data writing stage, and a second sampling stage; The signal of the reset signal end in the third reset stage is a valid level signal, and the signal in the third data writing stage and the second sampling stage is an invalid level signal, the signal of the scanning signal end in the third data writing stage is a valid level signal, and the signal in the third reset stage and the second sampling stage is an invalid level signal, the signal of the light emitting control signal end in the second sampling stage is a valid level signal, and the signal in the third reset stage and the third data writing stage is an invalid level signal, the signal of the sensing control signal end in the second sampling stage is a valid level signal, and the signal in the third reset stage and the third data writing stage is an invalid level signal; In the second sensing stage, the driving method of the pixel driving circuit includes: In the third reset stage, the reset sensing subcircuit provides the reference signal provided by the control signal terminal to the third node under the control of the signal of the reset signal terminal; In the third data writing phase, the node control subcircuit provides the signal of the data signal terminal to the first node under the control of the signal of the scan signal terminal, and stores the voltage difference between the signal of the first node and the signal of the first power terminal; In the second sampling phase, the light emitting control subcircuit provides the signal of the first power supply terminal to the second node under the control of the signal of the light emitting control signal terminal, the driving subcircuit provides the driving signal to the third node under the control of the signals of the first node and the second node, and the reset sensing subcircuit Under the control of the signal of the control signal terminal, the signal of the first node is provided to the control signal terminal.

11. The method according to claim 10, wherein: The display substrate further comprises: an integrated circuit electrically connected to the pixel driving circuit; The integrated circuit acquires the signal of the first node, processes the signal of the first node, and provides the processed signal of the first node to the pixel driving circuit to compensate for the threshold voltage of the driving transistor in the pixel driving circuit.

12. A display substrate, comprising: Base, The substrate comprises: a display area and a non-display area surrounding the display area, the display area comprises: a first display area and a second display area, the second display area is located at least on one side of the first display area; The first display area includes: a plurality of first sub-pixels, the second display area includes: a plurality of second sub-pixels, and at least one of the first sub-pixels and the second sub-pixels includes: the pixel driving circuit according to any one of claims 1 to 5.

13. The display substrate according to claim 12, wherein: The pixel driving circuit includes: at least one P-type transistor and at least one N-type transistor; An orthographic projection of the at least one P-type transistor on the substrate at least partially overlaps with an orthographic projection of the at least one N-type transistor on the substrate.

14. The display substrate according to claim 13, wherein: The transistor includes an active pattern, and an orthographic projection of the active pattern of the at least one N-type transistor on the substrate at least partially overlaps with an orthographic projection of the active pattern of the at least one P-type transistor on the substrate.

15. The display substrate according to claim 14, wherein: An orthographic projection of the active pattern of the at least one N-type transistor on the substrate is located within an orthographic projection of the active pattern of the at least one P-type transistor on the substrate.

16. The display substrate according to claim 14, wherein: The display area further includes: at least one first power line; The orthographic projection of the first power line on the substrate at least partially overlaps with the orthographic projection of the active pattern of the at least one P-type transistor on the substrate, and the orthographic projection of the first power line on the substrate at least partially overlaps with the orthographic projection of the active pattern of the at least one N-type transistor on the substrate; The active pattern of the at least one P-type transistor is located on a side of the first power line close to the substrate, and the active pattern of the at least one N-type transistor is located on a side of the first power line far from the substrate.

17. The display substrate according to claim 12, wherein: The display area further comprises: pixel units arranged in an array, at least one light emitting control signal line, at least one reset signal line, at least one scanning signal line, at least one sensing control signal line, at least one data signal line, at least one control signal line and at least one first power supply line, at least one pixel unit comprises: at least one sub-pixel arranged along a first direction; The at least one pixel unit is electrically connected to the light emitting control signal line, the reset signal line, the scanning signal line, the sensing control signal line, N data signal lines, N control signal lines and N first power lines, respectively, where N is the number of sub-pixels in a pixel unit.

18. The display substrate according to claim 17, wherein: Pixel structures of adjacent sub-pixels among the plurality of sub-pixels arranged along the first direction are at least partially symmetrically arranged with respect to a virtual straight line extending along a second direction, and the first direction and the second direction intersect.

19. The display substrate according to claim 12, wherein: The display area further includes: at least one data signal line and at least one control signal line, wherein the data signal line and the control signal line at least partially extend along the second direction; The data signal line is electrically connected to a data signal terminal connected to the pixel driving circuit, and the control signal line is electrically connected to a control signal terminal connected to the pixel driving circuit; The data signal lines connecting adjacent sub-pixels among the multiple sub-pixels arranged along the first direction are symmetrically arranged relative to the center line of the adjacent sub-pixels, and the control signal lines connecting adjacent sub-pixels among the multiple sub-pixels arranged along the first direction are symmetrically arranged relative to the center line of the adjacent sub-pixels.

20. The display substrate according to claim 12, wherein: The display area further includes: at least one first power line; the first power line at least partially extends along the second direction; The first power line is electrically connected to the first power terminal connected to the pixel driving circuit, adjacent first power lines are electrically connected, and the first power lines connected to adjacent sub-pixels in a plurality of sub-pixels arranged along the first direction are symmetrically arranged relative to the midline of the adjacent sub-pixels.

21. The display substrate according to claim 20, wherein: The first power line includes: a first connection line, a second connection line and a plurality of connection blocks, the first connection line and the second connection line are arranged along a first direction and extend along a second direction, the connection block is arranged between the first connection line and the second connection line, the pixel driving circuit includes: a capacitor, the capacitor includes: a first plate and a second plate; The orthographic projection of the connecting block on the substrate at least partially overlaps with the orthographic projection of the first electrode plate on the substrate, and the multiple connecting blocks located between the first connecting line and the second connecting line are arranged along the second direction and are arranged at intervals, and a closed area is formed between adjacent connecting blocks arranged along the second direction and adjacent first connecting lines and second connecting lines.

22. The display substrate according to claim 12, wherein: The display area further includes: at least one light emitting control signal line, at least one reset signal line, at least one scan signal line and at least one sensing control signal line, wherein at least one of the light emitting control signal line, the reset signal line, the scan signal line and the sensing control signal line at least partially extends along the first direction; The light emitting control signal line is electrically connected to the light emitting control signal terminal connected to the pixel driving circuit, the reset signal line is electrically connected to the reset signal terminal connected to the pixel driving circuit, the scanning signal line is electrically connected to the scanning signal terminal connected to the pixel driving circuit, and the sensing control signal line is electrically connected to the sensing control signal terminal connected to the pixel driving circuit; The orthographic projections of the light emitting control signal line, the scanning signal line, the sensing control signal line and the reset signal line connected to at least one sub-pixel on the substrate are arranged in sequence along the second direction; The light emitting control signal line is arranged in a different layer from at least one of the reset signal line, the scanning signal line and the sensing control signal line.

23. The display substrate according to claim 12, further comprising: A driving structure layer is provided on the substrate, wherein the driving structure layer is provided with an anode connection line, a light emitting control signal line, a reset signal line, a scanning signal line, a sensing control signal line, a first power line, a data signal line, a control signal line and the pixel driving circuit, wherein the driving structure layer at least comprises: a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer and a fourth conductive layer stacked in sequence in a direction away from the substrate, wherein the pixel driving circuit comprises: at least one P-type transistor, at least one N-type transistor and a capacitor, wherein the transistor comprises: an active pattern, a gate electrode, a first pole and a second pole, and wherein the capacitor comprises: a first plate and a second plate; The first semiconductor layer at least includes: the active pattern of the at least one P-type transistor located in at least one sub-pixel; The first conductive layer at least includes: the light emitting control signal line and the at least one The gate electrode of a P-type transistor and the first plate of the capacitor; The second conductive layer at least includes: the first power line, the second electrode plate of the capacitor located in at least one sub-pixel, and the first electrode and the second electrode of the at least one P-type transistor; The second semiconductor layer at least includes: an active pattern of the at least one N-type transistor located in at least one sub-pixel; The third conductive layer at least includes: the reset signal line, the scan signal line, the sensing control signal line, and a gate electrode, a first electrode, and a second electrode of the at least one N-type transistor located in at least one sub-pixel; The fourth conductive layer at least includes: the data signal line, the control signal line, and the anode connection line located in at least one sub-pixel.

24. The display substrate according to claim 19, wherein: At least a portion of at least one of the data signal line and the control signal line is a transparent conductive signal line.

25. The display substrate according to claim 23, further comprising: A light emitting structure layer located on a side of the driving structure layer away from the substrate, the light emitting structure layer comprising: a fifth conductive layer and a pixel definition layer sequentially stacked on the substrate, the fifth conductive layer at least comprising: a first electrode of the light emitting device, the pixel definition layer being provided with a plurality of pixel openings, the pixel openings comprising: a first pixel opening, a second pixel opening and a third pixel opening; The light emitting device comprises: a first light emitting device, a second light emitting device and a third light emitting device, wherein the first light emitting device, the second light emitting device and the third light emitting device emit light of different colors; The first pixel opening exposes the first electrode of the first light emitting device, the second pixel opening exposes the first electrode of the second light emitting device, and the third pixel opening exposes the first electrode of the third light emitting device; The area of ​​the first pixel opening located in the first display area is smaller than the area of ​​the first pixel opening located in the second display area, the area of ​​the second pixel opening located in the first display area is smaller than the area of ​​the second pixel opening located in the second display area, and the area of ​​the third pixel opening located in the first display area is smaller than the area of ​​the third pixel opening located in the second display area.

26. The display substrate according to claim 12, wherein: The light transmittance of the first display area is greater than the light transmittance of the second display area, and the sub-pixel density of the first display area is less than or equal to the sub-pixel density of the second display area.

27. A display device comprising the display substrate according to any one of claims 12 to 26 and a photosensor; The orthographic projection of the photosensor on the substrate at least partially overlaps with the first display area.

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