Resistive random access memory and erasing compilation method, chip, and electronic device

Abstract

The present application discloses a resistive random access memory and an erasing compilation method, a chip, and an electronic device. The erasing compilation method for the resistive random access memory comprises: performing a first erasing compilation operation on memory cells of the resistive random access memory; when the first erasing compilation operation ends and a preset waiting time has elapsed, verifying the memory cells for which the first erasing compilation operation ends, so as to determine problematic memory cells among the memory cells for which the first erasing compilation operation ends; and performing a second erasing compilation operation on the problematic memory cells. The erasing compilation method in the present application can improve the accuracy and integrity of the erasing operation, reduce the erasing failure rate, and thus enhance the durability of the resistive random access memory.

Description

Resistive random access memory and erasure compilation method, chip and electronic device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed on October 31, 2023, with application number 202311435193.9 and titled “Resistive Random Access Memory and Erasure Compilation Method, Chip and Electronic Device”. Technical Field

[0003] Embodiments of the present disclosure relate to the field of storage technology, and in particular to an erase and compile method for a resistive random access memory, a resistive random access memory, an in-memory computing chip, and an electronic device. Background Art

[0004] For Resistive Random Access Memory (ReRAM), the erase compilation method usually uses a combination of an erase pulse and a reverse write pulse. Specifically, as shown in Figure 1, after applying an erase pulse to the memory cell, it is verified to determine whether the erasure is successful. If it is unsuccessful, the next erase pulse is applied and verified. After the verification of the successful erasure, a reverse write pulse is applied to the memory cell to verify whether the erasure is complete. If the verification of the erasure is still successful, the writing of the memory cell is terminated. For the ReRAM cell that failed the verification, the next erase pulse is applied and verified. After the erase verification, the reverse write pulse is continued for verification. This cycle is repeated until the erasure is successful and the erase compilation process is completed.

[0005] However, from the perspective of the filament theory of RRAM, when the metal filament is thermally melted by the erase pulse, the RRAM enters a high-resistance state. Due to the activity of the metal atoms and the incomplete melting of the conductive filament, there are still very few metal atoms close to each other or the breakpoints of the filament are too close to each other. It is possible that after the memory cell is successfully erased and verified, the filaments of a small number of memory cells will automatically reconnect after a period of time. Since the filament may automatically reconnect after it is melted, the RRAM is not erased cleanly, that is, the number of erased failed cells is high. As the number of uses increases, the number of such failed cells will increase significantly, thereby greatly reducing the durability of the RRAM.

[0006] Summary of the Invention

[0007] The present disclosure aims to solve at least one of the technical problems existing in the prior art. To this end, one purpose of the present disclosure is to provide an erase compilation method for a resistive random access memory (RRAM), which can improve the accuracy and integrity of the erase operation, reduce the erase failure rate, and thus enhance the durability of the RRAM.

[0008] The second purpose of the disclosed embodiment is to provide a resistive random access memory.

[0009] The third objective of the disclosed embodiment is to provide an in-memory computing chip.

[0010] The fourth objective of the embodiments of the present disclosure is to provide an electronic device.

[0011] In order to achieve the above-mentioned purpose, the erase compilation method of the resistive random access memory of the first aspect of the present invention includes: performing a first erase compilation operation on the storage unit of the resistive random access memory; after the first erase compilation operation is completed and waiting for a preset time, verifying the storage unit where the first erase compilation operation is completed to determine the storage unit with problems among the storage units where the first erase compilation operation is completed; and performing a second erase compilation operation on the storage unit with problems.

[0012] According to the erase compilation method of the resistive random access memory of the embodiment of the present disclosure, a waiting time is introduced after the first erase compilation operation is completed, and erase verification is performed after waiting for the preset time, so that there is sufficient time after the first erase compilation operation for the storage unit whose wire is not completely blown to switch the state, and the problematic storage unit is determined more accurately. In addition, a second erase compilation operation is performed on the problematic storage unit, which ensures the accuracy and completeness of the erase, reduces the possibility of failure caused by too fast operation, reduces the erase failure rate, and thus enhances the durability of the resistive random access memory.

[0013] In some embodiments, the value of the preset time t satisfies 30s≤t≤25min.

[0014] In some embodiments, the preset time is set to t=5 min.

[0015] In some embodiments, a first erase and compile operation is performed on the memory cell of the resistive random access memory, including: a first reset step, applying a reset voltage to the memory cell of the resistive random access memory to switch the memory cell to a high-resistance state; a first read step, applying a read voltage to the memory cell to detect the actual resistance state of the memory cell, wherein the read voltage is less than the reset voltage; if the actual resistance state of the memory cell is a high-resistance state, the first erase and compile operation ends.

[0016] In some embodiments, performing a first erase and compile operation on the storage unit of the resistive random access memory further includes: if the actual resistance state of the storage unit is not a high-resistance state, returning to the first reset step, and looping the first reset step and the first read step until the actual resistance state of the storage unit is a high-resistance state or the number of cycles of the first reset step and the first read step reaches a first preset number, and the first erase and compile operation ends.

[0017] In some embodiments, verifying the memory cell at the end of the first erase compilation operation to determine the memory cell with a problem among the memory cells at the end of the first erase compilation operation includes: applying a read voltage to the memory cell at the end of the first erase compilation operation to detect the actual resistance state of the memory cell at the end of the first erase compilation operation; if the actual resistance state of the memory cell at the end of the first erase compilation operation is not a high resistance state, then the memory cell is the memory cell with a problem.

[0018] In some embodiments, performing a second erase compilation operation on the problematic memory cell includes: a second reset step of applying a reset voltage to the problematic memory cell to switch the problematic memory cell to a high-resistance state; a second read step of applying a read voltage to the problematic memory cell to detect an actual resistance state of the problematic memory cell; if the actual resistance state of the problematic memory cell is a high-resistance state, terminating the second erase compilation operation on the problematic memory cell.

[0019] In some embodiments, performing a second erase compilation operation on the problematic memory cell further includes: if the actual resistance state of the problematic memory cell is not a high-resistance state, returning to the second reset step, and looping the second reset step and the second read step until the actual resistance state of the problematic memory cell is switched to a high-resistance state or the number of cycles of the second reset step and the second read step reaches a first preset number.

[0020] In some embodiments, the value L of the first preset number of times satisfies: 1 time ≤ L ≤ 1000 times.

[0021] In some embodiments, the erase program method further includes: before performing the first erase program operation on the storage unit of the resistive random access memory, performing a second preset number of set-reset operations on the storage unit of the resistive random access memory.

[0022] In some embodiments, in response to the second preset number of times being multiple times, a second preset number of set-reset operations are performed on the storage unit of the resistive random access memory, including: a set step, applying a set voltage to the storage unit so that the storage unit switches to a low resistance state; a third reset step, applying a reset voltage to the storage unit so that the storage unit switches to a high resistance state; and repeating the set step and the third reset step for the second preset number of times.

[0023] In some embodiments, the value N of the second preset number satisfies 10 times ≤ N ≤ 25 times.

[0024] In some embodiments, the second preset number of times is N=20 times.

[0025] In order to achieve the above-mentioned purpose, the resistive random access memory of the second embodiment of the present disclosure is erased and compiled using the erase and compile method of the resistive random access memory described in the above embodiment.

[0026] According to the resistive random access memory of the embodiment of the present disclosure, by adopting the erase compilation method of the resistive random access memory described in the above embodiment, a waiting time is introduced after the first erase compilation operation is completed, and erase verification is performed after waiting for the preset time, so that there is sufficient time after the first erase compilation operation for the storage unit whose wire is not completely blown to switch the state, and the problematic storage unit is determined more accurately. In addition, a second erase compilation operation is performed on the problematic storage unit, thereby ensuring the accuracy and completeness of the erase, reducing the possibility of failure caused by too fast operation, and reducing the erase failure rate, thereby enhancing the durability of the resistive random access memory.

[0027] In order to achieve the above-mentioned purpose, the in-memory computing chip of the third embodiment of the present disclosure includes the resistive random access memory as described in the above embodiment, and the resistive random access memory includes multiple storage units.

[0028] According to the in-memory computing chip of the embodiment of the present disclosure, the resistive random access memory described in the above embodiment is adopted. After the first erase compilation operation is completed, a waiting time is introduced, and erase verification is performed after waiting for the preset time, so that there is sufficient time after the first erase compilation operation for the storage unit whose wire is not completely blown to switch the state, and the problematic storage unit is determined more accurately. A second erase compilation operation is performed on the problematic storage unit, which ensures the accuracy and completeness of the erasure, reduces the possibility of failure caused by too fast operation, reduces the erase failure rate, and thus enhances the durability of the in-memory computing chip.

[0029] In order to achieve the above-mentioned objectives, the electronic device according to the fourth embodiment of the present disclosure includes the in-memory computing chip described in the above embodiments.

[0030] According to an electronic device according to an embodiment of the present disclosure, the electronic device includes the in-memory computing chip described in the above embodiment, and the in-memory computing chip uses the resistive random access memory erase compilation method proposed in the embodiment of the present disclosure. After the first erase compilation operation is completed, a waiting time is introduced, and erase verification is performed after waiting for the preset time, so that there is sufficient time after the first erase compilation operation to switch the state of the storage unit whose wire is not completely blown, and the problematic storage unit is determined more accurately. A second erase compilation operation is performed on the problematic storage unit, ensuring the accuracy and completeness of the erase, reducing the possibility of failure caused by too fast operation, and reducing the erase failure rate, thereby enhancing the stability and durability of the electronic device.

[0031] Additional aspects and advantages of the embodiments of the present disclosure will be given in part in the description below and in part will become apparent from the description below or will be learned through practice of the embodiments of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The above and / or additional aspects and advantages of the present disclosure will become apparent and readily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0033] FIG1 is a schematic diagram of an erase and compile method of a resistive random access memory in the related art;

[0034] FIG2 is a schematic structural diagram of a resistive random access memory storage unit according to an embodiment of the present disclosure;

[0035] FIG3 is a schematic diagram of resistance state switching of a resistive random access memory according to an embodiment of the present disclosure;

[0036] FIG4 is a voltage-current (V1) characteristic diagram of a resistive random access memory according to an embodiment of the present disclosure;

[0037] FIG5 is a schematic diagram of a 1T1R array of a resistive random access memory according to an embodiment of the present disclosure;

[0038] FIG6 is a schematic diagram of the basic architecture of an in-memory computing chip according to an embodiment of the present disclosure;

[0039] FIG7 is a flow chart of an erase and compile method of a resistive random access memory according to an embodiment of the present disclosure;

[0040] FIG8 is a schematic diagram of an erase voltage and a verification voltage according to one embodiment of the present disclosure;

[0041] FIG9 is a simplified flowchart of an erasure compilation method according to an embodiment of the present disclosure;

[0042] FIG10 is an overall flow chart of an erase and compile method of a resistive random access memory according to an embodiment of the present disclosure;

[0043] FIG11 is a block diagram of an in-memory computing chip according to one embodiment of the present disclosure;

[0044] FIG12 is a block diagram of an electronic device according to one embodiment of the present disclosure.

[0045] Reference numerals:

[0046] electronic device 100;

[0047] In-memory computing chip 1;

[0048] Resistive random access memory 10;

[0049] Storage unit 11. DETAILED DESCRIPTION

[0050] Embodiments of the present disclosure will be described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. Embodiments of the present disclosure will be described in detail below.

[0051] Resistive random access memory (ReRAM) is a new type of non-volatile memory composed of a material that can switch between different resistance states. The resistance of this material can be adjusted in response to changes in external voltage. In RRAM, data is stored by changing the material's resistance state (typically switching between high and low resistance states). This storage method has advantages such as fast write speeds, low power consumption, high density, and long life, and is therefore widely researched and applied in various fields.

[0052] Figure 2 is a schematic diagram of the structure of a resistive random access memory (RRAM) storage unit according to an embodiment of the present disclosure. As shown in Figure 2, the RRAM storage unit is a MIM structure formed by stacking a metal (second electrode) - a resistive dielectric (resistive layer) - a metal (first electrode). The resistive layer acts as an ion transport and storage medium, utilizing resistance switching characteristics to achieve data storage.

[0053] Figure 3 is a schematic diagram of the resistance state switching of a resistive random access memory according to an embodiment of the present disclosure. As shown in Figure 3, when a set operation is performed on a memory cell of the resistive random access memory, a conductive path is formed within the resistive layer, and the memory cell changes to a low resistance state (LRS). When a reset operation is performed on the memory cell, the conductive path of the resistive layer is blocked, and the memory cell switches from a low resistance state (LRS) to a high resistance state (HRS).

[0054] Therefore, the memory cell of the RRAM can be switched from a high-resistance state to a low-resistance state through a Set operation, that is, storing data "1", and can be switched from a low-resistance state to a high-resistance state through a Reset operation, that is, storing data "0". The RRAM stores data 0 and 1 through this high-low resistance state transition, thereby achieving the purpose of writing and erasing.

[0055] Figure 4 is a voltage-current (V1) characteristic diagram of a resistive random access memory according to an embodiment of the present disclosure. As shown in Figure 4, under different voltage conditions, the resistive switching state of the resistive random access memory changes, thereby enabling erase and program operations.

[0056] Figure 5 is a schematic diagram of a 1T1R array of a resistive random access memory according to an embodiment of the present disclosure, i.e., an array of a 1T1R structure consisting of a transistor and a resistive random access memory. Figure 6 is a schematic diagram of the basic architecture of an in-memory computing chip according to an embodiment of the present disclosure, wherein the memory cells adopt a 1T1R structure.

[0057] The following describes an erase compile method of a resistive random access memory according to an embodiment of the present disclosure with reference to FIG. 7 .

[0058] FIG7 is a flow chart of a method for erasing and compiling a resistive random access memory according to an embodiment of the present disclosure. As shown in FIG7 , the method for erasing and compiling a resistive random access memory includes at least steps S1-S3, which are as follows:

[0059] S1, performing the first erase and compile operation on the storage unit of the resistive random access memory.

[0060] In some embodiments, a memory cell can be the smallest data unit in a resistive random access memory (RRAM). Each memory cell consists of a variable resistor element whose resistance state can be switched between high resistance and low resistance. Each memory cell represents the state of a bit (0 or 1). By applying voltage or current to the memory cell, the resistance state of the material can be changed, thereby enabling the storage and reading of information.

[0061] In some embodiments, an erase program operation may refer to applying a specific erase pulse or voltage to a memory cell in a resistive random access memory (RRAM) to change the resistance state of the memory cell and erase the information. During an erase program operation, the resistance state of the memory cell is typically changed from a low resistance state to a high resistance state so that data can be restored in a subsequent write operation. The erase program operation is very important because it allows the memory cell to be reused to store new information, ensuring the multi-writability of the RRAM.

[0062] In some embodiments, a first erase and program operation is performed on the memory cells of the resistive random access memory. This operation is intended to erase the data in the memory cells. However, due to the material properties of the resistive random access memory and the influence of the external environment, some memory cells may not be completely erased after the first erase and program operation, leaving some residual information. Therefore, these problematic memory cells need to be processed again later.

[0063] S2, after the first erase and compile operation is completed and a preset time is waited, verifying the memory cells where the first erase and compile operation is completed to determine memory cells with problems among the memory cells where the first erase and compile operation is completed.

[0064] In some embodiments, in a resistive random access memory, when the metal wire is thermally melted by an erase pulse and enters a high-resistance state, due to the activity of the metal atoms and the conductive wire is not completely melted (there are still very few metal atoms close to being connected or the breakpoints of the wire are too close to each other), it may cause a small number of storage cells that have been successfully erased and verified to automatically reconnect after a period of time. Since the wire may automatically reconnect after being melted, it will cause unclean erasure, that is, the problem of a high number of failed cells erased. Therefore, the purpose of setting a preset waiting time is to ensure that the storage cell has enough time to stabilize after the erase compilation operation is completed. Then, the system verifies these storage cells to determine whether there is a problem that any storage cell is not completely erased after the first erase compilation operation.

[0065] In some embodiments, the length of the preset waiting time can generally be adjusted based on material properties, environmental conditions, and device design. The length of the preset waiting time may affect the accuracy of the verification, so it needs to be reasonably set based on actual conditions.

[0066] In some embodiments, verifying the memory cell at the end of the first erase compile operation typically requires a read operation. By applying a read voltage or current to the memory cell and measuring the corresponding resistance value, the resistance state of the memory cell can be determined. If the resistance state does not reach the expected high resistance state, it can be determined that it is a problematic memory cell. These problematic memory cells may need to be processed again in a second erase compile operation to ensure that they are completely erased.

[0067] S3, performing a second erase and compile operation on the problematic memory cell.

[0068] Specifically, in the second erase program operation, for memory cells that were not completely erased after the first erase program operation, a specific erase pulse or voltage needs to be applied again to change the resistance state of these memory cells to ensure their complete erasure. The purpose of the second erase program operation is to repair the problems of memory cells that were not completely erased in the first erase program operation, restoring these memory cells to their original state to facilitate subsequent re-writing and reading operations.

[0069] In some embodiments, the parameters of the second erase compile operation, such as the amplitude, width, or frequency of the applied erase pulse, can be adjusted based on the verification results of the first erase compile operation. This adjustment can be made based on the electrical characteristics of the problematic memory cell and the reason why the first erase compile operation failed to erase. By fine-tuning the erase parameters, the effectiveness of the second erase compile operation can be improved, ensuring that the problematic memory cell is completely erased. At the same time, unnecessary damage caused by excessive erase pulses can be avoided to ensure the stability and durability of the memory cell.

[0070] According to the erase compilation method of the resistive random access memory of the embodiment of the present disclosure, a waiting time is introduced after the first erase compilation operation is completed, and erase verification is performed after waiting for the preset time, so that there is sufficient time after the first erase compilation operation for the storage unit whose wire is not completely blown to switch the state, and the problematic storage unit is determined more accurately. In addition, a second erase compilation operation is performed on the problematic storage unit, which ensures the accuracy and completeness of the erase, reduces the possibility of failure caused by too fast operation, reduces the erase failure rate, and thus enhances the durability of the resistive random access memory.

[0071] In some embodiments, the value of the preset time t satisfies 30s≤t≤25min. For example, the value of t is 30s, 80s, 2min, 5min, 10min, 15min, 20min, or 25min. This preset time range is intended to ensure that after the first erase and compile operation, the memory cells have sufficient time to stabilize, facilitating a subsequent verification operation to accurately identify problematic memory cells. Furthermore, after the verification operation, problematic memory cells can be accurately detected so that a second erase and compile operation can be performed.

[0072] In some embodiments, the selection of the preset time can be set based on the characteristics of the resistive random access memory and the actual application requirements. This range is selected to balance the efficiency and accuracy of the erase operation and ensure that the system can achieve good performance and stability in different application scenarios. Different application scenarios have different requirements for response speed and erase accuracy. For example, in some applications with high real-time requirements, a shorter waiting time may be required to complete the erase compilation operation as quickly as possible and provide a fast response. In some application scenarios with high stability and reliability requirements, a longer waiting time may be required to ensure the stability of the storage unit and accurately detect problematic storage units.

[0073] Therefore, the preset time t is set within the range of 30s ≤ t ≤ 25min, which can meet the needs of most application scenarios and also provides flexibility for system designers to select an appropriate waiting time based on specific application requirements. This range is set with consideration for versatility and practicality, making the erase compilation method effective in a variety of application scenarios.

[0074] Furthermore, in specialized applications, such as aerospace or extreme temperature environments, the characteristics of RRAM may differ. In these special scenarios, the preset time can be adjusted based on actual needs. For example, in extreme temperature environments, the preset time could be extended to several hours to ensure the accuracy and reliability of erase and program operations under these extreme conditions.

[0075] In some embodiments, the preset time is set to t = 5 minutes. The selection of a preset time of 5 minutes is based on a deep understanding of the internal characteristics of the resistive random access memory and experimental verification results. During this time period, the memory cell has sufficient time to stabilize, ensuring that subsequent verification and correction operations can be performed accurately and reliably, and achieving the best operational results.

[0076] Specifically, the first erase compilation operation can reduce the erase failure rate to a very low level, such as 0.1*xppm. However, at room temperature, the erase failure rate will continue to increase to 10*x ppm within 24 hours, which cannot meet the chip's requirements. Through the second erase compilation operation, these problematic 10*x ppm storage cells can be further corrected. Experimental verification shows that the best operation is to wait 5 minutes after the first erase compilation operation and then perform the second erase compilation operation, and the erase failure rate can be reduced to 0.1*x ppm. Moreover, after a 24-hour delay, the chip's maximum erase failure rate can be reduced to 0.5*x ppm, which can meet the chip's requirements for erase failure rate.

[0077] In some embodiments, performing a first erase program operation on a memory cell of a resistive random access memory includes: a first reset step and a first read step.

[0078] In the first reset step, a specific reset voltage is applied to the memory cell of the resistive random access memory. This voltage can cause the memory cell to switch to a high-resistance state. The high-resistance state can mean that the resistance of the memory cell is very high, almost equivalent to an open circuit, and current can hardly pass through. In this state, the memory cell is non-conductive, that is, no current flows, and it can be regarded as a state where the data has been successfully erased.

[0079] Specifically, the application of a reset voltage may cause the resistive material in the RRAM to undergo some physical or chemical changes, such as changes in the electron arrangement or adjustments to the lattice structure. These changes increase the resistance of the memory cell to a very high level, making it virtually impossible for current to pass through, i.e., reaching a high-resistance state. In this high-resistance state, the memory cell will not respond to read or write operations, meaning it no longer stores a specific data bit, thus erasing the data.

[0080] In some embodiments, the specific reset voltage value is related to the physical properties of the memory cell. During the design phase, engineers typically determine the appropriate reset voltage value based on the material properties and device specifications. This voltage value must be large enough to ensure that the memory cell's resistance state can reliably switch to a high-resistance state, thereby erasing data.

[0081] In some embodiments, a read voltage is applied to a memory cell to which a reset voltage has been applied to detect the actual resistance state of the memory cell. The read voltage may be a voltage signal used to read the resistance state of the memory cell. In a resistive random access memory, this voltage is usually small and sufficient to read the resistance value. The actual configuration may be the actual resistance value of the memory cell at a specific voltage. Specifically, under the action of the reset voltage, the resistance state of the memory cell is switched to a high resistance state. Under the action of the read voltage, the system can measure the resistance value of the memory cell. If the measured resistance value is within the high resistance range, it means that the memory cell has successfully switched to the high resistance state and the data has been erased. If the resistance value is not within the high resistance range, it means that the memory cell has not switched to the high resistance state, indicating that the erasure of the memory cell is incomplete and requires further processing or erasing operations.

[0082] In some embodiments, the read voltage is lower than the reset voltage. This is because in a resistive random access memory (RRAM), the reset voltage is typically a higher voltage, sufficient to change the resistance state of the memory cell to a high-resistance state. However, during a read operation, the resistance state of the memory cell does not need to be changed; only the current state needs to be detected. Therefore, by setting the read voltage lower than the reset voltage, it is sufficient to read the resistance value of the memory cell without changing the state of the memory cell. In this way, the system can determine whether the memory cell is currently in a high-resistance state or a non-high-resistance state for subsequent operations.

[0083] In some embodiments, if the actual resistance state of the memory cell detected in the first read step is high resistance, it indicates that the data has been erased and there is no need to recycle the first reset step and the first read step, and the first erase program operation ends.

[0084] In some embodiments, if the actual resistance state of the memory cell is not a high-resistance state, indicating that the memory cell has not been completely erased, it is necessary to return to the first reset step and cycle through the first reset step and the first read step until the actual resistance state of the memory cell is a high-resistance state or the number of cycles of the first reset step and the first read step reaches a first preset number, at which point the first erase program operation ends. This indicates that the memory cell has been successfully erased and can proceed to the subsequent verification step and programming operation.

[0085] Furthermore, in some special application scenarios, the value of the first preset number of times may need to be adjusted to ensure complete erasure of the storage unit. For example, there may be certain fluctuations in the manufacturing process, resulting in different erasure quality of the storage unit. Therefore, the setting of the first preset number of times can be adjusted according to the specific situation to ensure high erasure quality of the storage unit, thereby achieving data integrity and stability.

[0086] In some embodiments, verifying memory cells after the first erase and compile operation has been completed to determine memory cells with problems among the memory cells after the first erase and compile operation has been completed includes applying a read voltage to the memory cells after the first erase and compile operation has been completed, where the read voltage can detect the actual resistance state of the memory cells. Therefore, by applying an appropriate read voltage, the actual resistance state of the memory cells after the first erase and compile operation can be detected, thereby determining whether the actual resistance state is a high-resistance state or a non-high-resistance state.

[0087] Furthermore, if the actual resistance state of a memory cell after the first erase and compile operation is not high-resistance, this indicates that the first erase and compile operation did not completely erase the memory cell, and previously stored data may still remain. Such a memory cell can be identified as a problematic memory cell. The system can then mark this memory cell as requiring further processing.

[0088] Through this verification step, the system can accurately determine which memory cells were not fully erased after the first erase program operation. This allows the system to perform a targeted second erase program operation to ensure that all memory cells are correctly erased, improving the accuracy and success rate of the overall erase program operation. This method ensures the stability and reliability of the RRAM during operation.

[0089] In some embodiments, a second erase program operation is performed on the problematic memory cell, including a second reset step and a second read step.

[0090] Specifically, in the second reset step, a reset voltage is applied to the memory cell identified as having a problem. This reset voltage can also be a relatively high voltage, so that the memory cell with the problem switches to a high-resistance state. In the high-resistance state, the memory cell is non-conductive, which can be considered a state where the data has been successfully erased.

[0091] Furthermore, a read voltage is applied to the problematic memory cell to which the reset voltage has been applied to detect the actual resistance state of the problematic memory cell. This means that by measuring the resistance value of the memory cell under the read voltage, it is possible to determine whether the resistance state of the memory cell is high-resistance or non-high-resistance.

[0092] If the actual resistance state of the problematic memory cells is high, this means that the problematic memory cells have been correctly erased. At this point, the second erase program operation on the problematic memory cells can be completed. The memory cells are in a writable state and can be used to store new data.

[0093] In some embodiments, if the actual resistance state of the problematic memory cell is not a high-resistance state, this means that the resistance state of the problematic memory cell did not successfully switch to a high-resistance state during the second erase program operation. This may be due to physical or electrical characteristics within the memory cell, such as residual charge or special properties of the material. Since the resistance state of the memory cell did not reach a high-resistance state, the cell may still retain previously stored data.

[0094] Furthermore, in this case, the second reset step is returned to, and the second reset step and the second reading step are cycled until the actual resistance state of the problematic memory cell is switched to a high resistance state or the number of cycles of the second reset step and the second reading step reaches a first preset number.

[0095] In some embodiments, the preset number of times is set to avoid infinite loops. That is, if the preset number of loops is reached and the actual resistance state of the problematic memory cell has not yet switched to a high-impedance state, the system may determine that the memory cell is difficult to completely erase and has a hardware failure or other problem. In this case, the system may record the memory cell as unavailable to avoid affecting the stability and operational efficiency of the overall system.

[0096] Therefore, through this loop operation, the system can try to erase the problematic memory cell multiple times until its resistance state switches to a high-resistance state. This ensures that the data inside the memory cell is completely erased, ensuring data security and reliability.

[0097] In some embodiments, the value L of the first preset number of times satisfies: 1 time ≤ L ≤ 1000 times. For example, the value of L is 1 time or 2 times or 10 times or 50 times or 100 times or 200 times or 300 times or 500 times or 600 times or 800 times or 900 times or 1000 times. The range of the first preset number of times (L) is set to ensure that the system has enough opportunities to attempt erasure when handling abnormal situations. Too few erasure times may result in the storage unit not being completely erased, while too many erasure times may increase the time of the entire erase compilation process, affect the efficiency of the operation, and waste system resources. Therefore, limiting the number of erasures to a reasonable range can not only ensure the accuracy of the erasure, but also avoid unnecessary waste of resources.

[0098] In some embodiments, the value of the first preset number (L) can be determined based on the characteristics, manufacturing process, usage environment, and erase requirements of the RRAM. Generally, this value should be fully verified and analyzed to ensure that the system can effectively complete the erase program operation in most cases.

[0099] In short, during the erase compilation process, after the first erase compilation is completed, a preset time is waited, and then the memory cells are erased and verified to determine which memory cells have problems after the first erase compilation operation. As shown in Figure 8, the erase verification voltage is lower than the erase operation voltage. If the erase verification result is a successful erase, that is, the memory cell is in a high-impedance state, then the memory cell is a pass, indicating that the memory cell has no problems. Conversely, if the erase verification result is an erase failure, that is, the memory cell is not in a high-impedance state, then the erase operation is repeated again. If the number of loops exceeds the preset number, the memory cell is considered a failed memory cell.

[0100] In some embodiments, the erase compilation method further includes: before performing the first erase compilation operation on the storage cell of the resistive random access memory, performing a second preset number of set-reset operations on the storage cell of the resistive random access memory, that is, performing a preset number of write + erase operations on the storage cell of the resistive random access memory, which can be referred to as a Dummy cycle in an embodiment. This means that the storage cell will be repeatedly set (set to a non-high-resistance state) and reset (set to a high-resistance state). Through this operation, the storage cell can be pre-processed to eliminate potential instability and ensure that the storage cell can reliably switch states during the erase compilation operation.

[0101] In some embodiments, the resistance state of a memory cell is changed multiple times through a preset number of set-reset operations, ensuring that the material within the memory cell is sufficiently stable when switching resistance states. This allows the memory cell to more easily and stably switch to the desired high-resistance state during actual erase compilation operations, ensuring erase accuracy and reducing the initial erase cycle failure rate. For example, experimental data shows that the initial erase cycle failure rate of a memory cell that has undergone a preset number of set-reset operations can be reduced from the original x ppm to 0.1*x ppm.

[0102] In some embodiments, the specific value of the second preset number of times can be adjusted based on the characteristics and manufacturing process of the resistive random access memory. Generally, a higher second preset number of times increases the state stability of the memory cell, but the time required for operation also increases accordingly. Therefore, when determining a specific value, it is necessary to strike a balance between accuracy and operational efficiency and select an appropriate second preset number of times.

[0103] In some embodiments, in response to the second preset number being multiple times, performing a set-reset operation on a memory cell of the resistive random access memory for a second preset number of times includes: a set step and a third reset step.

[0104] Specifically, applying a set voltage to a memory cell causes electron or ion migration in the dielectric within the memory cell, causing the material's resistance state to change. This electric field-induced resistance change causes the memory cell to switch to a low-resistance state, which typically corresponds to the "1" state of the memory cell and indicates a relatively low resistance.

[0105] Furthermore, when a memory cell is in a low-resistance state, it indicates that the charge density in the dielectric (usually a metal oxide) within the memory cell is high, resulting in a low resistance, corresponding to the data state of "1." By applying a sufficient voltage to the memory cell, known as a reset voltage, these charges can be rearranged, causing the dielectric resistance state to increase, thereby erasing the data and switching the memory cell state to a high-resistance state, known as "0."

[0106] Furthermore, the setting step and the third resetting step are repeated for a second predetermined number of times. This alternating operation enables the memory cell to switch between the low resistance state and the high resistance state multiple times, thereby increasing the stability of the material inside the memory cell and ensuring that the memory cell can switch states reliably.

[0107] Therefore, before the actual erase program operation, the resistance state of the memory cell is made very stable through multiple set and reset operations. In this way, when the erase program operation is performed, the initial state of the memory cell has been pre-processed to a stable state, improving the reliability and accuracy of the erase program operation.

[0108] In some embodiments, the set voltage and reset voltage can be determined based on the specific characteristics and manufacturing process of the resistive random access memory. The magnitude and duration of the set voltage and reset voltage need to be precisely controlled to ensure that the resistance state of the memory cell can be stably switched without damaging the memory cell or causing irreversible changes. Therefore, precise adjustment of the set voltage and reset voltage is very important for the reliability and stability of the resistive random access memory.

[0109] In some embodiments, the value N of the second preset number of times satisfies 10 times ≤ N ≤ 25 times. For example, the value of N is 10 times or 12 times or 15 times or 18 times or 20 times or 25 times. This value range can be based on the characteristics and actual needs of the resistive random access memory. In actual applications, after a certain number of set-reset operations, the resistance state of the memory cell will be more stable, and the accuracy and reliability of erasure will be improved. For example, when N = 10, it means that 10 set-reset operations are performed to ensure that the resistance state in the memory cell is stable. Similarly, when N = 25, 25 set-reset operations are performed. Selecting the number of preset times usually requires a trade-off between performance and efficiency. Increasing the preset number of times can improve the reliability of erasure, but it will also increase the time of the erase compilation operation.

[0110] In some embodiments, the value of the second preset number of times is N=20 times. This means that the memory cell needs to perform 20 set-reset operations before the erase compilation operation. This value is determined based on actual needs, the characteristics of the resistive random access memory, and the application scenario. 20 set-reset operations are considered to be sufficient to enable the resistance state of the memory cell to switch stably before the erase compilation operation, thereby ensuring the quality of the erase compilation.

[0111] As described above, the method of the embodiment of the present disclosure, as shown in FIG9 , the entire erase and compile process may include a preset number of dummy cycles—a first erase and compile operation—waiting for a preset time—a second erase and compile operation.

[0112] FIG10 is a flow chart of an overall method for erasing and compiling a resistive random access memory according to an embodiment of the present disclosure. As shown in FIG10 , the overall flow of the method for erasing and compiling a resistive random access memory includes at least steps S10-S17, which are as follows:

[0113] S10, performing a second preset number of set-reset operations on a storage unit of the resistive random access memory.

[0114] S11, performing a first erase and program operation on the storage unit of the resistive random access memory.

[0115] S12, determine whether the actual resistance state of the memory cell is high resistance state, if so, proceed to step S13, if not, return to step S11. The return to step S11 can be executed repeatedly until the number of cycles reaches the first preset number (1000 times) and then stop.

[0116] S13, the first erase and compile operation is completed, and the preset time (5 minutes) is waited.

[0117] S14, determining whether the actual resistance state of the memory cell after the first erase and compile operation is completed is a high resistance state, if so, proceeding to step S17, if not, proceeding to step S15.

[0118] S15, determining that the memory cell is a memory cell with a problem, and performing a second erase and compile operation on the memory cell with the problem.

[0119] S16: Determine whether the actual resistance state of the problematic memory cell is high resistance. If so, proceed to step S17; if not, return to step S15. The return to step S15 may be repeated until the number of cycles reaches the first preset number (1000).

[0120] S17, determining that the storage unit is a good storage unit, and ending the erase and compile operation on the storage unit.

[0121] To sum up, by introducing the first erase compilation operation and the second erase compilation operation, and introducing a preset waiting time after the first erase compilation operation, and detecting the actual resistance state of the storage unit after each erase compilation operation, the problem of incomplete erasure can be effectively solved, the accuracy and completeness of the erasure are ensured, the erase failure rate is reduced, and the stability and durability of the resistive random access memory are enhanced.

[0122] The embodiments of the present disclosure further provide a resistive random access memory, which is erased and compiled using the erase and compile method of the resistive random access memory described in the above embodiments.

[0123] According to the resistive random access memory 10 of the embodiment of the present disclosure, by adopting the erase compilation method of the resistive random access memory described in the above embodiment, a waiting time is introduced after the first erase compilation operation is completed, and erase verification is performed after waiting for the preset time, so that there is sufficient time after the first erase compilation operation to switch the state of the storage unit whose wire is not completely blown, and the problematic storage unit is determined more accurately. In addition, a second erase compilation operation is performed on the problematic storage unit, which ensures the accuracy and completeness of the erase, reduces the possibility of failure caused by too fast operation, reduces the erase failure rate, and thus enhances the durability of the resistive random access memory 10.

[0124] The following describes an in-memory computing chip according to an embodiment of the present disclosure with reference to FIG11 .

[0125] Figure 11 is a block diagram of an in-memory computing chip according to an embodiment of the present disclosure. As shown in Figure 11, the in-memory computing chip 1 includes a resistive random access memory 10 as described in the above embodiment. The resistive random access memory 10 includes a plurality of storage cells 11. This means that the in-memory computing chip has the ability to store large-scale data, and each storage cell 11 can store one bit of data (0 or 1). These storage cells 11 use resistive random access memory technology, which has the advantages of fast write speed, low power consumption, high density and long life. These characteristics enable the in-memory computing chip 1 to efficiently store and process large-scale data.

[0126] According to the in-memory computing chip 1 of the embodiment of the present disclosure, the resistive random access memory 10 described in the above embodiment is adopted. After the first erase compilation operation is completed, a waiting time is introduced, and erase verification is performed after waiting for the preset time, so that there is enough time after the first erase compilation operation to switch the state of the storage unit whose wire is not completely blown, and the problematic storage unit is determined more accurately. For the problematic storage unit, a second erase compilation operation is performed, which ensures the accuracy and completeness of the erasure, reduces the possibility of failure caused by too fast operation, reduces the erase failure rate, and thus enhances the durability of the in-memory computing chip 1.

[0127] In some embodiments, the in-memory computing chip 1 can be widely used in various scenarios requiring large-scale data storage and processing, such as artificial intelligence, big data analysis, embedded systems, and other fields. Its efficient storage and processing capabilities, as well as the application of the erase-compile method, make the in-memory computing chip reliable and stable, providing reliable hardware support for various applications.

[0128] The following describes an electronic device according to an embodiment of the present disclosure with reference to FIG. 12 .

[0129] Figure 12 is a block diagram of an electronic device according to an embodiment of the present disclosure. As shown in Figure 12, the electronic device 100 includes the in-memory computing chip 1 described in the above embodiment.

[0130] In some embodiments, the electronic device 100 can be widely used in various fields, including but not limited to smartphones, tablet computers, embedded systems, and IoT devices. Its efficient data storage and processing capabilities, as well as its guaranteed data security, make the electronic device 100 more reliable and secure when processing sensitive information and large-scale data.

[0131] According to the electronic device 100 of the embodiment of the present disclosure, the electronic device 100 includes the in-memory computing chip 1 described in the above embodiment. The in-memory computing chip 1 uses the erase compilation method of the resistive random access memory proposed in the embodiment of the present disclosure. After the first erase compilation operation is completed, a waiting time is introduced, and erase verification is performed after waiting for the preset time, so that there is enough time after the first erase compilation operation to switch the state of the storage unit whose wire is not completely blown, and the problematic storage unit is determined more accurately. A second erase compilation operation is performed on the problematic storage unit, ensuring the accuracy and completeness of the erase, reducing the possibility of failure caused by too fast operation, and reducing the erase failure rate, thereby enhancing the stability and durability of the electronic device 100.

[0132] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "illustrative embodiments," "example," "specific example," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with the embodiment or example is included in at least one embodiment or example of the present disclosure. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example.

[0133] Although the embodiments of the present disclosure have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions, and variations may be made to the embodiments without departing from the principles and purpose of the embodiments of the present disclosure, and that the scope of the embodiments of the present disclosure is defined by the claims and their equivalents.

Claims

1. A method for erasing and compiling a resistive random access memory, characterized in that: include: Performing a first erase compilation operation on a storage unit of the resistive random access memory; After the first erase and compile operation is completed and a preset time is waited, verifying the storage unit at which the first erase and compile operation is completed to determine the storage unit with problems among the storage units at which the first erase and compile operation is completed; A second erase and compile operation is performed on the problematic memory cell.

2. The erase compilation method of the resistive random access memory according to claim 1, characterized in that: The value t of the preset time satisfies 30s≤t≤25min.

3. The erase compilation method of the resistive random access memory according to claim 2, characterized in that: The preset time value is t=5min.

4. The erase compilation method of the resistive random access memory according to claim 1, characterized in that: Performing a first erase and compile operation on a storage unit of the resistive random access memory includes: A first resetting step, applying a reset voltage to a storage unit of the resistive random access memory so that the storage unit switches to a high impedance state; A first reading step, applying a reading voltage to the memory cell to detect an actual resistance state of the memory cell, wherein the reading voltage is less than the reset voltage; If the actual resistance state of the memory cell is a high resistance state, the first erase program operation ends.

5. The erase compilation method of the resistive random access memory according to claim 4, characterized in that: Performing a first erasing and compiling operation on the storage unit of the resistive random access memory also includes: If the actual resistance state of the storage unit is not a high-resistance state, return to the first reset step, and loop the first reset step and the first read step until the actual resistance state of the storage unit is a high-resistance state or the number of cycles of the first reset step and the first read step reaches a first preset number, and the first erase compilation operation ends.

6. The erase compilation method of the resistive random access memory according to claim 1, characterized in that: Verifying the storage unit at which the first erase and compile operation is completed to determine the storage unit with problems among the storage units at which the first erase and compile operation is completed, comprises: Applying a read voltage to the memory cell where the first erase and program operation is completed to detect the actual resistance state of the memory cell where the first erase and program operation is completed; If the actual resistance state of the memory cell at the end of the first erase compilation operation is not a high resistance state, then the memory cell is the memory cell with the problem.

7. The erase compilation method of the resistive random access memory according to claim 1, characterized in that: Performing a second erase compilation operation on the problematic storage unit includes: a second resetting step of applying a reset voltage to the problematic memory cell so that the problematic memory cell switches to a high impedance state; A second reading step, applying a reading voltage to the problematic memory cell to detect an actual resistance state of the problematic memory cell; If the actual resistance state of the problematic memory cell is a high resistance state, the second erase program operation on the problematic memory cell is terminated.

8. The erase compilation method of the resistive random access memory according to claim 7, characterized in that: Performing a second erase compilation operation on the problematic storage unit also includes: If the actual resistance state of the problematic storage unit is not a high-resistance state, return to the second reset step, and loop the second reset step and the second reading step until the actual resistance state of the problematic storage unit switches to a high-resistance state or the number of cycles of the second reset step and the second reading step reaches a first preset number.

9. The erase compilation method of the resistive random access memory according to claim 5 or 8, characterized in that: The value L of the first preset number of times satisfies: 1 time ≤ L ≤ 1000 times.

10. The erase compilation method of a resistive random access memory according to any one of claims 1 to 8, characterized in that: The erasure compilation method further comprises: Before performing a first erase compilation operation on the storage unit of the resistive random access memory, a second preset number of set-reset operations are performed on the storage unit of the resistive random access memory.

11. The erase compilation method of the resistive random access memory according to claim 10, characterized in that: In response to the second preset number being a plurality of times, performing a second preset number of set-reset operations on a storage unit of the resistive random access memory, including: A setting step, applying a setting voltage to the memory cell so that the memory cell switches to a low resistance state; a third resetting step of applying a reset voltage to the memory cell so that the memory cell switches to a high impedance state; The setting step and the third resetting step are repeatedly performed for the second preset number of times.

12. The erase compilation method of the resistive random access memory according to claim 11, characterized in that: The value N of the second preset number of times satisfies 10 times≤N≤25 times.

13. The erase compilation method of the resistive random access memory according to claim 12, characterized in that: The value of the second preset number of times is N=20 times.

14. A resistive random access memory, characterized in that: The resistive random access memory is erased and compiled using the erase and compilation method of the resistive random access memory described in any one of claims 1 to 13.

15. An in-memory computing chip, characterized in that: It includes the resistive random access memory as claimed in claim 14, wherein the resistive random access memory includes a plurality of storage units.

16. An electronic device, characterized in that: Including the in-memory computing chip as described in claim 15.

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