Semiconductor device

Abstract

This semiconductor device comprises a substrate, a plurality of substrate terminals provided so as to pierce the substrate in the thickness direction of the substrate, a semiconductor chip including a plurality of chip terminals, and a first encapsulating resin. The plurality of chip terminals are electrically connected to the plurality of substrate terminals. The first encapsulating resin covers a chip front surface, a first chip side surface, and a second chip side surface of the semiconductor chip. The plurality of substrate terminals include a heat dissipation terminal including a portion lying on the outer side of the semiconductor chip in a plan view. The semiconductor device includes a heat dissipation member provided so as to be in contact with each of the chip back surface, the encapsulating surface of the first encapsulating resin, and the terminal front surface of the heat dissipation terminal.

Description

Semiconductor Devices

[0001] The present disclosure relates to semiconductor devices.

[0002] Patent Document 1 discloses a semiconductor device including a substrate on which a wiring portion is provided, a semiconductor element, and a sealing resin provided on the substrate for sealing the semiconductor element. The wiring portion includes a main surface wiring portion provided on the substrate and a through wiring portion that penetrates the substrate. The semiconductor element is mounted on the main surface wiring portion.

[0003] Japanese Patent Application Laid-Open No. 2021-5687

[0004] [Summary] Incidentally, there is room for improvement in the heat dissipation performance of semiconductor devices.

[0005] a semiconductor device according to one embodiment of the present disclosure, the semiconductor device comprising: a substrate including a substrate surface and a substrate back surface opposite the substrate surface; a plurality of substrate terminals arranged to penetrate the substrate in the thickness direction of the substrate and including a terminal surface exposed from the substrate surface and a terminal back surface including a portion exposed from the substrate back surface; a semiconductor chip including a chip surface facing the terminal surface, a chip back surface opposite the chip surface, a chip side surface connecting the chip surface and the chip back surface; and a plurality of chip terminals formed on the chip surface and electrically connected to the terminal surfaces of the plurality of substrate terminals; and a first sealing resin covering the chip surface and the chip side surface of the semiconductor chip, wherein the plurality of substrate terminals include a heat dissipation terminal including a portion positioned outward from the semiconductor chip when viewed in the thickness direction of the semiconductor chip, and the semiconductor device comprises a heat dissipation member arranged to contact each of the chip back surface, the sealing surface of the first sealing resin, and the terminal surfaces of the heat dissipation terminals.

[0006] FIG. 1 is a schematic perspective view of a semiconductor device according to one embodiment. FIG. 2 is a schematic plan view of the interior of the semiconductor device of FIG. 1. FIG. 3 is a schematic back view of the semiconductor device of FIG. 1. FIG. 4 is a schematic cross-sectional view of the semiconductor device taken along line F4-F4 in FIG. 2. FIG. 5 is a schematic plan view of an enlarged portion of the semiconductor device of FIG. 2. FIG. 6 is a schematic cross-sectional view of an enlarged portion of the semiconductor device of FIG. 4. FIG. 7 is a schematic plan view showing an exemplary manufacturing process of a semiconductor device according to one embodiment. FIG. 8 is a schematic plan view of a manufacturing process subsequent to the process shown in FIG. 7. FIG. 9 is a schematic plan view of a manufacturing process subsequent to the process shown in FIG. 8. FIG. 10 is a schematic plan view of a manufacturing process subsequent to the process shown in FIG. 9. FIG. 11 is a schematic cross-sectional view of the semiconductor device taken along line F11-F11 in FIG. 10, showing a manufacturing process subsequent to the process shown in FIG. 10. FIG. 12 is a schematic cross-sectional view of a semiconductor device according to a modified example. FIG. 13 is a schematic plan view of the interior of the semiconductor device according to the modified example. FIG. 14 is a schematic cross-sectional view of the semiconductor device taken along line F14-F14 in FIG. 13. 15, 16, and 17 are schematic cross-sectional views of a portion of a semiconductor device according to a modified example.

[0007] DETAILED DESCRIPTION Hereinafter, several embodiments of semiconductor devices according to the present disclosure will be described with reference to the accompanying drawings. Note that for simplicity and clarity of description, components shown in the drawings are not necessarily drawn to scale. Also, hatching lines may be omitted in cross-sectional views to facilitate understanding. The accompanying drawings merely illustrate embodiments of the present disclosure and should not be considered to limit the present disclosure.

[0008] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0009] The phrase "at least one" as used herein means "one or more" of the desired options. As an example, the phrase "at least one" as used herein means "only one option" or "both of two options" when the number of options is two. As another example, the phrase "at least one" as used herein means "only one option" or "any combination of two or more options" when the number of options is three or more.

[0010] As used in this specification, "the length (dimension) of A is equal to the length (dimension) of B" or "the length (dimension) of A and the length (dimension) of B are equal to each other" also includes a relationship in which the difference between the length (dimension) of A and the length (dimension) of B is, for example, within 10% of the length (dimension) of A.

[0011] <Embodiment> [Configuration of Semiconductor Device] The overall configuration of a semiconductor device 10 according to one embodiment will be described with reference to FIGS. 1 to 4. FIG. 1 schematically illustrates a perspective view of the semiconductor device 10. FIG. 2 schematically illustrates a planar view of the interior of the semiconductor device 10. FIG. 3 schematically illustrates a rear surface structure of the semiconductor device 10. FIG. 4 schematically illustrates a cross-sectional view of the semiconductor device 10 taken along line F4-F4 in FIG. 2. In FIG. 1, a semiconductor chip 20, a first sealing resin 50, and a heat dissipation member 70 (described later) are indicated by dashed lines. In FIG. 2, a substrate 40 and a second sealing resin 60 (described later) are indicated by a common two-dot chain line. In FIG. 3, the semiconductor chip 20 is indicated by a two-dot chain line. In this disclosure, the term "plan view" refers to viewing the semiconductor device 10 or components of the semiconductor device 10 in the Z direction of the X, Y, and Z axes, which are orthogonal to each other, in FIG. 1.

[0012] 1 and 4 , the semiconductor device 10 includes a semiconductor chip 20, a plurality of substrate terminals 30, a substrate 40, a first sealing resin 50, a second sealing resin 60, and a heat dissipation member 70. The plurality of substrate terminals 30 are supported by the substrate 40. The semiconductor chip 20 is mounted on the plurality of substrate terminals 30. The first sealing resin 50 is provided on the substrate 40 so as to cover the periphery of the semiconductor chip 20. The second sealing resin 60 is provided on the substrate 40 so as to seal the semiconductor chip 20, the first sealing resin 50, and the heat dissipation member 70. Each component of the semiconductor device 10 will be described below.

[0013] 1, the substrate 40 and the second sealing resin 60 constitute the front, back, and side surfaces of the semiconductor device 10. In the example shown in Fig. 1, the semiconductor device 10 is formed in the shape of a rectangular flat plate with its thickness direction aligned in the Z direction.

[0014] The substrate 40 is formed in the shape of a rectangular flat plate with its thickness direction in the Z direction. Therefore, the Z direction can be said to be the thickness direction of the substrate 40. The substrate 40 includes a substrate front surface 40S and a substrate back surface 40R facing opposite each other in the Z direction, and first to fourth substrate side surfaces 40A to 40D (see FIG. 2 ) connecting the substrate front surface 40S and the substrate back surface 40R. The substrate back surface 40R constitutes the back surface of the semiconductor device 10. The first substrate side surface 40A and the second substrate side surface 40B constitute both end surfaces of the substrate 40 in the X direction. The third substrate side surface 40C and the fourth substrate side surface 40D constitute both end surfaces of the substrate 40 in the Y direction.

[0015] The second sealing resin 60 includes a sealing surface 60S facing the same side as the substrate surface 40S, and first to fourth sealing side surfaces 60A to 60D (see FIG. 2) that intersect with the sealing surface 60S. The sealing surface 60S constitutes the device surface of the semiconductor device 10. The first sealing side surface 60A and the second sealing side surface 60B constitute both end surfaces of the second sealing resin 60 in the X direction. The third sealing side surface 60C and the fourth sealing side surface 60D constitute both end surfaces of the second sealing resin 60 in the Y direction.

[0016] The first sealing side surface 60A faces the same side as the first substrate side surface 40A, the second sealing side surface 60B faces the same side as the second substrate side surface 40B, the third sealing side surface 60C faces the same side as the third substrate side surface 40C, and the fourth sealing side surface 60D faces the same side as the fourth substrate side surface 40D. In the example shown in Figures 1 and 2, the first sealing side surface 60A and the first substrate side surface 40A are flush with each other, the second sealing side surface 60B and the second substrate side surface 40B are flush with each other, the third sealing side surface 60C and the third substrate side surface 40C are flush with each other, and the fourth sealing side surface 60D and the fourth substrate side surface 40D are flush with each other. The first sealing side surface 60A and the first substrate side surface 40A, and the second sealing side surface 60B and the second substrate side surface 40B constitute device side surfaces on both sides of the semiconductor device 10 in the X direction. The third sealing side surface 60C and the third substrate side surface 40C, and the fourth sealing side surface 60D and the fourth substrate side surface 40D constitute device side surfaces on both sides of the semiconductor device 10 in the Y direction.

[0017] (Board Terminals) As shown in FIG. 4 , the multiple board terminals 30 are arranged to penetrate the board 40 in the Z direction. As shown in FIGS. 2 and 3 , the multiple board terminals 30 are arranged along the first to fourth board side surfaces 40A to 40D in a plan view. As shown in FIG. 4 , each board terminal 30 includes a terminal front surface 30S exposed from the board front surface 40S of the board 40, a terminal back surface 30R including a portion exposed from the board back surface 40R, and multiple terminal side surfaces 30A connecting the terminal front surface 30S and the terminal back surface 30R. As shown in FIGS. 2 and 3 , one of the multiple terminal side surfaces 30A is exposed from one of the first to fourth board side surfaces 40A to 40D. Each board terminal 30 is made of a material containing, for example, copper (Cu), aluminum (Al), or the like. In this embodiment, each board terminal 30 is made of a material containing Cu.

[0018] 4, each substrate terminal 30 includes a through wiring portion 31 that penetrates the substrate 40 in the Z direction, and a surface wiring portion 32 that extends from the through wiring portion 31 along the substrate surface 40S. In one example, the through wiring portion 31 and the surface wiring portion 32 are integrated. That is, the through wiring portion 31 and the surface wiring portion 32 are integrally formed from the same metal material. Each substrate terminal 30 is formed by, for example, plating.

[0019] The through wiring portion 31 and the surface wiring portion 32 may be provided separately. In this case, the through wiring portion 31 and the surface wiring portion 32 may be made of different metal materials.

[0020] 2 to 4, in a plan view, the through wiring portion 31 of each substrate terminal 30 is disposed closer to the first to fourth substrate side surfaces 40A to 40D than the semiconductor chip 20. In other words, the through wiring portion 31 of each substrate terminal 30 is disposed outward from the semiconductor chip 20 in a plan view. In this way, the package structure of the semiconductor device 10 is a fan out package.

[0021] The through wiring portions 31 of the multiple substrate terminals 30 are arranged along the first to fourth substrate side surfaces 40A to 40D in a plan view. The through wiring portions 31 include terminal side surfaces 30A. The terminal side surfaces 30A of each through wiring portion 31 include side surfaces that are flush with the first to fourth substrate side surfaces 40A to 40D. These flush side surfaces constitute exposed side surfaces 30AA that are exposed from the first to fourth substrate side surfaces 40A to 40D. The portions of the terminal back surface 30R that correspond to the through wiring portions 31 include exposed surfaces 30RA that are exposed from the substrate 40.

[0022] A plating layer 34 is formed on both the exposed surface 30RA and the exposed side surface 30AA. The plating layer 34 formed on the exposed surface 30RA is provided so as to protrude from the substrate back surface 40R. The plating layer 34 formed on the exposed side surface 30AA is provided so as to protrude from the first to fourth substrate side surfaces 40A to 40D. In this embodiment, the plating layer 34 formed on the exposed surface 30RA of the terminal back surface 30R and the plating layer 34 formed on the exposed side surface 30AA are integrated. The plating layer 34 includes at least one of Au (gold), Ni (nickel), Sn (tin), and Pd (palladium), for example.

[0023] In plan view, the surface wiring portion 32 of each substrate terminal 30 includes a portion that extends from the through wiring portion 31 toward the semiconductor chip 20. The surface wiring portion 32 of each substrate terminal 30 is disposed at a position that overlaps the semiconductor chip 20 in plan view.

[0024] 2 and 3 , among the multiple board terminals 30, board terminals arranged at the four corners of the board 40 in a plan view (hereinafter referred to as "corner terminals 30C") include two through wiring portions 31. The two through wiring portions 31 of each corner terminal 30C are arranged at the same position as each other in the X direction and spaced apart from each other in the Y direction. The two through wiring portions 31 are connected by a surface connecting portion 33. The surface connecting portion 33 is provided, for example, on the board surface 40S of the board 40.

[0025] In the following description, one of the multiple board terminals 30 will be referred to as the "heat dissipation terminal 30P." In one example, the heat dissipation terminal 30P is one of the four corner terminals 30C that is closer to the first board side surface 40A and the fourth board side surface 40D. Therefore, the multiple board terminals 30 can be said to include a heat dissipation terminal 30P that includes a portion disposed outward from the semiconductor chip 20 in a planar view. Like the other board terminals 30, the heat dissipation terminal 30P thus includes a terminal front surface 30S, a terminal back surface 30R facing the opposite side from the terminal front surface 30S, and a terminal side surface 30A connecting the terminal front surface 30S and the terminal back surface 30R. At least a portion of the terminal side surface 30A of the heat dissipation terminal 30P is exposed from the board 40. More specifically, of the two through wiring portions 31 of the heat dissipation terminal 30P, the terminal side surface 30A facing the same side as the first substrate side surface 40A is exposed from the substrate 40 (first substrate side surface 40A). These terminal side surfaces 30A are, for example, flush with the first substrate side surface 40A. Of the two through wiring portions 31 of the heat dissipation terminal 30P, the terminal side surface 30A of the through wiring portion 31 closer to the corner portion formed by the first substrate side surface 40A and the fourth substrate side surface 40D is exposed from the fourth substrate side surface 40D.

[0026] 3 and 4 , the through wiring portion 31 of the heat dissipation terminal 30P in this embodiment extends further toward the semiconductor chip 20 than the through wiring portions 31 of the substrate terminals 30 other than the heat dissipation terminal 30P. Therefore, the volume of the through wiring portion 31 of the heat dissipation terminal 30P is larger than the volume of the through wiring portion 31 of the substrate terminals 30 other than the heat dissipation terminal 30P. In addition, in one example, the shortest distance between the through wiring portion 31 of the heat dissipation terminal 30P and the semiconductor chip 20 in a plan view is smaller than the shortest distance between the through wiring portion 31 of the substrate terminals 30 other than the heat dissipation terminal 30P and the semiconductor chip 20.

[0027] 3, 4, and 6, a detailed configuration of the semiconductor chip 20 and a mounting structure between the semiconductor chip 20 and each substrate terminal 30 will be described. Fig. 6 schematically shows an enlarged cross-sectional structure of a portion of the semiconductor chip 20 and its surrounding area.

[0028] As shown in FIG. 4 , a semiconductor chip 20 is mounted on the surface wiring portion 32 of each substrate terminal 30. The semiconductor chip 20 is formed in the shape of a rectangular flat plate with its thickness direction in the Z direction. The semiconductor chip 20 includes a semiconductor substrate 21 that constitutes the chip body. The semiconductor substrate 21 is made of a material containing, for example, silicon (Si). The semiconductor chip 20 is, for example, an LSI (Large Scale Integration).

[0029] The semiconductor substrate 21 includes a front surface 21S and a back surface 21R that face opposite each other in the Z direction. The front surface 21S faces the same side as the chip front surface 20S of the semiconductor chip 20. The back surface 21R faces the same side as the chip back surface 20R. In the example shown in FIG. 4 , the back surface 21R constitutes the chip back surface 20R.

[0030] 6 , the semiconductor chip 20 includes wiring 22 provided on the main body surface 21S of the semiconductor substrate 21, and an insulating layer 23 covering the main body surface 21S. Although not shown, a plurality of wirings 22 are provided within the insulating layer 23. The plurality of wirings 22 includes portions that face the surface wiring portions 32 of the plurality of substrate terminals 30 of the semiconductor substrate 21 in the Z direction. The insulating layer 23 includes a plurality of openings that individually expose the plurality of wirings 22 in the Z direction. The plurality of wirings 22 are made of a material that includes at least one of Al, Cu, Au, and titanium (Ti), for example.

[0031] 4, the semiconductor chip 20 includes a heat generating portion 25. The heat generating portion 25 is provided on the semiconductor substrate 21. The heat generating portion 25 is a region of the semiconductor substrate 21 that generates more heat than regions other than the heat generating portion 25. In other words, the heat generating portion 25 is a region of the semiconductor substrate 21 that is likely to become hot. The heat generating portion 25 includes, for example, a transistor.

[0032] 2, the heat generating portion 25 is disposed closer to the first chip side surface 20A in the X direction than the center of the semiconductor substrate 21 (see FIG. 4). In other words, the center of the heat generating portion 25 in the X direction is located closer to the first chip side surface 20A than the center of the semiconductor substrate 21 in the X direction. Here, in this embodiment, the X direction is an example of the "first direction."

[0033] In this embodiment, the heat generating portion 25 is disposed closer to the fourth chip side surface 20D in the Y direction than the center of the semiconductor substrate 21. In other words, the center of the heat generating portion 25 in the Y direction is located closer to the fourth chip side surface 20D than the center of the semiconductor substrate 21 in the Y direction.

[0034] In a plan view, the multiple substrate terminals 30 arranged around the heat generating portion 25 near the first chip side surface 20A and the fourth chip side surface 20D are electrically connected to the heat generating portion 25. Therefore, the heat dissipation terminals 30P are substrate terminals electrically connected to the heat generating portion 25. Note that the heat dissipation terminals 30P are insulated from the heat generating portion 25 and may be electrically connected to components of the semiconductor chip 20 other than the heat generating portion 25.

[0035] 3 and 4, the semiconductor chip 20 includes a plurality of chip terminals 24 formed on the chip surface 20S. The plurality of chip terminals 24 are individually bonded to a plurality of wirings 22 (see FIG. 6). The chip terminals 24 are formed in a cylindrical shape extending from the wirings 22 in the Z direction.

[0036] 6, the chip terminal 24 includes a cylindrical terminal body 24A and a barrier layer 24B provided on the tip surface of the terminal body 24A. The chip terminal 24 includes at least one of Cu, Al, and Ti. The barrier layer 24B is, for example, a plating layer. The barrier layer 24B includes at least one of Au, Ni, and Pd. In one example, the barrier layer 24B is made of a material containing Ni.

[0037] A barrier layer 35 is provided in a region of the surface wiring portion 32 of each substrate terminal 30 that faces the chip terminal 24 in the Z direction. The barrier layer 35 can be said to constitute a part of the terminal surface 30S. In one example, the barrier layer 35 is formed in a circular shape in a plan view. The shape of the barrier layer 35 in a plan view can be changed as desired. The barrier layer 35 includes at least one of Ni and Ti, for example.

[0038] The barrier layer 24B of each chip terminal 24 and the barrier layer 35 of the surface wiring portion 32 corresponding to that barrier layer 24B are bonded together by a conductive bonding material SD. As a result, the semiconductor chip 20 is mounted on the plurality of surface wiring portions 32. The barrier layer 35 is a layer that suppresses a decrease in the wettability of the conductive bonding material SD. In this way, the plurality of chip terminals 24 are electrically connected to the surface wiring portions 32 of the plurality of substrate terminals 30. Here, the conductive bonding material SD may be, for example, Ag paste or solder paste.

[0039] In this embodiment, the semiconductor substrate 21 includes a step portion 26. The step portion 26 is formed on the first chip side surface 20A. The first chip side surface 20A is divided into a front-side chip side surface 20AA, which is closer to the chip front surface 20S than the step portion 26, and a back-side chip side surface 20AB, which is closer to the chip back surface 20R than the step portion 26. The front-side chip side surface 20AA is connected to the chip front surface 20S. The back-side chip side surface 20AB is connected to the chip back surface 20R. The back-side chip side surface 20AB curves outward at the connection end with the chip back surface 20R. Therefore, a corner portion 27 formed by the back-side chip side surface 20AB and the chip back surface 20R of the semiconductor chip 20 is formed in a protruding shape that protrudes outward. Although not shown, the step portion 26 is also formed on the second to fourth chip side surfaces 20B to 20D (see FIG. 2). In other words, the step portion 26 is formed around the entire periphery of the semiconductor substrate 21 .

[0040] (First Sealing Resin) As shown in FIG. 4 , a first sealing resin 50 is filled between the chip surface 20S of the semiconductor chip 20 and the substrate surface 40S of the substrate 40. Therefore, it can be said that the first sealing resin 50 covers the chip surface 20S of the semiconductor chip 20. The first sealing resin 50 is also called underfill. In this embodiment, the first sealing resin 50 and the second sealing resin 60 are formed from different materials. In one example, the thermal conductivity of the first sealing resin 50 is greater than the thermal conductivity of the second sealing resin 60. In one example, the thermal conductivity of the first sealing resin 50 is greater than the thermal conductivity of air.

[0041] 2 and 4, the first sealing resin 50 covers first to fourth chip side surfaces 20A to 20D as chip side surfaces of the semiconductor chip 20. Thus, the first sealing resin 50 includes a first cover portion 51 covering the first chip side surface 20A, a second cover portion 52 covering the second chip side surface 20B, a third cover portion 53 covering the third chip side surface 20C, and a fourth cover portion 54 covering the fourth chip side surface 20D.

[0042] In one example, the first cover portion 51 covers the entire first chip side surface 20A in the Z direction. In another example, the first cover portion 51 covers the entire first chip side surface 20A in the Y direction. In one example, the second cover portion 52 covers the entire second chip side surface 20B in the Z direction. In one example, the second cover portion 52 covers the entire second chip side surface 20B in the Y direction.

[0043] In one example, the third cover portion 53 covers the entire third chip side surface 20C in the Z direction. In another example, the third cover portion 53 covers the entire third chip side surface 20C in the X direction. In one example, the fourth cover portion 54 covers the entire fourth chip side surface 20D in the Z direction. In one example, the fourth cover portion 54 covers the entire fourth chip side surface 20D in the X direction.

[0044] In this embodiment, the first to fourth cover parts 51 to 54 have the same cross-sectional shape. Therefore, hereinafter, the cross-sectional shape of the first cover part 51 will be described in detail with reference to Fig. 6, and a detailed description of the cross-sectional shapes of the second to fourth cover parts 52 to 54 will be omitted.

[0045] As shown in FIG. 6 , the first cover portion 51 includes, as the sealing surface 50S of the first sealing resin 50, an inclined surface 51A that slopes toward the terminal surface 30S of the heat dissipation terminal 30P as it increases away from the first chip side surface 20A. The inclined surface 51A is connected to a corner portion 27 defined by the chip back surface 20R and the first chip side surface 20A of the semiconductor chip 20. That is, as shown in FIG. 6 , the inclined surface 51A slopes from one of both X-direction edges of the chip back surface 20R that is closer to the first chip side surface 20A toward the terminal surface 30S of the heat dissipation terminal 30P. Note that, because the first cover portion 51 is formed over the entire Y-direction of the first chip side surface 20A, it can also be said that the inclined surface 51A slopes toward the substrate surface 40S as it increases away from the first chip side surface 20A. In the example shown in FIG. 6 , the inclined surface 51A of the first cover portion 51 is formed in a curved, concave shape.

[0046] The first cover portion 51 is provided so as not to protrude from the chip back surface 20R at the corner portion 27 of the semiconductor chip 20. The back surface side chip side surface 20AB at the corner portion 27 curves outward as it approaches the chip back surface 20R, making it difficult for the first cover portion 51 to protrude from the chip back surface 20R. In one example, in the Z direction, the end portion of the first cover portion 51 closer to the chip back surface 20R is at the same position as the chip back surface 20R.

[0047] As shown in FIG. 2 , the first sealing resin 50 is formed to partially cover the terminal surfaces 30S of the multiple board terminals 30 around the semiconductor chip 20 in a plan view. More specifically, the first to fourth cover portions 51 to 54 are formed to partially cover the terminal surfaces 30S of the multiple board terminals 30 around the semiconductor chip 20 in a plan view. As shown in FIG. 6 , the first cover portion 51 of the first sealing resin 50 covers a portion of the terminal surface 30S of the heat dissipation terminal 30P that is closer to the first chip side surface 20A of the semiconductor chip 20. In one example, the first cover portion 51 covers each of the surface wiring portion 32 and a portion of the through wiring portion 31 of the heat dissipation terminal 30P. In one example, the first cover portion 51 covers the surface wiring portion 32 of the board terminals 30 other than the heat dissipation terminal 30P, but does not cover the through wiring portion 31.

[0048] (Heat Dissipation Member) The configuration of the heat dissipation member 70 will be described with reference to Fig. 2 and Fig. 4 to Fig. 6. Fig. 5 shows a schematic planar structure of a part of the heat dissipation member 70 and its surrounding area in an enlarged scale.

[0049] As shown in FIGS. 2 and 4, the heat dissipation member 70 is provided so as to contact the chip rear surface 20R of the semiconductor chip 20, the sealing surface 50S of the first sealing resin 50, and the terminal surfaces 30S of the heat dissipation terminals 30P.

[0050] The heat dissipation member 70 is configured to transfer heat from the semiconductor chip 20 to the heat dissipation terminals 30P. The heat dissipation member 70 has a thermal conductivity greater than that of the semiconductor substrate 21 of the semiconductor chip 20. The heat dissipation member 70 has a thermal conductivity greater than that of the second sealing resin 60. The heat dissipation member 70 has a thermal conductivity greater than that of the first sealing resin 50. The heat dissipation member 70 is made of, for example, a metal material. In one example, the material constituting the heat dissipation member 70 includes at least one of Au, Cu, and Ag. In one example, the thickness of the heat dissipation member 70 is 5 μm or more and 30 μm or less. The thickness of the heat dissipation member 70 can be changed as desired.

[0051] 2 and 4 , the heat dissipation member 70 includes a first heat dissipation portion 71 in contact with the chip back surface 20R, a second heat dissipation portion 72 in contact with the first cover portion 51, and a third heat dissipation portion 73 in contact with the terminal surface 30S of the heat dissipation terminal 30P. In one example, the first heat dissipation portion 71, the second heat dissipation portion 72, and the third heat dissipation portion 73 are integrated.

[0052] The first heat dissipation portion 71 may be formed so as to cover the entire heat generating portion 25 of the semiconductor chip 20 in a plan view. In this embodiment, the first heat dissipation portion 71 is formed over the entire chip back surface 20R in a plan view. In other words, it can be said that the heat dissipation member 70 is formed over the entire chip back surface 20R. The thickness of the first heat dissipation portion 71 is thinner than the thickness of the semiconductor chip 20.

[0053] The second heat dissipation portion 72 is in contact with the inclined surface 51A of the first cover portion 51. The second heat dissipation portion 72 is formed along the curved concave shape of the inclined surface 51A. In other words, the second heat dissipation portion 72 is formed in a curved concave shape. The second heat dissipation portion 72 is formed on a part of the inclined surface 51A in the Y direction. On the other hand, the second heat dissipation portion 72 is formed over the entire inclined surface 51A in the X direction. The second heat dissipation portion 72 is formed at the same position on the inclined surface 51A in the Y direction as the heat dissipation terminal 30P.

[0054] In a plan view, the width dimension of the second heat dissipation portion 72 is equal to the width dimension of the surface wiring portion 32 of the heat dissipation terminal 30P. Here, the width dimension of the second heat dissipation portion 72 is the dimension in a direction perpendicular to the direction in which the second heat dissipation portion 72 extends in a plan view. The width dimension of the surface wiring portion 32 is the dimension in a direction perpendicular to the direction in which the surface wiring portion 32 extends in a plan view. Note that the width dimension of the second heat dissipation portion 72 can be changed as desired. In one example, the width dimension of the second heat dissipation portion 72 may be larger than the width dimension of the surface wiring portion 32 of the heat dissipation terminal 30P.

[0055] The third heat dissipation portion 73 is in contact with at least a terminal surface 30S of one of the heat dissipation terminals 30P that corresponds to one of the through wiring portions 31. In one example, the third heat dissipation portion 73 is formed over most of the terminal surface 30S of one of the through wiring portions 31.

[0056] As shown in Fig. 5 , in this embodiment, the heat dissipation member 70 is made of conductive ink. For example, Au or Ag may be used as the conductive ink. The heat dissipation member 70 is formed by, for example, inkjet printing. As shown in Fig. 5 , the heat dissipation member 70 formed by inkjet printing is made of a large number of dots 76. The dots 76 are formed in a circular shape in a plan view. The large number of dots 76 are arranged such that two adjacent dots 76 partially overlap each other, thereby forming the heat dissipation member 70.

[0057] The heat dissipation surface 70S of the heat dissipation member 70, which is formed by the large number of dots 76, includes an uneven shape. That is, adjacent dots 76 partially overlap each other, thereby forming the heat dissipation surface 70S in an uneven shape.

[0058] 7 to 11, an example of a method for manufacturing the semiconductor device 10 will be described. The method for manufacturing the semiconductor device 10 mainly includes a step of preparing a substrate 40, a step of mounting the semiconductor chip 20 on the plurality of substrate terminals 30, a step of forming a first sealing resin 50, a step of forming a heat dissipation member 70, a step of forming a second sealing resin 60, and a step of singulating.

[0059] FIG. 7 shows an example of a process for preparing a substrate 40. In the process for preparing a substrate 40, a substrate base material 840 is prepared. FIG. 7 schematically shows the planar structure of the substrate base material 840. The substrate base material 840 includes a substrate 40 and a plurality of substrate terminals 30. The substrate terminals 30 are connected by a frame (not shown) that surrounds the substrate terminals 30. The substrate terminals 30 and the frame may be integrally formed as a single unit, and can be said to constitute a lead frame. The substrate base material 840 may include a substrate 40 and a plurality of substrate terminals 30 for forming a plurality of semiconductor devices 10. FIG. 7 shows a portion of the substrate base material 840 that corresponds to one substrate 40.

[0060] The substrate base material 840 is formed in a flat plate shape with its thickness direction in the Z direction. The substrate base material 840 includes a substrate front surface 841 and a substrate back surface 842 (see FIG. 11 ) that face opposite each other in the Z direction. The substrate front surface 841 constitutes the substrate front surface 40S of each of the plurality of substrates 40. The substrate back surface 842 constitutes the substrate back surface 40R of each of the plurality of substrates 40 (see FIG. 11 ).

[0061] A plurality of board terminals 30 are provided in portions of the board base material 840 corresponding to the plurality of boards 40. Therefore, it can be said that one board 40 includes a plurality of board terminals 30 provided so as to penetrate the board 40 in the Z direction, which is the thickness direction of the board 40. Each board terminal 30 includes a terminal front surface 30S exposed from the board front surface 40S and a terminal back surface 30R exposed from the board back surface 40R (see FIG. 11 ).

[0062] FIG. 8 shows an example of a process for mounting a semiconductor chip 20 on a plurality of substrate terminals 30, and schematically illustrates a portion of a substrate base material 840 and the planar structure of the semiconductor chip 20. In the process of mounting the semiconductor chip 20 on a plurality of substrate terminals 30, first, a conductive bonding material SD (see FIG. 6 ) is applied onto the barrier layers 35 of the plurality of substrate terminals 30. Next, a plurality of chip terminals 24 (see FIG. 6 ) of the semiconductor chip 20 are placed on the plurality of substrate terminals 30 on the conductive bonding material SD. Next, the conductive bonding material SD is melted by, for example, a reflow process, and then solidified. As a result, the plurality of chip terminals 24 are bonded to the plurality of substrate terminals 30 by the conductive bonding material SD. This electrically connects the plurality of chip terminals 24 to the plurality of substrate terminals 30.

[0063] 9 is an example of a process for forming the first sealing resin 50, and schematically illustrates the planar structure of the substrate base material 840, the semiconductor chip 20, and the first sealing resin 50. In the process for forming the first sealing resin 50, a resin material is filled between the substrate surface 841 (40S) of the substrate base material 840 (substrate 40) and the semiconductor chip 20 by, for example, resin molding. In this case, the first sealing resin 50 is formed so as to cover the chip surface 20S (see FIG. 11) and the first to fourth chip side surfaces 20A to 20D of the semiconductor chip 20.

[0064] 10 is an example of a process for forming the heat dissipation member 70, and schematically illustrates the planar structure of the substrate base material 840, the semiconductor chip 20, the first sealing resin 50, and the heat dissipation member 70. In the process for forming the heat dissipation member 70, the heat dissipation member 70 is formed by inkjet printing. More specifically, conductive ink is ejected by inkjet printing onto the chip back surface 20R of the semiconductor chip 20, the first cover portion 51 of the first sealing resin 50, and the terminal surfaces 30S of the heat dissipation terminals 30P. This forms the heat dissipation member 70 in contact with each of the chip back surface 20R, the sealing surface 50S of the first sealing resin 50, and the terminal surfaces 30S of the heat dissipation terminals 30P.

[0065] FIG. 11 shows an example of a process for forming the second sealing resin 60, and schematically illustrates the cross-sectional structure of the substrate base material 840, the semiconductor chip 20, the first sealing resin 50, the heat dissipation member 70, and the second sealing resin 60.

[0066] The step of forming the second sealing resin 60 is performed after the step of forming the heat dissipation member 70. In the step of forming the second sealing resin 60, a resin layer 860 is formed on the substrate base material 840 by, for example, transfer molding so as to cover the semiconductor chip 20, the first sealing resin 50, and the heat dissipation member 70. The resin layer 860 includes a plurality of second sealing resins 60 (see FIG. 4 ). The material constituting the resin layer 860 is different from the material constituting the first sealing resin 50. The material constituting the first sealing resin 50 has a higher thermal conductivity than the material constituting the resin layer 860. In one example, the material constituting the first sealing resin 50 has a higher thermal conductivity than air.

[0067] Next, in the singulation step, the resin layer 860, the substrate base material 840, and the plurality of substrate terminals 30 are cut along the cutting lines CL in Fig. 11 by, for example, a dicing process. This results in the formation of a plurality of second sealing resins 60 and a plurality of substrates 40 (both see Fig. 4). Then, the terminal side surfaces 30A (see Fig. 4) of the through wiring portions 31 of the plurality of substrate terminals 30 are exposed from the first to fourth substrate side surfaces 40A to 40D (see Fig. 2) of the substrate 40.

[0068] Next, although not shown, the method for manufacturing the semiconductor device 10 includes a step of forming a plating layer 34 (see FIG. 4 ). The plating layer 34 is formed by, for example, electroless plating. As a result, the plating layer 34 is formed on each of the exposed surfaces 30RA and exposed side surfaces 30AA of the terminal back surfaces 30R of the multiple board terminals 30 exposed from the first sealing resin 50. Through the above steps, the semiconductor device 10 is manufactured.

[0069] The manufacturing process of the semiconductor device 10 can be modified as desired. For example, a dicing process may be used to cut the substrate base material 840 and the plurality of substrate terminals 30 along the cutting lines CL in FIG. 11 , and also to cut the resin layer 860 partway in the Z direction. This process forms the terminal side surfaces 30A (exposed side surfaces 30AA). Therefore, before separating the resin layer 860, i.e., before singulating, a plating layer 34 may be formed on each of the exposed surfaces 30RA and 30AA. Subsequently, the resin layer 860 is cut again by dicing. The semiconductor device 10 may be manufactured through the above processes.

[0070] [Operation of the Embodiment] The operation of the semiconductor device 10 of this embodiment will be described. For example, when the semiconductor device 10 is mounted on a wiring substrate (not shown), heat from the semiconductor chip 20 transfers to the wiring substrate via the multiple chip terminals 24 and the multiple substrate terminals 30. The semiconductor device 10 of this embodiment includes a heat dissipation member 70 that contacts the chip rear surface 20R of the semiconductor chip 20, the sealing surface 50S of the first sealing resin 50, and the terminal surface 30S of the heat dissipation terminal 30P. Therefore, heat from the semiconductor chip 20 transfers to the wiring substrate via the heat dissipation member 70 and the heat dissipation terminal 30P. As described above, the semiconductor device 10 of this embodiment has a heat transfer path from the semiconductor chip 20 to the wiring substrate that includes multiple paths: a first path including the multiple chip terminals 24 and the multiple substrate terminals 30, and a second path including the heat dissipation member 70 and the heat dissipation terminal 30P. This facilitates heat dissipation from the semiconductor chip 20 to the wiring substrate, thereby preventing the temperature of the semiconductor chip 20 from becoming excessively high.

[0071] Effects of the Embodiment The semiconductor device 10 of the present embodiment provides the following effects: (1) The semiconductor device 10 includes a substrate 40 including a substrate front surface 40S and a substrate back surface 40R opposite the substrate front surface 40S, a plurality of substrate terminals 30 provided to penetrate the substrate 40 in the Z direction and including a terminal front surface 30S exposed from the substrate front surface 40S and a terminal back surface 30R including a portion exposed from the substrate back surface 40R, a semiconductor chip 20 including a chip front surface 20S facing the terminal front surface 30S, a chip back surface 20R opposite the chip front surface 20S, first to fourth chip side surfaces 20A to 20D connecting the chip front surface 20S and the chip back surface 20R, and a plurality of chip terminals 24 formed on the chip front surface 20S and electrically connected to the terminal surfaces 30S of the plurality of substrate terminals 30, and a first sealing resin 50 covering the chip front surface 20S and the first to fourth chip side surfaces 20A to 20D of the semiconductor chip 20. The plurality of substrate terminals 30 include heat dissipation terminals 30P that include portions that are arranged outward from the semiconductor chip 20 in a plan view. The semiconductor device 10 includes a heat dissipation member 70 that is provided so as to be in contact with each of the chip rear surface 20R, the sealing surface 50S of the first sealing resin 50, and the terminal surfaces 30S of the heat dissipation terminals 30P.

[0072] According to this configuration, the heat transfer paths of the semiconductor chip 20 are formed as a path that moves to the heat dissipation terminals 30P via the heat dissipation member 70 and a path that moves to the substrate terminals 30 via the chip terminals 24. In this way, the number of heat transfer paths of the semiconductor chip 20 is increased, thereby improving the heat dissipation performance of the semiconductor device 10.

[0073] (2) The heat dissipation member 70 is made of conductive ink. With this configuration, the heat dissipation member 70 can be formed by inkjet printing, which reduces the manufacturing cost of the heat dissipation member 70 compared to when the heat dissipation member is formed by, for example, pressing a metal plate. In addition, because it is inkjet printing, the layout of the printing area can be easily changed. Therefore, the shape of the heat dissipation member 70 can be easily changed.

[0074] (3) The heat dissipation member 70 is formed over the entire surface of the chip rear surface 20R of the semiconductor chip 20. This configuration makes it easier for heat from the semiconductor chip 20 to move from the chip rear surface 20R to the heat dissipation member 70. Therefore, the heat dissipation performance of the semiconductor device 10 can be improved.

[0075] (4) The first sealing resin 50 is filled between the chip surface 20S of the semiconductor chip 20 and the substrate surface 40S of the substrate 40. The first sealing resin 50 and the second sealing resin 60 are made of different materials.

[0076] With this configuration, for example, a material suitable for the characteristics required for the first sealing resin 50 (for example, heat dissipation performance) and a material suitable for the characteristics required for the second sealing resin 60 (for example, sealing performance) can be selected.

[0077] (5) The thermal conductivity of the first sealing resin 50 is greater than the thermal conductivity of the second sealing resin 60. With this configuration, heat from the semiconductor chip 20 is more likely to transfer to the plurality of substrate terminals 30 of the substrate 40 via the first sealing resin 50. In addition, heat from the heat dissipation member 70 is more likely to transfer from the portion of the heat dissipation member 70 that contacts the sealing surface 50S of the first sealing resin 50 to the substrate terminals 30 via the first sealing resin 50. Therefore, the heat dissipation performance of the semiconductor device 10 can be improved.

[0078] (6) The thermal conductivity of the first sealing resin 50 is greater than that of air. This configuration further enhances the effect of (5). For example, in a configuration in which a metal plate is provided in contact with the chip back surface and the substrate terminals of a semiconductor chip and the second sealing resin 60 is omitted (hereinafter referred to as the "comparative configuration"), a third portion of the metal plate connecting a first portion bonded to the chip back surface and a second portion connected to the substrate terminal is disposed in the air. In contrast, in this embodiment, the second heat dissipation portion 72 of the heat dissipation member 70, which connects the first heat dissipation portion 71 that contacts the chip back surface 20R and the third heat dissipation portion 73 that contacts the heat dissipation terminal 30P, contacts the first sealing resin 50. This makes it easier for heat to be dissipated from the second heat dissipation portion 72 to the first sealing resin 50 compared to the comparative configuration.

[0079] (7) The first sealing resin 50 is formed so as to partially cover the substrate terminals 30 and the heat dissipation terminals 30P around the semiconductor chip 20 in a plan view. According to this configuration, the semiconductor chip 20 is connected to the substrate terminals 30 and the heat dissipation terminals 30P by the first sealing resin 50. Therefore, heat from the semiconductor chip 20 is more likely to move to the substrate terminals 30 and the heat dissipation terminals 30P via the first sealing resin 50.

[0080] (8) The semiconductor chip 20 includes a heat generating portion 25 and a first chip side surface 20A facing the X direction. The heat generating portion 25 is disposed closer to the first chip side surface 20A in the X direction relative to the semiconductor chip 20. The heat dissipation terminal 30P is disposed adjacent to the first chip side surface 20A in the X direction in a plan view. The first sealing resin 50 includes a first cover portion 51 that covers the first chip side surface 20A. The heat dissipation member 70 is in contact with the first cover portion 51.

[0081] This configuration can shorten the length of the heat transfer path from the heat generating portion 25 to the heat dissipation terminal 30P, which makes it easier to dissipate heat from the heat generating portion 25 to the heat dissipation terminal 30P, thereby improving the heat dissipation performance of the semiconductor device 10.

[0082] (9) The first cover portion 51 covers the entire first chip side surface 20A in the Z direction. This configuration allows a smooth connection between the portion of the heat dissipation member 70 that contacts the chip back surface 20R of the semiconductor chip 20 (first heat dissipation portion 71) and the portion of the heat dissipation member 70 that contacts the sealing surface 50S of the first sealing resin 50 (second heat dissipation portion 72). Therefore, when the heat dissipation member 70 is formed by, for example, inkjet printing, breakage between the first heat dissipation portion 71 and the second heat dissipation portion 72 can be suppressed.

[0083] (10) The first cover part 51 includes an inclined surface 51A that slopes toward the terminal surface 30S of the heat dissipation terminal 30P with increasing distance from the first chip side surface 20A as the sealing surface 50S of the first sealing resin 50. The inclined surface 51A is connected to a corner portion 27 defined by the chip back surface 20R and the first chip side surface 20A.

[0084] This configuration allows for a smoother connection between the portion of the heat dissipation member 70 that contacts the chip back surface 20R of the semiconductor chip 20 (first heat dissipation portion 71) and the portion of the heat dissipation member 70 that contacts the sealing surface 50S of the first sealing resin 50 (second heat dissipation portion 72). Therefore, when the heat dissipation member 70 is formed by, for example, inkjet printing, breakage between the first heat dissipation portion 71 and the second heat dissipation portion 72 can be further suppressed.

[0085] (11) The inclined surface 51A of the first cover portion 51 is formed in a curved concave shape. The portion of the heat dissipation member 70 that contacts the inclined surface 51A is formed along the curved concave shape of the inclined surface 51A.

[0086] This configuration reduces the distance in the Z direction between the portion of the heat dissipation member 70 that contacts the inclined surface 51A (the second heat dissipation portion 72) and the substrate 40 (the substrate terminals 30), thereby shortening the heat transfer path from the second heat dissipation portion 72 to the substrate 40 (the substrate terminals 30).

[0087] (12) The first cover portion 51 covers a portion of the terminal surface 30S of the heat dissipation terminal 30P that is closer to the first chip side surface 20A. This configuration allows a smooth connection between the portion of the heat dissipation member 70 that contacts the sealing surface 50S of the first sealing resin 50 (the second heat dissipation portion 72) and the portion that contacts the terminal surface 30S of the heat dissipation terminal 30P (the third heat dissipation portion 73). Therefore, when the heat dissipation member 70 is formed by, for example, inkjet printing, breakage between the second heat dissipation portion 72 and the third heat dissipation portion 73 can be prevented. In addition, because the first cover portion 51 covers the portion of the terminal surface 30S that is closer to the first chip side surface 20A, the heat dissipation member 70 can contact the terminal surface 30S of the heat dissipation terminal 30P while suppressing an increase in the length of the second heat dissipation portion 72. This allows a shorter heat transfer path from the semiconductor chip 20 to the heat dissipation terminal 30P via the heat dissipation member 70.

[0088] (13) The plurality of substrate terminals 30 include through wiring portions 31 that penetrate the substrate 40 in the Z direction. The heat dissipation member 70 contacts the terminal surface 30S corresponding to the through wiring portions 31 of the heat dissipation terminals 30P.

[0089] According to this configuration, for example, when the semiconductor device 10 is mounted on a wiring board (not shown), heat from the heat dissipation member 70 is more likely to transfer to the wiring board via the through wiring portion 31. Therefore, the heat dissipation performance of the semiconductor device 10 can be improved.

[0090] (14) The thickness of the heat dissipation member 70 is 5 μm or more and 30 μm or less. This configuration allows the semiconductor device 10 to be made thinner than a configuration in which a metal plate is bonded to the chip back surface 20R of the semiconductor chip 20 using, for example, solder paste.

[0091] (15) The heat dissipation member 70 has a heat dissipation surface 70S. The heat dissipation surface 70S includes an uneven shape. With this configuration, the second sealing resin 60 penetrates into the uneven heat dissipation surface 70S, which can improve the adhesion between the heat dissipation member 70 and the second sealing resin 60 due to, for example, an anchor effect.

[0092] (16) The heat dissipation member 70 includes a first heat dissipation portion 71 in contact with the chip back surface 20R, a second heat dissipation portion 72 in contact with the first cover portion 51, and a third heat dissipation portion 73 in contact with the terminal surface 30S of the heat dissipation terminal 30P. The first heat dissipation portion 71, the second heat dissipation portion 72, and the third heat dissipation portion 73 are integrated.

[0093] With this configuration, compared to a configuration in which the first heat dissipation section 71, the second heat dissipation section 72, and the third heat dissipation section 73 are provided separately, heat is more easily transferred from the first heat dissipation section 71 to the third heat dissipation section 73 via the second heat dissipation section 72. Therefore, the heat dissipation performance of the semiconductor device 10 can be improved.

[0094] (17) The heat dissipation terminal 30P includes a terminal back surface 30R facing the opposite side to the terminal front surface 30S, and a terminal side surface 30A connecting the terminal front surface 30S and the terminal back surface 30R. At least a portion of the terminal side surface 30A of the heat dissipation terminal 30P is exposed from the substrate 40.

[0095] According to this configuration, heat can be more easily dissipated from the heat dissipation terminal 30P to the outside of the semiconductor device 10 compared to a configuration in which the entire terminal side surface 30A of the heat dissipation terminal 30P is covered by the substrate 40. Therefore, the heat dissipation performance of the semiconductor device 10 can be improved.

[0096] (18) The terminal side surface 30A of the heat dissipation terminal 30P that is exposed from the substrate 40 is provided with a plating layer 34. With this configuration, for example, when the semiconductor device 10 is mounted on a wiring board (not shown) with solder paste, the solder paste comes into contact with the plating layer 34 formed on the terminal side surface 30A. This makes it easier for heat to be dissipated from the heat dissipation terminal 30P to the wiring board.

[0097] (19) A method for manufacturing a semiconductor device 10 includes preparing a substrate 40 including a substrate surface 40S, a substrate back surface 40R opposite the substrate surface 40S, and a plurality of substrate terminals 30 that are formed so as to penetrate the substrate 40 in the Z direction and include a terminal surface 30S exposed from the substrate surface 40S and a terminal back surface 30R that includes a portion exposed from the substrate back surface 40R; electrically connecting a plurality of chip terminals 24 of a semiconductor chip 20 to the plurality of substrate terminals 30, the plurality of chip terminals 24 including a chip surface 20S facing the terminal surface 30S, a chip back surface 20R opposite the chip surface 20S, first to fourth chip side surfaces 20A to 20D connecting the chip surface 20S and the chip back surface 20R, and the plurality of chip terminals 24 formed on the chip surface 20S; and forming a first sealing resin 50 to cover the chip surface 20S and the first to fourth chip side surfaces 20A to 20D of the semiconductor chip 20. The plurality of substrate terminals 30 include heat dissipation terminals 30P that include portions that are arranged outward from the semiconductor chip 20 in a plan view. The manufacturing method for the semiconductor device 10 includes forming a heat dissipation member 70 that contacts each of the chip back surface 20R, the sealing surface 50S of the first sealing resin 50, and the terminal surface 30S of the heat dissipation terminal 30P.

[0098] According to this configuration, the heat transfer paths of the semiconductor chip 20 are formed as a path that moves to the heat dissipation terminals 30P via the heat dissipation member 70 and a path that moves to the substrate terminals 30 via the chip terminals 24. In this way, the number of heat transfer paths of the semiconductor chip 20 is increased, thereby improving the heat dissipation performance of the semiconductor device 10.

[0099] (20) The heat dissipation member 70 is formed by inkjet printing. This configuration reduces the manufacturing cost of the heat dissipation member 70 compared to when the heat dissipation member is formed by, for example, pressing a metal plate. In addition, since the layout of the printing area can be easily changed by inkjet printing, the shape of the heat dissipation member 70 can be easily changed.

[0100] <Modifications> The above embodiment can be modified as follows: The following modifications can be combined with each other to the extent that they are not technically inconsistent.

[0101] The position of the heat generating portion 25 of the semiconductor chip 20 in a plan view can be changed as desired. In one example, the heat generating portion 25 may be disposed in the center of the semiconductor chip 20 in a plan view.

[0102] All of the terminal side surfaces 30A of the multiple board terminals 30 may be covered by the board 40. In this case, the plating layer 34 is formed only on the exposed surface 30RA of the terminal back surface 30R. Similarly, all of the terminal side surfaces 30A of the heat dissipation terminals 30P may be covered by the board 40.

[0103] The number of board terminals 30 can be changed as desired. The plating layer 34 formed on the exposed surface 30RA of the board terminal 30 may be omitted. The heat dissipation terminal 30P is not limited to the corner terminal 30C among the multiple board terminals 30 and can be changed as desired. The heat dissipation terminal 30P may be formed by a board terminal 30 located at the center of the board 40 in the Y direction, for example.

[0104] The heat dissipation terminal 30P does not have to be electrically connected to the semiconductor chip 20. In other words, the heat dissipation terminal 30P may be in an electrically floating state. Figure 12 schematically shows an example of the cross-sectional structure of the semiconductor device 10 including the heat dissipation terminal 30P in an electrically floating state.

[0105] 12 , the entire heat dissipation terminal 30P is disposed closer to the first sealing side surface 60A of the second sealing resin 60 than the semiconductor chip 20. In other words, the heat dissipation terminal 30P does not include a portion that overlaps with the semiconductor chip 20 in a planar view. In the example shown in FIG. 12 , of the multiple substrate terminals 30, the substrate terminal 30V that is disposed closer to the second sealing side surface 60B of the second sealing resin 60 is in an electrically floating state. The entire substrate terminal 30V is disposed closer to the second sealing side surface 60B than the semiconductor chip 20. In other words, the substrate terminal 30V does not include a portion that overlaps with the semiconductor chip 20 in a planar view.

[0106] 12 , a plurality of (three in FIG. 12 ) substrate terminals 30 arranged between the heat dissipation terminal 30P and the substrate terminal 30V in the X direction are electrically connected to the chip terminals 24 of the semiconductor chip 20. Each of these substrate terminals 30 is electrically connected to a plurality of chip terminals 24. Of the three substrate terminals 30, two substrate terminals 30 closer to the heat dissipation terminal 30P are arranged in positions overlapping with the heat generating portion 25 of the semiconductor chip 20 in a planar view. Of the three substrate terminals 30, one substrate terminal 30 closer to the substrate terminal 30V is arranged closer to the substrate terminal 30V than the heat generating portion 25 in a planar view.

[0107] The first cover portion 51 of the first sealing resin 50 covers a portion of the terminal surface 30S of the heat dissipation terminal 30P that is closer to the first chip side surface 20A of the semiconductor chip 20. In one example, the first cover portion 51 covers the surface wiring portion 32 of the heat dissipation terminal 30P. The second cover portion 52 of the first sealing resin 50 covers a portion of the terminal surface 30S of the substrate terminal 30V that is closer to the second chip side surface 20B of the semiconductor chip 20.

[0108] As in the above embodiment, the heat dissipation member 70 is provided so as to be in contact with the chip rear surface 20R of the semiconductor chip 20, the sealing surface 50S of the first sealing resin 50, and the terminal surface 30S of the heat dissipation terminal 30P. The heat dissipation member 70 is in contact with portions of the terminal surface 30S of the heat dissipation terminal 30P that correspond to both the through wiring portion 31 and the surface wiring portion 32. The configuration of the heat dissipation member 70 is the same as in the above embodiment. The semiconductor device 10 shown in FIG. 12 can achieve the same effects as (1) to (12) and (14) to (20) of the above embodiment.

[0109] The multiple board terminals 30 may include a first heat dissipation terminal 30P and a second heat dissipation terminal 30Q as multiple heat dissipation terminals. In one example, as shown in FIG. 13 , the first heat dissipation terminal 30P and the second heat dissipation terminal 30Q may be distributed on both sides of the semiconductor chip 20 in the X direction. The first heat dissipation terminal 30P is disposed in the same position as the heat dissipation terminal 30P in the above embodiment. The second heat dissipation terminal 30Q is disposed on the second substrate side surface 40B and closer to the third substrate side surface 40C. Here, the first heat dissipation terminal 30P and the second heat dissipation terminal 30Q are terminals having the same function and may be electrically connected to each other. In one example, the first heat dissipation terminal 30P and the second heat dissipation terminal 30Q may be ground terminals. At least one of the first heat dissipation terminal 30P and the second heat dissipation terminal 30Q does not have to be electrically connected to the semiconductor chip 20. That is, at least one of the first heat dissipation terminal 30P and the second heat dissipation terminal 30Q may be in an electrically floating state. In one example, both the first heat dissipation terminal 30P and the second heat dissipation terminal 30Q may be in an electrically floating state.

[0110] As shown in FIGS. 13 and 14 , the heat dissipation member 70 is in contact with each of the terminal surfaces 30S of the first heat dissipation terminal 30P and the second heat dissipation terminal 30Q. More specifically, the heat dissipation member 70 includes a second heat dissipation portion 72 that is in contact with the inclined surface 51A of the first cover portion 51 of the first sealing resin 50, a third heat dissipation portion 73 that is in contact with a region of the terminal surface 30S of the first heat dissipation terminal 30P that corresponds to the through wiring portion 31, a fourth heat dissipation portion 74 that is in contact with the inclined surface 52A of the second cover portion 52 of the first sealing resin 50, and a fifth heat dissipation portion 75 that is in contact with a region of the terminal surface 30S of the second heat dissipation terminal 30Q that corresponds to the through wiring portion 31. The fourth heat dissipation portion 74 is connected to the first heat dissipation portion 71. The fifth heat dissipation portion 75 is connected to the fourth heat dissipation portion 74. In this manner, the first to fifth heat dissipation portions 71 to 75 are integrated.

[0111] 13 , the fourth heat dissipation portion 74 is formed on a portion of the second cover portion 52 in the Y direction. The fourth heat dissipation portion 74 is formed over the entire second cover portion 52 in the X direction. The fifth heat dissipation portion 75 is formed over the entire region of the terminal surface 30S of the second heat dissipation terminal 30Q that corresponds to one of the through wiring portions 31.

[0112] This configuration forms two heat transfer paths: a first heat transfer path through which heat from the semiconductor chip 20 moves to the first heat dissipation terminal 30P, and a second heat transfer path through which heat moves to the second heat dissipation terminal 30Q. In this way, the increase in the number of heat transfer paths makes it easier to transfer the heat from the semiconductor chip 20 to the wiring board on which the semiconductor device 10 is mounted.

[0113] 13, the semiconductor chip 20 may include a first heat generating portion 25P and a second heat generating portion 25Q as the plurality of heat generating portions 25. In a plan view, the first heat generating portion 25P and the second heat generating portion 25Q are spaced apart from each other. The first heat generating portion 25P is disposed closer to the first chip side surface 20A and the fourth chip side surface 20D in a plan view. The second heat generating portion 25Q is disposed closer to the second chip side surface 20B and the third chip side surface 20C in a plan view.

[0114] The first heat dissipation terminal 30P is arranged in a position adjacent to the first heat generating portion 25P in the X direction in a plan view. The first heat dissipation terminal 30P is arranged in a position adjacent to the first chip side surface 20A of the semiconductor chip 20 in the X direction. The first heat generating portion 25P is arranged in a position adjacent to the first cover portion 51 of the first sealing resin 50 in the X direction. Because the second heat dissipation portion 72 of the heat dissipation member 70 is formed on the inclined surface 51A of the first cover portion 51, the second heat dissipation portion 72 is arranged in a position adjacent to the first heat generating portion 25P in the X direction in a plan view.

[0115] The second heat dissipation terminal 30Q is arranged in a position adjacent to the second heat generating portion 25Q in the X direction in a plan view. The second heat dissipation terminal 30Q is arranged in a position adjacent to the second chip side surface 20B of the semiconductor chip 20 in the X direction. The second heat generating portion 25Q is arranged in a position adjacent to the second cover portion 52 of the first sealing resin 50 in the X direction. Because the fourth heat dissipation portion 74 of the heat dissipation member 70 is formed on the inclined surface 52A of the second cover portion 52, the fourth heat dissipation portion 74 is arranged in a position adjacent to the second heat generating portion 25Q in the X direction in a plan view.

[0116] The first heat dissipation portion 71 of the heat dissipation member 70 may be formed partially on the chip back surface 20R of the semiconductor chip 20 in a plan view. In this case, the first heat dissipation portion 71 may be formed in a position overlapping the heat generating portion 25 of the semiconductor chip 20 in a plan view.

[0117] The third heat dissipation portion 73 of the heat dissipation member 70 may be in contact with the entire surface of the terminal surface 30S of the heat dissipation terminal 30P that corresponds to the through wiring portion 31. The third heat dissipation portion 73 of the heat dissipation member 70 may be in contact with the terminal surface 30S of the heat dissipation terminal 30P that corresponds to each of the two through wiring portions 31 and the surface connecting portion 33.

[0118] The heat dissipation member 70 may include a partially thickened region. For example, as shown in Fig. 15 , the heat dissipation member 70 may include a first laminated portion 77 formed at the boundary between the first heat dissipation portion 71 and the second heat dissipation portion 72 of the heat dissipation member 70, and a second laminated portion 78 formed at the boundary between the second heat dissipation portion 72 and the third heat dissipation portion 73. For example, the third heat dissipation portion 73 may be thicker than the first heat dissipation portion 71.

[0119] The first laminate portion 77 is formed to straddle the boundary between the semiconductor chip 20 and the first cover portion 51 of the first sealing resin 50. The second laminate portion 78 is formed to straddle the boundary between the first cover portion 51 and a region of the terminal surface 30S of the heat dissipation terminal 30P corresponding to the through wiring portion 31. The thickness T1 of the first laminate portion 77 is thicker than the thickness TB of the portion of the second heat dissipation portion 72 between the first laminate portion 77 and the second laminate portion 78. The thickness T1 of the first laminate portion 77 is thicker than the thickness TA of the first heat dissipation portion 71, for example. The thickness T2 of the second laminate portion 78 is thicker than the thickness TB of the portion of the second heat dissipation portion 72 between the first laminate portion 77 and the second laminate portion 78. In the example shown in FIG. 15 , the thickness T1 of the first laminate portion 77 is thicker than the thickness T2 of the second laminate portion 78. In the example shown in FIG. 15 , the thickness T2 of the second laminate portion 78 is equal to or less than the thickness TC of the third heat dissipation portion 73. Both the first laminated portion 77 and the second laminated portion 78 are formed by overlapping a plurality of dots 76 (see FIG. 5) of conductive ink, for example.

[0120] According to this configuration, by increasing the thickness of the portion of the heat dissipation member 70 formed on the boundary between the first cover part 51 and the semiconductor chip 20, where a step is likely to be formed, it is possible to avoid separation of the heat dissipation member 70 due to the step. Furthermore, by increasing the thickness of the portion of the heat dissipation member 70 formed on the boundary between the first cover part 51 and the heat dissipation terminal 30P, where a step is likely to be formed, it is possible to avoid separation of the heat dissipation member 70 due to the step. Therefore, it is possible to prevent difficulty in heat transfer from the first heat dissipation part 71 to the third heat dissipation part 73 via the second heat dissipation part 72.

[0121] The relationship between the thickness T1 of the first laminated portion 77 and the thickness T2 of the second laminated portion 78 can be changed as desired. For example, the thickness T1 of the first laminated portion 77 may be equal to or smaller than the thickness T2 of the second laminated portion 78. Furthermore, the thickness T2 of the second laminated portion 78 may be greater than the thickness TC of the third heat dissipation portion 73.

[0122] The heat dissipation member 70 may be formed of a metal film instead of inkjet printing. The first sealing resin 50 may be formed of a material having a thermal conductivity equal to or lower than that of air.

[0123] The first sealing resin 50 and the second sealing resin 60 may be made of the same material. The inclined surface 51A of the first cover portion 51 of the first sealing resin 50 is not limited to the curved concave shape shown in Figure 6 and can be changed as desired. In one example, the inclined surface 51A may be a flat surface that slopes toward the substrate surface 40S as it moves away from the first chip side surface 20A of the semiconductor chip 20.

[0124] The first sealing resin 50 may be formed to cover the entire terminal surfaces 30S of the substrate terminals 30 other than the heat dissipation terminals 30P among the plurality of substrate terminals 30. In this case, the second heat dissipation portion 72 of the heat dissipation member 70 may be formed, for example, over the entire inclined surface 51A of the first cover portion 51. The second heat dissipation portion 72 may also be formed, for example, over the entire inclined surface of at least one of the second to fourth cover portions 52 to 54. In one example, the second heat dissipation portion 72 may be formed over the entire inclined surfaces of the first to fourth cover portions 51 to 54. This configuration allows the heat dissipation member 70 to improve the heat dissipation performance of the semiconductor chip 20.

[0125] The first sealing resin 50 does not have to cover the terminal surface 30S of the heat dissipation terminal 30P that corresponds to the through wiring portion 31. The second sealing resin 60 may be omitted.

[0126] The configuration of the semiconductor device 10 can be modified as desired. For example, the semiconductor device 10 may be modified as shown in a first modified example illustrated in FIG. 16 and a second modified example illustrated in FIG. 17 . (First Modified Example) As shown in FIG. 16 , the semiconductor device 10 includes a plurality of electrode terminals 80 instead of the plurality of substrate terminals 30 (see FIG. 4 ). Each electrode terminal 80 includes a front surface electrode 81, a back surface electrode 82, and a through-hole wiring 83. The front surface electrode 81 is formed on the substrate front surface 40S of the substrate 40. The plurality of front surface electrodes 81 are arranged spaced apart from one another on the substrate front surface 40S. The back surface electrode 82 is formed on the substrate back surface 40R of the substrate 40. The plurality of back surface electrodes 82 are arranged spaced apart from one another on the substrate back surface 40R. The through-hole wiring 83 penetrates the substrate 40 in the Z direction. The through-hole wiring 83 electrically connects the front surface electrode 81 and the back surface electrode 82. Therefore, the plurality of through-wires 83 electrically connect the plurality of front surface electrodes 81 and the plurality of back surface electrodes 82 individually. The front surface electrode 81, the back surface electrode 82, and the through-wires 83 may be provided individually. Therefore, the front surface electrode 81, the back surface electrode 82, and the through-wires 83 may be made of different materials. In one example, the front surface electrode 81 is made of a material containing at least one of Cu and Al. The back surface electrode 82 is made of a material containing at least one of Ni, Pd, and Au. The through-wires 83 are made of a material containing at least one of Cu and Al.

[0127] In one example, the shape and arrangement of the surface electrodes 81 in a plan view are the same as those of the board terminals 30 in the above embodiment. Note that the shape and arrangement of the surface electrodes 81 in a plan view can be changed as desired.

[0128] The semiconductor chip 20 is mounted on a plurality of surface electrodes 81. More specifically, a plurality of chip terminals 24 of the semiconductor chip 20 are individually and electrically connected to a plurality of surface electrodes 81. The bonding mode between the chip terminals 24 and the surface electrodes 81 is the same as, for example, the bonding mode between the chip terminals 24 and the substrate terminals 30 in the above embodiment.

[0129] The plurality of surface electrodes 81 include a heat dissipation electrode 81P including a portion disposed outward from the semiconductor chip 20 in a plan view. In one example, the position of the heat dissipation electrode 81P in a plan view is the same as the position of the heat dissipation terminal 30P in the above embodiment. Note that the position of the heat dissipation electrode 81P can be changed as desired.

[0130] The heat dissipation member 70 is provided so as to be in contact with the chip rear surface 20R of the semiconductor chip 20, the sealing surface 50S (the inclined surface 51A of the first cover portion 51) of the first sealing resin 50, and the heat dissipation electrode 81P. The shape of the heat dissipation member 70 is the same as that of the heat dissipation member of the above embodiment, for example.

[0131] The manufacturing method of the semiconductor device 10 in the first modified example differs from the above embodiment mainly in the preparation of the substrate 40. More specifically, although not shown, a plurality of through holes for forming a plurality of through wirings 83 are formed in a substrate base material 840. Next, a metal material is filled into each through hole to form the plurality of through wirings 83. Next, a plurality of front surface electrodes 81 are formed on a substrate front surface 841 of the substrate base material 840. Next, a plurality of back surface electrodes 82 are formed on a substrate back surface 842 of the substrate base material 840. In one example, each of the plurality of through wirings 83, the plurality of front surface electrodes 81, and the plurality of back surface electrodes 82 may be formed by plating.

[0132] In the manufacturing method of the semiconductor device 10 of the first modified example, the semiconductor chip 20 is mounted on a plurality of surface electrodes 81. This mounting method is similar to that of the above embodiment. The manufacturing method of the semiconductor device 10 of the first modified example includes forming a heat dissipation member 70 so as to contact each of the chip rear surface 20R, the sealing surface 50S of the first sealing resin 50, and the heat dissipation electrodes 81P. The heat dissipation member 70 is formed by, for example, inkjet printing, as in the above embodiment. Note that the semiconductor device 10 of the first modified example can achieve the same effects as the above embodiment.

[0133] 17, the semiconductor device 10 includes a plurality of substrate terminals 90 formed by a lead frame, instead of the plurality of substrate terminals 30. The plurality of substrate terminals 90 include a terminal front surface 90S and a terminal back surface 90R that face opposite each other in the Z direction. The terminal front surface 90S faces the same side as the substrate front surface 40S of the substrate 40. The terminal back surface 90R faces the same side as the substrate back surface 40R. The terminal front surface 90S is exposed from the substrate surface 40S. In one example, the terminal surface 90S is flush with the substrate surface 40S.

[0134] The plurality of substrate terminals 90 include through-wiring portions 91 provided to penetrate the substrate 40, and thin-walled portions 92 that are thinner than the through-wiring portions 91. The terminal surface 90S is formed to be flush with the through-wiring portions 91 and the thin-walled portions 92.

[0135] Portions of the terminal back surface 90R corresponding to the through wiring portions 91 are exposed from the substrate back surface 40R. In one example, the portions of the terminal back surface 90R corresponding to the through wiring portions 91 are flush with the substrate back surface 40R. In a second modified example, terminal side surfaces 90A corresponding to the through wiring portions 91 of the plurality of substrate terminals 90 are not exposed from the substrate 40. Note that the terminal side surfaces 90A corresponding to the through wiring portions 91 of the plurality of substrate terminals 90 may be exposed from the first to fourth substrate side surfaces 40A to 40D of the substrate 40.

[0136] The thin portion 92 is provided within the substrate 40 in the Z direction. The thin portion 92 extends from the through wiring portion 91 in a direction intersecting the Z direction. The thin portion 92 includes a portion that is arranged at a position that overlaps the semiconductor chip 20 in a plan view. The chip terminal 24 of the semiconductor chip 20 is electrically connected to the thin portion 92.

[0137] The plurality of board terminals 90 include heat dissipation terminals 90P that include portions that are arranged outward in plan view from the semiconductor chip 20. The shape of the heat dissipation member 70 is the same as, for example, the shape of the heat dissipation member in the above embodiment.

[0138] The heat dissipation member 70 is provided so as to contact the chip rear surface 20R of the semiconductor chip 20, the sealing surface 50S (the inclined surface 51A of the first cover portion 51) of the first sealing resin 50, and the heat dissipation terminals 90P. The shape of the heat dissipation member 70 is the same as, for example, the shape of the heat dissipation member 70 in the above embodiment. Note that the semiconductor device 10 of the second modified example can achieve the same effects as the above embodiment.

[0139] One or more of the various examples described herein can be combined to the extent that they are not technically inconsistent. The term "on" as used in this disclosure includes the meanings of "on" and "above," unless the context clearly indicates otherwise. Thus, for example, the expression "a first element is disposed on a second element" means that in some embodiments, the first element may be in contact with the second element and disposed directly on the second element, but in other embodiments, the first element may be disposed above the second element without contacting the second element. In other words, the term "on" does not exclude a structure in which another element is formed between the first element and the second element.

[0140] The Z direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure are not limited to the "up" and "down" in the Z direction described herein being "up" and "down" in the vertical direction. For example, the X direction may be the vertical direction, or the Y direction may be the vertical direction.

[0141] <Supplementary Notes> The technical ideas that can be understood from this disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the supplementary notes are given the reference numerals of the corresponding components in the above embodiment. The reference numerals are shown as examples to aid understanding, and the components described in each supplementary note should not be limited to the components indicated by the reference numerals.

[0142] [Note 1] A semiconductor chip (20) including: a substrate (40) including a substrate surface (40S) and a substrate back surface (40R) opposite to the substrate surface (40S); a plurality of substrate terminals (30) provided to penetrate the substrate (40) in a thickness direction (Z direction) of the substrate (40), and including a terminal surface (30S) exposed from the substrate surface (40S) and a terminal back surface (30R) including a portion exposed from the substrate back surface (40R); a chip surface (20S) facing the terminal surface (30S), a chip back surface (20R) opposite to the chip surface (20S), chip side surfaces (20A to 20D) connecting the chip surface (20S) and the chip back surface (20R); and a plurality of chip terminals (24) formed on the chip surface (20S) and electrically connected to the terminal surfaces (30S) of the plurality of substrate terminals (30); A semiconductor device (10) comprising: a first sealing resin (50) covering the chip surface (20S) and the chip side surfaces (20A to 20D) of the semiconductor chip (20); wherein the plurality of substrate terminals (30) include a heat dissipation terminal (30P) including a portion disposed outward from the semiconductor chip (20) when viewed in the thickness direction (Z direction) of the semiconductor chip (20); and the semiconductor device (10) comprises a heat dissipation member (70) provided so as to contact each of the chip back surface (20R), the sealing surface (50S) of the first sealing resin (50), and the terminal surface (30S) of the heat dissipation terminal (30P).

[0143] [Supplementary Note 2] The semiconductor device according to Supplementary Note 1, wherein the heat dissipation member (70) is made of conductive ink.

[0144] [Supplementary Note 3] The semiconductor device according to Supplementary Note 1 or 2, wherein the heat dissipation member (70) is formed over the entire back surface (20R) of the chip.

[0145] [Appendix 4] The semiconductor device according to any one of Appendices 1 to 3, wherein the first sealing resin (50) is filled between the chip surface (20S) of the semiconductor chip (20) and the substrate surface (40S) of the substrate (40).

[0146] [Appendix 5] The semiconductor device described in Appendix 4, wherein the first sealing resin (50) is formed so as to partially cover the substrate terminals (30) and the heat dissipation terminals (30P) around the semiconductor chip (20) when viewed from the thickness direction (Z direction) of the substrate (40).

[0147] [Supplementary Note 6] The semiconductor chip (20) includes a heat generating portion (25) and a first chip side surface (20A) as the chip side surface, facing a first direction (X direction) perpendicular to a thickness direction (Z direction) of the semiconductor chip (20), wherein the heat generating portion (25) is arranged closer to the first chip side surface (20A) relative to the semiconductor chip (20) in the first direction (X direction), the heat dissipation terminal (30P) is arranged at a position adjacent to the first chip side surface (20A) in the first direction (X direction) when viewed from the thickness direction (Z direction) of the semiconductor chip (20), the first sealing resin (50) includes a first cover portion (51) that covers the first chip side surface (20A), and the heat dissipation member (70) is in contact with the first cover portion (51). This is the semiconductor device described in Supplementary Note 5.

[0148] [Supplementary Note 7] The semiconductor device according to Supplementary Note 6, wherein the first cover portion (51) covers the entire first chip side surface (20A) in the thickness direction (Z direction) of the semiconductor chip (20).

[0149] [Appendix 8] The semiconductor device according to Appendix 7, wherein the first cover portion (51) includes, as the sealing surface (50S), an inclined surface (51A) that inclines toward the terminal surface (30S) of the heat dissipation terminal (30P) as it moves away from the first chip side surface (20A), and the inclined surface (51A) is connected to a corner portion (27) formed by the chip back surface (20R) and the first chip side surface (20A).

[0150] [Appendix 9] The semiconductor device according to Appendix 8, wherein the inclined surface (51A) of the first cover portion (51) is formed in a curved concave shape, and a portion (72) of the heat dissipation member (70) that contacts the inclined surface (51A) is formed along the curved concave shape of the inclined surface (51A).

[0151] [Appendix 10] The semiconductor device according to any one of Appendices 6 to 9, wherein the first cover portion (51) covers a portion of the terminal surface (30S) of the heat dissipation terminal (30P) that is closer to the first chip side surface (20A).

[0152] [Appendix 11] The semiconductor device according to any one of Appendices 1 to 10, wherein the plurality of substrate terminals (30) include through-hole wiring portions (31) that penetrate the substrate (40) in a thickness direction (Z direction) of the substrate (40), and the heat dissipation member (70) is in contact with the terminal surface (30S) that corresponds to the through-hole wiring portion (31) of the heat dissipation terminal (30P).

[0153] [Appendix 12] The semiconductor device according to appendix 11, wherein the plurality of substrate terminals (30) include a surface wiring portion (32) extending from the through wiring portion (31) along the substrate surface (40S).

[0154] [Appendix 13] The semiconductor device according to Appendix 12, wherein the surface wiring portion (32) includes a portion arranged at a position overlapping the semiconductor chip (20) when viewed from the thickness direction (Z direction) of the substrate (40), and the chip terminal (24) is electrically connected to the surface wiring portion (32).

[0155] [Appendix 14] The semiconductor device according to any one of Appendices 1 to 10, wherein the plurality of substrate terminals (90) include a through wiring portion (91) provided to penetrate the substrate (40), and a thin portion (92) that is thinner than the through wiring portion (91) and is provided within the substrate (40) in a thickness direction (Z direction) of the substrate (40), the thin portion (92) extending from the through wiring portion (91) in a direction intersecting the thickness direction (Z direction) of the substrate (40), and the heat dissipation member (70) is in contact with the terminal surface (90S) of the heat dissipation terminal (90P) that corresponds to the through wiring portion (91).

[0156] [Appendix 15] The semiconductor device according to Appendix 14, wherein the thin portion (92) includes a portion arranged at a position overlapping the semiconductor chip (20) when viewed from the thickness direction (Z direction) of the substrate (40), and the chip terminal (24) is electrically connected to the thin portion (92).

[0157] [Appendix 16] The semiconductor device according to any one of Appendices 1 to 15, further comprising a second sealing resin (60) that covers the first sealing resin (50), the heat dissipation member (70), and the chip rear surface (20R).

[0158] [Supplementary Note 17] The semiconductor device according to Supplementary Note 16, wherein the first sealing resin (50) and the second sealing resin (60) are formed of different materials.

[0159] [Supplementary Note 18] The semiconductor device according to Supplementary Note 17, wherein the thermal conductivity of the first sealing resin (50) is greater than the thermal conductivity of the second sealing resin (60).

[0160] [Supplementary Note 19] The semiconductor device according to Supplementary Note 16, wherein the thermal conductivity of the first sealing resin (50) is greater than the thermal conductivity of air.

[0161] [Supplementary Note 20] The semiconductor device according to any one of Supplementary Notes 1 to 19, wherein the thickness of the heat dissipation member (70) is 5 μm or more and 30 μm or less.

[0162] [Appendix 21] The semiconductor device according to any one of Appendices 6 to 10, wherein the heat dissipation member (70) includes a first heat dissipation portion (71) in contact with the chip back surface (20R), a second heat dissipation portion (72) in contact with the first cover portion (51), and a third heat dissipation portion (73) in contact with the terminal surface (30S) of the heat dissipation terminal (30P), and the first heat dissipation portion (71), the second heat dissipation portion (72), and the third heat dissipation portion (73) are integrated.

[0163] [Appendix 22] The semiconductor device according to any one of Appendices 1 to 21, wherein the heat dissipation terminal (30P) includes a terminal side surface (30A) connecting the terminal front surface (30S) and the terminal back surface (30R), and at least a portion of the terminal side surface (30A / 30AA) of the heat dissipation terminal (30P) is exposed from the substrate (40).

[0164] [Supplementary Note 23] The semiconductor device according to any one of Supplementary Notes 1 to 22, wherein the material constituting the heat dissipation member (70) includes at least one of Au, Cu, and Ag.

[0165] [Supplementary Note 24] The semiconductor device according to any one of Supplementary Notes 1 to 23, wherein the heat dissipation terminal (30P) is in an electrically floating state.

[0166] [Appendix 25] The semiconductor device according to any one of Appendices 1 to 23, wherein the plurality of substrate terminals (30) include a plurality of the heat dissipation terminals (30P), and the heat dissipation member (70) is in contact with each of the terminal surfaces (30S) of the plurality of heat dissipation terminals (30P).

[0167] [Supplementary Note 26] The semiconductor device according to Supplementary Note 24, wherein at least one of the plurality of heat dissipation terminals (30P) is in an electrically floating state.

[0168] [Supplementary Note 27] The semiconductor device according to any one of Supplementary Notes 1 to 26, wherein the heat dissipation member (70) has a heat dissipation surface (70S), and the heat dissipation surface (70S) includes an uneven shape.

[0169] [Supplementary Note 28] The semiconductor device according to Supplementary Note 1, wherein the heat dissipation member (70) is made of a metal film.

[0170] [Supplementary Note 29] The semiconductor device according to Supplementary Note 16, wherein the first sealing resin (50) and the second sealing resin (60) are made of the same material.

[0171] [Supplementary Note 30] The semiconductor chip (20) includes a first heat generating portion (25P) and a second heat generating portion (25Q), and a first chip side surface (20A) and a second chip side surface (20B) as the chip side surfaces facing opposite each other in a first direction (X direction) orthogonal to a thickness direction (Z direction) of the semiconductor chip (20), wherein the first heat generating portion (25P) is arranged closer to the first chip side surface (20A) with respect to the semiconductor chip (20) in the first direction (X direction), and the second heat generating portion (25Q) is arranged closer to the second chip side surface (20B) with respect to the semiconductor chip (20) in the first direction (X direction), and the plurality of substrate terminals (30) include a first heat dissipation terminal (30P) and a second heat dissipation terminal (30Q) as the heat dissipation terminals, The semiconductor device according to Appendix 5, wherein the first heat dissipation terminal (30P) is arranged at a position adjacent to the first chip side surface (20A) in the first direction (X direction) when viewed from the thickness direction (Z direction) of the semiconductor chip (20), the second heat dissipation terminal (30Q) is arranged at a position adjacent to the second chip side surface (20B) in the first direction (X direction) when viewed from the thickness direction (Z direction) of the semiconductor chip (20), the first sealing resin (50) includes: a first cover portion (51) covering the first chip side surface (20A) and a second cover portion (52) covering the second chip side surface (20B), and the heat dissipation member (70) is in contact with both the first cover portion (51) and the second cover portion (52).

[0172] [Appendix 31] A semiconductor device (10) comprising: a substrate (40) including a substrate surface (40S) and a substrate back surface (40R) facing the opposite side to the substrate surface (40S); a semiconductor chip (20) including: a chip surface (20S) facing the plurality of surface electrodes (81); a chip back surface (20R) opposite the chip surface (20S); chip side surfaces (20A-20D) connecting the chip surface (20S) and the chip back surface (20R); and a plurality of chip terminals (24) formed on the chip surface (20S) and electrically connected to the plurality of surface electrodes (81); and a first sealing resin (50) covering the chip surface (20S) and the chip side surfaces (20A-20D) of the semiconductor chip (20), The plurality of surface electrodes (81) include a heat dissipation electrode (81P) including a portion disposed outward from the semiconductor chip (20) when viewed from the thickness direction (Z direction) of the semiconductor chip (20), and the semiconductor device (10) includes a heat dissipation member (70) provided so as to contact each of the chip back surface (20R), the sealing surface (50S) of the first sealing resin (50), and the heat dissipation electrode (81P).

[0173] [Appendix 32] The semiconductor device according to Appendix 31, comprising: a plurality of back electrodes (82) formed on the back surface (40R) of the substrate; and a plurality of through-wires (83) that penetrate the substrate (40) in a thickness direction (Z direction) of the substrate (40) and individually electrically connect the plurality of front surface electrodes (81) and the plurality of back electrodes (82).

[0174] [Appendix 33] Preparing a substrate (840 / 40) including a substrate surface (40S), a substrate back surface (40R) opposite to the substrate surface (40S), a plurality of substrate terminals (30) including a terminal surface (30S) exposed from the substrate surface (40S), and a terminal back surface (30R) including a portion exposed from the substrate back surface (40R); Electrically connecting the plurality of chip terminals (24) of a semiconductor chip (20) to the plurality of substrate terminals (30); A method for manufacturing a semiconductor device (10), comprising: forming a first sealing resin (50) so as to cover the chip surface (20S) and the chip side surfaces (20A to 20D) of the semiconductor chip (20), wherein the plurality of substrate terminals (30) include a heat dissipation terminal (30P) including a portion that is arranged outward from the semiconductor chip (20) when viewed in the thickness direction (Z direction) of the semiconductor chip (20), and the method for manufacturing the semiconductor device (10) comprises forming a heat dissipation member (70) that contacts each of the chip back surface (20R), the sealing surface (50S) of the first sealing resin (50), and the terminal surface (30S) of the heat dissipation terminal (30P).

[0175] [Supplementary Note 34] The method for manufacturing a semiconductor device according to Supplementary Note 33, wherein the heat dissipation member (70) is formed by inkjet printing.

[0176] [Supplementary Note 35] The method for manufacturing a semiconductor device according to Supplementary Note 33 or 34, further comprising forming a second sealing resin (60) that covers the first sealing resin (50) and the heat dissipation member (70) after forming the heat dissipation member (70).

[0177] [Appendix 36] A method for manufacturing a semiconductor device (10), comprising: preparing a substrate (840 / 40) including a substrate surface (40S), a substrate back surface (40R) facing the opposite side to the substrate surface (40S), and a plurality of surface electrodes (81) formed on the substrate surface (40S); electrically connecting a plurality of chip terminals (24) of a semiconductor chip (20) to the plurality of surface electrodes (81), the semiconductor chip (20) including a chip surface (20S) facing the plurality of surface electrodes (81), a chip back surface (20R) opposite to the chip surface (20S), chip side surfaces (20A to 20D) connecting the chip surface (20S) and the chip back surface (20R), and a plurality of chip terminals (24) formed on the chip surface (20S); and forming a first sealing resin (50) so as to cover the chip surface (20S) and the chip side surfaces (20A to 20D) of the semiconductor chip (20), The plurality of surface electrodes (81) include a heat dissipation electrode (81P) including a portion arranged outward from the semiconductor chip (20) when viewed from the thickness direction (Z direction) of the semiconductor chip (20), and the manufacturing method of the semiconductor device (10) comprises forming a heat dissipation member (70) in contact with each of the back surface (20R) of the chip, the sealing surface (50S) of the first sealing resin (50), and the heat dissipation electrode (81P).

[0178] The above description is merely illustrative. Those skilled in the art will recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) listed for the purpose of illustrating the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and variations that fall within the scope of the present disclosure, including the claims.

[0179] 10...Semiconductor device 20...Semiconductor chip 20S...Chip surface 20R...Chip back surface 20A to 20D...First to fourth chip side surfaces 20AA...Chip side surface on the surface side 20AB...Chip side surface on the back side 21...Semiconductor substrate 21S...Main body surface 21R...Main body back surface 22...Wiring 23...Insulating layer 24...Chip terminal 24A...Terminal body 24B...Barrier layer 25...Heat generating portion 25P...First heat generating portion 25Q...Second heat generating portion 26...Step portion 27...Corner portion 30, 30V...Substrate terminal 30P...Heat dissipation terminal (first heat dissipation terminal) 30Q...Second heat dissipation terminal 30C...Corner terminal 30S...Terminal surface 30R...Terminal back surface 30RA...Exposed surface 30A...Terminal side surface 30AA...Exposed side surface 31...Through-through wiring portion 32...Surface wiring portion 33...Surface connecting portion 34...Plating layer 35...Barrier layer 40...Substrate 40S...Substrate surface 40R...Substrate back surface 40A to 40D...First to fourth substrate side surfaces 50...First sealing resin 50S...Sealing surface 51 to 54...First to fourth cover portions 51A, 52A...Inclined surfaces 60...Second sealing resin 60S...Sealing surface 60A to 60D...First to fourth sealing side surfaces 70...Heat dissipation member 70S...Heat dissipation surface 71...First heat dissipation portion 72...Second heat dissipation portion 73...Third heat dissipation portion 74...Fourth heat dissipation portion 75...Fifth heat dissipation portion 76...Dot 77...First laminated portion 78...Second laminated portion 80...Electrode terminal 81...Surface electrode 81P...Heat dissipation electrode 82...Back electrode 83...Through-through wiring 90...Substrate terminal 90P...heat dissipation terminal 90S...terminal surface 90R...terminal back surface 90A...terminal side surface 91...through wiring portion 92...thin portion 840...substrate base material 841...substrate surface 842...substrate back surface 860...resin layer SD...conductive bonding material TA...thickness of first heat dissipation portion TB...thickness of second heat dissipation portion TC...thickness of third heat dissipation portion T1...thickness of first laminated portion T2...thickness of second laminated portion CL...cutting line

Claims

1. A semiconductor device comprising: a substrate including a substrate surface and a substrate back surface opposite to the substrate surface; a plurality of substrate terminals extending through the substrate in a thickness direction of the substrate and including a terminal surface exposed from the substrate surface and a terminal back surface including a portion exposed from the substrate back surface; a semiconductor chip including a chip surface facing the terminal surface, a chip back surface opposite to the chip surface, a chip side surface connecting the chip surface and the chip back surface, and a plurality of chip terminals formed on the chip surface and electrically connected to the terminal surfaces of the plurality of substrate terminals; and a first sealing resin covering the chip surface and the chip side surface of the semiconductor chip, wherein the plurality of substrate terminals include a heat dissipation terminal including a portion located outboard of the semiconductor chip when viewed in the thickness direction of the semiconductor chip, and the semiconductor device comprises a heat dissipation member arranged to be in contact with each of the chip back surface, the sealing surface of the first sealing resin, and the terminal surface of the heat dissipation terminal.

2. The semiconductor device according to claim 1, wherein the heat dissipation member is made of conductive ink.

3. The semiconductor device according to claim 1 or 2, wherein the heat dissipation member is formed over the entire back surface of the chip.

4. The semiconductor device according to any one of claims 1 to 3, wherein the first sealing resin is filled between the chip surface of the semiconductor chip and the substrate surface of the substrate.

5. The semiconductor device according to claim 4, wherein the first sealing resin is formed so as to partially cover the substrate terminals and the heat dissipation terminals around the semiconductor chip when viewed in the thickness direction of the substrate.

6. The semiconductor device according to claim 5, wherein the semiconductor chip includes a heat generating portion and a first chip side surface as the chip side surface facing a first direction perpendicular to a thickness direction of the semiconductor chip, the heat generating portion is arranged closer to the first chip side surface relative to the semiconductor chip in the first direction, the heat dissipation terminal is arranged in a position adjacent to the first chip side surface in the first direction when viewed from the thickness direction of the semiconductor chip, the first sealing resin includes a first cover portion covering the first chip side surface, and the heat dissipation member is in contact with the first cover portion.

7. The semiconductor device according to claim 6, wherein the first cover portion covers the entire side surface of the first chip in the thickness direction of the semiconductor chip.

8. The semiconductor device described in claim 7, wherein the first cover portion includes, as the sealing surface, an inclined surface that inclines toward the terminal surface of the heat dissipation terminal as it moves away from the first chip side surface, and the inclined surface is connected to a corner portion formed by the chip back surface and the first chip side surface.

9. The semiconductor device according to claim 8, wherein the inclined surface of the first cover portion is formed in a curved concave shape, and the portion of the heat dissipation member that contacts the inclined surface is formed along the curved concave shape of the inclined surface.

10. The semiconductor device according to any one of claims 6 to 9, wherein the first cover portion covers a portion of the surface of the heat dissipation terminal that is closer to a side surface of the first chip.

11. A semiconductor device as claimed in any one of claims 1 to 10, wherein the plurality of substrate terminals include through-hole wiring portions that penetrate the substrate in a thickness direction of the substrate, and the heat dissipation member is in contact with the terminal surface corresponding to the through-hole wiring portions of the heat dissipation terminals.

12. The semiconductor device according to claim 11, wherein the plurality of substrate terminals include a surface wiring portion extending from the through wiring portion along the substrate surface.

13. The semiconductor device according to claim 12, wherein the surface wiring portion includes a portion arranged at a position overlapping the semiconductor chip when viewed in the thickness direction of the substrate, and the chip terminal is electrically connected to the surface wiring portion.

14. A semiconductor device as claimed in any one of claims 1 to 10, wherein the plurality of substrate terminals include a through-hole wiring portion arranged to penetrate the substrate, and a thin-walled portion thinner than the through-hole wiring portion and arranged within the substrate in the thickness direction of the substrate, the thin-walled portion extending from the through-hole wiring portion in a direction intersecting the thickness direction of the substrate, and the heat dissipation member is in contact with the terminal surface of the heat dissipation terminal corresponding to the through-hole wiring portion.

15. The semiconductor device according to claim 14, wherein the thin portion includes a portion positioned to overlap the semiconductor chip when viewed in the thickness direction of the substrate, and the chip terminal is electrically connected to the thin portion.

16. The semiconductor device according to any one of claims 1 to 15, further comprising a second sealing resin that covers the first sealing resin, the heat dissipation member, and the rear surface of the chip.

17. The semiconductor device according to claim 16, wherein the first sealing resin and the second sealing resin are made of different materials.

18. The semiconductor device according to claim 17, wherein the thermal conductivity of the first sealing resin is greater than the thermal conductivity of the second sealing resin.

19. The semiconductor device according to claim 16, wherein the thermal conductivity of the first sealing resin is greater than the thermal conductivity of air.

20. The semiconductor device according to any one of claims 1 to 19, wherein the heat dissipation component has a thickness of 5 μm or more and 30 μm or less.

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