Display device

Abstract

This display device comprises a CMOS wafer and a light-emitting diode disposed in a first area of the CMOS wafer. The light-emitting diode can include a first electrode structure, a light-emitting layer disposed on the first electrode structure, and a second electrode structure disposed on a semiconductor bonding structure. The first electrode structure includes a metal layer, a reflective layer disposed on the metal layer, and a first transparent conductive oxide layer disposed on the reflective layer.

Description

display device

[0001] The present invention relates to a display device, and more specifically, to a display device including a CMOS wafer and a light-emitting diode.

[0002] Electronic devices such as smartphones, laptop computers, navigation systems, and smart televisions that provide images to users include display devices for displaying the images. Augmented reality devices, virtual reality devices, and video projection devices may include micro-display devices. Micro-display devices may include CMOS wafers and light-emitting diodes arranged on the CMOS wafers to display high-brightness images while operating at low power.

[0003] An object of the present invention is to provide a display device with reduced optical loss and reduced defects.

[0004] A display device according to one embodiment of the present invention includes a complementary metal oxide semiconductor (CMOS) wafer and a plurality of light-emitting diodes disposed on the CMOS wafer and arranged in a first region of the CMOS wafer on a plane. Each of the plurality of light-emitting diodes includes a first electrode structure, a light-emitting layer disposed on the first electrode structure, and a second electrode structure disposed on the light-emitting layer. The first electrode structure includes a metal layer, a reflective layer disposed on the metal layer, and a first transparent conductive oxide layer disposed on the reflective layer.

[0005] According to the above, a first electrode structure with reduced defects can be provided. The first electrode structure can be formed through a bonding process of a CMOS wafer and a semiconductor substrate.

[0006] The side reflective layer can increase light output efficiency by reflecting light generated from the light-emitting diode. The lens can reduce light loss by focusing the emitted light.

[0007] The auxiliary electrodes placed within the trenches can reduce the voltage drop occurring at the common electrode by being connected to the common electrode as a whole.

[0008] Figure 1 is a perspective view of a display device according to an embodiment of the present invention.

[0009] Fig. 2 is a drawing illustrating a cross-section of the display device illustrated in Fig. 1.

[0010] FIG. 3a is a plan view showing a common electrode arranged in a display area and a non-display area of ​​a display device according to one embodiment of the present invention.

[0011] FIG. 3b is a plan view illustrating the arrangement relationship of a common electrode, a voltage transmission electrode, and auxiliary electrodes according to one embodiment of the present invention.

[0012] Fig. 4a is a plan view showing an enlarged portion of a part of the first region of Fig. 3a.

[0013] Figure 4b is a cross-sectional view corresponding to I-I' of Figure 4a.

[0014] Figure 4c is an enlarged cross-sectional view of the contact area between the second contact electrode and the first electrode structure.

[0015] Figure 4d is an enlarged cross-sectional view of the contact area between the passivation layer and the lens.

[0016] Figures 4e and 4f are cross-sectional views illustrating in detail the first electrode structure of Figure 4b.

[0017] Figure 4g is a cross-sectional view illustrating in detail the light-emitting diode of Figure 4b.

[0018] Fig. 5a is a plan view showing an enlarged portion of a part of the second area of ​​Fig. 3a.

[0019] Figure 5b is a cross-sectional view corresponding to II-II' of Figure 5a.

[0020] Figure 6a is a plan view showing an enlarged portion of a part of area 3-1 of Figure 3a.

[0021] Fig. 6b is a cross-sectional view corresponding to III-III' of Fig. 6a.

[0022] Figure 7a is a plan view showing an enlarged portion of a part of area 3-2 of Figure 3a.

[0023] Fig. 7b is a cross-sectional view corresponding to IV-IV' of Fig. 7a.

[0024] Figure 8a is a cross-sectional view corresponding to a second region according to one embodiment of the present invention.

[0025] Figure 8b is a cross-sectional view corresponding to area 3-2 according to one embodiment of the present invention.

[0026] FIGS. 9A to 9S are cross-sectional views illustrating a manufacturing process of a display device according to one embodiment of the present invention.

[0027] FIG. 10a is a plan view illustrating the arrangement relationship of a common electrode, a voltage transmission electrode, and an auxiliary electrode according to one embodiment of the present invention.

[0028] FIG. 10b is a plan view showing an enlarged portion of a part of area 3-2 according to one embodiment of the present invention.

[0029] Figures 10c and 10d are cross-sectional views corresponding to V-V' of Figure 10b.

[0030] FIG. 10e is a plan view showing an enlarged portion of a part of area 3-2 according to one embodiment of the present invention.

[0031] FIG. 10f is a plan view illustrating the arrangement relationship of a common electrode, a voltage transmission electrode, and an auxiliary electrode according to one embodiment of the present invention.

[0032] FIG. 11A is a cross-sectional view of a display device according to one embodiment of the present invention.

[0033] FIG. 11b is a cross-sectional view of a light emitting diode according to one embodiment of the present invention.

[0034] FIG. 11c is a cross-sectional view illustrating in detail a first electrode structure according to one embodiment of the present invention.

[0035] In this specification, when it is said that a component (or region, layer, portion, etc.) is “placed on,” “connected to,” or “coupled to” another component, it means that it can be placed / connected / coupled directly on the other component, or a third component may be placed between them.

[0036] In this specification, identical drawing numbers refer to identical components. Furthermore, in the drawings, the thicknesses, proportions, and dimensions of the components are exaggerated for the purpose of effectively illustrating the technical contents. In this specification, "and / or" includes any combination of one or more of the associated components.

[0037] While terms such as "first" and "second" may be used to describe various components, these components should not be limited by these terms. These terms are used solely to distinguish one component from another. For example, without departing from the scope of the present invention, a first component may be referred to as a "second component," and similarly, a second component may also be referred to as a "first component." Singular expressions include plural expressions unless the context clearly indicates otherwise.

[0038] Additionally, terms such as "below," "below," "above," and "above" are used to describe the relationships between components depicted in the drawings. These terms are relative concepts and are described based on the directions indicated in the drawings.

[0039] It should be understood that terms such as "include" or "have" are intended to specify the presence of a feature, number, step, operation, component, part or combination thereof described in the specification, but do not preclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts or combinations thereof.

[0040] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. Furthermore, terms defined in commonly used dictionaries should be interpreted to have a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an overly idealistic or overly formal sense unless explicitly defined herein.

[0041] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0042]

[0043] FIG. 1 is a perspective view of a display device (DD) according to an embodiment of the present invention.

[0044] Referring to FIG. 1, a display device (DD) according to an embodiment of the present invention may have a rectangular shape having long sides extending in a first direction (DR1) and short sides extending in a second direction (DR2) intersecting the first direction (DR1). However, the present invention is not limited thereto, and the display device (DD) may have various shapes such as a circle or a polygon. Hereinafter, a direction substantially perpendicular to a plane defined by the first direction (DR1) and the second direction (DR2) is defined as a third direction (DR3). In the present specification, the meaning of "when viewed in a plan view" is defined as a state viewed from the third direction (DR3).

[0045] The upper surface of the display device (DD) can be defined as a display surface (DS) and can have a plane defined by a first direction (DR1) and a second direction (DR2). Images (IM) generated in the display device (DD) can be provided to a user through the display surface (DS).

[0046] A display surface (DS) may include a display area (DA) and a non-display area (NDA) surrounding the display area (DA). The display area (DA) displays an image, and the non-display area (NDA) does not display an image. The non-display area (NDA) may surround the display area (DA), but is not limited thereto, and the non-display area (NDA) may not be positioned on one side of the display area (DA).

[0047] A plurality of pixels (PX) may be arranged in the display area (DA). The pixels (PX) may be arranged in a matrix form. Each pixel (PX) may include a pixel circuit and a light-emitting diode. The pixels (PX) may all generate light of the same color. In one embodiment of the present invention, the pixels (PX) may include a plurality of groups that generate light of different colors.

[0048]

[0049] Fig. 2 illustrates an example of a cross-section of the display device (DD) illustrated in Fig. 1.

[0050] Referring to FIG. 2, the display device (DD) may include a circuit element layer (10), a light emitting element layer (20), and a lens layer (30). However, the present invention is not limited thereto, and in one embodiment of the present invention, the lens layer (30) may be omitted, and another functional layer may be added.

[0051] The circuit element layer (10) may include a pixel circuit. The pixel circuit may control the operation of a light-emitting diode of the light-emitting element layer (20) described below. The pixel circuit may include at least one transistor. The circuit element layer (10) may include a CMOS wafer. The CMOS wafer may include nMOSFETs (NMOS) and pMOSFETs (PMOS) that are complementarily connected. A plurality of pixel areas are regularly arranged on the CMOS wafer, and a pixel circuit is arranged in each pixel area.

[0052] The light-emitting element layer (20) may include a light-emitting diode electrically connected to the pixel circuit. The light-emitting diode is a type of compound semiconductor and is an electrically driven light-emitting diode that includes gallium (Ga), phosphorus (P), and arsenic (As) as its main semiconductor materials. When a forward current is applied to the pn junction structure, electrons and holes combine at the junction surface to generate light of a specific wavelength corresponding to the band gap energy.

[0053] The lens layer (30) is disposed on the light-emitting element layer (20) and may include a lens. The lens may be disposed to correspond to the light-emitting diode. The lens collects light emitted from the light-emitting diode. The light collected by the lens may be transmitted through the light guide unit.

[0054]

[0055] FIG. 3A is a plan view showing a common electrode (CME) according to one embodiment of the present invention, arranged in a display area (DA) and a non-display area (NDA) of a display device (DD). The display area (DA) and the non-display area (NDA) of the display device (DD) can be equally applied to the circuit element layer (10), i.e., the CMOS wafer, described in FIG. 2. Hereinafter, the circuit element layer (10) is described as a CMOS wafer (10), and the same reference numerals are used.

[0056] The common electrode (CME) can cover at least the display area (DA). The common electrode (CME) transmits an externally applied power voltage to the entire display area (DA). Hereinafter, the display area (DA) is referred to as the first area (DA) and is referred to by the same reference numeral.

[0057] The non-display area (NDA) can be divided into multiple areas. In the present embodiment, the non-display area (NDA) can include a second area (NDA1) and a third area (NDA2).

[0058] The second region (NDA1) may be arranged outside the first region (DA) and may be an region in which dummy light-emitting diodes, which will be described later, are arranged. In the present embodiment, the second region (NDA1) may surround the first region (DA), but is not necessarily limited thereto. The dummy light-emitting diodes have the same stacked structure as the light-emitting diodes of the first region (DA), but are not electrically connected to the common electrode (CME) and thus cannot be driven (or emit light). The structural characteristics of the dummy light-emitting diodes will be described later.

[0059] When forming light emitting diodes in a specific region through the same process, the outer region may have different process conditions compared to the inner region. For example, the thickness of the deposited metal layer may be smaller, or the etching rate may be different. Accordingly, defective light emitting diodes may be formed in the outer region. Considering this, the light emitting diodes formed in the outer region are not used as effective light emitting diodes, but as dummy light emitting diodes. If the process conditions and process efficiency are consistent regardless of the regions, the dummy light emitting diodes may be omitted, and thus, in one embodiment of the present invention, the second region (NDA1) may be omitted.

[0060] The third region (NDA2) may include an inner region (NDA21, hereinafter referred to as the 3-1 region) and an outer region (NDA22, hereinafter referred to as the 3-2 region) that are distinguished according to the arrangement of the common electrode (CME). The 3-1 region (NDA21) is arranged closer to the first region (DA) than the 3-2 region (NDA22).

[0061] A common electrode (CME) is disposed in the 3-1 region (NDA21), but no light-emitting diodes or dummy light-emitting diodes are disposed therein. In the present embodiment, the 3-1 region (NDA21) may surround the 2nd region (NDA1), but is not necessarily limited thereto. The range of the 3-1 region (NDA21) may be determined by the edge of the common electrode (CME).

[0062] The 3-2 area (NDA22) may be an area where a common electrode (CME) is not placed. In the present embodiment, the 3-2 area (NDA22) may surround the 3-1 area (NDA21), but is not necessarily limited thereto. A plurality of driving circuits may be placed in the 3-2 area (NDA22) of the CMOS wafer (10, see FIG. 2). For example, scan drivers may be placed in the left and right areas of the 3-2 area (NDA22), with the 1st area (DA) interposed therebetween. A data driver may be placed in a portion of the 3-2 area (NDA22) located below the 1st area (DA). In addition, an analog circuit, such as a power circuit, may be placed in a portion of the 3-2 area (NDA22). The above-described scan driver, data driver, and analog circuit may be embedded in the CMOS wafer. That is, the scan driver, data driver, and analog circuit may include transistors formed in the same manner as the pixel circuit.

[0063] A pad area (PDA) having a plurality of pad electrodes (PD) may be arranged on one side of the 3-2 area (NDA22). The pad area (PDA) may correspond to a portion of the 3-2 area (NDA22). A circuit board may be connected to the pad area (PDA). In Fig. 3a, only four pad electrodes (PD) that receive a power voltage applied to the common electrode (CME) are illustrated, but more pad electrodes may be arranged in the pad area (PDA). The pad electrodes that are not illustrated may receive data image signals or control signals from the outside and provide them to the data driver.

[0064] Referring to Fig. 3a, a voltage transfer electrode (VTE) may be arranged in the 3-2 region (NDA22). Four voltage transfer electrodes (VTE) corresponding to four pad electrodes (PD) are illustrated. The voltage transfer electrode (VTE) may extend from the common electrode (CME) toward the pad area (PDA). The voltage transfer electrode (VTE) may be formed through the same process as the common electrode (CME), may have the same laminated structure, and may have an integral shape. The voltage transfer electrode (VTE) and the common electrode (CME) may be different portions of one electrode formed through the same process.

[0065] FIG. 3b is a plan view illustrating the arrangement relationship of a common electrode (CME), a voltage transmission electrode (VTE), and an auxiliary electrode (SE) according to one embodiment of the present invention.

[0066] The auxiliary electrode (SE) overlaps the common electrode (CME) and the voltage transfer electrode (VTE), respectively. Within the third direction (DR3), the auxiliary electrode (SE) is positioned below the common electrode (CME) and the voltage transfer electrode (VTE).

[0067] The auxiliary electrode (SE) may include a plurality of first auxiliary electrodes (SE1) extending in a first direction (DR1) and a plurality of second auxiliary electrodes (SE2) extending in a second direction (DR2). The first auxiliary electrodes (SE1) are arranged in the second direction (DR2), and the second auxiliary electrodes (SE2) are arranged in the first direction (DR1).

[0068] A unit area (UA) may be located within an area defined by the two most adjacent first auxiliary electrodes (SE1) among the first auxiliary electrodes (SE1) and the two most adjacent second auxiliary electrodes (SE2) among the second auxiliary electrodes (SE2). However, the unit area (UA) is arranged within the display area (DA) of Fig. 3a. One unit area (UA) is representatively illustrated in Fig. 3b. At least a light-emitting diode is arranged in the unit area (UA). A detailed description thereof will be provided later.

[0069] A part of the auxiliary electrode (SE) overlaps a common electrode (CME), and the part overlapping the common electrode (CME) is entirely connected to the common electrode (CME), thereby reducing a voltage drop occurring at the common electrode (CME). Another part of the auxiliary electrode (SE) overlaps a voltage transfer electrode (VTE), and the part overlapping the voltage transfer electrode (VTE) is entirely connected to the voltage transfer electrode (VTE), thereby reducing the resistance of a voltage transfer path between a pad electrode (PD, see Fig. 3a) and the common electrode (CME). The auxiliary electrode (SE) is formed by the same process regardless of the regions, and may have an integral shape.

[0070] Fig. 4a is a plan view showing an enlarged portion (A1) of the first area (DA) of Fig. 3a. Fig. 4b is a cross-sectional view corresponding to line I-I' of Fig. 4a. Fig. 4c is an enlarged cross-sectional view showing a contact area (B1) between the second contact electrode (135) and the first electrode structure (ES1, or first electrode member). Fig. 4d is an enlarged cross-sectional view showing a contact area (B2) between the passivation layer (150) and the lens (LS). Figs. 4e and 4f are cross-sectional views showing in detail the first electrode structure (ES1) of Fig. 4b. Fig. 4g is a cross-sectional view showing in detail the light emitting diode (LED) of Fig. 4b.

[0071] Figure 4a illustrates first auxiliary electrodes (SE1) and second auxiliary electrodes (SE2) that intersect each other. The first auxiliary electrodes (SE1) are respectively positioned in the first trenches (TC1), and the second auxiliary electrodes (SE2) are respectively positioned in the second trenches (TC2).

[0072] The first region (DA) may include a plurality of unit regions (UA) and a boundary region (BA) between the unit regions (UA). Each of the unit regions (UA) is an inner region defined by two adjacent first trenches (TC1) among the first trenches (TC1) and two adjacent second trenches (TC2) among the second trenches (TC2). The boundary region (BA) is a region where the first trenches (TC1) and the second trenches (TC2) are located.

[0073] In this embodiment, the boundary area (BA) is defined as the area where the first trenches (TC1) and the second trenches (TC2) are arranged, but is not limited thereto. The plurality of unit areas (UA) may be defined narrower than those defined in Fig. 4a. In this case, the width of the boundary area (BA) may be further increased, and for example, the boundary area (BA) may be defined to have a width greater than the widths of the first auxiliary electrodes (SE1) and the second auxiliary electrodes (SE2).

[0074] In Fig. 4a, light emitting diodes (LED), lenses (LS), and first openings (COP1) arranged in unit areas (UA) are illustrated. The common electrode (CME) of Fig. 4b and the light emitting diodes (LED) of Fig. 4b are connected through the first openings (COP1). In a plan view, each of the first openings (COP1) may be arranged on the inside of a corresponding lens (LS) among the lenses (LS). In a plan view, each of the lenses (LS) may be arranged on the inside of a corresponding light emitting diode (LED) among the light emitting diodes (LED).

[0075] Fig. 4b is a detailed illustration of Fig. 2. The display device (DD) may include a CMOS wafer (10), a light emitting element layer (20), and a lens layer (30).

[0076] A CMOS wafer (10) includes a silicon substrate (101). A plurality of source / drain regions (111) are defined in the silicon substrate (101). Each of the source / drain regions (111) may be a region doped with a dopant. The source / drain regions (111) may become a source or a drain of a transistor depending on a signal flow. A pair of source / drain regions (111) may define a transistor together with a gate (121, or gate electrode) described below. When one of the source / drain regions (111) arranged on both sides of the gate (121) is a source region, the other may be a drain region. A first contact electrode (125) described below is electrically connected to the source region or the drain region.

[0077] Shallow trench isolation (STI) regions (115) may be further defined on the silicon substrate (101). The STI regions (115) can isolate the transistors to prevent leakage current. The STI regions (115) may be arranged differently depending on the design of the pixel circuit.

[0078] Gates (121) are disposed on a silicon substrate (101). The gates (121) may include a metal. Each of the gates (121) is disposed to correspond to a pair of source / drain regions (111). A first insulating layer (123) is disposed on the silicon substrate (101). The first insulating layer (123) may include an oxide layer, such as a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or an aluminum oxide layer. Although a single layer of the first insulating layer (123) is illustrated, the first insulating layer (123) is not limited to a single layer.

[0079] A CMOS wafer (10) includes a first contact electrode (125). It can be connected to a source / drain region (111) through a first contact hole (CH1) defined in a first insulating layer (123). An upper surface of the first contact electrode (125) can define a plane (or flat surface) that is the same as an upper surface of the first insulating layer (123). The first contact electrode (125) can be formed by a damascene process. The first contact electrode (125) can include a metal such as copper or tungsten.

[0080] A second insulating layer (130) is disposed on the first insulating layer (123). A second contact hole (CH2) exposing the first contact electrode (125) may be defined in the second insulating layer (130). The second insulating layer (130) may include an oxide layer, such as a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or an aluminum oxide layer. Although a single layer of the second insulating layer (130) is illustrated, the second insulating layer (130) is not limited to a single layer.

[0081] A second contact electrode (135) may be disposed in the second contact hole (CH2). The upper surface of the second contact electrode (135) may define the same plane (or flat surface) as the upper surface of the second insulating layer (130). The second contact electrode (135) may include a metal structure (135-1) disposed inside the second contact hole and a barrier layer (135-2) disposed between the side surface of the metal structure (135-1) and the inner surface of the second contact hole (CH2), and disposed between the lower surface of the metal structure (135-1) and the upper surface of the first contact electrode (125) exposed through the second contact hole (CH2).

[0082] The metal structure (135-1) may include a metal such as copper or tungsten. The barrier layer (135-2) also has conductivity. The barrier layer (135-2) can increase the bonding strength to the second insulating layer (130) and the first contact electrode (125) and prevent the metal atoms of the metal structure (135-1) from diffusing into the second insulating layer (130).

[0083] The barrier layer (135-2) may include a metal layer of a barrier metal and a nitride layer made of a barrier metal nitride. The nitride layer of the barrier metal may be disposed closer to the second insulating layer (130) than the barrier metal layer. The barrier metal layer improves bonding strength, and the nitride layer of the barrier metal prevents diffusion of atoms of the metal structure (135-1). The barrier metal may include titanium or tantalum. The barrier layer (135-2) may include a titanium nitride layer and a titanium layer, or a tantalum nitride layer and a tantalum layer.

[0084] In one embodiment of the present invention, the second contact electrode (135) may include a tungsten structure, a titanium layer surrounding the side and lower surfaces of the tungsten structure, and a titanium nitride layer surrounding the titanium layer. In one embodiment of the present invention, the second contact electrode (135) may include a copper structure, a tantalum layer surrounding the side and lower surfaces of the copper structure, and a tantalum nitride layer surrounding the tantalum layer.

[0085] As illustrated in FIG. 4c, in one embodiment of the present invention, the upper surface of the second contact electrode (135) may be concave. A first electrode structure (ES1) described later may be in contact with the concave upper surface of the second contact electrode (135). The second contact electrode (135) may be formed by a damascene process. In the damascene process, the second contact electrode (135) is polished more than the second insulating layer (130) in the CMP (Chemical Mechanical Polishing) process, resulting in a dishing phenomenon in the second contact electrode (135).

[0086] Referring again to FIG. 4B, light emitting diodes (LEDs) are arranged on the second insulating layer (130). The light emitting diodes (LEDs) illustrated in FIG. 4A can generate light of the same color. In one embodiment of the present invention, one of the light emitting diodes (LEDs) illustrated in FIG. 4A can generate red light, another can generate green light, and another can generate blue light. The remaining one can generate one of red light, green light, blue light, and white light.

[0087] The light emitting diode (LED) of FIG. 4B may include a first electrode, a second electrode, and a light emitting layer disposed therebetween. In the present embodiment, the first electrode is described as a first electrode structure (ES1), and the second electrode is described as a second electrode structure (ES2). In addition, the light emitting layer includes a semiconductor junction structure (SJS). In other words, the light emitting diode (LED) according to the present embodiment may include a first electrode structure (ES1), a semiconductor junction structure (SJS) disposed on the first electrode structure (ES1), and a second electrode structure (ES2) disposed on the semiconductor junction structure (SJS). The first electrode structure (ES1) contacts the second contact electrode (135) and may have a larger diameter than the semiconductor junction structure (SJS) and the second electrode structure (ES2). In the present embodiment, the semiconductor junction structure (SJS) and the second electrode structure (ES2) may have the same diameter. On a plane, the semiconductor junction structure (SJS) and the second electrode structure (ES2) may be arranged inside the first electrode structure (ES1). In one embodiment of the present invention, the first electrode structure (ES1) may have the same diameter as the semiconductor junction structure (SJS) and the second electrode structure (ES2).

[0088] As illustrated in Fig. 4a, when the light-emitting diode (LED) has a circular shape, the first electrode structure (ES1) may also have a circular shape. However, the shape of the first electrode structure (ES1) is not limited thereto. The first electrode structure (ES1) may have an oval shape, or a polygonal shape such as a square or octagon.

[0089] In the present embodiment, the first electrode structure (ES1) is described as an anode (or anode structure), and the second electrode structure (ES2) is described as a cathode (or cathode structure), but is not limited thereto. In one embodiment of the present invention, the first electrode structure (ES1) may be a cathode, and the second electrode structure (ES2) may be an anode. Depending on whether the first electrode structure (ES1) is an anode or a cathode, the stacking configuration of the semiconductor junction structure (SJS) may vary.

[0090] The light emitting element layer (20) may include a first side insulating layer (SI1) disposed on the side of the first electrode structure (ES1), the side of the semiconductor junction structure (SJS), the side of the second electrode structure (ES2), and the upper surface of the second electrode structure (ES2). The first side insulating layer (SI1) surrounds the light emitting diode (LED) except for the first opening (COP1) and the lower surface of the first electrode structure (ES1).

[0091] The first side insulating layer (SI1) prevents contact between the light-emitting diode (LED) and the side reflective layer (SRL) described below. The first side insulating layer (SI1) may include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, an aluminum oxide layer, a zirconium oxide layer, a hafnium oxide layer, or a titanium oxide layer. In Fig. 4a, the first side insulating layer (SI1) is illustrated as a single layer, but is not limited thereto. The first side insulating layer (SI1) may have a single layer structure of the above-described layers or a multilayer structure arbitrarily selected from the above-described layers.

[0092] A side reflective layer (SRL) is disposed on the outer side of the first side insulating layer (SI1). The side reflective layer (SRL) can increase light efficiency by reflecting light generated from a light emitting diode (LED) so that the light generated from the LED is emitted through the first opening (COP1). The side reflective layer (SRL) can include gold (Au), copper (Cu), silver (Ag), titanium (Ti), or aluminum (Al).

[0093] The side reflection layer (SRL) is arranged to correspond to at least the side surface of the first electrode structure (ES1), the side surface of the semiconductor junction structure (SJS), and the side surface of the second electrode structure (ES2). A portion of the side reflection layer (SRL) may be further arranged on the upper surface of the second electrode structure (ES2).

[0094] In the present embodiment, the side reflective layers (SRL) may be arranged spaced apart from each light-emitting diode (LED). The side reflective layers (SRL) may be separated and spaced apart from each other at the boundary area (BA). However, the present invention is not limited thereto, and the side reflective layers (SRL) may have an integral shape. For example, the reflective layers (SRL) may have an integral shape within the first area (DA) of FIG. 4A.

[0095] The light emitting element layer (20) may further include a second side insulating layer (SI2) disposed on the inner side of the first side insulating layer (SI1). The second side insulating layer (SI2) is disposed to protect a portion of the side of the light emitting diode (LED) during the manufacturing process of the light emitting diode (LED). A detailed description thereof will be provided later.

[0096] The second side insulating layer (SI2) can be in contact with the side surface of the semiconductor bonding structure (SJS) and the side surface of the second electrode structure (ES2). The second side insulating layer (SI2) can be further disposed on a portion of the upper surface of the second electrode structure (ES2). The second side insulating layer (SI2) can be further disposed on a portion of the upper surface of the first electrode structure (ES1) exposed by the semiconductor bonding structure (SJS). The second side insulating layer (SI2) can include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, an aluminum oxide layer, a zirconium oxide layer, a hafnium oxide layer, or a titanium oxide layer. In FIG. 4A, the second side insulating layer (SI2) is illustrated as a single layer, but is not limited thereto. The second side insulating layer (SI2) can have a single layer structure of the above-described layers or a multilayer structure arbitrarily selected from the above-described layers.

[0097] The first opening (COP1) corresponds to the light-emitting area of ​​the light-emitting diode (LED) and corresponds to a passage connecting the second electrode structure (ES2) to the common electrode (CME).

[0098] A planarization layer (140) is disposed on the second insulating layer (130). The planarization layer (140) overlaps a plurality of unit areas (UA) and boundary areas (BA) and is disposed on a plurality of light-emitting diodes (LEDs). The planarization layer (140) fills areas where light-emitting diodes (LEDs) are not disposed. The planarization layer (140) may include an organic material.

[0099] The planarization layer (140) may be arranged to correspond to the side surface of the first electrode structure (ES1) and the side surface of the semiconductor junction structure (SJS). A portion of the planarization layer (140) may be arranged to correspond to the side surface of the second electrode structure (ES2), and another portion may be arranged on the second electrode structure (ES2) and may overlap the side surface reflective layer (SRL). The planarization layer (140) may be in contact with the side surface reflective layer (SRL). A second opening (COP2) corresponding to the first opening (COP1) may be arranged in the planarization layer (140). The second opening (COP2) may be aligned with the first opening (COP1), but the second opening (COP2) formed by a different process from the first opening (COP1) may have a larger area than the first opening (COP1).

[0100] In one embodiment of the present invention, the planarization layer (140) may be disposed on the second electrode structure (ES2). The upper surface of the planarization layer (140) may define the same plane as the upper surface of the side reflection layer (SRL). In this case, the second opening (COP2) may be omitted.

[0101] In the planarization layer (140), trenches (TC1, TC2) of FIG. 4a are defined, and second trenches (TC2) are exemplarily illustrated in FIG. 4b. Second auxiliary electrodes (SE2) are arranged in the second trenches (TC2). The first auxiliary electrodes (SE1) illustrated in FIG. 4a are formed by the same process as the second auxiliary electrodes (SE2) and may have the same structure as the structure of the second auxiliary electrodes (SE2) described below.

[0102] The second auxiliary electrode (SE2) may include a metal structure (SE2-1) disposed inside the second trench (TC2) and a barrier layer (SE2-2) disposed between the metal structure (SE2-1) and the second trench (TC2). The metal structure (SE2-1) may include a metal such as copper or tungsten. The barrier layer (SE2-2) has conductivity like the metal structure (SE2-1). The barrier layer (SE2-2) may increase the bonding strength to the planarization layer (140) and prevent metal atoms of the metal structure (SE2-1) from diffusing into the planarization layer (140).

[0103] The barrier layer (SE2-2) may include a barrier metal layer and a nitride layer of the barrier metal. The nitride layer of the barrier metal may be arranged closer to the planarization layer (140) than the barrier metal layer. The barrier metal layer may include titanium or tantalum. The nitride layer of the barrier metal may include a titanium nitride layer or a tantalum nitride layer. The second auxiliary electrode (SE2) may also be formed by a damascene method like the second contact electrode (135), and the upper surface of the second auxiliary electrode (SE2) may be concave.

[0104] A common electrode (CME) is disposed on the planarization layer (140). The common electrode (CME) may overlap the unit areas (UA) and the boundary area (BA). The common electrode (CME) may include a transparent conductive material to emit light generated from a light emitting diode (LED). The common electrode (CME) may include a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), zinc tin oxide (ZTO), or indium gallium zinc oxide (IGZO).

[0105] A common electrode (CME) is connected to second electrode structures (ES2) of light-emitting diodes (LEDs) through first openings (COP1) and second openings (COP2). A power supply voltage applied through the common electrode (CME) can be transmitted to the light-emitting diodes (LEDs). Fig. 4b illustrates an example of a common electrode (CME) connected to two light-emitting diodes (LEDs). One of the two light-emitting diodes (LEDs) may be defined as a first light-emitting diode (LED) and the other may be defined as a second light-emitting diode (LED).

[0106] The common electrode (CME) is in contact with the upper surface of the second auxiliary electrodes (SE2). Since the upper surface of the second auxiliary electrodes (SE2) is in contact with the common electrode (CME) along the longitudinal direction of the second trench (TC2) as shown in Fig. 4a, the common electrode (CME) and the second auxiliary electrodes (SE2) can secure a sufficient contact area.

[0107] A passivation layer (150) is disposed on the common electrode (CME). The passivation layer (150) protects the common electrode (CME). The passivation layer (150) may overlap the display area (DA) and the non-display area (NDA) of FIGS. 3A and 3B and may protect the voltage transfer electrodes (VTE). The passivation layer (150) may include an organic material or an inorganic material.

[0108] Lenses (LS) are arranged on the passivation layer (150). Two lenses (LS) corresponding to the first and second light-emitting diodes (LED) are illustrated. The lenses (LS) focus light emitted from the light-emitting diodes (LED). The lenses (LS) include an organic material and may have a hemispherical shape. The diameter of the lenses (LS) may be 1 micrometer or less.

[0109] As illustrated in FIGS. 4b and 4d, the passivation layer (150) may include a concave region (150-c). A step is formed in the region corresponding to the first opening (COP1) of FIG. 4b, and such a step may be transferred to each of the common electrode (CME) and the passivation layer (150). Depending on the material or thickness of the passivation layer (150), the step may be removed.

[0110] Hereinafter, the laminated structure of the first electrode structure (ES1) will be described in detail with reference to FIGS. 4E and 4F. Although not separately illustrated, the first electrode structure (ES1) according to an embodiment of the present invention may omit some layers from the structure illustrated in FIGS. 4E and 4F, or may further include other functional layers.

[0111] Referring to FIG. 4e, the first electrode structure (ES1) may include at least a metal layer (ML), a reflective layer (RL) disposed on the metal layer (ML), and a transparent conductive oxide layer (TCO1, hereinafter referred to as a first transparent conductive oxide layer) disposed on the reflective layer (RL). The metal layer (ML), the reflective layer (RL), and the first transparent conductive oxide layer (TCO1) may be sequentially laminated, or additional functional layers may be further disposed between the metal layer (ML), the reflective layer (RL), and the first transparent conductive oxide layer (TCO1).

[0112] The metal layer (ML) corresponds to the adhesive layer that bonds the CMOS wafer and the semiconductor substrate during the display device manufacturing process. In other words, the metal layer (ML) is a layer formed by bonding the metal layer of the CMOS wafer and the metal layer of the semiconductor substrate.

[0113] The metal layer (ML) may include at least one metal layer. The at least one metal layer may include any one of gold (Au), copper (Cu), silver (Ag), tin (Sn), titanium (Ti), zirconium (Zr), and tantalum (Ta), or an alloy of two of these metals.

[0114] In this embodiment, a three-layer metal layer (ML) including first to third metal layers (ML1, ML2, ML3) is exemplarily illustrated. The second metal layer (ML2) includes any one of gold (Au), copper (Cu), silver (Ag), tin (Sn), titanium (Ti), zirconium (Zr), and tantalum (Ta), but may include a different metal from the first and third metal layers (ML1, ML3). Each of the first and third metal layers (ML1, ML3) may include any one of (Au), copper (Cu), silver (Ag), tin (Sn), titanium (Ti), zirconium (Zr), and tantalum (Ta). In one embodiment of the present invention, the metal layer (ML) may include two consecutive metal layers among the first to third metal layers (ML1, ML2, ML3).

[0115] The reflective layer (RL) reflects light generated in the semiconductor junction structure (SJS) toward the semiconductor junction structure (SJS). The reflective layer (RL) may include gold (Au), copper (Cu), silver (Ag), titanium (Ti), or aluminum (Al).

[0116] The first transparent conductive oxide layer (TCO1) injects holes into the semiconductor junction structure (SJS). The first transparent conductive oxide layer (TCO1) has a high work function, which is advantageous for hole injection, and can transmit light reflected from the reflective layer (RL). The first transparent conductive oxide layer (TCO1) includes at least one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), zinc tin oxide (ZTO), and indium gallium zinc oxide (IGZO).

[0117] Although the first electrode structure (ES1) in this embodiment is described as an anode and has the structure described above, if the first electrode structure (ES1) is a cathode, the structure of the first electrode structure (ES1) may be changed. The electron injection functional layer and the reflective layer may be integrated into a single metal layer. That is, the metal layer functions as both an electron injection layer and a reflective layer. Accordingly, the cathode structure may include two distinct metal layers.

[0118] The first electrode structure (ES1) may have a thickness of 500 nm or less. As the thickness of the first electrode structure (ES1) increases, a process error occurs depending on the thickness. For example, the etching rate may vary depending on the thickness. If the thickness of the first electrode structure (ES1) is thick, the first electrode structure (ES1) is formed to have a more inclined side surface. In order to form the first electrode structure (ES1) having a vertical side surface, the first electrode structure (ES1) preferably has a thickness of 500 nm or less.

[0119] According to FIG. 4e, the first electrode structure (ES1) may include a first barrier layer (BRL1) disposed between a metal layer (ML) and a reflective layer (RL), a second barrier layer (BRL2) disposed between the reflective layer (RL) and a first transparent conductive oxide layer (TCO1), and a third barrier layer (BRL3) disposed under the metal layer (ML). Each of the first to third barrier layers (BRL1) to (BRL3) may include a barrier metal layer and a nitride layer of the barrier metal. The barrier metal layer improves adhesion between adjacent layers, and the nitride layer of the barrier metal prevents diffusion of atoms of the adjacent layers.

[0120] In the present embodiment, the first barrier layer (BRL1) may include a nitride layer (BMLN) of a barrier metal including titanium nitride, and barrier metal layers (BML) each including titanium, which are respectively disposed on the upper and lower sides of the nitride layer of the barrier metal. The titanium nitride layer may, for example, block metal atoms of the metal layer (ML) from moving to the reflective layer (RL), thereby preventing electromigration from occurring in the reflective layer (RL).

[0121] In the present embodiment, the second barrier layer (BRL2) may include a nitride layer (BMLN) of a barrier metal including titanium nitride. The titanium nitride layer may, for example, block atomic movement between the first transparent conductive oxide layer (TCO1) and the reflective layer (RL), thereby preventing voids from forming in the first transparent conductive oxide layer (TCO1) or oxidation of the reflective layer (RL).

[0122] In this embodiment, the third barrier layer (BRL3) may include a nitride layer (BMLN) of a barrier metal including titanium nitride, and barrier metal layers (BML) including titanium, which are respectively disposed on the upper and lower sides of the nitride layer of the barrier metal. This may prevent electromigration from occurring between the second contact electrode (135) of FIG. 4b and the metal layer (ML).

[0123] FIG. 4F illustrates a first electrode structure (ES1) having a simplified laminated structure compared to FIG. 4E. The metal layer (ML) may include a single metal layer. The first barrier layer (BRL10) may include a nitride layer (BMLN) of a barrier metal and a barrier metal layer (BML) disposed on the upper side of the nitride layer (BMLN) of the barrier metal. The third barrier layer (BRL30) may include a nitride layer (BMLN) of a barrier metal and a barrier metal layer (BML) disposed under the nitride layer (BMLN) of the barrier metal. The nitride layer (BMLN) of the barrier metal of the first barrier layer (BRL10) may contact the upper surface of the metal layer (ML), and the nitride layer (BMLN) of the barrier metal of the third barrier layer (BRL30) may contact the lower surface of the metal layer (ML).

[0124] The laminated structure of FIG. 4f may also be formed by having specific layers in the laminated structure of FIG. 4e having the same material. For example, when the metal layer (ML) of FIG. 4e has a single-layer structure of titanium (Ti) and the barrier metal layer (BML) of the first and third barrier layers (BRL1, BRL3) includes titanium (Ti), the barrier metal layer (BML) and the metal layer (ML) of the first and third barrier layers (BRL1, BRL3) adjacent to the metal layer (ML) may be a single metal layer.

[0125] A light emitting diode (LED) is described in detail with reference to FIG. 4G. In FIG. 4G, the first electrode structure (ES1) is schematically illustrated as a single layer, and the semiconductor junction structure (SJS) is illustrated in detail. Although the first electrode structure (ES1) is illustrated as having a disc shape, the shape of the first electrode structure (ES1) is not limited thereto. In the present embodiment, the light emitting diode (LED) may have a cylindrical shape, but is not limited thereto.

[0126] A semiconductor junction structure (SJS) may include an active layer (ACT), a p-type semiconductor layer (SP) disposed on one side of the active layer (ACT), and an n-type semiconductor layer (SN) disposed on the other side of the active layer (ACT). In the present embodiment, since the first electrode structure (ES1), which is an anode, is disposed on the lower side of the active layer (ACT), the p-type semiconductor layer (SP) is disposed on the lower side of the active layer (ACT).

[0127] The active layer (ACT) can be formed with a single-quantum well (SQW) or multi-quantum well (MQW) structure. Light can be emitted through the combination of electron-hole pairs in response to an electrical signal applied through the p-type semiconductor layer (SP) and the n-type semiconductor layer (SN). The active layer (ACT) can emit light with a wavelength of 400 nm to 900 nm, and a double heterostructure can be used.

[0128] In one embodiment of the present invention, the active layer (ACT) may have a structure in which semiconductor materials having a large band gap energy and semiconductor materials having a small band gap energy are alternately laminated, and may include semiconductor materials of group 3 to 5 selected according to the wavelength of the light emitted.

[0129] The p-type semiconductor layer (SP) includes at least one semiconductor material selected from the group consisting of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may be doped with a first conductivity type dopant such as magnesium (Mg), zinc (Zn), calcium (Ca), or barium (Ba). For example, the p-type semiconductor layer (SP) may be p-GaN doped with magnesium (Mg). However, the material constituting the p-type semiconductor layer (SP) is not limited thereto, and various other materials may also constitute the p-type semiconductor layer (SP).

[0130] The n-type semiconductor layer (SN) includes at least one semiconductor material selected from the group consisting of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may be doped with a second conductivity type dopant such as silicon (Si), germanium (Ge), or tin (Sn). However, the material constituting the n-type semiconductor layer (SN) is not limited thereto, and various other materials may also constitute the n-type semiconductor layer (SN).

[0131] Although not shown, the light emitting diode (LED) may further include a cladding layer. The cladding layer may be disposed on the upper side and / or lower side of the active layer (ACT). The cladding layer may include an AlGaN layer or an InAlGaN layer. The light emitting diode (LED) may further include a tensile strain barrier reducing layer (TSBR) disposed on the upper side and / or lower side of the active layer (ACT). The TSBR layer may be a strain relief layer disposed between semiconductor layers having different lattice structures to act as a buffer to reduce a difference in lattice constants. The TSBR layer may be composed of a p-type semiconductor layer such as p-GaInP, p-AlInP, p-AlGaInP, etc., but the present invention is not limited thereto.

[0132] In the present embodiment, the second electrode structure (ES2) may include a transparent conductive oxide layer (hereinafter, referred to as the second transparent conductive oxide layer (TCO2)). The second transparent conductive oxide layer (TCO2) may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), zinc tin oxide (ZTO), or indium gallium zinc oxide (IGZO). The second transparent conductive oxide layer corresponds to a protective layer in the manufacturing process of a light-emitting diode (LED) and can inject electrons into a semiconductor junction structure (SJS). A detailed description of the protective layer role of the second transparent conductive oxide layer will be described later with reference to the manufacturing method.

[0133] The second electrode structure (ES2) may further include an electrode metal layer disposed between the second transparent conductive oxide layer and the semiconductor junction structure (SJS). The electrode metal layer may include a metal having a lower work function than the second transparent conductive oxide layer. The electrode metal layer may improve the electron injection performance of the second electrode structure (ES2). The electrode metal layer may include aluminum (Al), titanium (Ti), indium (In), gold (Au), silver (Ag), nickel (Ni), copper (Cu), oxides thereof, or alloys thereof.

[0134]

[0135] Fig. 5a is an enlarged plan view of a portion (A2) of the second area (NDA1) of Fig. 3a. Fig. 5b is a cross-sectional view corresponding to II-II' of Fig. 5a. Hereinafter, the differences from the portion (A1) of the first area (DA) described with reference to Figs. 4a to 4d will be described.

[0136] Referring to FIG. 5A, first auxiliary electrodes (SE1) are respectively disposed in first trenches (TC1) and second auxiliary electrodes (SE2) are respectively disposed in second trenches (TC2) within the second region (NDA1). The first auxiliary electrodes (SE1) extend from the first auxiliary electrodes (SE1) of FIG. 4A, and the second auxiliary electrodes (SE2) extend from the second auxiliary electrodes (SE2) of FIG. 4A.

[0137] The second region (NDA1) may include unit regions (UA) and boundary regions (BA) between the unit regions (UA). The arrangement relationship between the unit regions (UA) and the boundary regions (BA) of the third region (NDA2) may be the same as the arrangement relationship between the unit regions (UA) and the boundary regions (BA) of the second region (NDA1). Dummy light-emitting diodes (DED) are arranged in the unit regions (UA) of the second region (NDA1), and lenses (LS) and first openings (COP1) are not arranged.

[0138] The dummy light-emitting diode (DED) illustrated in FIG. 5b may have substantially the same laminated structure as the light-emitting diode (LED) illustrated in FIG. 4b. This is because the dummy light-emitting diode (DED) is formed by the same process as the light-emitting diode (LED). The second electrode structure (ES2) of the dummy light-emitting diode (DED) is not exposed to the outside and is not connected to the common electrode (CME). This is because the first opening (COP1) is not formed in the first side insulating layer (SI1), the second side insulating layer (SI2), and the side reflective layer (SRL). Therefore, the dummy light-emitting diode (DED) cannot be driven or emit light.

[0139]

[0140] Fig. 6a is an enlarged plan view of a portion (A3) of the 3-1 area (NDA21) of Fig. 3a. Fig. 6b is a cross-sectional view corresponding to III-III' of Fig. 6a. Hereinafter, the differences between the portion (A1) of the first area (DA) described above and the portion (A2) of the second area (NDA1) described above will be described.

[0141] Referring to FIG. 6a, first auxiliary electrodes (SE1) are respectively disposed in first trenches (TC1) and second auxiliary electrodes (SE2) are respectively disposed in second trenches (TC2) within the 3-1 region (NDA21). The first auxiliary electrodes (SE1) extend from the first auxiliary electrodes (SE1) of FIG. 5a, and the second auxiliary electrodes (SE2) extend from the second auxiliary electrodes (SE2) of FIG. 5a.

[0142] The 3-1 region (NDA21) may include unit regions (UA) and boundary regions (BA) between the unit regions (UA). The arrangement relationship between the unit regions (UA) and the boundary regions (BA) of the 3-1 region (NDA21) may be the same as the arrangement relationship between the unit regions (UA) and the boundary regions (BA) of the 2nd region (NDA1). In the unit regions (UA) of the 3-1 region (NDA21), light-emitting diodes (LED) or dummy light-emitting diodes (DED) are not arranged, and lenses (LS) and first openings (COP1) are not arranged.

[0143] Referring to FIG. 6b, the CMOS wafer (10) is schematically illustrated to include only a silicon substrate (101), a first insulating layer (123), and a second insulating layer (130). However, a scan driver may be formed in the 3-1 region (NDA21) of the CMOS wafer (10), and the scan driver may be a circuit including transistors similar to those illustrated in FIG. 4b.

[0144] A common wiring (CML) may be arranged on the second insulating layer (130) within the 3-1 region (NDA21). The common wiring (CML) within the 3-1 region (NDA21) may be electrically connected to a common electrode (CME). In addition, the common wiring (CML) may not only overlap the 3-1 region (NDA21), but may also extend to overlap the voltage transmission electrodes (VTE), as described below with reference to FIG. 7b.

[0145] The common wiring (CML) may include a first conductive structure (CS1) having the same laminated structure as the first electrode structure (ES1) of FIG. 4B. The common wiring (CML) may further include an insulating structure (IC) disposed on an upper surface of the first conductive structure (CS1). The insulating structure (IC) may include a first insulating pattern layer (IC1) formed through the same process as the second side insulating layer (SI2) and a second insulating pattern layer (IC2) formed through the same process as the first side insulating layer (SI1). The second insulating pattern layer (IC2) may or may not be in contact with the side surface of the first conductive structure (CS1). An opening (IC-OP) may be defined in the insulating structure (IC), and in one embodiment of the present invention, the insulating structure (IC) may be omitted.

[0146] The common wiring (CML) may further include a second conductive structure (CS2) disposed on the first conductive structure (CS1) and electrically connected to the first conductive structure (CS1). The second conductive structure (CS2) may be connected to the side surface of the first conductive structure (CS1) and may be connected to the top surface of the first conductive structure (CS1) through an opening (IC-OP) of an insulating structure (IC). The second conductive structure (CS2) may be formed through the same process as the side reflection layer (SRL) of FIG. 4b and may include the same material. The second conductive structure (CS2) may be spaced apart from the side reflection layer (SRL) of FIGS. 4b and 5b and may be electrically insulated from it.

[0147] Although the present embodiment exemplarily illustrates a common wiring (CML) including a first conductive structure (CS1), an insulating structure (IC), and a second conductive structure (CS2), the common wiring (CML) is not limited thereto. As described above, the common wiring (CML) may include only the first conductive structure (CS1), or may include the first conductive structure (CS1) and an insulating structure (IC).

[0148] The common wiring (CML) may be connected to the common electrode (CME) through the auxiliary electrode (SE) of FIG. 3b, for example, the second auxiliary electrodes (SE2) of FIG. 6b. The second auxiliary electrodes (SE2) are respectively disposed in the second trenches (TC2). Through holes (TH) extending from one region of the second trenches (TC2) may be defined in the planarization layer (140). The second auxiliary electrodes (SE2) may be connected to the common wiring (CML) through the through holes (TH).

[0149] Although FIGS. 6A and 6B illustrate that the through holes (TH) are formed to overlap the second trenches (TC2), the present invention is not limited thereto. The through holes (TH) may further be formed to overlap the first trenches (TC1) of FIG. 6A, and their number, shape, and position are not particularly limited.

[0150]

[0151] Fig. 7a is an enlarged plan view of a portion (A4) of the 3-2 area (NDA22) of Fig. 3a. Fig. 7b is a cross-sectional view corresponding to IV-IV' of Fig. 7a. Hereinafter, the differences from the portion (A3) of the 3-1 area (NDA21) described above will be described.

[0152] FIG. 7A illustrates a portion (A4) of the 3-2 region (NDA22) of FIG. 3A in which pad electrodes (PD) are arranged. Within the 3-2 region (NDA22), first auxiliary electrodes (SE1) are arranged in each of the first trenches (TC1), and second auxiliary electrodes (SE2) are arranged in each of the second trenches (TC2). The first auxiliary electrodes (SE1) extend from the first auxiliary electrodes (SE1) of FIG. 6A, and the second auxiliary electrodes (SE2) extend from the second auxiliary electrodes (SE2) of FIG. 6A. The 3-2 region (NDA22) may include unit regions (UA) and boundary regions (BA) between the unit regions (UA). The pad electrodes (PD) may overlap some of the unit regions (UA) and some of the boundary regions (BA).

[0153] The region where the voltage transfer electrodes (VTEs) overlap in the 3-2 region (NDA22) of FIG. 3a may have the same structure as the partial region (A4) illustrated in FIGS. 7a and 7b, except for the pad electrode (PD). However, the region where the voltage transfer electrodes (VTEs) do not overlap in the 3-2 region (NDA22) may have a different structure from the partial region (A4) illustrated in FIGS. 7a and 7b. In the region where the voltage transfer electrodes (VTEs) do not overlap in the 3-2 region (NDA22), the first auxiliary electrodes (SE1), the first trenches (TC1), the second auxiliary electrodes (SE2), and the second trenches (TC2) may not be disposed.

[0154] The common wiring (CML) of FIG. 7b extends from the 3-1 region (NDA21) of FIGS. 6a and 6b along the voltage transmission electrode (VTE) to the 3-2 region (NDA22). The common wiring (CML) can be connected to the voltage transmission electrode (VTE) via the second auxiliary electrodes (SE2). The second auxiliary electrodes (SE2) arranged in the second trenches (TC2) can be connected to the common wiring (CML) via the through holes (TH) defined in the planarization layer (140).

[0155] An opening (150-OP) is defined in the passivation layer (150) to expose a portion of a voltage transmission electrode (VTE) (hereinafter, a connection area). A pad electrode (PD) disposed on the passivation layer (150) is connected to the connection area of ​​the voltage transmission electrode (VTE) through the opening (150-OP).

[0156]

[0157] Fig. 8a is a cross-sectional view corresponding to a second region (NDA1) according to one embodiment of the present invention. Fig. 8b is a cross-sectional view corresponding to a third-second region (NDA22). Fig. 8a is a cross-sectional view corresponding to Fig. 5b, and Fig. 8b is a cross-sectional view corresponding to Fig. 7b.

[0158] Although not shown separately, the trench (TC2) formed in the first area (DA) of FIG. 4b can also be deformed like the trench (TC2) of FIG. 8a, and the trench (TC2) formed in the third-first area (NDA21) of FIG. 7b can also be deformed like the trench (TC2) of FIG. 8b.

[0159] The trench (TC2) of FIG. 8a is formed deeper than the trench (TC2) illustrated in FIGS. 4b and 5b. Accordingly, a portion of the side reflection layer (SRL) may be exposed by the trench (TC2) of FIG. 8a. The second auxiliary electrodes (SE2) may contact the side reflection layer (SRL).

[0160] The trench (TC2) of Fig. 8b is also formed deeper than the trench (TC2) illustrated in Figs. 6b and 7b. Accordingly, the through holes (TH) additionally formed in some areas of Figs. 6b and 7b can be omitted. In addition, the contact area between the second auxiliary electrodes (SE2) and the common wiring (CML) can be further increased.

[0161]

[0162] FIGS. 9A to 9S are cross-sectional views illustrating a manufacturing process of a display device according to one embodiment of the present invention. FIGS. 9A to 9S illustrate FIGS. 4B, 5B, 6B, and 7B sequentially in one drawing, but it is obvious that the first area (DA), the second area (NDA1), the third-first area (NDA21), and the third-second area (NDA22) may be discontinuous.

[0163] As illustrated in Fig. 9a, a CMOS wafer (10) is provided. The CMOS wafer (10) includes a silicon substrate (101), a first insulating layer (123), and a second insulating layer (130). The CMOS wafer (10) of Fig. 9a is illustrated simply compared to the CMOS wafer (10) of Fig. 4b, except for the second contact electrode (135). The second contact electrode (135) positioned within the second contact hole (CH2) can be formed through a damascene process. The manufacturing process of the CMOS wafer (10) is not particularly limited.

[0164] As illustrated in FIG. 9a, a first conductive layer (CL1) may be disposed on a second insulating layer (130) of a CMOS wafer (10). The first conductive layer (CL1) may be formed through a deposition process, and the type of deposition process used to form the first conductive layer (CL1) is not particularly limited. The first conductive layer (CL1) may include at least one metal layer. The first conductive layer (CL1) may include the first metal layer (ML1) of FIG. 4e, or may include the first and second metal layers (ML1, ML2). The first conductive layer (CL1) may further include a barrier layer disposed under at least one of the metal layers. The barrier layer may be the third barrier layer (BRL3) of FIG. 4e or the third barrier layer (BRL30) of FIG. 4f.

[0165] In this embodiment, the first conductive layer (CL1) is described as including the third barrier layer (BRL3) of FIG. 4e and the first and second metal layers (ML1, ML2) disposed on the third barrier layer (BRL3).

[0166] Next, as illustrated in Fig. 9b, a semiconductor substrate (SUB-S) is provided. Fig. 9b illustrates a semiconductor substrate (SUB-S) aligned on a CMOS wafer (10).

[0167] The semiconductor substrate (SUB-S) may include a silicon substrate (201), a buffer layer (202) disposed under the silicon substrate (201), a semiconductor bonding layer (203) disposed under the buffer layer (202), and a second conductive layer (CL2) disposed under the semiconductor bonding layer (203). The buffer layer (202) may be an epitaxial layer grown from the silicon substrate (201).

[0168] The semiconductor junction layer (203) may include an active layer (ACT), a p-type semiconductor layer (SP) disposed on one side of the active layer (ACT), and an n-type semiconductor layer (SN) disposed on the other side of the active layer (ACT). In the present embodiment, the semiconductor junction layer (203) may have the same laminated structure as the semiconductor junction structure (SJS) described with reference to FIG. 4g. That is, the semiconductor junction layer (203) may include an n-type semiconductor layer (SN), an active layer (ACT) disposed under the n-type semiconductor layer (SN), and a p-type semiconductor layer (SP) disposed under the active layer (ACT). The n-type semiconductor layer (SN) may have a greater thickness than the n-type semiconductor layer (SN) illustrated in FIG. 4g. This is because, as described below, a portion thereof is removed during the grinding process.

[0169] The second conductive layer (CL2) may include a transparent conductive oxide layer, a reflective layer disposed on a lower side of the transparent conductive oxide layer, and at least one metal layer disposed on an upper side of the reflective layer. The second conductive layer (CL2) may include at least one of the first transparent conductive oxide layer (TCO1), the reflective layer (RL), and the second and third metal layers (ML2, ML3) of FIG. 4e. The second conductive layer (CL2) may include the third metal layer (ML3) or may include the second and third metal layers (ML2, ML3).

[0170] The second conductive layer (CL2) may further include a barrier layer. The barrier layer may include the first barrier layer (BRL1) of FIG. 4e or the first barrier layer (BRL10) of FIG. 4f. The barrier layer may further include the second barrier layer (BRL2) of FIG. 4e, or may only include the second barrier layer (BRL2) of FIG. 4e.

[0171] In this embodiment, the second conductive layer (CL2) is described as including the first transparent conductive oxide layer (TCO1) of FIG. 4e, the second barrier layer (BRL2) under the first transparent conductive oxide layer (TCO1), the reflective layer (RL) under the second barrier layer (BRL2), the first barrier layer (BRL1) under the reflective layer (RL), and the third metal layer (ML3) under the first barrier layer (BRL1).

[0172] Next, as illustrated in FIG. 9c, a semiconductor substrate (SUB-S) is bonded onto a CMOS wafer (10). The second conductive layer (CL2) can be bonded to the first conductive layer (CL1) through a high-temperature and high-pressure process. In this embodiment, the second metal layer (ML2) of FIG. 4e and the third metal layer (ML3) of FIG. 4e can be bonded. Accordingly, a first electrode layer (ESL1) having the same laminated structure as the first electrode structure (ES1) described in FIG. 4e can be formed. From FIG. 9d onwards, the first electrode layer (ESL1) is illustrated as a single layer.

[0173] According to one embodiment of the present invention, the uppermost metal layer of the first conductive layer (CL1) and the lowermost metal layer of the second conductive layer (CL2) include the same metal, and the uppermost metal layer and the lowermost metal layer can form a single metal layer after the bonding process of the first conductive layer (CL1) and the second conductive layer (CL2). For example, the second metal layer (ML2) of FIG. 4e can be a single metal layer formed after the bonding process. The first conductive layer (CL1) of FIG. 7c may include the third barrier layer (BRL3) of FIG. 4e, the first metal layer (ML1) on the third barrier layer (BRL3), and the uppermost metal layer disposed on the first metal layer (ML1), and the second conductive layer (CL2) of FIG. 7c may include the first transparent conductive oxide layer (TCO1) of FIG. 4e, the second barrier layer (BRL2) under the first transparent conductive oxide layer (TCO1), the reflective layer (RL) under the second barrier layer (BRL2), the first barrier layer (BRL1) under the reflective layer (RL), the third metal layer (ML3) under the first barrier layer (BRL1), and the lowermost metal layer disposed under the third metal layer (ML3). Through the bonding process of FIG. 9c, the uppermost metal layer of the first conductive layer (CL1) and the lowermost metal layer of the second conductive layer (CL2) can form a single metal layer, the second metal layer (ML2) of FIG. 4e. As described above, this corresponds to the case where the uppermost metal layer of the first conductive layer (CL1) and the lowermost metal layer of the second conductive layer (CL2) include the same metal. The uppermost metal layer of the first conductive layer (CL1) and the lowermost metal layer of the second conductive layer (CL2) can include any one of gold (Au), copper (Cu), silver (Ag), tin (Sn), titanium (Ti), zirconium (Zr), and tantalum (Ta).

[0174] A method for forming a first electrode layer (ESL1) having the same structure as the first electrode structure (ES1) of FIG. 4f is briefly described as follows. The first conductive layer (CL1) of FIGS. 9a to 9c includes the third barrier layer (BRL30) of FIG. 4f, and the first metal layer on the upper side of the third barrier layer (BRL30). The second conductive layer (CL2) of FIGS. 9b and 9c includes the first transparent conductive oxide layer (TCO1) of FIG. 4f, the second barrier layer (BRL2) under the first transparent conductive oxide layer (TCO1), the reflective layer (RL) under the second barrier layer (BRL2), the first barrier layer (BRL10) under the reflective layer (RL), and the second metal layer under the first barrier layer (BRL10).

[0175] When the first conductive layer (CL1) and the second conductive layer (CL2) are combined as shown in FIG. 9c, a first electrode layer (ESL1) having the same laminated structure as the first electrode structure (ES1) of FIG. 4f can be formed. At this time, if the first metal layer and the second metal layer include the same metal, a single-layer metal layer (ML) including a single metal can be formed, as shown in FIG. 4f. If the first metal layer and the second metal layer include different metals, the metal of the first metal layer and the metal of the second metal layer can diffuse into each other to form an alloy layer.

[0176] Next, as illustrated in FIG. 9d, a portion of the semiconductor substrate (SUB-S) of FIG. 9c is removed to form a semiconductor junction structure layer (SJSL). A semiconductor grinding process may be performed. The silicon substrate (201) and the buffer layer (202) of FIG. 9c may be completely removed, and a portion of the semiconductor junction layer (203) may be removed. FIG. 9d illustrates a semiconductor junction structure layer (SJSL) formed by removing a portion of the semiconductor junction layer (203).

[0177] The semiconductor junction structure layer (SJSL) may have the same laminated structure as the semiconductor junction structure (SJS) of FIG. 4f. The corresponding layers of the semiconductor junction structure layer (SJSL) and the semiconductor junction structure (SJS) may have the same thickness.

[0178] At this time, in a non-illustrated portion of the region (hereinafter, referred to as the alignment key region), both the semiconductor joint structure layer (SJSL) and the first electrode layer (ESL1) can be removed. The alignment key formed on the CMOS wafer (10) can be exposed to the outside through the alignment key region. The alignment key can be used in the photolithography process performed in the subsequent process.

[0179] Next, as illustrated in FIG. 9e, a second electrode layer (ESL2) can be formed on the semiconductor junction structure layer (SJSL). The second electrode layer (ESL2) can have the same laminated structure as the second electrode structure (ES2) described in FIG. 4g. A transparent conductive oxide layer of the second electrode layer (ESL2) can be formed through a deposition process. The second electrode layer (ESL2) can further include a metal layer disposed under the transparent conductive oxide layer. A metal layer in contact with the semiconductor junction structure layer (SJSL) can be formed through a first deposition process. A transparent conductive oxide layer can be directly formed on the metal layer through a second deposition process.

[0180] According to one embodiment of the present invention, a second electrode layer (ESL2) may be formed in advance between the buffer layer (202) and the semiconductor bonding layer (203). At this time, the process of removing a portion of the semiconductor bonding layer (203) of FIG. 9d may not be performed, and only the silicon substrate (201) and the buffer layer (202) may be removed.

[0181] Next, as illustrated in FIG. 9f, the semiconductor junction structure layer (SJSL) and the second electrode layer (ESL2) can be patterned. After forming a hard mask (MSK) through a photolithography process, the semiconductor junction structure layer (SJSL) and the second electrode layer (ESL2) of FIG. 9e can be etched using the hard mask (MSK). The hard mask (MSK) can include an insulating pattern. From the semiconductor junction structure layer (SJSL) of FIG. 9e, semiconductor junction structures (SJS) overlapping the first region (DA) and the second region (NDA1) are formed. From the second electrode layer (ESL2) of FIG. 9e, second electrode structures (ES2) overlapping the semiconductor junction structures (SJS) are formed. In the third region (NDA2), the semiconductor junction structure layer (SJSL) and the second electrode layer (ESL2) are removed.

[0182] During the etching process, the side surfaces of the semiconductor junction structures (SJS) and the second electrode structures (ES2) may be damaged, but the damage occurring to the side surfaces of the semiconductor junction structures (SJS) and the second electrode structures (ES2) can be repaired through a wet treatment process.

[0183] Next, as illustrated in FIG. 9g, after removing the hard mask (MSK) of FIG. 9f, a first insulating layer (SI-1) is formed on the CMOS wafer (10). The first insulating layer (SI-1) is an inorganic layer and can be formed through an inorganic deposition process. The first insulating layer (SI-1) is disposed on the first electrode layer (ESL1), surrounds the side surfaces of the semiconductor junction structures (SJS) and the second electrode structures (ES2), and is disposed on the upper surface of the second electrode structures (ES2).

[0184] Next, as illustrated in FIG. 9h, the first insulating layer (SI-1) and the first electrode layer (ESL1) are patterned. Accordingly, light-emitting diodes (LEDs) overlapping the first region (DA) and dummy light-emitting diodes (DEDs) overlapping the second region (NDA1) are formed.

[0185] A photolithography process may be performed for the above patterning. The second side insulating layer (SI2) described with reference to FIG. 4b is formed from the first insulating layer (SI-1), and first electrode structures (ES1) overlapping the first region (DA) and the second region (NDA1) are formed from the first electrode layer (ESL1). If the step of forming the first insulating layer (SI-1) of FIG. 9g is omitted, the second side insulating layer (SI2) is not formed.

[0186] A first conductive structure (CS1) is formed from the first electrode layer (ESL1) and overlapping the third region (NDA2). The first conductive structure (CS1) may have the same laminated structure as the first electrode structure (ES1), as described with reference to FIGS. 6B and 7B. A first insulating pattern layer (IC1) is formed from the first insulating layer (SI-1) of FIG. 9G and disposed on the first conductive structure (CS1). The first insulating pattern layer (IC1) may cover the upper surface of the first conductive structure (CS1).

[0187] Due to a process error between the photolithography process of FIG. 9h and the etching process using the hard mask (MSK) of FIG. 9f, the first electrode structures (ES1) having a larger area than the second electrode structures (ES2) may be formed. In the photolithography process of FIG. 9h, the second side insulating layer (SI2) is protected by a photoresist (not shown). The first electrode structures (ES1) are formed to have a larger area to protect the second side insulating layer (SI2) and the side surfaces of the semiconductor junction structures (SJS) protected by the second side insulating layer (SI2). Accordingly, the second side insulating layer (SI2) may be disposed on a portion of the upper surface of the first electrode structures (ES1).

[0188] Next, as illustrated in Fig. 9i, a second insulating layer (SI-2) is formed on a CMOS wafer (10). The second insulating layer (SI-2) is an inorganic layer and can be formed through a deposition process of an inorganic material.

[0189] The second insulating layer (SI-2) is disposed on the second side insulating layer (SI2) and covers the side surfaces of the first electrode structures (ES1). The second insulating layer (SI-2) covers the side surfaces of the first conductive structure (CS1) and is disposed on the first insulating pattern layer (IC1). The second insulating layer (SI-2) is disposed on a portion of the upper surface of the CMOS wafer (10).

[0190] Next, as illustrated in FIG. 9j, the second insulating layer (SI-2) is patterned. The processes of FIGS. 9i and 9j can be performed within a single photolithography process.

[0191] The first side insulating layer (SI1) of FIG. 9j can be formed from the second insulating layer (SI-2) of FIG. 9i. The first side insulating layer (SI1) having an integral shape within the first region (DA) and the second region (NDA1) is illustrated, but a plurality of separate first side insulating layers (SI1) may be formed for each light-emitting diode (LED) and each dummy light-emitting diode (DED).

[0192] A second insulating pattern layer (IC2) may be disposed on the first insulating pattern layer (IC1) within the third region (NDA2). The laminated structure of the first insulating pattern layer (IC1) and the second insulating pattern layer (IC2) may be defined as the insulating structure (IC) of FIGS. 6b and 7b. An opening (IC-OP) exposing the upper surface of the first conductive structure (CS1) is defined in the insulating structure (IC). The shape of the opening (IC-OP) is not particularly limited. As in FIG. 9j, both edges of the first conductive structure (CS1) may also be exposed from the insulating structure (IC).

[0193] Next, as illustrated in FIG. 9k, a metal layer (ML-R) is formed on a CMOS wafer (10). The metal layer (ML-R) is formed through a deposition process. The metal layer (ML-R) is formed to overlap the first region (DA), the second region (NDA1), and the third region (NDA2). The metal layer (ML-R) may include gold (Au), copper (Cu), silver (Ag), titanium (Ti), or aluminum (Al).

[0194] As illustrated in FIG. 9l, a side reflection layer (SRL) and a second conductive structure (CS2) can be formed from a metal layer (ML-R) through a photolithography process.

[0195] A side reflection layer (SRL) can be formed to overlap the first area (DA) and the second area (NDA1). The side reflection layer (SRL) is disposed on the outer side of the first side insulating layer (SI1) and contacts the first side insulating layer (SI1). Although a plurality of side reflection layers (SRL) disposed on each of a plurality of second side insulating layers (SI2) are illustrated, in one embodiment of the present invention, the side reflection layers (SRL) may have an integral shape within the first area (DA) and the second area (NDA1).

[0196] When patterning the conductive layer (ML-R), a first opening (COP1) can be formed at the same time. The first opening (COP1) penetrates the first side insulating layer (SI1), the second side insulating layer (SI2), and the side reflective layer (SRL) of the light emitting diode (LED), and exposes a portion of the upper surface of the second electrode structure (ES2). The first opening (COP1) is not formed in the dummy light emitting diode (DED). In the wet etching process for forming the first opening (COP1), the transparent conductive oxide of the second electrode structure (ES2) can protect the semiconductor junction structure (SJS) disposed therebelow from the etchant.

[0197] A second conductive structure (CS2) can be formed to overlap the third region (NDA2). The second conductive structure (CS2) is disposed on the first conductive structure (CS1) and the insulating structure (IC), and contacts a portion of the first conductive structure (CS1) exposed from the insulating structure (IC). The second conductive structure (CS2) can be connected to the first conductive structure (CS1) at least through an opening (IC-OP). The stacked structure of the first conductive structure (CS1), the insulating structure (IC), and the second conductive structure (CS2) can be defined as a common wiring (CML) described with reference to FIGS. 6b and 7b.

[0198] As illustrated in FIG. 9m, a planarization layer (140) is formed in which a second trench (TC2) is defined. The planarization layer (140) of the organic layer is formed on a CMOS wafer (10) through an inkjet process or a coating process. Thereafter, a second trench (TC2) is formed in the planarization layer (140) through a first photolithography process. Although not illustrated separately, when forming the second trench (TC2), the first trench (TC1) illustrated in FIGS. 4a, 5a, 6a, and 7a may also be formed.

[0199] A through hole (TH) extending from the second trench (TC2) can be further formed through a secondary photolithography process. The through hole (TH) is formed in an area overlapping the common line (CML) of the third area (NDA2).

[0200] In one embodiment of the present invention, when the second trench (TC2) is formed deeper through the first photolithography process, the second trench (TC2) illustrated in FIGS. 8a and 8b is formed, and the second photolithography process for forming the through hole (TH) of FIG. 9m can be omitted.

[0201] As illustrated in FIG. 9n, a second auxiliary electrode (SE2) is formed in the second trench (TC2). When forming the second auxiliary electrode (SE2), the first auxiliary electrode (SE1) illustrated in FIGS. 4a, 5a, 6a, and 7a may also be formed.

[0202] A second auxiliary electrode (SE2) can be formed by a damascene process. A thin barrier layer is formed on a planarization layer (140) through a first deposition process, and then a metal layer is formed thicker than the barrier layer through a second deposition process. A metal layer having steps formed in the second trenches (TC2) and the surrounding area is formed. The barrier layer and the metal layer disposed on the planarization layer (140) are removed through a CMP process. Accordingly, a second auxiliary electrode (SE2) including a barrier layer (SE2-2) and a metal structure (SE2-1) disposed only on the inside of the second trench (TC2) can be formed.

[0203] Thereafter, as illustrated in FIG. 9o, second openings (COP2) are formed in the planarization layer (140). The second openings (COP2) are formed to correspond to the first openings (COP1), and the second electrode structure (ES2) is exposed to the outside. The second electrode structure (ES2) of the dummy light-emitting diode (DED) is not exposed to the outside. The second openings (COP2) having a larger diameter than the diameter of the first openings (COP1) are illustrated as an example, but are not limited thereto.

[0204] Next, as illustrated in FIG. 9p, a common electrode (CME) is formed on the planarization layer (140) to overlap the first region (DA), the second region (NDA1), and the third-first region (NDA21). A voltage transmission electrode (VTE) is formed on the planarization layer (140) to overlap the third-second region (NDA22).

[0205] A common electrode (CME) and a voltage transmission electrode (VTE) having an integral shape are formed through a photolithography process. The common electrode (CME) is electrically connected to a light emitting diode (LED) through a first opening (COP1) and a second opening (COP2). A transparent conductive oxide layer is formed on a planarization layer (140) through a deposition process and then patterned to form a common electrode (CME) and a voltage transmission electrode (VTE) having the shape illustrated in FIG. 3a.

[0206] Next, as illustrated in FIG. 9q, a passivation layer (150) covering a common electrode (CME) is formed on a planarization layer (140). The passivation layer (150) covers a voltage transmission electrode (VTE), and an opening (150-OP) exposing a connection area of ​​the voltage transmission electrode (VTE) is formed in the passivation layer (150).

[0207] Thereafter, as illustrated in FIG. 9r, a pad electrode (PD) connected to the connection area of ​​the voltage transmission electrode (VTE) is formed on the planarization layer (140). The pad electrode (PD) can be connected to the connection area of ​​the voltage transmission electrode (VTE) through an opening (150-OP).

[0208] In addition, as illustrated in FIG. 9s, lenses (LS) can be formed to overlap light-emitting diodes (LEDs) on the planarization layer (140). The lenses (LS) can be formed by patterning an organic layer through a photolithography process, or by dropping an organic material through an inkjet process and then drying it.

[0209]

[0210] FIG. 10a is a plan view illustrating the arrangement relationship of a common electrode (CME), a voltage transmission electrode (VTE), and an auxiliary electrode (SE) according to an embodiment of the present invention. FIG. 10b is a plan view illustrating an enlarged portion of a portion of a 3-2 region (NDA22) according to an embodiment of the present invention. FIG. 10c and FIG. 10d are cross-sectional views corresponding to V-V' of FIG. 10b. FIG. 10e is a plan view illustrating an enlarged portion of a portion of a 3-2 region (NDA21) according to an embodiment of the present invention. FIG. 10f is a plan view illustrating the arrangement relationship of a common electrode (CME) and an auxiliary electrode (SE) according to an embodiment of the present invention.

[0211] Fig. 10a corresponds to Fig. 3b. According to Fig. 10a, the auxiliary electrode (SE) may include a cut region (SE-C). In the present embodiment, some of the second auxiliary electrodes (SE2) are shown as being cut. The cut region (SE-C) of the auxiliary electrode (SE) may overlap the voltage transmission electrode (VTE).

[0212] The auxiliary electrode (SE) may include a first portion (SE-1) overlapping the common electrode (CME) and a second portion (SE-2) overlapping the voltage transfer electrode (VTE) and the pad electrode (PD) of Fig. 3a. The pad electrode (PD) of Fig. 3a does not overlap the first portion (SE-1). The first portion (SE-1) and the second portion (SE-2) may be spaced apart from each other in a plane.

[0213] Fig. 10b is an enlarged view of the terminal region of the voltage transfer electrode (VTE) of Fig. 10a. A pad electrode (PD) overlapping the second portion (SE-2) is shown. As described above, the first portion (SE-1) of the auxiliary electrode (SE) and the second portion (SE-2) of the auxiliary electrode (SE) are spaced apart from each other. The edge (or terminal) of the second portion (SE-2) of the auxiliary electrode (SE) is shown as being aligned on a plane with the edge of the voltage transfer electrode (VTE), but is not limited thereto.

[0214] Referring to FIG. 10c, a common wiring (CML) may also have a cut region (CML-C) defined. The cut region (CML-C) of the common wiring (CML) may be defined to be substantially the same as the cut region (SE-C) of the auxiliary electrode (SE), but is not limited thereto. The common wiring (CML) includes a first common portion (CML-1) and a second common portion (CML-2) spaced apart from the first common portion (CML-1). The first common portion (CML-1) is disposed below the first portion (SE-1) of the auxiliary electrode (SE) and is electrically connected to the first portion (SE-1) of the auxiliary electrode (SE). The second common portion (CML-2) is disposed below the second portion (SE-2) of the auxiliary electrode (SE) and is electrically connected to the second portion (SE-2) of the auxiliary electrode (SE).

[0215] Second contact electrodes (135) and a connection electrode (125-1) may be arranged to electrically connect the pad electrode (PD) and the common electrode (CME). The connection electrode (125-1) may be formed through the same process as the first contact electrode (125) of FIG. 4B and may include the same laminated structure and the same material. The connection electrode (125-1) overlaps the cut region (SE-C) of the auxiliary electrode (SE) and may replace the functions of the cut auxiliary electrode (SE) and the cut common wiring (CML). That is, the power voltage applied through the pad electrode (PD) may pass through the connection electrode (125-1) to the common electrode (CME) of FIG. 10A. Referring to FIG. 10C, the power voltage may be transmitted in parallel to the common electrode (CME) of FIG. 10A through the voltage transmission electrode (VTE).

[0216] Referring to FIG. 10d, a cutting area (VTE-C) corresponding to the cutting area (SE-C) of the auxiliary electrode (SE) may also be defined for the voltage transmission electrode (VTE). The width and length of the cutting area (SE-C) of the auxiliary electrode (SE) and the cutting area (VTE-C) of the voltage transmission electrode (VTE) are not limited to being the same. At this time, the pad electrode (PD) and the common electrode (CME) may be electrically connected only by the path defined by the second contact electrodes (135) and the connection electrode (125-1). In one embodiment of the present invention, the first part (VTE-1) of the voltage transmission electrode (VTE) may be omitted. The second part (SE-2) of the voltage transmission electrode (VTE) may correspond to the first conductive layer of the pad electrode (PD).

[0217] Referring to FIG. 10e, the edge (or end) of the second portion (SE-2) of the auxiliary electrode (SE) may be non-aligned on the plane with the edge of the voltage transmission electrode (VTE). The ends of the second portion (SE-2) of the first auxiliary electrode (SE1) and the second portion (SE-2) of the second auxiliary electrode (SE2) may be disposed on the inside of the voltage transmission electrode (VTE) on the plane.

[0218] Referring to FIG. 10f, the voltage transfer electrode (VTE) may be omitted compared to the display device described with reference to FIGS. 10a to 10d. Since the voltage transfer electrode (VTE) is omitted, the first portion (SE-1) and the second portion (SE-2) of FIG. 10c may be electrically connected only by the path defined by the second contact electrodes (135) and the connection electrode (125-1).

[0219]

[0220] Fig. 11a is a cross-sectional view of a display device according to an embodiment of the present invention. Fig. 11b is a cross-sectional view of a light emitting diode (LED-1) according to an embodiment of the present invention. Fig. 11c is a cross-sectional view illustrating in detail a first electrode structure (ES10) according to an embodiment of the present invention.

[0221] Fig. 11a corresponds to Fig. 4b, and the same reference numerals are used for the same components among those illustrated in Fig. 4b and Fig. 11a. Hereinafter, the different components among those illustrated in Fig. 4b and Fig. 11a will be described.

[0222] In Fig. 11a, an inverted structure light-emitting diode (LED-1) can be applied. In this embodiment, the first electrode structure (ES10) is described as a cathode (or cathode structure), and the second electrode structure (ES20) is described as an anode (or anode structure).

[0223] As illustrated in FIG. 11b, a semiconductor junction structure (SJS-1) is disposed on a first electrode structure (ES10), and the first electrode structure (ES10) is disposed on the semiconductor junction structure (SJS-1). The semiconductor junction structure (SJS-1) may include an n-type semiconductor layer (SN) disposed on the first electrode structure (ES10), an active layer (ACT) disposed on the n-type semiconductor layer (SN), and a p-type semiconductor layer (SP) disposed on the active layer (ACT). In one embodiment of the present invention, an electron blocking layer may be further disposed between the active layer (ACT) and the p-type semiconductor layer (SP). In one embodiment of the present invention, the light emitting diode (LED-1) may further include a clad layer or a TSBR layer.

[0224] The n-type semiconductor layer (SN) may include a first portion (SN-P1) having a larger diameter (or a transverse length in cross-section) and positioned closer to the first electrode structure (ES10) and a second portion (SN-P2) having a smaller diameter (or a transverse length in cross-section) and positioned further away from the first electrode structure (ES10). A step may be formed between the first portion (SN-P1) and the second portion (SN-P2). A side surface of the first portion (SN-P1) may be an inclined surface (ICS) inclined to the first electrode structure (ES10), and a side surface of the second portion (SN-P2) may be substantially perpendicular to the first electrode structure (ES10).

[0225] The second electrode structure (ES20) may include a transparent conductive oxide layer. The second electrode structure (ES20) may include at least one of ITO (indium tin oxide), IZO (indium zinc oxide), ZnO (zinc oxide), ZTO (zinc tin oxide), and IGZO (indium gallium zinc oxide).

[0226] The first electrode structure (ES10) may have the laminated structure of FIG. 11C. Compared to the laminated structure of FIG. 4E, the first transparent conductive oxide layer (TCO1) and the second barrier layer (BRL2) may be omitted. The first electrode structure (ES10) may include a metal layer (ML-C) disposed on the first barrier layer (BRL1). The metal layer (ML-C) has the function of the reflective layer (RL) of FIG. 4E and the function of an electron injection layer. The metal layer (ML-C) may have a multilayer structure and may include a first metal layer corresponding to a reflective layer. The metal layer (ML-C) may further include a second metal layer having a lower work function than the reflective layer. The metal layer (ML-C) may include a magnesium alloy or an aluminum alloy. In one embodiment of the present invention, the first electrode structure (ES10) may omit the first transparent conductive oxide layer (TCO1) and the second barrier layer (BRL2) compared to the laminated structure of FIG. 4F. Additionally, the metal layer (ML-C) described above can be placed in place of the reflective layer (RL).

[0227] Again, referring to FIG. 11a, the second side insulating layer (SI2) may contact a side surface of a portion of the semiconductor junction structure (SJS-1) and a side surface of the second electrode structure (ES20). The second side insulating layer (SI2) may contact side surfaces of the p-type semiconductor layer (SP), the active layer (ACT), and the second portion (SN-P2), and the second side insulating layer (SI2) may expose the inclined surface (ICS) described in FIG. 11b. The second side insulating layer (SI2) may be further disposed on a portion of the upper surface of the second electrode structure (ES20).

[0228] A first side insulating layer (SI1) is disposed on the outer side of the second side insulating layer (SI2). The first side insulating layer (SI1) can contact the inclined surface (ICS). A first opening (COP1) is defined in the first side insulating layer (SI1) and the second side insulating layer (SI2).

[0229] A side reflective layer (SRL) is disposed on the outer side of the first side insulating layer (SI1). In the present embodiment, the side reflective layer (SRL) is illustrated as being disposed continuously on adjacent light-emitting diodes (LED-1), but is not limited thereto. As illustrated in Fig. 4b, the side reflective layer (SRL) may be separated and spaced apart from the boundary area (BA). In the present embodiment, unlike the first side insulating layer (SI1), the side reflective layer (SRL) is not disposed on the upper surface of the second electrode structure (ES20), but is not limited thereto.

[0230] According to the present embodiment, unlike in FIG. 4e, the planarization layer (140) is omitted. The boundary area (BA) is defined by the light-emitting diodes (LED-1). The area where the light-emitting diodes (LED-1) are not arranged or spaced apart corresponds to the boundary area (BA). For example, when the light-emitting diodes (LED-1) are arranged in a matrix form, the boundary area (BA) between them may have a grid shape on a plane. FIG. 11a illustrates the boundary area (BA) based on the side surface of the first electrode structure (ES10).

[0231] The auxiliary electrode (SE) arranged in the boundary area (BA) may have a grid shape as illustrated in FIG. 3b. FIG. 11a illustrates second auxiliary electrodes (SE2), which are part of the auxiliary electrode (SE). The second auxiliary electrodes (SE2) may include a metal structure (SE2-1) and a barrier layer (SE2-2) arranged between the metal structure (SE2-1) and the second trench (TC2). Since the second auxiliary electrodes (SE2) are not formed in the trench (TC2) of FIG. 4b but are arranged in the area between the light-emitting diodes (LED-1), they may have different widths depending on the area in the cross-section.

[0232] During the manufacturing process, a planarization process, such as a grinding process, is performed, thereby providing a flat upper surface for the side reflective layer (SRL) and the auxiliary electrode (SE). A portion of the first side insulating layer (SI1) may also be removed during the planarization process. A common electrode (CME) is disposed on the upper surface provided by the side reflective layer (SRL) and the auxiliary electrode (SE), and may be electrically connected to the second electrode structure (ES20) through the first opening (COP1).

[0233]

[0234] Although the present invention has been described with reference to the above embodiments, those skilled in the art will understand that various modifications and changes can be made to the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. Furthermore, the embodiments disclosed in the present invention are not intended to limit the technical idea of ​​the present invention, and all technical ideas falling within the scope of the following claims and equivalents thereof should be construed as being included within the scope of the rights of the present invention.

[0235] A variety of electronic devices are being developed, including VR (Virtual Reality) electronic devices, AR (Augemented Reality) electronic devices, and MR (Mixed Reality) electronic devices. These electronic devices include high-resolution displays. The present invention provides a high-resolution display device that can be applied to the aforementioned electronic devices.

Claims

1. CMOS (complementary metal oxide semiconductor) wafer; and A plurality of light-emitting diodes are disposed on the CMOS wafer and are disposed within a first region of the CMOS wafer on a plane, Each of the above plurality of light-emitting diodes, First electrode structure; A light-emitting layer disposed on the first electrode structure; and Including a second electrode structure disposed on the above light-emitting layer, The above first electrode structure, metal layer; a reflective layer disposed on the metal layer; and A display device comprising a first transparent conductive oxide layer disposed on the reflective layer.

2. In paragraph 1, The above metal layer, A display device comprising at least one of gold (Au), copper (Cu), silver (Ag), tin (Sn), titanium (Ti), zirconium (Zr), and tantalum (Ta), or an alloy of at least two of these metals.

3. In paragraph 1, The above metal layer, Comprising a first metal layer and a second metal layer disposed on the first metal layer, A display device wherein the first metal layer includes one of gold (Au), copper (Cu), silver (Ag), tin (Sn), titanium (Ti), zirconium (Zr), and tantalum (Ta), and the second metal layer includes another one of gold (Au), copper (Cu), silver (Ag), tin (Sn), titanium (Ti), zirconium (Zr), and tantalum (Ta).

4. In paragraph 3, The above metal layer, Further comprising a third metal layer disposed on the second metal layer, A display device wherein the third metal layer includes one of gold (Au), copper (Cu), silver (Ag), tin (Sn), titanium (Ti), zirconium (Zr), and tantalum (Ta), and includes a metal different from the second metal layer.

5. In paragraph 1, The above first electrode structure, a first barrier layer disposed between the metal layer and the reflective layer; and Further comprising a second barrier layer disposed between the reflective layer and the first transparent conductive oxide layer, A display device, wherein each of the first barrier layer and the second barrier layer includes a nitride layer of a barrier metal.

6. In paragraph 5, The first barrier layer further includes a barrier metal layer disposed on at least one of the upper and lower sides of the nitride layer of the barrier metal, A display device wherein the barrier metal layer comprises titanium or tantalum.

7. In paragraph 1, The above first electrode structure, Further comprising a barrier layer disposed on the lower side of the metal layer, A display device wherein the barrier layer comprises titanium nitride or tantalum nitride.

8. In paragraph 1, The above CMOS wafer, A silicon substrate with defined source / drain regions; A gate disposed on the silicon substrate; A first insulating layer covering the gate and disposed on the silicon substrate; A first contact electrode electrically connected to the source / drain region through a first contact hole defined in the first insulating layer; A second insulating layer covering the first contact electrode and disposed on the first insulating layer; and A display device including a second contact electrode connected to the first contact electrode through a second contact hole penetrating the second insulating layer and electrically connected to the first metal structure.

9. In paragraph 8, The above second contact electrode is, A metal structure arranged inside the second contact hole; and A barrier layer is disposed between the side surface of the metal structure and the inner surface of the second contact hole, and is disposed between the lower surface of the metal structure and the upper surface of the first contact electrode exposed through the second contact hole. A display device wherein the barrier layer comprises a barrier metal layer and a nitride layer of the barrier metal.

10. In paragraph 8, The upper surface of the second contact electrode is a concave display device.

11. In paragraph 1, A display device wherein the second electrode structure includes a second transparent conductive oxide layer.

12. In paragraph 11, The above second electrode structure is a cathode of each of the plurality of light-emitting diodes, A display device wherein the second electrode structure further includes an electrode metal layer disposed between the second transparent conductive oxide layer and the semiconductor adhesive structure.

13. In paragraph 11, The above second electrode structure is an anode of each of the plurality of light-emitting diodes, The above first electrode structure is a cathode of each of the plurality of light-emitting diodes, The above light-emitting layer is, n-type semiconductor layer; An active layer disposed on the n-type semiconductor layer; and A p-type semiconductor layer is disposed on the above active layer, A display device, wherein the n-type semiconductor layer includes a first portion and a second portion having a smaller width in cross-section than the first portion, and a side surface of the second portion is an inclined surface inclined with respect to the first electrode structure.

14. In paragraph 1, A display device in which, on a plane, the light-emitting layer is arranged on the inner side of the first electrode structure.

15. In paragraph 1, A first side insulating layer disposed on the side of the first electrode structure, the side of the light-emitting layer, the side of the second electrode structure, and the upper surface of the second electrode structure; and A display device further comprising a side reflective layer disposed on the outer side of the first side insulating layer.

16. In paragraph 15, A display device wherein the side reflective layer corresponds to at least the side of the first electrode structure, the side of the light-emitting layer, and the side of the second electrode structure.

17. In paragraph 15, Further comprising a second side insulating layer, A portion of the upper surface of the first electrode structure is exposed from the light-emitting layer, The second side insulating layer is arranged on the inner side of the first side insulating layer and corresponds to the upper surface of the first electrode structure, the side surface of the light-emitting layer, and the side surface of the second electrode structure and the upper surface of the second electrode structure. A display device in which an opening is defined in the side reflective layer, the first side insulating layer, and the second side insulating layer to expose a portion of the upper surface of the second electrode structure.

18. In paragraph 17, Including more common electrodes, The above plurality of light-emitting diodes include a first light-emitting diode and a second light-emitting diode, The above common electrode electrically connects the second electrode structure of the first light-emitting diode and the second electrode structure of the second light-emitting diode, A display device in which the common electrode is bonded to a portion of the upper surface of the second electrode structure through the opening.

19. In paragraph 1, A planarizing layer disposed on the CMOS wafer and arranged to correspond to a side surface of the first electrode structure and a side surface of the light-emitting layer; and Further comprising a common electrode disposed on the above flattening layer and electrically connected to the second electrode structure of each of the plurality of light-emitting diodes, On a plane, the first region of the CMOS wafer includes a plurality of unit regions in which the plurality of light-emitting diodes are arranged and a boundary region between the plurality of unit regions, A display device in which the above-mentioned flattening layer overlaps the plurality of unit areas and the above-mentioned boundary area.

20. In paragraph 19, Including additional auxiliary electrodes, In the above flattening layer, a plurality of first trenches are defined that overlap the boundary area and extend in a first direction, and a plurality of second trenches are defined that overlap the boundary area and extend in a second direction intersecting the first direction. A display device in which the auxiliary electrode is arranged inside the first trenches and the second trenches and electrically connected to the common electrode.

21. In paragraph 20, The above auxiliary electrode is, a metal structure arranged inside the first trenches and the second trenches; and A display device comprising a barrier layer disposed between the metal structure and the first trenches and the second trenches.

22. In paragraph 1, Further comprising a plurality of dummy light-emitting diodes arranged within a second region outside the first region of the CMOS wafer on a plane, The above plurality of dummy light-emitting diodes are non-luminous display devices.

23. In paragraph 22, Further comprising a common electrode overlapping the first region and the second region and electrically connected to the second electrode structure of each of the plurality of light-emitting diodes, A display device in which the above common electrode is not electrically connected to the plurality of dummy light-emitting diodes.

24. In paragraph 22, A display device in which the above plurality of dummy light-emitting diodes have the same laminated structure as the above plurality of light-emitting diodes.

25. In paragraph 22, A common electrode overlapping the first region and the second region and electrically connected to the second electrode structure of each of the plurality of light-emitting diodes; A voltage transmitting electrode extending from the common electrode to a third region outside the second region of the CMOS wafer; A display device further comprising a pad electrode electrically connected to the voltage transmitting electrode in the third region.

26. In paragraph 25, Further comprising a passivation layer overlapping the first region, the second region, and the third region, covering the common electrode and the voltage transmission electrode, and having an opening defined therein that exposes a connection region of the voltage transmission electrode; A display device in which the above pad electrode is electrically connected to the connection area of ​​the voltage transmission electrode through the opening of the passivation layer.

27. In paragraph 25, A display device further comprising a common wiring disposed below the voltage transmitting electrode and electrically connected to the voltage transmitting electrode.

28. In paragraph 27, A display device in which the above common wiring includes a first conductive structure having the same laminated structure as the first electrode structure.

29. In paragraph 28, The above common wiring is, An insulating structure disposed on the upper surface of the first challenging structure; and A display device further comprising a second conductive structure disposed on at least the first conductive structure and electrically connected to the first conductive structure.

30. In paragraph 29, A planarization layer disposed between the common wiring and the voltage transmission electrode, and having a plurality of trenches defined therein; and A display device further comprising an auxiliary electrode arranged in the plurality of trenches to electrically connect the common wiring and the voltage transmission electrode.

31. In paragraph 30, A display device in which each of the auxiliary electrodes extends from one area of ​​the plurality of trenches and is electrically connected to the common wiring through through holes penetrating the planarization layer.

32. In paragraph 30, The third region of the CMOS wafer includes an inner region where the common electrode is arranged and an outer region where the common electrode is not arranged, The above auxiliary electrode is a display device that electrically connects the common electrode and the common wiring in the inner region.

33. In paragraph 1, A common electrode electrically connected to the second electrode structure of each of the plurality of light-emitting diodes and overlapping the first region; A pad electrode disposed in an outer region of the first region and receiving a power supply voltage; An auxiliary electrode including a first portion arranged on the lower side of the common electrode and electrically connected thereto and a second portion spaced apart from the first portion and arranged on the lower side of the pad electrode and electrically connected thereto; and Further comprising a common wiring including a first part disposed on the lower side of the first part of the auxiliary electrode and electrically connected to the second part and disposed on the lower side of the second part of the auxiliary electrode and electrically connected to the first part, A display device in which the above CMOS wafer includes a connection electrode electrically connected to each of the first portion of the common wiring and the second portion of the common wiring.

34. In paragraph 33, The above CMOS wafer, A silicon substrate with defined source / drain regions; A gate disposed on the silicon substrate; A first insulating layer covering the gate and disposed on the silicon substrate; A first contact electrode electrically connected to the source / drain region through a first contact hole defined in the first insulating layer; A second insulating layer covering the first contact electrode and disposed on the first insulating layer; and Further comprising a second contact electrode electrically connected to the first metal structure and connected to the first contact electrode through a second contact hole penetrating the second insulating layer; A display device in which the above-mentioned connecting electrode and the above-mentioned first contact electrode are arranged on the same layer.

35. In paragraph 1, A display device further comprising a plurality of lenses arranged on the plurality of light-emitting diodes, each corresponding to the plurality of light-emitting diodes.

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