Memory apparatus and operation method therefor, and memory system and operation method therefor

Abstract

Disclosed in the embodiments of the present application are a memory apparatus and an operation method therefor, and a memory system and an operation method therefor. The memory apparatus comprises: a storage unit array, which comprises a plurality of storage units, wherein a preset number of storage units form a code word; and a peripheral circuit, which is coupled to the storage unit array and is configured to: acquire a first result corresponding to the code word under a target reading voltage, wherein the first result represents the number of bits that have flipped between two reading results of the code word under the corresponding reading voltage and a voltage near the corresponding reading voltage; adjust the target reading voltage on the basis of the first result corresponding to the code word under the target reading voltage; acquire a first result corresponding to the code word under the adjusted reading voltage; and determine a valley voltage on the basis of a plurality of first results, wherein the valley voltage is used as a reading voltage for when a read operation is executed on the code word.

Description

Memory device and operating method thereof, memory system and operating method thereof Technical Field

[0001] The present application relates to, but is not limited to, a memory device and an operating method thereof, a memory system and an operating method thereof. Background Art

[0002] With the advancement of technology, the integrated circuit industry has seen a growing market. Within this industry, the processes and technologies for non-volatile memory devices have seen rapid advancements in recent years, with NAND memory being particularly widely used. NAND memory achieves data storage by capturing and storing charge within the gate dielectric layer of its memory cells. However, over time, the charge stored in the memory cells changes with age, repeated read operations, and temperature fluctuations, affecting the accuracy of data read from the cells.

[0003] Summary of the Invention

[0004] In a first aspect, an embodiment of the present application provides a memory device, comprising: a memory cell array comprising a plurality of memory cells, a preset number of the memory cells forming a codeword; a peripheral circuit coupled to the memory cell array and configured to: obtain a first result corresponding to at least one of the codewords at a target read voltage; the first result comprising a representation of the number of bits flipped in two read results of at least one of the codewords at a first read voltage and a second read voltage; the difference between the first read voltage and the second read voltage being less than a preset voltage; adjusting the target read voltage based on the first result corresponding to at least one of the codewords at the target read voltage; obtaining a first result corresponding to at least one of the codewords at the adjusted read voltage; and determining a valley voltage based on a plurality of the first results; the valley voltage being used as a read voltage when performing a read operation on at least one of the codewords.

[0005] In a second aspect, an embodiment of the present application provides a memory system, comprising: the memory device described in any one of the first aspects; and a memory controller coupled to the memory device and controlling the memory device.

[0006] In a third aspect, an embodiment of the present application provides a memory system, comprising: at least one memory device, the memory device comprising a plurality of memory cells, a preset number of the memory cells forming a codeword; a memory controller, coupled to the at least one memory device and configured to: obtain a first result corresponding to at least one of the codewords at a target read voltage; the first result comprises a representation of the number of bits flipped in two read results of at least one of the codewords at a first read voltage and a second read voltage; the difference between the first read voltage and the second read voltage is less than a preset voltage; adjusting the target read voltage based on the first result corresponding to at least one of the codewords at the target read voltage; obtaining a first result corresponding to at least one of the codewords at the adjusted read voltage; determining a valley voltage based on multiple first results; the valley voltage being used as a read voltage when performing a read operation on at least one of the codewords.

[0007] In a fourth aspect, an embodiment of the present application provides an operating method for a memory device, comprising: obtaining a first result corresponding to at least one codeword at a target read voltage; the first result includes a representation of the number of bits flipped in two read results of at least one of the codewords at a first read voltage and a second read voltage; the difference between the first read voltage and the second read voltage is less than a preset voltage; the memory device includes a memory cell array, the memory cell array includes a plurality of memory cells, and a preset number of the memory cells form at least one; adjusting the target read voltage according to the first result corresponding to at least one of the codewords at the target read voltage; obtaining a first result corresponding to at least one of the codewords at the adjusted read voltage; determining a valley voltage according to the plurality of first results; the valley voltage is used as a read voltage when performing a read operation on at least one of the codewords.

[0008] In a fifth aspect, an embodiment of the present application provides an operating method for a memory system, comprising: before performing a read operation on data stored in a memory device of the memory system, sending a first instruction, wherein the first instruction indicates obtaining a valley voltage; the valley voltage is obtained according to the operating method described in any one of the fourth aspects; performing a read operation on the data stored in the memory device according to the valley voltage; and performing an error correction code (ECC) decoding operation on the read result of the read operation.

[0009] In a sixth aspect, an embodiment of the present application provides an operating method of a memory system, comprising: obtaining a first result corresponding to a codeword at a target read voltage; the first result includes a representation of the number of bits flipped in two read results of at least one of the codewords at a first read voltage and a second read voltage; the difference between the first read voltage and the second read voltage is less than a preset voltage; the memory system comprises at least one memory device, the memory device comprises a plurality of storage cells, a preset number of the storage cells forming at least one of the codewords; adjusting the target read voltage according to the first result corresponding to at least one of the codewords at the target read voltage; obtaining a first result corresponding to at least one of the codewords at the adjusted read voltage; determining a valley voltage according to the plurality of first results; the valley voltage is used as a read voltage when performing a read operation on at least one of the codewords.

[0010] In a seventh aspect, the present application provides a memory device, comprising: a memory cell array comprising a plurality of memory cells, a preset number of the memory cells forming a codeword; a peripheral circuit coupled to the memory cell array, comprising control logic and a page buffer; the control logic being configured to: read stored data of at least one of the codewords at a target first read voltage to obtain a second result, and store the second result in a first latch of the page buffer; adjust the target first read voltage to obtain a second read voltage, read stored data of at least one of the codewords at the target second read voltage to obtain a third result, and store the third result in a second latch of the page buffer; the difference between the first read voltage and the second read voltage is less than a preset voltage; perform a logical operation on the second result and the third result to obtain a fourth result, and store the fourth result in the third latch of the page buffer; and count the number of bits in the fourth result that represent that the third result is flipped compared to the second result to obtain a first result.

[0011] In an eighth aspect, the present application provides an operating method for a memory device, the method comprising: reading the stored data of a codeword at a target first read voltage to obtain a second result, and storing the second result in a first latch of a page buffer; the memory device comprises a memory cell array and a page buffer, the memory cell array comprises a plurality of memory cells, and a preset number of the memory cells form a codeword; adjusting the target first read voltage to obtain a second read voltage, reading the stored data of at least one codeword at the target second read voltage to obtain a third result, and storing the third result in a second latch of the page buffer; the difference between the first read voltage and the second read voltage is less than a preset voltage; performing a logical operation on the second result and the third result to obtain a fourth result, and storing the fourth result in the third latch of the page buffer; and counting the number of bits in the fourth result that represent that the third result is flipped compared to the second result to obtain a first result. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar components or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments disclosed in this application and should not be construed as limiting the scope of this application.

[0013] FIG1 is a schematic diagram of an exemplary system having a memory system according to an embodiment of the present application;

[0014] FIG2 a is a schematic diagram of an exemplary memory card having a memory system according to an embodiment of the present application;

[0015] FIG2 b is a schematic diagram of an exemplary solid-state drive having a memory system according to an embodiment of the present application;

[0016] FIG3 a is a schematic diagram showing the distribution of storage cells of a three-dimensional NAND memory according to an embodiment of the present application;

[0017] FIG3 b is a schematic diagram of an exemplary memory including peripheral circuits according to an embodiment of the present application;

[0018] FIG4 is a cross-sectional schematic diagram of a memory cell array including a NAND memory string according to an embodiment of the present application;

[0019] FIG5 is a schematic diagram of an exemplary memory device including a memory cell array and peripheral circuits according to an embodiment of the present application;

[0020] FIG6 is a schematic diagram of an exemplary read operation flow of a memory system provided by the present application;

[0021] FIG7 is a schematic diagram of an implementation flow of an operating method of a memory device provided in one embodiment of the present application;

[0022] FIG8 is a schematic diagram of a threshold voltage distribution corresponding to a memory cell including three memory bits provided in one embodiment of the present application;

[0023] FIG9 is a schematic diagram of a threshold voltage distribution corresponding to a memory cell including four memory bits provided in one embodiment of the present application;

[0024] FIG10 is a schematic diagram of a method for confirming the valley voltage of the first-stage read voltage L1 corresponding to the lower page shown in FIG8 according to an embodiment of the present application;

[0025] FIG11 is a flowchart of an operating method of a memory device according to an embodiment of the present application;

[0026] FIG12 is a block diagram of a memory system provided by an embodiment of the present application;

[0027] FIG13 is a block diagram of a memory system provided by another embodiment of the present application;

[0028] FIG14 is a timing diagram of an exemplary reread operation provided by the present application;

[0029] FIG15 is a timing diagram of determining a valley voltage and performing a read operation according to an embodiment of the present application;

[0030] FIG16 is a block diagram of a computer-readable storage medium according to an embodiment of the present application. DETAILED DESCRIPTION

[0031] The exemplary embodiments disclosed herein will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0032] In the following description, numerous specific details are provided to provide a more thorough understanding of the present application. However, it will be apparent to those skilled in the art that the present application can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present application; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0033] In addition, the accompanying drawings are merely schematic illustrations of the present application and are not necessarily drawn to scale. Identical reference numerals in the figures denote identical or similar parts, and thus repetitive descriptions thereof will be omitted. Some of the blocks shown in the accompanying drawings are functional entities that do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0034] The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all steps. For example, some steps may be decomposed, while others may be combined or partially combined. Therefore, the actual execution order may vary depending on the actual situation.

[0035] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present application. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, identify the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0036] The memory device in the embodiments of the present application includes but is not limited to a three-dimensional NAND memory. For ease of understanding, the three-dimensional NAND memory is used as an example for description.

[0037] FIG1 shows a block diagram of an exemplary system 100 with a memory device according to some aspects of the present application. System 100 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having storage therein. As shown in FIG1 , system 100 can include a host 108 and a memory system 102, the memory system 102 having one or more memory devices 104 and a memory controller 106. Host 108 can be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. Host 108 can be configured to send data to or receive data from memory device 104.

[0038] According to some embodiments, memory controller 106 is coupled to memory device 104 and host 108 and is configured to control memory device 104. Memory controller 106 can manage data stored in memory device 104 and communicate with host 108. In some embodiments, memory controller 106 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0039] In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment Solid State Disk (SSD) or embedded Multi Media Card (eMMC), which is used as data storage for mobile devices such as smartphones, tablet computers, laptop computers, etc., as well as enterprise storage arrays.

[0040] The memory controller 106 may be configured to control operations of the memory device 104, such as read, erase, and program operations. The memory controller 106 may also be configured to manage various functions regarding data stored or to be stored in the memory device 104, including, but not limited to, bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 may also be configured to process error correction codes for data read from or written to the memory device 104.

[0041] The memory controller 106 may also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 may communicate with an external device (e.g., the host 108) according to a specific communication protocol. For example, the memory controller 106 may communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnection (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer Small Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, etc.

[0042] The memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). In other words, the memory system 102 can be implemented and packaged into different types of terminal electronic products.

[0043] In one example as shown in FIG2 a , the memory controller 106 and the single memory device 104 can be integrated into a memory card 202. The memory card 202 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. The memory card 202 can also include a memory card connector 204 that couples the memory card 202 to a host (e.g., the host 108 in FIG1 ).

[0044] In another example, as shown in FIG2 b , the memory controller 106 and the plurality of memory devices 104 can be integrated into an SSD 206. The SSD 206 can also include an SSD connector 208 that couples the SSD 206 to a host (e.g., the host 108 in FIG1 ). In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0045] Figure 3a illustrates a schematic structural diagram of a memory cell array of a three-dimensional NAND memory. As shown in Figure 3a, the memory cell array of the three-dimensional NAND memory comprises several parallel, staggered rows of memory cell rows parallel to gate isolation structures. Every two rows of memory cell rows are separated by a gate isolation structure and an upper select gate isolation structure, and each memory cell row includes multiple memory cells. The gate isolation structure may include a first gate isolation structure and a second gate isolation structure. The first gate isolation structure divides the memory cell array into multiple memory blocks. The multiple second gate isolation structures may divide the memory blocks into multiple finger storage areas. An upper select gate isolation structure disposed between each finger storage area may divide the finger storage area into two parts, thereby dividing the finger storage area into two memory slices. The memory block shown in Figure 3a includes six memory slices. In practical applications, the number of memory slices in a memory block is not limited to this.

[0046] In some embodiments, each memory block may be coupled to multiple word lines, and multiple memory cells coupled to each independently controlled word line constitute a page. For example, all memory cells in each memory slice in FIG3 a are coupled to constitute a page.

[0047] It should be noted that the number of memory cell rows between the gate isolation structure and the upper select gate isolation structure shown in FIG3a is merely illustrative and does not limit the number of memory cell rows contained in a finger storage area of ​​the 3D NAND memory device described herein. In actual applications, the number of memory cell rows contained in a finger storage area can be adjusted based on actual conditions, such as 2, 4, 8, or 16.

[0048] FIG3 b shows a schematic circuit diagram of an exemplary memory device 300 including peripheral circuitry according to some aspects of the present disclosure. Memory device 300 may be an example of memory device 104 in FIG1 . Memory device 300 may include a memory cell array 301 and peripheral circuitry 302 coupled to memory cell array 301. For illustration, memory cell array 301 is described as a three-dimensional NAND-type memory cell array, wherein memory cells 306 are NAND-type memory cells provided in an array of memory strings 308, each memory string 308 extending vertically above a substrate (not shown). In some embodiments, each memory string 308 includes a plurality of memory cells 306 coupled in series and vertically stacked. Each memory cell 306 may hold a continuous analog value, such as a voltage or charge, that depends on the number of electrons trapped within the region of the memory cell 306. Each memory cell 306 may be a floating-gate memory cell including a floating-gate transistor, or a charge-trapping memory cell including a charge-trapping transistor.

[0049] In some embodiments, each memory cell 306 is a single-level cell (SLC) that has two possible storage states and can therefore store one bit of data. For example, the first storage state "0" can correspond to a first voltage range, and the second storage state "1" can correspond to a second voltage range. In some embodiments, each memory cell 306 is a multi-level cell (MLC) that can store more than one bit of data in more than four storage states. For example, an MLC can store two bits per cell (also referred to as a double-level cell), three bits per cell (also referred to as a trinary-level cell (TLC)), four bits per cell (also referred to as a quad-level cell (QLC)), five bits per cell (also referred to as a penta-level cell (PLC)), or more than five bits per cell. Each MLC can be programmed to take on a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to assume one of three possible programming levels from the erased state by writing one of three possible nominal storage values ​​to the cell, a fourth nominal storage value can be used for the erased state.

[0050] It should be noted that the storage state mentioned here is the storage state of the storage unit mentioned in this application. Different storage cells have different numbers of storage states. For example, an SLC type storage cell has 2 storage states (that is, two memory states), wherein these 2 storage states include: a programming state and an erased state. For another example, an MLC type storage cell has 4 storage states, wherein these 4 storage states include: an erased state and three programming states. For another example, a TLC type storage cell has 8 storage states, wherein these 8 storage states include: one erased state and seven programming states. In some embodiments, a QLC type storage cell has 16 storage states, wherein these 16 storage states include: one erased state and fifteen programming states.

[0051] As shown in FIG3 b , each memory string 308 may include a lower select transistor (BSG) 310 (also known as a source-side select transistor) at its source terminal and a top select transistor (TSG) 312 (also known as a drain-side select transistor) at its drain terminal. The BSG 310 and the TSG 312 may be configured to activate the selected memory string 308 during read and program operations. In some embodiments, the sources of the memory strings 308 in the same memory block 304 are coupled via the same source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all memory strings 308 in the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG 312 of each memory string 308 is coupled to a corresponding bit line (BL) 316, from which data can be read or written via an output bus (not shown). In some embodiments, each memory string 308 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of a transistor having TSG 312) or a deselect voltage (e.g., 0V) to a corresponding TSG 312 via one or more TSG lines 313 and / or by applying a select voltage (e.g., higher than the threshold voltage of a transistor having BSG 310) or a deselect voltage (e.g., 0V) to a corresponding BSG 310 via one or more BSG lines 315.

[0052] As shown in FIG3 b , a memory string 308 can be organized into a plurality of memory blocks 304, each of which can have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is a basic data unit for erase operations, i.e., all memory cells 306 on the same memory block 304 are erased simultaneously. To erase the memory cells 306 in a selected memory block 304, the source lines 314 coupled to the selected memory block 304 and to unselected memory blocks 304 in the same plane as the selected memory block 304 can be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)). It should be understood that in some examples, erase operations can be performed at the half-block level, at the quarter-block level, or at any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 306 of adjacent memory strings 308 can be coupled by word lines 318, which select which row of memory cells 306 is affected by read and program operations. In some embodiments, referring to FIG. 3 a , multiple memory cells are isolated from each other by an upper select gate isolation structure and a gate isolation structure. The memory cells between the upper select gate isolation structure and the gate isolation structure are arranged into multiple memory cell rows, with each memory cell row being parallel to the gate isolation structure and the upper select gate isolation structure. The memory cells in a memory slice sharing the same word line form a physical page 320. Each physical page 320 can be mapped to at least one logical page based on the storage mode of the corresponding memory cell 306 (e.g., SLC or MLC as described above). The logical page can constitute the basic data unit for programming and reading operations.

[0053] 3a and 3b, each memory cell 306 in the plurality of memory cells is coupled to a corresponding word line 318, and each memory string 308 is coupled to a corresponding bit line 316 via a corresponding selection transistor (eg, top selection transistor (TSG) 312).

[0054] FIG4 illustrates a cross-sectional schematic diagram of an exemplary memory cell array 301 including a NAND memory string 308 according to some aspects of the present disclosure. As shown in FIG4 , the NAND memory cell array 301 may include a stacked structure 410 comprising a plurality of gate layers 411 and a plurality of insulating layers 412 alternately stacked in sequence, and a channel structure vertically extending through the gate layers 411 and the insulating layers 412. The channel structure is coupled to each gate layer to form a memory cell, and the channel structure is coupled to the plurality of gate layers in the stacked structure 410 to form the memory string 308. The gate layers 411 and the insulating layers 412 may be alternately stacked, with two adjacent gate layers 411 separated by an insulating layer 412.

[0055] The constituent material of the gate layer 411 may include a conductive material. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, for example, a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stacked structure 410 may extend laterally as an upper selection gate line, the gate layer 411 at the bottom of the stacked structure 410 may extend laterally as a lower selection gate line, and the gate layer 411 extending laterally between the upper selection gate line and the lower selection gate line may serve as a word line layer.

[0056] In some embodiments, the stacked structure 410 may be disposed on a substrate 401. The substrate 401 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0057] In some embodiments, memory string 308 includes a channel structure extending vertically through stacked structure 410. In some embodiments, the channel structure includes a channel hole filled with one or more semiconductor materials (e.g., serving as a semiconductor channel) and one or more dielectric materials (e.g., serving as a memory film). In some embodiments, the semiconductor channel includes silicon, such as polycrystalline silicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trapping / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a pillar shape). In some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially in this order from the center of the pillar toward the outer surface of the pillar. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0058] Referring back to FIG3 b , the peripheral circuit 302 can be coupled to the memory cell array 301 via the bit lines 316 , word lines 318 , source lines 314 , BSG lines 315 , and TSG lines 313 . The peripheral circuit 302 can include any suitable analog, digital, and mixed signal circuits for facilitating the operation of the memory cell array 301 by applying voltage and / or current signals to and sensing voltage and / or current signals from each target memory cell 306 via the bit lines 316 , word lines 318 , source lines 314 , BSG lines 315 , and TSG lines 313 . The peripheral circuit 302 can include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, FIG5 shows some exemplary peripheral circuits, including a page buffer / sense amplifier 504 , a column decoder / bit line driver 506 , a row decoder / word line driver 508 , a voltage generator 510 , a control logic 512 , a register 514 , an interface 516 , and a data bus 518 . It should be understood that in some examples, additional peripheral circuits not shown in FIG. 5 may also be included.

[0059] The page buffer / sense amplifier 504 can be configured to read data from the memory cell array 301 and program (write) data to the memory cell array 301 according to a control signal from the control logic 512. In one example, the page buffer / sense amplifier 504 can store program data (write data) to be programmed into the memory cell array 301. In another example, the page buffer / sense amplifier 504 can perform a program verification operation to ensure that the data has been correctly programmed into the memory cell 306 coupled to the selected word line 318. In yet another example, the page buffer / sense amplifier 504 can also sense a low-power signal from the bit line 316 representing the data bit stored in the memory cell 306 and amplify the small voltage swing to a recognizable logic level during a read operation. The column decoder / bit line driver 506 can be configured to be controlled by the control logic 512 and select one or more memory strings 308 by applying a bit line voltage generated from the voltage generator 510.

[0060] The row decoder / word line driver 508 can be configured to be controlled by control logic 512 and to select / deselect memory blocks 304 of the memory cell array 301 and to select / deselect word lines 318 of the memory blocks 304. The row decoder / word line driver 508 can also be configured to drive the word lines 318 using word line voltages generated from a voltage generator 510. In some embodiments, the row decoder / word line driver 508 can also select / deselect and drive the BSG lines 315 and the TSG lines 313. As described in detail below, the row decoder / word line driver 508 is configured to perform a programming operation on the memory cells 306 coupled to the selected word line(s) 318. The voltage generator 510 can be configured to be controlled by control logic 512 and to generate word line voltages (e.g., a read voltage, a program voltage, a pass voltage, a channel boosting voltage, a verify voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 301.

[0061] The control logic 512 can be coupled to each of the other parts in the peripheral circuit described above and is configured to control the operation of each of the other parts in the peripheral circuit. The register 514 can be coupled to the control logic 512 and includes a status register, a command register, and an address register for storing status information, command operation code (OP code), and command address for controlling the operation of each peripheral circuit. The interface 516 can be coupled to the control logic 512 and act as a control buffer to buffer control commands received from a host (not shown) and relay them to the control logic 512, as well as buffer status information received from the control logic 512 and relay it to the host. The interface 516 can also be coupled to the column decoder / bit line driver 506 via the data bus 518 and act as a data I / O interface and data buffer to buffer data and relay it to the memory cell array 301 or relay or buffer data from the memory cell array 301.

[0062] The basic principle of 3D NAND memory is that data is written by injecting a certain amount of charge into a memory cell, via carriers (electrons or holes) across a charge barrier. The stored data can then be read based on the threshold voltage at which the memory cell turns on. Therefore, to ensure accurate data is read, a robust and efficient ECC (Error Correction Code) algorithm is typically used during data reading.

[0063] However, as the charge stored in a memory cell changes over time due to age, repeated read operations, and temperature fluctuations, this can affect the accuracy of data reads. When the threshold voltage shifts significantly upward or downward, the likelihood of read errors is high when reading the data from the memory cell using the original read voltage. Furthermore, when the read error exceeds the ECC's error correction capability, data read failures can occur.

[0064] FIG6 is a schematic diagram illustrating an exemplary read operation flow for a memory system. As shown in FIG6 , when a memory controller controls a memory device to perform a read operation, it first performs a default read operation (FW default read) on the memory cell at the corresponding physical address. If the default read operation fails, a reread operation (Read retry) is performed. If the reread operation fails, a soft decode operation is performed. If the soft decode operation fails, a Redundant Array of Independent Disks (RAID) operation is performed. If the RAID operation fails, the read operation ceases and the read fails due to uncorrectable errors. The memory controller then sends a Read Fail signal to the host 108. The reread operation and the default read operation can be applied to hard decode.

[0065] In some embodiments, a reread operation can typically be performed by querying a retry table provided by the manufacturer. The reread operation is essentially an error correction mechanism. The retry table can provide a reference voltage for reading data. By querying the retry table, each storage cell is read again using a read voltage that deviates from the normal threshold voltage and correcting errors with the ECC error correction algorithm in an attempt to correctly read the data. If the read error data is corrected, the retry table query is stopped. If the read error data cannot be corrected, the retry table query is continued until the entire retry table is traversed.

[0066] The aforementioned rereading method requires querying the trial-and-error table one by one, which inevitably increases the number of trial-and-error operations and takes a long time. Furthermore, the trial-and-error tables provided by manufacturers are only reference values ​​for specific environments. Real-world usage scenarios vary greatly, so the manufacturer's trial-and-error tables don't cover many scenarios. Consequently, even after traversing the trial-and-error table data, corrections may not be possible, resulting in a significant waste of command processing time. In short, rereading by repeatedly polling the trial-and-error table is time-consuming, affecting the response time of subsequent commands and, consequently, device performance.

[0067] In view of one or more of the above problems, an embodiment of the present application provides an operating method for a memory device.

[0068] FIG7 is a schematic diagram illustrating a flow chart of an implementation method for operating a memory device according to an embodiment of the present application. As shown in FIG7 , the memory device includes a memory cell array, wherein the memory cell array includes a plurality of memory cells, and a predetermined number of the memory cells form a code word (CW). The operating method of the memory device specifically includes the following steps:

[0069] Step S10: Obtaining a first result corresponding to at least one codeword at a target read voltage; the first result includes a number of bits flipped in the at least one codeword read at the first read voltage and at the second read voltage; and the difference between the first read voltage and the second read voltage is less than a preset voltage.

[0070] Step S20: adjusting the target read voltage according to a first result corresponding to at least one codeword at the target read voltage;

[0071] Step S30: obtaining a first result corresponding to at least one codeword under the adjusted read voltage;

[0072] Step S40: determining a valley voltage according to the plurality of first results; the valley voltage is used as a read voltage when performing a read operation on at least one codeword.

[0073] Here, the structure of the memory device is referred to in FIG. 3 b , which will not be described in detail here.

[0074] Here, a preset number of storage units forms a codeword.

[0075] In some embodiments, the number of storage cells included in a codeword is the same as the number of storage cells included in one encoding or decoding when performing error correction encoding or decoding. In some specific embodiments, the number of storage cells included in a codeword may be less than or equal to the number of storage cells coupled to a page, such as the number of storage cells included in a codeword is 1 / 4 of the number of storage cells coupled to a page. In some specific embodiments, a codeword may include a number ranging from 2 4 to 2 12 For example, a code word may include 2 4 , 2 8 or 2 12 storage units.

[0076] In general, different memory systems may choose codewords of different sizes to meet their performance, reliability, and storage requirements.

[0077] Memory cells in different types of memory devices (eg, MLC, TLC, or QLC) can store different numbers of bits. Therefore, for codewords of the same size, the number of memory cells included may also be different.

[0078] For example, in a specific embodiment, the size of the codeword is 4KB. Taking the memory cells in the memory cell array as MLC as an example, each memory cell stores 2 bits, so the number of memory cells included in the codeword is 2. 11 .

[0079] For example, in other embodiments, the size of the codeword is 4KB. Taking the memory cells in the memory cell array as QLC as an example, each memory cell stores 4 bits, so the number of memory cells included in the codeword is 2. 10 .

[0080] It should be noted that in practice, codewords will have some additional reserved space for management and error correction, so the number of storage units actually required may slightly exceed the above calculation result.

[0081] It is understandable that a codeword may include multiple storage units, and the number of storage units included in a codeword may be adjusted according to actual conditions.

[0082] It should be noted that, in some embodiments, during the process of reading the memory device, a read operation reads out a page of data. When the number of storage cells contained in a codeword may be less than the number of storage cells coupled to a page, the codeword is a unit that can be executed to obtain the first result, but multiple codewords are not actually excluded. In other words, the first result corresponding to at least one codeword under the current read voltage can be obtained here. For example, a page can include 4 codewords, and the page buffer hardware operation can count the fail bit count (FBC) of each of the 4 codewords at one time, and then add the FBC of the four codewords to obtain the FBC of a page, and the subsequent calculation uses the added value. It can be understood that the first result here is based on the data of a page and can include multiple codewords.

[0083] In some embodiments, before obtaining a first result corresponding to at least one codeword at a target read voltage, a read mode of the memory device is set to a single-level read mode (Single Level Read, SLR); the single-level read mode includes reading at least one bit of storage data stored in a memory cell using a first-level read voltage.

[0084] In some embodiments, a memory cell includes M bits, a memory device includes M pages, and an M-bit memory cell reads its M-bit stored data through an N-level read voltage; M and N are both integers greater than 1, and N=2 M -1; the method further comprises:

[0085] For each level of the multiple levels of read voltages corresponding to each type of page, a valley voltage of each level is determined according to a plurality of first results corresponding to the plurality of read voltages of each level.

[0086] For example, when the number of storage bits of a memory cell includes three bits, the corresponding storage states include states 0 to 7. Referring to FIG8 , the eight states are state 0 (also called the erased state) E, state 1 (also called the first storage state) P1, state 2 (also called the second storage state) P2, ... state 7 (also called the seventh storage state) P7. The binary data corresponding to the eight states are 111, 110, 100, 000, 010, 011, 001, and 101, respectively. Accordingly, the memory device includes three types of pages: lower page (LP), middle page (MP), and upper page (UP).

[0087] Taking the memory cell shown in FIG8 as an example, the three-bit memory cell reads its three-bit eight-state storage data through seven levels of read voltages (first-level read voltage L1, second-level read voltage L2, third-level read voltage L3, fourth-level read voltage L4, fifth-level read voltage L5, sixth-level read voltage L6, and seventh-level read voltage L7 shown in FIG8).

[0088] In some embodiments, the memory device operating method further includes: determining a valley voltage of each level of the multiple levels of read voltages corresponding to each type of page according to multiple first results corresponding to the multiple read voltages of each level.

[0089] Exemplarily, each type of page corresponds to multiple levels of read voltages. As shown in FIG8 , the bottom page corresponds to the first-level read voltage L1 and the fifth-level read voltage L5. The middle page corresponds to the second-level read voltage L2, the fourth-level read voltage L4, and the sixth-level read voltage L6. The top page corresponds to the third-level read voltage L3 and the seventh-level read voltage L7. For the first-level read voltage L1 and the fifth-level read voltage L5 corresponding to the bottom page, the valley voltage of the first-level read voltage L1 can be determined based on multiple first results corresponding to the multiple read voltages of the first-level read voltage L1. Then, the valley voltage of the fifth-level read voltage L5 can be determined based on multiple first results corresponding to the multiple read voltages of the fifth-level read voltage L5. In this way, the valley voltage of each level of the multi-level read voltage corresponding to the bottom page can be obtained. The process for determining the valley voltage of each level of the multi-level read voltage corresponding to the middle and top pages is similar to that for the bottom page and will not be further described here.

[0090] The lower page is usually closest to the source / drain, so the valley voltage of each level of the multi-level read voltage corresponding to the lower page is determined first, which has the fastest access speed and the shortest response time, and can ensure balanced performance and durability during data access.

[0091] It should be noted that the method of preferentially determining the valley voltage of each level of the multi-level read voltage corresponding to the lower page is only an example and is not used to limit the order of determining the valley voltage of each level of the multi-level read voltage corresponding to each type of page in the embodiment of the present application.

[0092] Exemplarily, when the number of storage bits of a memory cell includes four bits, the corresponding storage states include the 0th state to the 15th state. Referring to FIG9 , the 16 states are the 0th state (also called the erased state) E, the 1st state (also called the 1st storage state) P1, the 2nd state (also called the 2nd storage state) P2…the 15th state (also called the 15th storage state) P15, and the binary data corresponding to the 16 states are 1111, 0111, 0110….1110. Accordingly, the memory device includes four types of pages, namely, a lower page, a middle page, an upper page, and an extra page (Extra Page, XP). Here, the four storage bits corresponding to the 16 states are stored in the lower page, the middle page, the upper page, and the extra page, respectively.

[0093] Taking the memory cell shown in Figure 9 as an example, the four-bit memory cell reads its four-bit sixteen-state storage data through 15 levels of read voltages (the first level read voltage L1, the second level read voltage L2, the third level read voltage L3, the fourth level read voltage L4, the fifth level read voltage L5, the sixth level read voltage L6, the seventh level read voltage L7, the eighth level read voltage L8, the ninth level read voltage L9, the tenth level read voltage L10, the eleventh level read voltage L11, the twelfth level read voltage L12, the thirteenth level read voltage L13, the fourteenth level read voltage L14, and the fifteenth level read voltage L15 shown in Figure 9).

[0094] Exemplarily, each type of page corresponds to multiple levels of read voltages. As shown in FIG9 , the lower page corresponds to the second level read voltage L2, the eighth level read voltage L8, and the fourteenth level read voltage L14. The middle page corresponds to the third level read voltage L3, the seventh level read voltage L7, the ninth level read voltage L9, and the thirteenth level read voltage L13. The upper page corresponds to the fifth level read voltage L5, the tenth level read voltage L10, the twelfth level read voltage L12, and the fifteenth level read voltage L15. The additional page corresponds to the first level read voltage L1, the fourth level read voltage L4, the sixth level read voltage L6, and the eleventh level read voltage L11.

[0095] For the second-level read voltage L2, the eighth-level read voltage L8, and the fourteenth-level read voltage L14 corresponding to the lower page, the valley voltage of the second-level read voltage L2 can be determined based on the multiple first results corresponding to the multiple read voltages of the second-level read voltage L2. Then, the valley voltage of the eighth-level read voltage L8 can be determined based on the multiple first results corresponding to the multiple read voltages of the eighth-level read voltage L8. Finally, the valley voltage of the fourteenth-level read voltage L14 can be determined based on the multiple first results corresponding to the multiple read voltages of the fourteenth-level read voltage L14. In this way, the valley voltage of each level of the multi-level read voltage corresponding to the lower page can be obtained. The process for determining the valley voltage of each level of the multi-level read voltage corresponding to the middle and upper pages is similar to that for the lower page and will not be repeated here.

[0096] Figure 10 is a schematic diagram of a method for determining the valley voltage of the first-stage read voltage L1 corresponding to the lower page shown in Figure 8, according to one embodiment of the present application. Figure 11 is a flow chart of a method for operating a memory device according to one embodiment of the present application. The process of determining the valley voltage will be described in detail below in conjunction with Figures 8, 10, and 11.

[0097] In step S301, the first preset value and the second preset value are obtained; the first preset value is equal to the upper limit of the fail bit count (FBC) supported by the memory device.

[0098] In step S302 , the stored data of the codeword is read at a target read voltage to obtain a second result; and the second result is stored in a first latch of the memory device.

[0099] Exemplarily, as shown in FIG10 , stored data of at least one codeword is read at a target read voltage V0 to obtain a second result. Specifically, data stored in the lower page of memory cells in the codeword is read at the target read voltage V0, and memory cells with a threshold voltage less than the target read voltage V0 are marked as bit 1, while memory cells with a threshold voltage greater than the target read voltage V0 are marked as bit 0, thereby obtaining the second result, which is then stored in a first latch of the memory device.

[0100] It should be noted that the target read voltage V0 used for the first time here may refer to a preset read voltage that can distinguish two adjacent storage states of a memory cell of the memory device in a previous reading process, wherein the preset read voltage may be an empirical value; or it may be a default value configured when the memory device leaves the factory, which is obtained through a large number of simulation experiments before the memory device leaves the factory.

[0101] In step S303 , a first adjustment is performed on the target read voltage, and the stored data of the codeword is read at the adjusted target read voltage to obtain a third result; the third result is stored in the second latch of the memory device.

[0102] Here, the first adjustment can be understood as a small-amplitude adjustment. In some specific embodiments, the small amplitude here, that is, the step size of the first adjustment, is set to range from 5mV to 20mV. Exemplarily, the step size of the first adjustment can be 5mV, 10mV, 15mV, or 20mV.

[0103] It should be noted that the first read voltage and the second read voltage are associated before and after the first adjustment. That is, the second read voltage is obtained after the first adjustment of the first read voltage. Based on this, the voltage difference between the first read voltage and the second read voltage is the step size of the first adjustment. The difference between the first read voltage and the second read voltage being less than the preset voltage can be understood as the first read voltage and the second read voltage having a smaller voltage difference. The preset voltage is related to the step size of the first adjustment and can be a voltage slightly larger than the step size of the first adjustment. In some specific embodiments, the preset voltage is set in the range of 6mV to 21mV. For example, the preset voltage can be 6mV, 11mV, 16mV, or 21mV.

[0104] It should be noted that the first read voltage and the second read voltage are general concepts. The target read voltage and all subsequent read voltages after the second adjustment can be called the first read voltage, and all read voltages after the first adjustment can be called the second read voltage.

[0105] For example, as shown in FIG10 , the target read voltage V0 is first adjusted, and the stored data of the codeword is read at the adjusted target read voltage (V1 shown in FIG10 ), to obtain a third result. Specifically, the data stored in the lower page of the memory cells in the codeword is read at the adjusted target read voltage (V1 shown in FIG10 ), and the memory cells whose threshold voltage is less than the adjusted target read voltage (V1 shown in FIG10 ) are marked as bit 1, and the memory cells whose threshold voltage is greater than the adjusted target read voltage (V1 shown in FIG10 ) are marked as bit 0, to obtain a third result, which is stored in the second latch of the memory device.

[0106] 10 , the target read voltage V0 and the adjusted target read voltage V1 have a first voltage difference ΔV1 , which is the first adjustment step size. The first adjustment step size is relatively small, and the first adjustment can be understood as a small adjustment.

[0107] In step S304 , a logic operation is performed on the second result and the third result to obtain a fourth result; and the fourth result is stored in a third latch of the memory device.

[0108] Exemplarily, as shown in FIG10 , an XOR operation is performed on the second result and the third result to obtain a fourth result; and the fourth result is stored in a third latch of the memory device.

[0109] It should be noted that the XOR operation is one of the basic logical operations. In binary, if two binary numbers in the same position are the same, the result is "0", and if two binary numbers in the same position are different, the result is "1" (that is, the same is 0, and different is 1).

[0110] In step S305 , the number of bits in the fourth result indicating that the third result is flipped compared to the second result is counted to obtain the first result.

[0111] For example, as shown in FIG10 , the bits set to 1 in the fourth result represent the number of memory cells whose threshold voltages differ between the target read voltage V0 and the adjusted target read voltage V1. In other words, the bits set to 1 in the fourth result represent the number of bits in the codeword that are flipped between the two read results at the target read voltage V0 and the adjusted target read voltage V1. Because a single-stage read mode is employed, i.e., both read operations read a single bit of data stored in the lower page of the codeword memory cell. Therefore, the bits set to 1 in the fourth result represent the number of memory cells in which the codeword is flipped between the two read results at the target read voltage V0 and the adjusted target read voltage V1. This number is recorded as the first result Y1 corresponding to the target read voltage. It should be noted that the target read voltage V0 here is the first read voltage, and the adjusted target read voltage V1 is the second read voltage.

[0112] In step S306 , the first result is compared with a first preset value to determine whether the first result is less than or equal to the first preset value.

[0113] In some embodiments, the first preset value is equal to the upper limit of the fail bit count supported by the memory device. The upper limit of the fail bit count supported by the memory device means that the fail bits within the upper limit can be detected and corrected by the built-in error correction mechanism, while the fail bits exceeding the upper limit cannot be corrected. Specifically, when the first result is greater than the first preset value, i.e., the upper limit of the fail bit count supported by the memory device, it means that when the read voltage corresponding to the first result is used as the valley voltage, the read result may contain uncorrectable errors, and the data integrity and reliability are threatened. Therefore, in order to ensure that the first result can be used to determine the valley voltage, the range of the first result needs to be limited, and only the first result that is less than the first preset value can be used as one of the multiple first results for determining the valley voltage.

[0114] The magnitude of the first preset value depends on the type and storage density of the memory device. The first preset value can be an empirical value or a factory-configured default value for the memory device, which is derived from extensive simulation experiments before the memory device leaves the factory. For example, the first preset value ranges from 225 to 280. More specifically, the first preset value can be 225, 230, 240, 250, 260, 270, or 280.

[0115] If the first result is less than or equal to the first preset value, step S307 is executed.

[0116] As shown in FIG10 , if the first result corresponding to the target read voltage is less than the first preset value, step S307 is executed. In step S307 , a second adjustment is performed on the target read voltage to obtain a target adjusted read voltage; the second adjustment step size is greater than the first adjustment step size; and the first result corresponding to the codeword at the target adjusted read voltage is obtained.

[0117] Here, the second adjustment can be understood as a larger adjustment. In some specific embodiments, the larger adjustment, i.e., the step size of the second adjustment, is set to range from 50mV to 80mV. For example, the step size of the second adjustment can be 50mV, 60mV, 70mV, or 80mV.

[0118] It should be noted that the target read voltage and all subsequent read voltages after the second adjustment can be referred to as the first read voltage, and all read voltages after the first adjustment can be referred to as the second read voltage. For example, as shown in FIG10 , the target read voltage V0 is subjected to a second adjustment to obtain a target adjusted read voltage V2. The target read voltage V0 and the target adjusted read voltage V2 have a second voltage difference △V2, and the magnitude of the second voltage difference △V2 is the step size of the second adjustment. The step size of the second adjustment is greater than the step size of the first adjustment, that is, the second voltage difference △V2 is greater than the first voltage difference △V1. The amplitude of the second adjustment step size is relatively large, and the second adjustment can be understood as a relatively large adjustment. It should be noted that the target adjusted read voltage V2 here is the first read voltage.

[0119] Data stored in the lower page of the memory cell in the codeword is read at the target adjusted read voltage V2, memory cells whose threshold voltage is less than the adjusted target adjusted read voltage V2 are marked as bit 1, and memory cells whose threshold voltage is greater than the target adjusted read voltage V2 are marked as bit 0, to obtain a second result, which is stored in the first latch of the memory device.

[0120] A first adjustment is made to the target adjusted read voltage V2, and the stored data of the codeword is read at the adjusted target adjusted read voltage (V3 shown in FIG10 ), obtaining a third result. Specifically, the data stored in the lower page of the memory cells in the codeword is read at the adjusted target adjusted read voltage (V3 shown in FIG10 ), and memory cells with a threshold voltage less than the adjusted target adjusted read voltage (V3 shown in FIG10 ) are marked as bit 1, and memory cells with a threshold voltage greater than the adjusted target adjusted read voltage (V3 shown in FIG10 ) are marked as bit 0, obtaining a third result, which is stored in the second latch of the memory device. It should be noted that the adjusted target adjusted read voltage (V3 shown in FIG10 ) here is the second read voltage.

[0121] Performing an exclusive-OR operation on the second result and the third result to obtain a fourth result; and storing the fourth result in a third latch of the memory device. For example, as shown in FIG10 , the bits set to 1 in the fourth result represent the number of memory cells whose threshold voltages differ between the target adjusted read voltage V2 and the adjusted target adjusted read voltage V3. In other words, the bits set to 1 in the fourth result represent the number of bits of the codeword that are flipped between the two read results at the target adjusted read voltage V2 and the adjusted target adjusted read voltage V3. Because a single-stage read mode is employed, i.e., both read operations read a single bit of data stored in the lower page of the codeword memory cell. Therefore, the bits set to 1 in the fourth result represent the number of memory cells whose codeword is flipped between the two read results at the target adjusted read voltage V2 and the adjusted target adjusted read voltage V3. This number is recorded as the first result Y2 corresponding to the target adjusted read voltage V2.

[0122] It is understood that the direction of the initial second adjustment of the target read voltage V0 can be random, and it is sufficient to ensure that the absolute value of the voltage difference between the target adjusted read voltage V2 obtained after the second adjustment of the target read voltage V0 and the target read voltage V0 is equal to the second adjustment step size. It is understood that the target adjusted read voltage V2 can be greater than or less than the target read voltage V0.

[0123] In step S308 , the first result corresponding to the codeword under the adjusted read voltage is compared with a second preset value to determine whether the first result is less than or equal to the second preset value.

[0124] In some embodiments, the second preset value is used as a judgment threshold for determining the valley voltage. That is, when the first result is less than or equal to the second preset value, it indicates that the read voltage corresponding to the first result is used as the valley voltage, and the error rate of the read result is low and the reliability is high.

[0125] The size of the second preset value depends on the type and storage density of the memory device. The second preset value can be an empirical value or a default value configured at the factory for the memory device, which is derived from extensive simulation experiments before the memory device leaves the factory. For example, the second preset value ranges from 5 to 30. More specifically, the second preset value can be 5, 10, 15, 20, 25, or 30.

[0126] In some embodiments, when step S308 is executed after step S307, if the first result corresponding to the codeword at the adjusted read voltage (i.e., the target adjusted read voltage) is less than or equal to the second predetermined value, step S309 is executed, and the operation ends. It is understood that the target adjusted read voltage can be the valley voltage of the first-step read voltage L1 corresponding to the lower page shown in FIG8 .

[0127] In other embodiments, when step S308 is executed after step S307, if the first result corresponding to the codeword at the adjusted read voltage (i.e., the target adjusted read voltage) is greater than the second preset value, the process returns to step S306, compares the first result greater than the second preset value with the first preset value, and determines whether the first result is less than or equal to the first preset value. If the first result corresponding to the codeword at the adjusted read voltage (i.e., the target adjusted read voltage) is less than or equal to the first preset value and greater than the second preset value, the process continues to step S307. In this case, the target read voltage referred to in step S307 is the target adjusted read voltage. The target adjusted read voltage is second-adjusted based on the first result corresponding to the codeword at the target adjusted read voltage to obtain the adjusted read voltage and the first result corresponding to the codeword at the adjusted read voltage.

[0128] In some embodiments, according to the first result corresponding to the codeword at the target adjusted read voltage, the direction of the second adjustment of the target adjusted read voltage is related to the magnitude relationship between the first result Y1 corresponding to the target read voltage V0 and the first result Y2 corresponding to the target adjusted read voltage V2.

[0129] For example, as shown in FIG10 , after the second adjustment of the target read voltage V0, the target adjusted read voltage V2 is greater than the target read voltage V0, and Y2 is less than Y1. This indicates that adjusting the target read voltage V0 to the right (in the direction of increasing voltage) can reduce the number of bits flipped in the two read results at the corresponding read voltage. Therefore, when the second adjustment of the target adjusted read voltage is performed, the target adjusted read voltage V2 is preferentially adjusted further to the right to obtain the adjusted read voltage and the first result corresponding to the codeword at the adjusted read voltage.

[0130] It is understandable that the direction of the second adjustment of a certain read voltage is selected according to the change trend of the first result before and after the previous second adjustment, so as to further reduce the number of bits flipped in the two read results under the adjusted read voltage.

[0131] After obtaining the adjusted read voltage and the first result corresponding to the codeword under the adjusted read voltage, step S308 is continued.

[0132] If it is determined that the first result corresponding to the adjusted read voltage is less than or equal to the second preset value, step S309 is executed to end the operation.

[0133] In some embodiments, determining the valley voltage based on multiple first results includes: when the first result corresponding to the final adjusted read voltage is less than or equal to a second preset value, using the read voltage corresponding to the smallest first result as the valley voltage.

[0134] Illustratively, Table 1 is an example of multiple first results obtained through multiple iterations.

[0135] Table 1

[0136] As shown in Table 1, the first result obtained in the first iteration is 200, which can be understood as the first result corresponding to the target read voltage V0. The first result obtained in the second iteration is 160, which can be understood as the first result corresponding to the target adjusted read voltage V2. The first result obtained in the third iteration is 70, and the first result obtained in the fourth iteration is 5.

[0137] Exemplarily, the first preset value is set to 225, and the second preset value is set to 10.

[0138] In some embodiments, during the operation method of the memory device shown in FIG11 , if the first result obtained in the fourth iteration is less than or equal to a second preset value, a predetermined number of iterations may be continued to obtain multiple additional first results. This can further enhance the accuracy of determining the valley voltage based on the multiple first results. Specifically, the first results obtained in iterations 5 through 7 are shown in Table 1.

[0139] The read voltage corresponding to the smallest first result among the multiple first results in Table 1 is used as the valley voltage, that is, the read voltage corresponding to the first result obtained in the fourth iteration is used as the valley voltage.

[0140] It can be understood that the read voltage corresponding to the first result obtained in the fourth iteration is the valley voltage of the first-stage read voltage L1 corresponding to the lower page shown in FIG. 8 .

[0141] It should be noted that, in actual use, the number of iterations (i.e., the number of times the second adjustment is made to the read voltage) may vary according to actual needs. The implementation method of obtaining 7 first results after 7 iterations for determining the valley voltage is only an example, and the scope of protection of this application should not be excessively limited here.

[0142] If the judgment result of step S306 in FIG11 is that the first result is greater than the first preset value, step S310 is executed to adjust the target read voltage multiple times and obtain multiple first results corresponding to the codeword under the multiple adjusted read voltages.

[0143] It should be noted that the directions and step sizes of the multiple adjustments to the target read voltage may be random, so as to randomly obtain multiple first results.

[0144] After obtaining multiple first results, step S311 is executed.

[0145] In step S311, the plurality of first results are compared with a first preset value to determine whether the plurality of first results are all greater than the first preset value. If the plurality of first results are all greater than the first preset value, step S312 is executed.

[0146] In step S312, the number of storage units corresponding to the codewords is adjusted, and the number of storage units corresponding to one codeword after the adjustment is smaller than the number of storage units corresponding to one codeword before the adjustment. Then, step S302 is executed again.

[0147] It can be understood that by reducing the number of storage units corresponding to the codewords, the total amount of data contained in the fourth result can be reduced. The reduction in the total amount can reduce the number of statistics from the total amount to a certain extent, that is, the first result will also be reduced, so that the first result can more easily fall within the range of the first preset value.

[0148] It should be noted that the process of confirming the valley voltages of other levels of read voltages corresponding to the lower page, and the process of confirming the valley voltages of multi-level read voltages corresponding to the middle page and the upper page are similar to the methods disclosed in the above embodiments and will not be repeated here.

[0149] The operating method of the memory device provided in the embodiments of the present application is to count the number of bits flipped in two read results of a codeword containing a preset number of memory cells at a corresponding read voltage and a voltage near the corresponding read voltage as a first result, and adjust the target read voltage based on the first result corresponding to at least one codeword at a target read voltage to obtain the first result corresponding to at least one codeword at the adjusted read voltage. The valley voltage is determined based on the minimum value of the multiple first results as the read voltage when performing a read operation on the codeword. In this way, the time-consuming and incomplete scenario coverage problems caused by using a trial-and-error table can be effectively avoided, the space occupied by the trial-and-error table can be saved, the valley voltage can be found more quickly and accurately, the delay in determining the valley voltage can be effectively reduced, and the product reliability and user experience can be improved.

[0150] It should be noted that the method disclosed in the embodiments of the present application can solve many problems existing in the reread operation, but it is not used to limit the application scenarios in the embodiments of the present application. The method disclosed in the embodiments of the present application is also applicable to conventional read operations.

[0151] An embodiment of the present application provides a memory device, as shown in FIG3 b . The memory device 300 includes: a memory cell array 301 including a plurality of memory cells 306 , wherein a predetermined number of memory cells 306 form a codeword; and a peripheral circuit 302 coupled to the memory cell array 301 and configured to perform the following steps shown in FIG7 :

[0152] Step S10: Obtaining a first result corresponding to at least one codeword at a target read voltage; the first result includes a number of bits flipped in the at least one codeword read at the first read voltage and the second read voltage; the difference between the first read voltage and the second read voltage is less than a preset voltage; Step S20: Adjusting the target read voltage based on the first result corresponding to the at least one codeword at the target read voltage;

[0153] Step S30: obtaining a first result corresponding to at least one codeword under the adjusted read voltage;

[0154] Step S40: determining a valley voltage according to the plurality of first results; the valley voltage is used as a read voltage when performing a read operation on at least one codeword.

[0155] Here, the structure of the memory device refers to the aforementioned FIG. 3 b , and the structure of the peripheral circuit refers to the aforementioned FIG. 5 , which will not be described in detail here.

[0156] In some embodiments, the peripheral circuit is configured to: before obtaining a first result corresponding to a codeword at a target read voltage, set the read mode of the memory device to a single-level read mode; the single-level read mode includes reading at least one bit of storage data stored in a memory cell through a first-level read voltage.

[0157] In some embodiments, a memory cell includes M bits, a memory device includes M pages, and an M-bit memory cell reads its M-bit stored data through an N-level read voltage; M and N are both integers greater than 1, and N=2 M -1; the peripheral circuit is configured to: for each level of the multi-level read voltage corresponding to each type of page, determine the valley voltage of each level according to multiple first results corresponding to the multiple read voltages of each level.

[0158] Exemplarily, when the number of storage bits of a memory cell includes three bits, the corresponding storage states include the 0th state to the 7th state. Referring to FIG8 , the 8 states are the 0th state E, the 1st state P1, the 2nd state P2…the 7th state P7, and the binary data corresponding to the 8 states are 111, 110, 100, 000, 010, 011, 001, and 101, respectively. Accordingly, the memory device includes three types of pages, namely, the lower page, the middle page, and the upper page. Here, the three storage bits corresponding to the 8 states are stored in the lower page, the middle page, and the upper page, respectively. Taking the memory cell shown in FIG8 as an example, the three-bit memory cell reads its three-bit storage data through a 7-level read voltage.

[0159] Exemplarily, each type of page corresponds to multiple levels of read voltages. As shown in FIG8 , the lower page corresponds to a first-level read voltage L1 and a fifth-level read voltage L5. For the first-level read voltage L1 and the fifth-level read voltage L5 corresponding to the lower page, the valley voltage of the first-level read voltage L1 can be determined based on multiple first results corresponding to the multiple read voltages of the first-level read voltage L1. Then, the valley voltage of the fifth-level read voltage L5 can be determined based on multiple first results corresponding to the multiple read voltages of the fifth-level read voltage L5. In this way, the valley voltage of each level of the multiple levels of read voltages corresponding to the lower page can be obtained.

[0160] The process of determining the valley voltage of each level of the multi-level read voltage corresponding to the middle page and the upper page is similar to that of the lower page and will not be repeated here.

[0161] In some embodiments, the peripheral circuit is configured to: read the stored data of the codeword at a target read voltage to obtain a second result; perform a first adjustment on the target read voltage, and read the stored data of the codeword at the adjusted target read voltage to obtain a third result; perform a logical operation on the second result and the third result to obtain a fourth result; and count the number of bits in the fourth result that represent the flipping of the third result compared to the second result to obtain the first result.

[0162] In some embodiments, the peripheral circuit includes: a first latch D1, a second latch D2, and a third latch D3; wherein the first latch D1 is configured to store the second result; the second latch D2 is configured to store the third result; and the third latch D3 is configured to store the fourth result.

[0163] Exemplarily, the first latch D1 , the second latch D2 , and the third latch D3 are located in a page buffer of a peripheral circuit.

[0164] In some embodiments, an XOR operation is performed on the second result and the third result to obtain a fourth result, as shown in FIG10 . The bit-1 portion of the fourth result represents the number of memory cells whose threshold voltages differ between the target read voltage V0 and the adjusted target read voltage V1. In other words, the bit-1 portion of the fourth result represents the number of bits of the codeword flipped in the two reading results at the target read voltage V0 and the adjusted target read voltage V1. Since a single-stage read mode is adopted, that is, the two reading operations mentioned above both read one bit of data stored in the lower page of the memory cell of the codeword. Therefore, the bit-1 portion of the fourth result represents the number of memory cells of the codeword flipped in the two reading results at the target read voltage V0 and the adjusted target read voltage V1. This number is recorded as the first result Y1 corresponding to the target read voltage.

[0165] In some embodiments, the peripheral circuit is configured to: when the first result corresponding to the target read voltage is less than or equal to a first preset value, perform a second adjustment on the target read voltage to obtain a target adjusted read voltage; the step size of the second adjustment is greater than the step size of the first adjustment; and obtain the first result corresponding to the codeword under the target adjusted read voltage.

[0166] For example, as shown in FIG10 , a second adjustment is performed on the target read voltage V0 to obtain a target adjusted read voltage V2. The target read voltage V0 and the target adjusted read voltage V2 have a second voltage difference ΔV2, where the magnitude of the second voltage difference is the second adjustment step size. The second adjustment step size is greater than the first adjustment step size, i.e., the second voltage difference ΔV2 is greater than the first voltage difference ΔV1.

[0167] Data stored in the lower page of the memory cell in the codeword is read at the target adjusted read voltage V2, memory cells whose threshold voltage is less than the adjusted target adjusted read voltage V2 are marked as bit 1, and memory cells whose threshold voltage is greater than the target adjusted read voltage V2 are marked as bit 0, to obtain a second result, which is stored in the first latch of the memory device.

[0168] A first adjustment is performed on the target adjusted read voltage V2, and the stored data of the codeword is read at the adjusted target adjusted read voltage (V3 shown in FIG10 ), obtaining a third result. Specifically, data stored in the lower page of the memory cells in the codeword is read at the adjusted target adjusted read voltage (V3 shown in FIG10 ), and memory cells with a threshold voltage less than the adjusted target adjusted read voltage (V3 shown in FIG10 ) are marked as bit 1, and memory cells with a threshold voltage greater than the adjusted target adjusted read voltage (V3 shown in FIG10 ) are marked as bit 0, obtaining a third result, which is stored in a second latch of the memory device.

[0169] Performing an XOR operation on the second result and the third result to obtain a fourth result; and storing the fourth result in a third latch of the memory device. For example, as shown in FIG10 , the bits set to 1 in the fourth result represent the number of memory cells whose threshold voltages differ between the target adjusted read voltage V2 and the adjusted target adjusted read voltage V3. In other words, the bits set to 1 in the fourth result represent the number of bits of the codeword that are flipped between the two read results at the target adjusted read voltage V2 and the adjusted target adjusted read voltage V3. Because a single-stage read mode is employed, i.e., both read operations read a single bit of data stored in the lower page of the codeword memory cell. Therefore, the bits set to 1 in the fourth result represent the number of memory cells whose codeword is flipped between the two read results at the target adjusted read voltage V2 and the adjusted target adjusted read voltage V3. This number is recorded as the first result Y2 corresponding to the target adjusted read voltage V2.

[0170] In some embodiments, the peripheral circuit is configured to: when the first result corresponding to at least one of the codewords under the target adjusted read voltage is less than the first preset value and greater than the second preset value, continue to perform a second adjustment on the target adjusted read voltage, and obtain the first result corresponding to the codeword under the adjusted read voltage, until the first result corresponding to the final adjusted read voltage is less than or equal to the second preset value.

[0171] In some embodiments, the peripheral circuit is configured to use the read voltage corresponding to the smallest first result among the plurality of first results as the valley voltage when the first result corresponding to the final adjusted read voltage is less than or equal to a second preset value.

[0172] For example, referring to Table 1, the first result obtained in the first iteration is 200, which can be understood as the first result corresponding to the target read voltage V0. The first result obtained in the second iteration is 160, which can be understood as the first result corresponding to the target adjusted read voltage V2. The multiple first results obtained in iterations 3 to 7 are shown in Table 1.

[0173] In some embodiments, the peripheral circuit is configured to: obtain a first preset value; the first preset value is equal to an upper limit of a fail bit count supported by the memory device.

[0174] It can be understood that the number of flipped bits is the fail bit count. In other words, the first result being less than the first preset value is equivalent to the first result being less than the upper limit of the fail bit count supported by the memory device. The first result can then be used as one of multiple first results for determining the valley voltage.

[0175] Exemplarily, the first preset value is set to 225, and the second preset value is set to 10. The read voltage corresponding to the smallest first result among the multiple first results in Table 1 is used as the valley voltage, that is, the read voltage corresponding to the first result obtained in the fourth iteration is used as the valley voltage.

[0176] It can be understood that the read voltage corresponding to the first result obtained in the fourth iteration is the valley voltage of the first-stage read voltage L1 corresponding to the lower page shown in FIG. 8 .

[0177] In some embodiments, the peripheral circuit is configured to: when the first result corresponding to the target read voltage is greater than a first preset value, adjust the target read voltage multiple times, and obtain multiple first results corresponding to the codeword under the multiple adjusted read voltages.

[0178] It should be noted that the directions and step sizes of the multiple adjustments to the target read voltage may be random, so as to randomly obtain multiple first results.

[0179] When the plurality of first results are all greater than the first preset value, the number of storage units corresponding to the codeword is adjusted, and the number of storage units corresponding to one codeword after adjustment is less than the number of storage units corresponding to one codeword before adjustment.

[0180] It can be understood that by reducing the number of storage units corresponding to the codewords, the total amount of data contained in the fourth result can be reduced. The reduction in the total amount can reduce the number of statistics from the total amount to a certain extent, that is, the first result will also be reduced, so that the first result is easier to enter the range of the first preset value.

[0181] An embodiment of the present application provides a memory system, as shown in FIG12 , wherein the memory system 102 includes: one or more memory devices 104 as described in the above embodiments; and a memory controller 106 coupled to the memory device 104 and controlling the memory device 104 .

[0182] In some embodiments, the memory controller 106 is configured to: before performing a read operation on data stored in the memory device 104, send a first instruction instructing to obtain a valley voltage; the memory device 104 is configured to: receive the first instruction, obtain the valley voltage, and send the obtained valley voltage to the memory controller 106; the memory controller 106 is further configured to: perform a read operation on the data stored in the memory device 104 based on the valley voltage; and perform an error correction code decoding operation on the read result of the read operation.

[0183] In some embodiments, the error correction code decoding operation includes a hard decoding operation using a low density parity check code (LDPC).

[0184] In this way, the memory controller directly receives the valley voltage from the memory device, reducing data transmission time between the memory controller and the memory device and reserving sufficient time for subsequent error correction code decoding of the read results. Furthermore, the memory controller directly performs a read operation and an error correction code decoding operation based on the valley voltage, shortening overall operation time.

[0185] An embodiment of the present application provides a method for operating a memory system, the method comprising:

[0186] Before performing a read operation on data stored in a memory device of a memory system, a first instruction is sent, wherein the first instruction instructs obtaining a valley voltage; the valley voltage is obtained by any of the operating methods described in the above embodiments;

[0187] performing a reading operation on data stored in the memory device according to the valley voltage;

[0188] An error correction code decoding operation is performed on a read result of the read operation.

[0189] Another embodiment of the present application provides a memory system, as shown in Figure 13, the memory system 102 includes: at least one memory device 104, the memory device 104 includes multiple memory cells, and a preset number of memory cells form a codeword; a memory controller 106, coupled to the at least one memory device 104 and configured to: obtain a first result corresponding to the at least one codeword at a target read voltage; the first result includes a number of bits flipped in two read results representing the at least one codeword at the first read voltage and the second read voltage; the difference between the first read voltage and the second read voltage is less than a preset voltage; according to the first result corresponding to the at least one codeword at the target read voltage, the target read voltage is adjusted; the first result corresponding to the at least one codeword at the adjusted read voltage is obtained; and a valley voltage is determined based on the multiple first results; the valley voltage is used as the read voltage when performing a read operation on the at least one codeword.

[0190] In some embodiments, the memory controller 106 is configured to: before performing a read operation on data stored in the memory device 104 , send a second instruction, the second instruction instructing to obtain a plurality of first results corresponding to at least one codeword under a plurality of different read voltages;

[0191] The memory device 104 is configured to: receive a second instruction, obtain a plurality of first results corresponding to the codeword at a plurality of different read voltages, and send the obtained first results to the memory controller;

[0192] The memory controller 106 is further configured to: determine a valley voltage according to a plurality of first results corresponding to a plurality of different read voltages; and perform a read operation on data stored in the memory device according to the valley voltage.

[0193] In some embodiments, the memory device 104 is configured to: read the stored data of a codeword at a target read voltage to obtain a second result; perform a first adjustment on the target read voltage and read the stored data of at least one codeword at the target read voltage to obtain a third result; perform a logical operation on the second result and the third result to obtain a fourth result; and count the number of bits in the fourth result that represent a flip of the third result compared to the second result to obtain the first result.

[0194] In some embodiments, the data volume of the first result is less than a preset data volume threshold.

[0195] 14 is a timing diagram of an exemplary reread operation provided by the present application. DQx may be represented as a data bus signal, and Cycle Type may further represent the type of the data bus signal.

[0196] As shown in FIG14 , a read command may include, for example, two sub-commands (e.g., 00h and 30h). For example, the memory device transmits the address ADDR of the data to be read (e.g., two column addresses C1-C2 and three row addresses R1-R3) between the received sub-commands 00h and 30h. After the memory device receives sub-command 30h, within the read time, the data DATA (e.g., Dn) corresponding to the page of the received address may be cached in the page buffer, and then the data DATA may be read on demand. It should be noted that in the above embodiment, when performing a reread operation, the memory device and the memory controller need to frequently transmit data corresponding to a page, and transmitting this data takes a long time.

[0197] FIG15 is a timing diagram for determining a valley voltage and performing a read operation according to an embodiment of the present application. As shown in FIG15 , in addition to a conventional read command (e.g., a read command including two sub-commands (e.g., 00h and 30h)), an embodiment of the present application also includes a second instruction, e.g., the second instruction including sub-commands EBh and xxh. In an exemplary embodiment, the memory device 104 transmits the address ADDR of the data to be read (e.g., two column addresses C1-C2 and three row addresses R1-R3) between the received sub-commands 00h and 30h. After receiving sub-command 30h, the memory device 104 receives sub-commands EBh and xxh of the second instruction. Under the direction of the second instruction, the memory device 104 obtains a first result corresponding to the codeword at the corresponding read voltage and sends the obtained first result to the memory controller. The memory controller determines the valley voltage based on the multiple first results corresponding to the multiple different read voltages received from the memory device, and performs a read operation on the data stored in the memory device based on the valley voltage.

[0198] It should be noted that the second instruction provided in the embodiments of this application is merely an example and should not unduly limit the scope of protection of this application. In some embodiments, the data size of the first result is less than a preset data size threshold, for example, the data size of the first result ranges from 1 byte to 4 bytes. Therefore, during the process of determining the valley voltage, the amount of data transmitted between the memory device and the memory controller is small and the speed is fast, which is conducive to improving the overall speed of the read operation.

[0199] Another embodiment of the present application provides an operating method for a memory system, comprising: obtaining a first result corresponding to at least one codeword at a target read voltage; the first result includes a representation of the number of bits flipped in two read results of the at least one codeword at the first read voltage and the second read voltage; the difference between the first read voltage and the second read voltage is less than a preset voltage; the memory system comprises at least one memory device, the memory device comprises a plurality of storage cells, and a preset number of storage cells form a codeword; adjusting the target read voltage based on the first result corresponding to the at least one codeword at the target read voltage; obtaining a first result corresponding to the at least one codeword at the adjusted read voltage; determining a valley voltage based on the plurality of first results; the valley voltage being used as a read voltage when performing a read operation on the at least one codeword.

[0200] In some embodiments, the method further includes: before performing a read operation on data stored in a memory device of the memory system, sending a second instruction, the second instruction instructing to obtain multiple first results corresponding to the codeword at multiple different read voltages; determining a valley voltage based on the multiple first results corresponding to the multiple different read voltages; and performing a read operation on the data stored in the memory device based on the valley voltage.

[0201] In some embodiments, the data volume of the first result is less than a preset data volume threshold, for example, the data volume of the first result ranges from 1 byte to 4 bytes. Therefore, in the process of determining the valley voltage, the amount of data transmitted between the memory device and the memory controller is small and the speed is fast, which is conducive to improving the overall speed of the read operation.

[0202] In some embodiments, the method further includes: reading the stored data of the codeword at a target read voltage to obtain a second result; performing a first adjustment on the target read voltage, and reading the stored data of the codeword at the adjusted target read voltage to obtain a third result; performing a logical operation on the second result and the third result to obtain a fourth result; and counting the number of bits in the fourth result that represent the flipping of the third result compared to the second result to obtain the first result.

[0203] Exemplarily, the second result and the third result are XORed to obtain a fourth result. Since a single-stage read mode is employed, i.e., both read operations performed at the target read voltage and the adjusted target read voltage read one bit of data stored in the lower page of the memory cell of the codeword, the bits that are 1 in the fourth result represent the number of bits or memory cells in which the codeword is flipped in the two read results at the target read voltage and the adjusted target read voltage.

[0204] Exemplarily, the first preset value is set to 225, and the second preset value is set to 10. The read voltage corresponding to the smallest first result among the multiple first results in Table 1 is used as the valley voltage, that is, the read voltage corresponding to the first result obtained in the fourth iteration is used as the valley voltage.

[0205] It can be understood that the read voltage corresponding to the first result obtained in the fourth iteration is the valley voltage of the first-stage read voltage L1 corresponding to the lower page shown in FIG. 8 .

[0206] It should be noted that the process of confirming the valley voltage of the multi-level read voltage corresponding to each type of page is similar to the method disclosed in the above embodiment, and will not be repeated here.

[0207] Another embodiment of the present application provides a memory device, as shown in Figure 5, which includes: a memory cell array 301, including multiple memory cells, a preset number of memory cells forming a codeword; a peripheral circuit, coupled to the memory cell array 301, including control logic 512 and a page buffer 504; the control logic 512 is configured to: read the stored data of at least one codeword at a first read voltage to obtain a second result, and store the second result in a first latch of the page buffer; adjust the first read voltage to obtain a second read voltage, read the stored data of the codeword at the second read voltage to obtain a third result, and store the third result in a second latch of the page buffer; the difference between the first read voltage and the second read voltage is less than a preset voltage; perform a logical operation on the second result and the third result to obtain a fourth result, and store the fourth result in the third latch of the page buffer; and count the number of bits in the fourth result that represent that the third result is flipped compared to the second result to obtain the first result.

[0208] Yet another embodiment of the present application provides a method for operating a memory device, the method comprising:

[0209] The stored data of the codeword is read at a first read voltage to obtain a second result, and the second result is stored in a first latch of the page buffer; the memory device includes a memory cell array and a page buffer, the memory cell array includes a plurality of memory cells, and a preset number of memory cells form a codeword; the first read voltage is adjusted to obtain a second read voltage, the stored data of the codeword is read at the second read voltage to obtain a third result, and the third result is stored in a second latch of the page buffer; the difference between the first read voltage and the second read voltage is less than a preset voltage; a logical operation is performed on the second result and the third result to obtain a fourth result, and the fourth result is stored in a third latch of the page buffer; the number of bits in the fourth result that represent the flipping of the third result compared to the second result is counted to obtain the first result.

[0210] Here and in the previous embodiment, the difference between the first read voltage and the second read voltage is less than the preset voltage, which can be understood as the first read voltage and the second read voltage having a smaller voltage difference. In some specific embodiments, the preset voltage range is set to 6mV to 21mV. For example, the preset voltage can be 6mV, 11mV, 16mV, or 21mV. The first results have the same meaning as the aforementioned first results, that is, they all include the number of bits that are flipped in the two read results at the first read voltage and the second read voltage that represent at least one codeword. It should be noted that the first result here, or the acquisition process of the FBC between the two read voltages with a very close voltage difference, can be packaged inside the memory device and accelerated by the page buffer in the memory device.

[0211] It should be noted that the concepts mentioned here and in the previous embodiment that are the same as those in the previous embodiment can be understood with reference to the description in the previous embodiment and will not be repeated here. Furthermore, the first result finally obtained in this and the previous embodiment can also be used in many scenarios beyond determining the valley voltage described above. For example, it can be used to determine the offset of a memory cell in a memory device.

[0212] Referring to FIG16 , FIG16 is a block diagram of a computer-readable storage medium provided in an embodiment of the present application. As shown in FIG16 , an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium 200 stores a computer program 210. When executed by a processor, the computer program 210 can implement a method for operating a memory system as described in the above technical solution. The method includes: obtaining a first result corresponding to at least one codeword at a target read voltage; the first result is used to represent the number of bits flipped in two read results of the at least one codeword at the first read voltage and the second read voltage; the difference between the first read voltage and the second read voltage is less than a preset voltage; the memory system includes at least one memory device, the memory device includes a plurality of memory cells, and the preset number of memory cells form a codeword; adjusting the target read voltage based on the first result corresponding to the at least one codeword at the target read voltage; obtaining a first result corresponding to the at least one codeword at the adjusted read voltage; determining a valley voltage based on the plurality of first results; and using the valley voltage as a read voltage when performing a read operation on the at least one codeword.

[0213] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. The above-mentioned serial numbers of the embodiments of the present application are for description only and do not represent the advantages and disadvantages of the embodiments.

[0214] The above description is only a preferred embodiment of the present application and does not limit the patent scope of the present application. All equivalent structural transformations made by using the contents of the present application description and drawings under the inventive concept of the present application, or direct / indirect application in other related technical fields are included in the patent protection scope of the present application. Industrial Applicability

[0215] The memory device and operating method thereof, as well as the memory system and operating method thereof, provided in the embodiments of the present application, effectively avoid the time-consuming and incomplete scenario coverage issues associated with using a trial-and-error table. This saves space occupied by the trial-and-error table, allows for faster and more accurate determination of the valley voltage, and effectively reduces the latency associated with determining the valley voltage. Furthermore, performing a read operation based on the obtained valley voltage significantly increases the probability of correctly reading stored data, improving product reliability and user experience.

Claims

1. A memory device, comprising: A memory cell array including a plurality of memory cells, and a preset number of the memory cells form a codeword; Peripheral circuits coupled to the memory cell array and configured to: Obtain a first result corresponding to at least one of the codewords at a target read voltage; the first result includes the number of bits that are flipped in the two read results of at least one of the codewords at a first read voltage and a second read voltage; The difference between the first read voltage and the second read voltage is less than a preset voltage; Adjust the target read voltage according to the first result corresponding to at least one of the codewords at the target read voltage; Obtain a first result corresponding to at least one of the codewords at the adjusted read voltage; Determine a valley voltage according to a plurality of the first results; the valley voltage is used as a read voltage when performing a read operation on at least one of the codewords.

2. The memory device according to claim 1, wherein, The peripheral circuits are configured to: Read the stored data of at least one of the codewords at the target read voltage to obtain a second result; Perform a first adjustment on the target read voltage, and read the stored data of at least one of the codewords at the adjusted target read voltage to obtain a third result; Perform a logical operation on the second result and the third result to obtain a fourth result; Count the number of bits in the fourth result that indicate that the third result is flipped compared to the second result to obtain a first result.

3. The memory device according to claim 2, wherein, The peripheral circuits include: a first latch, a second latch, and a third latch; The first latch is configured to store the second result; The second latch is configured to store the third result; The third latch is configured to store the fourth result.

4. The memory device according to claim 2, wherein, The peripheral circuits are configured to: When the first result corresponding to the target read voltage is less than or equal to a first preset value, perform a second adjustment on the target read voltage to obtain a target adjusted read voltage; the step size of the second adjustment is greater than the step size of the first adjustment; Obtain a first result corresponding to at least one of the codewords at the target adjusted read voltage.

5. The memory device according to claim 4, wherein, The peripheral circuits are configured to: When the first result corresponding to at least one of the codewords at the target adjusted read voltage is less than the first preset value and greater than a second preset value, continue to perform a second adjustment on the target adjusted read voltage, and obtain a first result corresponding to at least one of the codewords at the adjusted read voltage until the first result corresponding to the finally adjusted read voltage is less than or equal to the second preset value.

6. The memory device according to claim 5, wherein, The peripheral circuits are configured to: When the first result corresponding to the finally adjusted read voltage is less than or equal to the second preset value, use the read voltage corresponding to the first result with the smallest counted number in the first results as the valley voltage.

7. The memory device according to claim 2, wherein, The peripheral circuits are configured to: When the first result corresponding to the target read voltage is greater than the first preset value, perform multiple adjustments on the target read voltage, and obtain a plurality of first results respectively corresponding to at least one of the codewords at the read voltages after multiple adjustments; When all of the multiple first results are greater than the first preset value, adjust the number of memory cells corresponding to at least one of the codewords, and the number of memory cells corresponding to one codeword after adjustment is less than the number of memory cells corresponding to one codeword before adjustment.

8. The memory device according to claim 4 or 7, wherein, The peripheral circuit is configured to: Obtain the first preset value; the first preset value is equal to the upper limit of the failure bit count supported by the memory device.

9. The memory device according to claim 1, wherein, The peripheral circuit is configured to: Before obtaining the first result corresponding to at least one of the codewords at a target read voltage, set the read mode of the memory device to a single-level read mode; the single-level read mode includes reading at least one bit of stored data stored in the memory cell through a first-order read voltage.

10. The memory device according to claim 9, wherein, The storage unit includes M bits, the memory device includes M types of pages, and the M-bit storage unit reads its M-bit stored data through N-order read voltages; both M and N are integers greater than 1, and N = 2 M -1; The peripheral circuit is configured to: For each order of the multi-order read voltages corresponding to each type of page, determine the valley voltage of each order according to the multiple first results corresponding to the multiple read voltages of each order.

11. A memory system, comprising: One or more memory devices according to any one of claims 1 to 10; And A memory controller coupled to the memory device and controlling the memory device.

12. The memory system according to claim 11, wherein The memory controller is configured to: before reading data stored in the memory device, send a first instruction, and the first instruction instructs to obtain a valley voltage; The memory device is configured to: receive the first instruction, obtain the valley voltage, and send the obtained valley voltage to the memory controller; The memory controller is further configured to: perform a read operation on the data stored in the memory device according to the valley voltage; Perform an error correction code decoding operation on the read result of the read operation.

13. A memory system, comprising: At least one memory device, the memory device includes a plurality of memory cells, and a preset number of the memory cells form a codeword; A memory controller coupled to the at least one memory device and configured to: Obtain a first result corresponding to at least one of the codewords at a target read voltage; the first result includes the number of bits that flip in the two read results of at least one of the codewords at a first read voltage and a second read voltage; The difference between the first read voltage and the second read voltage is less than a preset voltage; Adjust the target read voltage according to the first result corresponding to at least one of the codewords at the target read voltage; Obtain a first result corresponding to at least one of the codewords at the adjusted read voltage; Determine a valley voltage according to the multiple first results; the valley voltage is used as a read voltage when performing a read operation on at least one of the codewords.

14. The memory system according to claim 13, wherein The memory controller is configured to: Before reading data stored in the memory device, send a second instruction, and the second instruction instructs to obtain multiple first results corresponding to at least one of the codewords at multiple different read voltages; The memory device is configured to: receive the second instruction, obtain a plurality of first results corresponding to at least one of the codewords at a plurality of different read voltages, and send the obtained first results to the memory controller; The memory controller is further configured to: determine a valley voltage according to the plurality of first results respectively corresponding to the plurality of different read voltages; perform a read operation on the data stored in the memory device according to the valley voltage.

15. The memory system according to claim 14, wherein, The memory device is configured to: read the stored data of at least one of the codewords at the target read voltage to obtain a second result; Perform a first adjustment on the target read voltage, and read the stored data of at least one of the codewords at the target read voltage to obtain a third result; Perform a logical operation on the second result and the third result to obtain a fourth result; Count the number of bits in the fourth result that represent the third result being flipped compared to the second result to obtain a first result.

16. The memory system according to claim 13, wherein, The data volume of the first result is less than a preset data volume threshold.

17. An operation method of a memory device, including: Obtain a first result corresponding to at least one codeword at a target read voltage; The first result includes the number of bits that represent a flip in the two read results of at least one of the codewords at a first read voltage and a second read voltage; the difference between the first read voltage and the second read voltage is less than a preset voltage; The memory device includes a memory cell array, the memory cell array includes a plurality of memory cells, and a preset number of the memory cells form one of the codewords; Adjust the target read voltage according to the first result corresponding to at least one of the codewords at the target read voltage; Obtain a first result corresponding to at least one of the codewords at the adjusted read voltage; Determine a valley voltage according to the plurality of first results; the valley voltage is used as the read voltage when performing a read operation on at least one of the codewords.

18. The operating method according to claim 17, wherein, Obtaining a first result corresponding to at least one codeword at a target read voltage includes: Read the stored data of at least one of the codewords at the target read voltage to obtain a second result; Perform a first adjustment on the target read voltage, and read the stored data of at least one of the codewords at the adjusted target read voltage to obtain a third result; Perform a logical operation on the second result and the third result to obtain a fourth result; Count the number of bits in the fourth result that represent the third result being flipped compared to the second result to obtain a first result.

19. The operating method according to claim 18, wherein, The method further includes: Store the second result in a first latch of the memory device, Store the third result in a second latch of the memory device; Store the fourth result in a third latch of the memory device.

20. The operating method according to claim 18, wherein The adjusting the target read voltage according to the first result corresponding to at least one of the codewords at the target read voltage includes: When the first result corresponding to the target read voltage is less than or equal to the first preset value, perform a second adjustment on the target read voltage to obtain a target adjusted read voltage; the step size of the second adjustment is greater than the step size of the first adjustment. Obtain the first results corresponding to at least one of the codewords at the target adjusted read voltage.

21. The operating method according to claim 20, wherein, The method further includes: When the first results corresponding to at least one of the codewords at the target adjusted read voltage are less than the first preset value and greater than the second preset value, continue to perform a second adjustment on the target adjusted read voltage and obtain the first results corresponding to at least one of the codewords at the adjusted read voltage until the first result corresponding to the finally adjusted read voltage is less than or equal to the second preset value.

22. The operating method according to claim 21, wherein, The determining the valley voltage according to the plurality of first results includes: When the first result corresponding to the finally adjusted read voltage is less than or equal to the second preset value, use the read voltage corresponding to the smallest first result among the first results as the valley voltage.

23. The operating method according to claim 17, wherein, The method further includes: When the first result corresponding to the target read voltage is greater than the first preset value, perform multiple adjustments on the target read voltage and obtain a plurality of first results corresponding to at least one of the codewords at the read voltages after multiple adjustments. When the plurality of first results are all greater than the first preset value, adjust the number of memory cells corresponding to at least one of the codewords, and the number of memory cells corresponding to one codeword after adjustment is less than the number of memory cells corresponding to one codeword before adjustment.

24. The operating method according to claim 20 or 23, wherein, The method further includes: Obtain the first preset value; the first preset value is equal to the upper limit of the failure bit count supported by the memory device.

25. The operating method according to claim 19, wherein, The method further includes: Before obtaining the first results corresponding to at least one of the codewords at the target read voltage, set the read mode of the memory device to a single-level read mode; the single-level read mode includes reading at least one bit of stored data stored in the memory cell through a first-order read voltage.

26. The operating method according to claim 25, wherein, The storage unit includes M bits, the memory device includes M types of pages, and the M-bit storage unit reads its M-bit stored data through N-level read voltages; both M and N are integers greater than 1, and N = 2 M - 1; The method further includes: For each order of the multi-order read voltages corresponding to each type of page, determine the valley voltage of each order according to the plurality of first results corresponding to the plurality of read voltages of each order.

27. An operation method of a memory system, including: Before performing a read operation on the data stored in the memory device of the memory system, send a first instruction, and the first instruction instructs to obtain the valley voltage. The valley voltage is obtained according to the operation method according to any one of claims 17 to 26. Perform a read operation on the data stored in the memory device according to the valley voltage. Perform an error correction code decoding operation on the read result of the read operation.

28. An operation method of a memory system, including: Obtain the first result corresponding to the codeword at the target read voltage. The first result includes the number of bits that flip in the two read results of at least one of the codewords at a first read voltage and a second read voltage; the difference between the first read voltage and the second read voltage is less than a preset voltage; the memory system includes at least one memory device, the memory device includes a plurality of memory cells, and a preset number of the memory cells form one of the codewords; Adjust the target read voltage according to the first result corresponding to at least one of the codewords at the target read voltage; Obtain the first result corresponding to at least one of the codewords at the adjusted read voltage; Determine a valley voltage according to a plurality of the first results; the valley voltage is used as the read voltage when performing a read operation on at least one of the codewords.

29. The operating method according to claim 28, wherein, The method further includes: Before performing a read operation on the data stored in the memory device of the memory system, send a second instruction, and the second instruction instructs to obtain the first result corresponding to at least one of the codewords at different read voltages; Determine a valley voltage according to a plurality of the first results respectively corresponding to a plurality of different read voltages; perform a read operation on the data stored in the memory device according to the valley voltage.

30. The operating method according to claim 29, wherein, The method further includes: Read the stored data of at least one of the codewords at the target read voltage to obtain a second result; Perform a first adjustment on the target read voltage, and read the stored data of at least one of the codewords at the adjusted target read voltage to obtain a third result; Perform a logical operation on the second result and the third result to obtain a fourth result; Count the number of bits in the fourth result that indicate that the third result has flipped compared to the second result to obtain a first result.

31. A memory device, comprising: A memory cell array including a plurality of memory cells, and a preset number of the memory cells form one of the codewords; Peripheral circuits coupled to the memory cell array, including control logic and a page buffer; The control logic is configured to: Read the stored data of at least one of the codewords at a first read voltage to obtain a second result, and store the second result in a first latch of the page buffer; Adjust the first read voltage to obtain a second read voltage, read the stored data of at least one of the codewords at the second read voltage to obtain a third result, and store the third result in a second latch of the page buffer; The difference between the first read voltage and the second read voltage is less than a preset voltage; Perform a logical operation on the second result and the third result to obtain a fourth result, and store the fourth result in a third latch of the page buffer; Count the number of bits in the fourth result that indicate that the third result has flipped compared to the second result to obtain a first result.

32. A method for operating a memory device, wherein, The method includes: Read the stored data of the codeword at a first read voltage to obtain a second result, and store the second result in a first latch of the page buffer; the memory device includes a memory cell array and a page buffer, the memory cell array includes a plurality of memory cells, and a preset number of the memory cells form one codeword; Adjust the first read voltage to obtain a second read voltage, read the stored data of at least one of the codewords at the second read voltage to obtain a third result, and store the third result in a second latch of the page buffer; the difference between the first read voltage and the second read voltage is less than a preset voltage; Perform a logical operation on the second result and the third result to obtain a fourth result, and store the fourth result in a third latch of the page buffer; Count the number of bits in the fourth result that represent a flip of the third result compared to the second result to obtain a first result.

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