Two-stage analog-to-digital converter for synchronous clock calibration and asynchronous clock quantization

Abstract

Disclosed in the present invention is a two-stage analog-to-digital converter for synchronous clock calibration and asynchronous clock quantization, comprising: an asynchronous control clock, a synchronous control clock, a residual voltage amplifier, and a two-stage analog-to-digital converter for quantizing an input signal. The quantization of each input signal performed by the two-stage analog-to-digital converter is controlled by the asynchronous control clock, and the capacitance calibration performed by the two-stage analog-to-digital converter is controlled by the synchronous control clock; in this way, the reliability and accuracy of capacitance calibration are guaranteed to a great extent, and the quantization speed of the analog-to-digital converter is also ensured. By using an adjustable frequency oscillator as the synchronous control clock, the settling time of each capacitor and the calculation time of a capacitance weight are flexibly adjusted, such that the settling time of the capacitor and the calculation time of the capacitance weight can be modified according to requirements.

Description

A two-stage analog-to-digital converter with synchronous clock calibration and asynchronous clock quantization Technical Field

[0001] The present invention relates to the field of analog-to-digital converters, in particular to a two-stage analog-to-digital converter with synchronous clock calibration and asynchronous clock quantization. Background Art

[0002] With the rapid development of modern communication technology, the demand for analog-to-digital converters (ADCs) in the communications field continues to increase, posing new challenges to the speed and accuracy of ADCs. To increase the quantization rate of ADCs, asynchronous control logic is currently widely used. Asynchronous control automatically advances to the quantization of the next capacitor after each capacitor is quantized, significantly saving quantization time. However, in the design of second-stage ADCs, an unavoidable problem is the capacitor mismatch generated during the manufacturing process. Therefore, capacitor calibration is generally required in the design of second-stage ADCs. During the capacitor calibration process, if a single capacitor is calculated incorrectly due to the asynchronous control logic, the overall calibration accuracy will be reduced. Therefore, traditional asynchronous ADCs have certain drawbacks in terms of capacitor calibration. Technical issues

[0003] To overcome the shortcomings of the prior art, the present invention provides a two-stage analog-to-digital converter with synchronous clock calibration and asynchronous clock quantization. A synchronous clock is used for capacitance calibration, while an asynchronous clock is used for control during normal operation of the analog-to-digital converter. This greatly ensures the reliability of capacitance calibration and the quantization speed of the analog-to-digital converter. Technical Solutions

[0004] To achieve the above objectives, the present invention provides a two-stage analog-to-digital converter with synchronous clock calibration and asynchronous clock quantization, characterized in that it includes an asynchronous control clock, a synchronous control clock, and a two-stage analog-to-digital converter for quantizing a VIN input signal; when the two-stage analog-to-digital converter quantizes the VIN input signal, it is controlled by the asynchronous control clock; when the two-stage analog-to-digital converter calibrates the capacitor, it is controlled by the synchronous control clock.

[0005] Furthermore, the synchronous control clock is an oscillator with adjustable frequency.

[0006] Furthermore, in the asynchronous control clock logic, the sampling end signal is used as the quantization start signal; after the sampling is completed, the VALID signal is pulled low, and the comparator of the two-stage analog-to-digital converter enters the first comparison cycle. The VALID signal is provided to the comparator after a certain delay and used as the comparison clock of the comparator, so that after the comparison of each capacitor is completed, the comparison of the next capacitor is automatically entered; the VALID signal is generated by performing a NOT logic on the comparison result of the comparator.

[0007] Furthermore, when the comparator is in a reset state, the VALID signal is pulled high, and after the comparator compares once, the VALID signal will flip automatically; the VALID signal can indicate whether the comparator has completed the comparison.

[0008] Furthermore, during capacitor calibration, the capacitors in the two-stage analog-to-digital converter are calibrated using a synchronous control clock to control the frequency of the synchronous control clock and flexibly adjust the setup time of each bit of capacitor and the calculation time of the capacitor weight; after the capacitor calibration is completed, the calibration completion signal is pulled high to indicate that the two-stage analog-to-digital converter has entered the normal quantization mode.

[0009] Furthermore, the two-stage analog-to-digital converter includes a first-stage analog-to-digital converter, a second-stage analog-to-digital converter and an amplifier; the first-stage analog-to-digital converter quantizes the input signal, the amplifier amplifies the residual voltage signal generated after the first-stage analog-to-digital converter quantizes the VIN signal, and the second-stage analog-to-digital converter quantizes the amplified residual voltage signal.

[0010] Furthermore, the asynchronous control clock controls the quantization of the input signal by the first-stage analog-to-digital converter and the second-stage analog-to-digital converter of the two-stage analog-to-digital converter through the third digital control circuit and the fourth digital control circuit respectively; the synchronous control clock controls the capacitance calibration in the first-stage analog-to-digital converter and the second-stage analog-to-digital converter of the two-stage analog-to-digital converter through the first digital control circuit and the second digital control circuit respectively.

[0011] Furthermore, the asynchronous control clock and the synchronous control clock are electrically connected to a synchronous-asynchronous alternating control circuit; the synchronous-asynchronous alternating control circuit controls the alternating output of the asynchronous control clock and the synchronous control clock, and when the capacitance of the two-stage analog-to-digital converter is calibrated, the synchronous-asynchronous alternating control circuit outputs the signal of the synchronous control clock to the two-stage analog-to-digital converter; when the two-stage analog-to-digital converter quantizes the VIN input signal, the synchronous-asynchronous alternating control circuit outputs the signal of the asynchronous control clock to the two-stage analog-to-digital converter. Beneficial effects

[0012] The present invention discloses a two-stage analog-to-digital converter with synchronous clock calibration and asynchronous clock quantization. During the capacitor calibration process, a synchronous clock is used for calibration. When the analog-to-digital converter is operating normally, an asynchronous clock is used to control the signal quantization. This greatly ensures the reliability and accuracy of the capacitor calibration and the quantization speed of the analog-to-digital converter. An oscillator with an adjustable frequency is used as the synchronous control clock to flexibly adjust the settling time of each bit of capacitance and the calculation time of the capacitance weight. The settling time of the capacitance and the calculation time of the capacitance weight can be changed according to demand. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 shows a schematic diagram of a two-stage analog-to-digital converter with synchronous clock calibration and asynchronous clock quantization;

[0014] Figure 2 is a schematic diagram of a single capacitor connection method;

[0015] Figure 3 is a timing diagram of an asynchronous control clock;

[0016] Figure 4 is a schematic diagram of the basic architecture of an analog-to-digital converter;

[0017] Figure 5 shows a timing diagram of a two-stage analog-to-digital converter with synchronous clock calibration and asynchronous clock quantization;

[0018] Figure 6 is a synchronous and asynchronous alternating control circuit diagram. Modes for Carrying Out the Invention

[0019] The present invention will be further described below with reference to the accompanying drawings.

[0020] As shown in Figure 1, a two-stage analog-to-digital converter with synchronous clock calibration and asynchronous clock quantization includes an asynchronous control clock 1, a synchronous control clock 2, and a two-stage analog-to-digital converter 3 that quantizes the VIN input signal; when the two-stage analog-to-digital converter 3 quantizes the VIN input signal, it is controlled by the asynchronous control clock 1; when the two-stage analog-to-digital converter 3 calibrates the capacitor, it is controlled by the synchronous control clock 2.

[0021] As shown in FIG1 , the two-stage analog-to-digital converter 3 includes a first-stage analog-to-digital converter 31, a second-stage analog-to-digital converter 32, and an amplifier 33; the first-stage analog-to-digital converter 31 quantizes the VIN input signal, the amplifier 33 amplifies the residual voltage signal generated after the first-stage analog-to-digital converter 31 quantizes the VIN signal, and the second-stage analog-to-digital converter 32 quantizes the amplified residual voltage signal.

[0022] The amplifier 33 is a fixed gain amplifier;

[0023] The synchronous control clock 2 is an oscillator with adjustable frequency.

[0024] As shown in FIG1 , in the asynchronous control clock (1) logic, the sampling end signal is used as the quantization start signal; after the sampling is completed, the VALID signal is pulled low, and the comparator of the two-stage analog-to-digital converter (3) enters the first comparison cycle. The VALID signal is used to provide the comparator with a certain delay and used as the comparison clock of the comparator, so that after each capacitor comparison is completed, the next capacitor comparison is automatically entered; the VALID signal is generated by performing a NOT logic on the comparison result of the comparator.

[0025] As shown in Figure 1, the asynchronous control clock 1 controls the quantization of the input signal by the first-stage analog-to-digital converter 31 and the second-stage analog-to-digital converter 32 of the two-stage analog-to-digital converter 3 through the third digital control circuit 6 and the fourth digital control circuit 7 respectively; the synchronous control clock 2 controls the capacitance calibration in the first-stage analog-to-digital converter 31 and the second-stage analog-to-digital converter 32 of the two-stage analog-to-digital converter 3 through the first digital control circuit 4 and the second digital control circuit 5 respectively.

[0026] As shown in Figure 1, when the first-stage analog-to-digital converter 1 samples the input signal, the positive terminal voltage signal of the VIN signal is input to one side plate of the first upper capacitor array through the sampling switch, and the negative terminal voltage signal of the VIN signal is input to one side plate of the first lower capacitor array through the sampling switch. The other plate of the first upper capacitor array and the other plate of the first lower capacitor array are both electrically connected to the third digital control circuit 6; the positive and negative terminal voltage signals of the VIN signal are respectively input to the positive and negative input terminals of the first comparator, and the output terminal of the first comparator outputs a signal to the third digital control circuit 6. The positive and negative input terminals of the first comparator are respectively electrically connected to the positive and negative input terminals of the amplifier 33.

[0027] When the second-stage analog-to-digital converter 2 receives the residual voltage signal, the positive terminal voltage signal of the residual voltage signal after amplification by the amplifier 33 is input to one side plate of the second upper capacitor array through the sampling switch, and the negative terminal voltage signal of the residual voltage signal after amplification by the amplifier 33 is input to one side plate of the second lower capacitor array through the sampling switch. The other plate of the second upper capacitor array and the other plate of the second lower capacitor array are both electrically connected to the fourth digital control circuit 7; the positive and negative terminal voltage signals of the residual voltage signal after amplification by the amplifier 3 are respectively input to the positive and negative input terminals of the second comparator, and the output terminal of the second comparator outputs a signal to the fourth digital control circuit 7.

[0028] As shown in FIG1 , the first comparator compares the positive terminal voltage signal and the negative terminal voltage signal of the VIN signal. When the positive terminal voltage signal is greater than the negative terminal voltage signal, the first comparator outputs 1. When the positive terminal voltage signal is less than or equal to the negative terminal voltage signal, the first comparator outputs 0. The second comparator compares the positive terminal voltage signal and the negative terminal voltage signal of the residual voltage signal after amplification by the amplifier 33. When the positive terminal voltage signal is greater than the negative terminal voltage signal, the second comparator outputs 1. When the positive terminal voltage signal is less than or equal to the negative terminal voltage signal, the second comparator outputs 0.

[0029] As shown in Figure 2, during the sampling process, the upper plate of the capacitor is connected to the VIN signal through the sampling switch S0, and the lower plate of the capacitor is connected to the VREFP reference high voltage, VREFN reference low voltage and VCM common mode voltage through the first setting switch S1, the second setting switch S2 and the third setting switch S3 respectively.

[0030] As shown in FIG3 , in the logic of the asynchronous control clock 1, the sampling end signal serves as the quantization start signal; after sampling is completed, the VALID signal is pulled low, and the comparator of the two-stage analog-to-digital converter 3 enters the first comparison cycle. The VALID signal is used to provide the comparator with a certain delay and serves as the comparison clock of the comparator, so that after each capacitor comparison is completed, the next capacitor comparison is automatically started; the VALID signal is generated by performing a NAND logic on the comparison result of the comparator; when the comparator is in the reset state, the VALID signal is pulled high, and after the comparator compares the result once, the VALID signal will automatically flip; the VALID signal can indicate whether the comparator has completed the comparison; therefore, the length of time it takes for the capacitor to establish depends on the comparison speed of the comparator and the delay provided in the circuit.

[0031] In normal quantization mode, asynchronous control clock 1 logic is used to increase the quantization speed of the analog-to-digital converter.

[0032] The idea behind calibration is to use the lower capacitor and the comparator as a small analog-to-digital converter to quantify the actual size of the higher capacitor.

[0033] As shown in Figure 4, assuming the calibration of capacitor C1 is used as an example, during the calibration process, during the sampling phase, the upper plate switch of capacitor C1 is short-circuited and connected to the VCM common-mode voltage. Except for the lower plate switch of capacitor C1P, which is connected to the positive voltage of the VIN signal, the lower plate switches of all other capacitors are all connected to the VCM common-mode voltage. After the sampling is completed, the lower plate switch of capacitor C1P is connected to the VCM common-mode voltage, while the other switches remain connected to the VCM common-mode voltage. At this time, the positive terminal voltage of the comparator is the voltage value of the flipped capacitor C1P. The flipped voltage of capacitor C1P is quantized by capacitor C0, that is, the capacitance weight of capacitor C0 * the quantization result. At this point, the actual capacitance value of capacitor C1P can be obtained. Similarly, the true weights of other capacitors can also be calculated.

[0034] It can be seen from this that the three processes of sampling establishment time, capacitance establishment time, and weight calculation all require time control. The delay time in the asynchronous control logic is relatively fixed, and it is impossible to flexibly control the two periods of time, capacitance establishment time and weight calculation time, resulting in unsatisfactory capacitance calibration effect in the completely asynchronous control clock 1 logic; therefore, a synchronous control clock 2 is used to calibrate the capacitance in the two-stage analog-to-digital converter 3.

[0035] As shown in Figures 1-5, during capacitance calibration, the capacitors in the two-stage analog-to-digital converter 3 are calibrated using a synchronous control clock 2, the frequency of the synchronous control clock 2 is controlled, and the setup time of each bit of capacitance and the calculation time of the capacitance weight are flexibly adjusted; after the capacitance calibration is completed, the calibration completion signal is pulled high to indicate that the two-stage analog-to-digital converter 3 has entered the normal quantization mode.

[0036] As shown in Figure 6, the asynchronous control clock 1 and the synchronous control clock 2 are electrically connected to the synchronous-asynchronous alternating control circuit; the synchronous-asynchronous alternating control circuit controls the alternating output of the asynchronous control clock 1 and the synchronous control clock 2. When the capacitance of the two-stage analog-to-digital converter 3 is calibrated, the synchronous-asynchronous alternating control circuit outputs the signal of the synchronous control clock 2 to the two-stage analog-to-digital converter 3; when the two-stage analog-to-digital converter 3 quantizes the VIN input signal, the synchronous-asynchronous alternating control circuit outputs the signal of the asynchronous control clock 1 to the two-stage analog-to-digital converter 3.

[0037] As shown in Figure 6, the synchronous-asynchronous alternating control circuit consists of a controller controlled by MOD_CALI and a group of no less than five D flip-flops. MOD_CALI controls whether the analog-to-digital converter is in the calibration state or the quantization state. CLK_CALI is the synchronous control clock 2 used for calibration, and CLK_ASCY is the VALID asynchronous control clock 1 used for quantization. Using this circuit can efficiently solve the problem of synchronous-asynchronous clock switching, thereby realizing the use of synchronous clock for capacitance calibration and the use of asynchronous clock for normal quantization. Example

[0038] As shown in Figures 1-5, before the two-stage analog-to-digital converter 3 quantizes the VIN signal, the capacitors in the two-stage analog-to-digital converter 3 are calibrated by using an adjustable frequency oscillator as a synchronous control clock 2, flexibly adjusting the settling time of each bit of capacitance and the calculation time of the capacitance weight; by changing the frequency of the synchronous control clock 2 to achieve the required capacitance settling time and capacitance weight calculation time, the capacitance settling time and capacitance weight calculation time can be changed as needed;

[0039] After the capacitance calibration in the two-stage analog-to-digital converter 3 is completed, the two-stage analog-to-digital converter 3 samples the electrical signal again. After the sampling is completed, the two-stage analog-to-digital converter 3 is controlled by the asynchronous control clock 1 to quantize the sampled signal;

[0040] After the input signal is quantized, the capacitance in the two-stage analog-to-digital converter 3 can be calibrated by the synchronous control clock 2 to facilitate the two-stage analog-to-digital converter 3 to quantize the sampled signal next time.

[0041] As shown in Figures 1-6, when the capacitance of the two-stage analog-to-digital converter 3 is calibrated, the MOD_CALI controller in the synchronous-asynchronous alternating control circuit controls the CLK_CALI synchronous control clock 2 to output a signal which is input into the two-stage analog-to-digital converter 3 through a group of D flip-flops for capacitance calibration; when the two-stage analog-to-digital converter 3 quantizes the electrical signal, the MOD_CALI controller in the synchronous-asynchronous alternating control circuit controls the CLK_ASCY asynchronous control clock 1 to output a signal which is input into the two-stage analog-to-digital converter 3 through a group of D flip-flops for quantizing the input signal.

[0042] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as within the scope of protection of the present invention.

Claims

1. A two-stage analog-to-digital converter with synchronous clock calibration and asynchronous clock quantization, characterized in that: The invention comprises an asynchronous control clock (1), a synchronous control clock (2) and a two-stage analog-to-digital converter (3) for quantizing a VIN input signal; when the two-stage analog-to-digital converter (3) quantizes the VIN input signal, it is controlled by the asynchronous control clock (1); when the two-stage analog-to-digital converter (3) calibrates the capacitance, it is controlled by the synchronous control clock (2).

2. A two-stage analog-to-digital converter with synchronous clock calibration and asynchronous clock quantization according to claim 1, characterized in that: The synchronous control clock (2) is an oscillator with adjustable frequency.

3. A two-stage analog-to-digital converter with synchronous clock calibration and asynchronous clock quantization according to claim 1, characterized in that: In the asynchronous control clock (1) logic, the sampling end signal is used as the quantization start signal; after the sampling is completed, the VALID signal is pulled low, and the comparator of the two-stage analog-to-digital converter (3) enters the first comparison cycle, and the VALID signal is provided to the comparator after a certain delay, and is used as the comparison clock of the comparator, so that after the comparison of each capacitor is completed, the comparison of the next capacitor is automatically entered; the VALID signal is generated by using the comparison result of the comparator to perform a non-AND logic.

4. A two-stage analog-to-digital converter with synchronous clock calibration and asynchronous clock quantization according to claim 3, characterized in that: When the comparator is in a reset state, the VALID signal is pulled high, and after the comparator compares once, the VALID signal will flip automatically; the VALID signal can indicate whether the comparator has completed the comparison.

5. A two-stage analog-to-digital converter with synchronous clock calibration and asynchronous clock quantization according to claim 2, characterized in that: During capacitance calibration, the capacitance in the two-stage analog-to-digital converter (3) is calibrated using a synchronous control clock (2), the frequency of the synchronous control clock (2) is controlled, and the establishment time of each bit of capacitance and the calculation time of the capacitance weight are flexibly adjusted; after the capacitance calibration is completed, the calibration completion signal is pulled high to indicate that the two-stage analog-to-digital converter (3) has entered a normal quantization mode.

6. A two-stage analog-to-digital converter with synchronous clock calibration and asynchronous clock quantization according to claim 1, characterized in that: The two-stage analog-to-digital converter (3) comprises a first-stage analog-to-digital converter (31), a second-stage analog-to-digital converter (32) and an amplifier (33); the first-stage analog-to-digital converter (31) quantizes an input signal, the amplifier (33) amplifies a residual voltage signal generated after the first-stage analog-to-digital converter (31) quantizes a VIN signal, and the second-stage analog-to-digital converter (32) performs quantization processing on the amplified residual voltage signal.

7. A two-stage analog-to-digital converter with synchronous clock calibration and asynchronous clock quantization according to claim 6, characterized in that: The asynchronous control clock (1) controls the quantization of an input signal by a first-stage analog-to-digital converter (31) and a second-stage analog-to-digital converter (32) of the two-stage analog-to-digital converter (3) through a third digital control circuit (6) and a fourth digital control circuit (7); and the synchronous control clock (2) controls the capacitance calibration in the first-stage analog-to-digital converter (31) and the second-stage analog-to-digital converter (32) of the two-stage analog-to-digital converter (3) through a first digital control circuit (4) and a second digital control circuit (5).

8. A two-stage analog-to-digital converter with synchronous clock calibration and asynchronous clock quantization according to claim 7, characterized in that: The asynchronous control clock (1) and the synchronous control clock (2) are electrically connected to a synchronous-asynchronous alternating control circuit; the synchronous-asynchronous alternating control circuit controls the asynchronous control clock (1) and the synchronous control clock (2) to be output alternately; when the capacitance of the two-stage analog-to-digital converter (3) is calibrated, the synchronous-asynchronous alternating control circuit outputs the signal of the synchronous control clock (2) to the two-stage analog-to-digital converter (3); when the two-stage analog-to-digital converter (3) quantizes a VIN input signal, the synchronous-asynchronous alternating control circuit outputs the signal of the asynchronous control clock (1) to the two-stage analog-to-digital converter (3).

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