Systems for thermal and power management in three-dimensional integrated circuits

Abstract

Systems and methods for temperature management in three-dimensional integrated circuits (3DICs) are disclosed. In an embodiment, a thermal sensing element (TSE) is disposed within a memory die bonded to and communicatively coupled with a logic integrated circuit. The TSE is communicatively coupled with temperature sensing circuitry in the logic integrated circuit and produces a voltage in proportion to a temperature within the memory die. The temperature sensing circuitry converts the voltage produced by the TSE to a temperature of the memory die, which allows the logic integrated circuit to control an operational parameter of one or more of the logic integrated circuit or the memory die based on the temperature.

Description

SYSTEMS FOR THERMAL AND POWER MANAGEMENT IN THREE- DIMENSIONAL INTEGRATED CIRCUITSCROSS-REFERENCE TO RELATED APPLICATION S)

[0001] This application claims the priority benefit, under 35 U.S.C. 119(e), of U.S. Application No. 63 / 597,586, filed November 9, 2023 and entitled “Systems for Thermal Management in Three-Dimensional Integrated Circuits,” and U.S. Application No. 63 / 613,838, filed December 22, 2023 and entitled “Three-Dimensional Integrated Circuits with Power Management,” both of which are incorporated herein by reference in their entirety for all purposes.BACKGROUND

[0002] As feature sizes and transistor sizes have decreased for computing hardware such as integrated circuits (ICs) including chips and semiconductor dies, the amount of heat generated by a single chip, such as a microprocessor, has increased. Computing hardware that has traditionally been air cooled has evolved to levels of power consumption requiring more heat dissipation than can be provided by air alone. In some cases, immersion cooling of ICs in a tank containing a coolant liquid is employed to maintain ICs at appropriate operating temperatures.

[0003] One type of immersion cooling is two-phase immersion cooling, in which heat from a semiconductor die is high enough to boil the coolant liquid. The boiling creates a coolant-liquid vapor in the tank, which is condensed by cooling coils back to liquid form. Heat from the semiconductor dies can then be sunk into the liquid-to-gas and gas-to-liquid phase transitions of the coolant liquid with the result that the semiconductor dies are kept at an acceptable temperature.

[0004] This improved heat removal capability has led to new computing hardware architectures to increase computational density, including bonding of computing hardware to co-located memory dies. However, increased amounts of heat may pose a risk to ICs or to bonds connecting co-located components, and no solution exists for effectively monitoring temperatures in co-located components without unacceptably reducing memory density.SUMMARY

[0005] Two-phase immersion cooling systems have provided marked improvements to heat removal for computational hardware including ICs, central processing units (CPUs), and graphics processing units (GPUs). This improved heat removal has enabled computational hardware to be run at higher frequencies, which has correspondingly increased computational speeds and enabled increasingly computationally intensive processes such as large language model (LLM), generative pre-trained transformer (GPT), and similar artificial intelligence (Al) training.

[0006] The high bandwidth and low latency requirements of these computationally intensive processes has driven IC designers to improve information transmission efficiency wherever possible. One way to improve the performance of high-computational-intensity processes is to co-locate the logic circuitry used to perform computations with the memory on which the computed data is stored. An exemplary co-located logic and memory architecture may include a memory die bonded directly on top of a logic IC.

[0007] However, this may have the drawback of exposing the memory die and bonds between memory and logic to the high amounts of waste heat generated by the logic IC. An amount of heat generated by a logic IC may quickly exceed design parameters for a memory die or similar component and lead to reduced performance, damage, or destruction of the memory die or similar component.

[0008] One or more of the integrated circuits (equivalently, dies) in a three-dimensional integrated circuit (3DIC) typically require power for proper operation.

[0009] The structure of a 3DIC makes providing such power more complex as it requires that power to one or more integrated circuit die in the 3DIC be delivered through a hybrid bond, metal layers, a through-substrate via (TSV) and a redistribution layer (RDL), each of which has inductance associated therewith. This inductance can result in voltage spikes, sometimes referred to as power noise, for example, as a result of changes in current drawn or returned onthe power or ground, respectively (for example, in accordance with the relation V = L ■where V is voltage, L is inductance, and is change in current with respect to time), by oneor more integrated circuit die in the 3DIC.

[0010] If power noise reaches an unacceptable level, it could cause improper operation of one or more integrated circuit die in the 3DIC.

[0011] Aspects disclosed herein to reduce such power noise and improve power integrity to reduce the possibility of improper operation of 3DICs and thereby improve the technology of 3DICs. This is accomplished without unacceptably reducing the density aspect of the performance of 3DICs.

[0012] While it may be possible to design and fabricate a memory die with self-contained temperature monitoring circuitry (e.g., including a thermal sensing element (TSE) and logic used to monitor the output of the TSE and communicate with one or more outside logic ICs), placing such self-contained circuitry within a memory die may unacceptably reduce the memory density of the memory die and remove many of the benefits of co-locating logic ICs and memory dies. However, the inventors have recognized and appreciated the benefit of disposing a TSE within the memory die and communicatively coupling the TSE to existing control circuitry within a co-located logic IC. This architecture has the benefit of improving temperature monitoring and thermal management for memory dies co-located with logic ICs without reducing the memory density of the memory dies by using a portion of the memory die for temperature monitoring circuitry.

[0013] The present technology may be utilized in and / or adapted to two-phase immersion cooling (2PIC) systems, single phase immersion cooling (1PIC) systems, direct liquid cooling (DLC) systems, air-cooled systems, or any server ecosystem utilizing temperature management.

[0014] In some aspects, the techniques described herein relate to a system for thermal management in three-dimensional integrated circuits (3DICs), the system including: a 3DIC including a logic integrated circuit (IC) and a memory die, the memory die bonded to the logic IC; a first thermal sensing element (TSE) disposed within the memory die and communicatively coupled to a control logic within the logic IC; wherein the control logic is configured to determine a temperature within the memory die using the first TSE.

[0015] In some aspects, the techniques described herein relate to a system, wherein: the logic IC and the memory die are bonded through a redistribution layer (RDL); and the first TSE and the control logic are communicatively coupled through the RDL.

[0016] In some aspects, the techniques described herein relate to a system, wherein the RDL includes a through- substrate via (TSV); and the first TSE and the control logic are communicatively coupled through the TSV.

[0017] In some aspects, the techniques described herein relate to a system, wherein the first TSE is disposed between at least one memory module of the memory die and the logic IC.

[0018] In some aspects, the techniques described herein relate to a system, wherein the control logic is further configured to control an operational parameter of the logic IC or the memory die based on the temperature within the memory die.

[0019] In some aspects, the techniques described herein relate to a system, wherein the operational parameter includes a frequency, a voltage, a current, a power, a data transfer rate, a computational speed, a processing speed, or a clock speed.

[0020] In some aspects, the techniques described herein relate to a system, wherein the control logic is further configured to control an operational parameter of the logic IC or the memory die based on a temperature limit of a bond mechanically coupling the memory die and the logic IC.

[0021] In some aspects, the techniques described herein relate to a system, wherein the bond includes at least one of a hybrid bond, a bump bond, or a micro-bump bond.

[0022] In some aspects, the techniques described herein relate to a system, further including a second TSE disposed within the logic IC.

[0023] In some aspects, the techniques described herein relate to a system, wherein the control logic is further configured to control an operational parameter of the logic IC or the memory die based on a temperature detected using the second TSE.

[0024] In some aspects, the techniques described herein relate to a system, wherein the operational parameter includes a frequency, a voltage, a current, a power, a data transfer rate, a computational speed, a processing speed, or a clock speed.

[0025] In some aspects, the techniques described herein relate to a system, further including a container at least partially filled with immersion cooling liquid, wherein: the 3DIC is disposed within the immersion cooling liquid; and the control logic is further configured to control an operational parameter of the logic IC or the memory die based on a boiling temperature of the immersion cooling liquid.

[0026] In some aspects, the techniques described herein relate to a method for thermal management in three-dimensional integrated circuits (3DICs), the method including: receiving, by an analog-to-digital converter (ADC) disposed in a logic integrated circuit (IC), a first voltage of a temperature sensing element (TSE) disposed in a memory die; converting, by theADC, the first voltage to a temperature, wherein the ADC is communicatively coupled to the first TSE; controlling, by the logic IC, an operational parameter of the logic IC or the memory die based on the temperature.

[0027] In some aspects, the techniques described herein relate to a method, wherein the ADC receives the first voltage through a redistribution layer (RDL) disposed between the logic IC and the memory die.

[0028] In some aspects, the techniques described herein relate to a method, wherein the operational parameter includes a frequency, a voltage, a current, a power, a data transfer rate, a computational speed, a processing speed, or a clock speed.

[0029] In some aspects, the techniques described herein relate to a method, further including: receiving, by the ADC, a second voltage of a second TSE, the second TSE disposed in the logic IC; converting, by the ADC, the second voltage to a second temperature; controlling, by the logic IC, the operational parameter of the logic IC or the memory die based on the second temperature.

[0030] In some aspects, the techniques described herein relate to a method, wherein the operational parameter includes a frequency, a voltage, a current, a power, a data transfer rate, a computational speed, a processing speed, or a clock speed.

[0031] In some aspects, the techniques described herein relate to a method, wherein the logic IC is further configured to control an operational parameter of the logic IC or the memory die based on a temperature limit of a bond mechanically coupling the memory die and the logic IC.

[0032] In some aspects, the techniques described herein relate to a method, wherein the bond includes at least one of a hybrid bond, a bump bond, or a micro-bump bond.

[0033] In some aspects, the techniques described herein relate to a three-dimensional integrated circuit (3DIC) including: a first integrated circuit (IC) die including a first substrate and a first IC; a second IC die including a second substrate and a second IC; a hybrid bond disposed between the first IC die and the second IC die; and a redistribution layer (RDL) disposed on the first IC die; wherein the first substrate of the first IC die is disposed between the RDL and the first IC of the first IC die; and wherein the RDL includes a passive filter component.

[0034] In some aspects, the techniques described herein relate to a 3DIC, wherein the first IC includes a logic IC and the second IC includes a memory.

[0035] In some aspects, the techniques described herein relate to a 3DIC, wherein: the second IC die includes a thermal sensing element (TSE), the TSE communicatively coupled to the first IC through the RDL.

[0036] In some aspects, the techniques described herein relate to a 3DIC, wherein the passive filter component includes a metal-insulator-metal (MiM) capacitor.

[0037] In some aspects, the techniques described herein relate to a 3DIC, wherein the 3DIC is configured to receive electrical power from an external source and the RDL is configured to electrically couple the electric power to the MiM capacitor.

[0038] In some aspects, the techniques described herein relate to a 3DIC, wherein the first substrate of the first IC die is disposed between the hybrid bond and the RDL.

[0039] In some aspects, the techniques described herein relate to a 3DIC, wherein the RDL is disposed between the hybrid bond and the first substrate of the first IC die.

[0040] In some aspects, the techniques described herein relate to a 3DIC, wherein the RDL includes an insulator layer and the MiM capacitor of the RDL includes a dielectric having a dielectric constant greater than a dielectric constant of the insulator layer of the RDL.

[0041] In some aspects, the techniques described herein relate to a 3DIC, wherein the MiM capacitor of the RDL includes a dielectric having a dielectric constant greater than about 9.

[0042] In some aspects, the techniques described herein relate to a 3DIC, wherein: the RDL includes a first metal layer, a second metal layer and a third metal layer; and the MiM capacitor is disposed between the first metal layer of the RDL and the third metal layer of the RDL.

[0043] All combinations of the foregoing concepts and additional concepts discussed in greater detail below (provided such concepts are not mutually inconsistent) are part of the inventive subject matter disclosed herein. In particular, all combinations of claimed subject matter appearing at the end of this disclosure are part of the inventive subject matter disclosed herein. The terminology used herein that also may appear in any disclosure incorporated by reference should be accorded a meaning most consistent with the particular concepts disclosed herein.BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The skilled artisan will understand that the drawings primarily are for illustrative purposes and are not intended to limit the scope of the inventive subject matter describedherein. The drawings are not necessarily to scale; in some instances, various aspects of the inventive subject matter disclosed herein may be shown exaggerated or enlarged in the drawings to facilitate an understanding of different features. In the drawings, like reference characters generally refer to like features (e.g., functionally similar and / or structurally similar elements).

[0045] FIG. 1 is a schematic representation of a cross section of a three-dimensional integrated circuit (3DIC) in accordance with some aspects.

[0046] FIG. 2 is a simplified schematic of an electrical conduction path defined by portions of the 3DIC of FIG. 1 for delivering power to one or more integrated circuit(s) in a first IC die and one or more integrated circuit(s) in a second IC die.

[0047] FIG. 3 is a schematic representation of a cross section of a 3DIC in accordance with some aspects.

[0048] FIG. 4 is a simplified schematic of an electrical conduction path defined by portions of the 3DIC of FIG. 3 for delivering power to one or more integrated circuit(s) in a first IC die and one or more integrated circuit(s) in a second IC die.

[0049] FIG. 5 is a schematic representation of a cross section of a 3DIC in accordance with some aspects.

[0050] FIG. 6 is a simplified schematic of an electrical conduction path defined by portions of the 3DIC of FIG. 5 for delivering power to one or more integrated circuit(s) in a first IC die and one or more integrated circuit(s) in a second IC die.

[0051] FIGS. 7A-7F illustrate a method of fabricating a 3DIC in accordance with some aspects.

[0052] FIG. 8 illustrates a 3DIC in accordance with the present technology.

[0053] FIG. 9. illustrates a circuit diagram of a 3DIC including a memory die, logic IC, and thermal management circuitry.

[0054] FIGS. 10A-D illustrate 3DICs having a plurality of thermal sensing elements (TSEs) disposed in first dies, the first dies communicatively coupled to respective second dies through a redistribution layer (RDL).

[0055] FIG. 11 depicts aspects of an immersion cooling system for dissipating heat from one or more semiconductor die packages via immersion cooling.

[0056] FIG. 12 illustrates a flowchart of an exemplary method in accordance with the present technology.DETAILED DESCRIPTION

[0057] FIG. 1 is a schematic representation of a cross section of a three-dimensional integrated circuit (3DIC) 1000 in accordance with some aspects. The 3DIC 1000 may include a first integrated circuit (IC) die 1002 and a second IC die 1004, which may be bonded to the first IC die 1002 by a hybrid bond 1006 (which may additionally or alternatively be a micro-bump bond, a C bond, a solder bond, or any suitable bond) disposed between the first IC die 1002 and the second IC die 1004. The 3DIC 1000 may further include a plurality of electrical conductors (e.g., conductors 1010-1019) that extend through the hybrid bond 1006, sometimes referred to herein as through-bond vias 1010-1019.

[0058] The first IC die 1002 may include a substrate 1020 and first integrated circuit(s) 1022 disposed (directly or indirectly) on the substrate 1020. The substrate 1020 may be a silicon or other type of substrate. The first integrated circuit(s) 1022 may include a plurality of alternating metal and insulating layers (e.g., metal layers 1024, 1026, 1028 and insulating layers 1023, 1025, 1027, 1029). For example, a first insulting layer 1023 may be disposed between the substrate 1020 and a first metal layer 1024. A second insulating layer 1025 may be disposed between the first metal layer 1024 and a second metal layer 1026. A top insulating layer 1029 may be disposed between a top metal layer 1028 and the hybrid bond 1006. The first integrated circuit(s) 1022 may further include a plurality of electrically conducting vias (e.g., vias 1030, 1032, 1034, 1036, 1038, 1039) that extend between pairs of the metal layers (e.g., between pairs of metal layers 1024, 1026, 1028). For example, vias 1030, 1032 may extend from the second metal layer 1026 to the top metal layer 1028. Vias 1034, 1036, 1038, 1039 may extend from the first metal layer 1024 to the second metal layer 1026.

[0059] The first IC die 1002 may further include a plurality of electrically conducting vias (e.g., vias 1040, 1042, 1044, 1046), sometimes referred to as through-substrate (or through-silicon) vias (TSVs) that extend from one or more of the metal layers (e.g., one or more of metal layers 1024, 1026, 1028) to and through the substrate 1020, and may further include a plurality of electrical conductors (e.g., conductors 1048, 1049) that extend from one or more of the metal layers (e.g., one or more of metal layers 1024, 1026, 1028) to one or more of the through -bondvias (e.g., one or more of the through-bond vias 1010-1019). For example, conductors 1048,1049 may extend from the top metal layer 1028 to through-bond vias 1012, 1018, respectively.

[0060] The second IC die 1004 may include a substrate 1090 and second integrated circuit(s) 1092 disposed (directly or indirectly) on the substrate 1090. The substrate 1090 may be a silicon or other type of substrate. The second integrated circuit(s) 1092 may include a plurality of alternating metal and insulating layers (e.g., metal layer 1093 and insulating layer 1094). A top insulating layer 1094 may be disposed between a top metal layer 1093 and the hybrid bond 1006. The second integrated circuit(s) 1092 may further include a plurality of electrically conducting vias (not shown) that extend between pairs of the metal layers (not shown).

[0061] The 3DIC 1000 may further include a redistribution layer 1050 disposed (directly or indirectly) on the substrate 1020. The redistribution layer 1050 may include a plurality of alternating metal and insulating layers (e.g., metal layers 1054, 1056, 1058 and insulating layers 1055, 1057, 1059). For example, an insulting layer 1055 may be disposed between a first metal layer 1054 and a second metal layer 1056. An insulting layer 1057 may be disposed between the second metal layer 1056 and a third metal layer 1058. The redistribution layer1050 may further include a plurality of electrically conducting vias (e.g., vias 1060, 1061, 1062, 1063, 1064) that extend between pairs of the metal layers (e.g., pairs of metal layers 1054, 1056, 1058) and may further include a plurality of electrical conductors (e.g., conductors 1065, 1066, 1067, 1068) that extend from one or more of the metal layers (e.g., one or more of metal layers 1054, 1056, 1058) to one or more of the through-substrate vias (e.g., one or more of through-substrate vias 1040, 1042, 1044, 1046). For example, conductors 1065, 1066, 1067, 1068 may extend from the third metal layer 1058 to through-substrate vias 1040, 1042, 1044, 1046, respectively.

[0062] The 3DIC 1000 may further include a plurality of bump (or other type) electrically conductive contacts (e.g., contacts 1070-1077) disposed (directly or indirectly) on the redistribution layer 1050. The 3DIC 1000 may be configured to receive electrical power from an external source (e.g., a power supply, a wall outlet [indirectly or directly], from a transformer, etc.) through one or more of the electrically conductive contacts (e.g., through contacts 1070-1071) and may be configured to be electrically connected to electrical ground (or other reference voltage) through one or more of the electrically conductive contacts (e.g., through contacts 1075-1076).

[0063] In addition, the 3DIC 1000 may be configured to receive input signals through one or more of the electrically conductive contacts (e.g., through one or more of contacts 1072-1074, 1077) and / or may be configured to supply output signals through one or more of the electrically conductive contacts (e.g., through one or more of contacts 1072-1074, 1077).

[0064] One or more of the integrated circuit(s) 1022 in the first IC die 1002 and / or one or more of the integrated circuit(s) 1092 in the second IC die 1004 may require power for proper operation.

[0065] In that regard, the redistribution layer 1050, the plurality of through-substrate vias (e.g., through-substrate vias 1040, 1042, 1044, 1046; also referred to as through-silicon vias, especially in embodiments in which the substrate comprises silicon), the plurality of metal layers (e.g., metal layers, 1024, 1026, 1028) and the plurality of vias (e.g., vias 1030, 1032, 1034, 1036, 1038, 1039) in the first IC die 1002 may be collectively configured to: (1) route electrical power, ground and input signals from one(s) of the plurality of bump (or other type) electrically conductive contacts (e.g., contacts 1070-1077) that are designated to receive such to one(s) of the integrated circuit(s) 1022 in the first IC die 1002 that are configured to receive such.

[0066] Further, the redistribution layer 1050, the plurality of through-substrate vias (e.g., through-substrate vias 1040, 1042, 1044, 1046), the plurality of metal layers (e.g., metal layers, 1024, 1026, 1028), the plurality of vias (e.g., vias 1030, 1032, 1034, 1036, 1038, 1039) and the plurality of conductors (e.g., conductors 1048, 1049) in the first IC die 1002, the plurality of through-hybrid bond vias (e.g., through-hybrid bond vias 1010-1019) and one or more metal layers in the second IC die 1004, may be collectively configured to route electrical power, ground and input signals from one(s) of the plurality of bump (or other type) electrically conductive contacts (e.g., contacts 1070-1077) that are designated to receive such to one(s) of the integrated circuit(s) in the second IC die 1004 that are configured to receive such.

[0067] The above structure of the 3DIC 1000 may make the providing of the power to the first IC die 1002 more complex as it may require that power to one or more of the integrated circuit(s) 1022 in the first IC die 1002 be delivered through an electrical path comprising the redistribution layer 1050, one or more of the through-substrate vias (e.g., one or more of through-substrate vias 1040, 1042, 1044, 1046), one or more of the plurality of metal layers (e.g., one or more of the metal layers, 1024, 1026, 1028) in the first IC die 1002 and one ormore of the plurality of vias (e.g., vias 1030, 1032, 1034, 1036, 1038, 1039) in the first IC die 1002, each of which may have inductance associated therewith.

[0068] In addition, the structure of the 3DIC 1000 may make the providing of the power to the second IC die 1004 more complex as it may require that power to one or more of the integrated circuit(s) 1092 in the second IC die 1004 be delivered through an electrical path comprising the redistribution layer 1050, one or more of the through-substrate vias (e.g., one or more of through-substrate vias 1040, 1042, 1044, 1046), one or more of the plurality of metal layers (e.g., one or more of the metal layers, 1024, 1026, 1028) in the first IC die 1002, one or more of the plurality of vias (e.g., vias 1030, 1032, 1034, 1036, 1038, 1039) in the first IC die 1002, one or more of the plurality of conductors (e.g., one or more of conductors 1048, 1049) in the first IC die 1002, one or more of the through-hybrid bond vias (e.g., one or more of through- hybrid bond vias 1010-1019) and one or more metal layers in the second IC die 1004, each of which may have inductance associated therewith.

[0069] The inductances mentioned above can result in voltage spikes, sometimes referred to as power noise, for example, as a result of changes in current drawn or returned on the power orground, respectively (for example, in accordance with the relation V = L ■ where V isvoltage, L is inductance, and is change in current with respect to time), on the part of one or more integrated circuit die (e.g., the first IC die 1002 and / or the second IC die 1004) in the 3DIC 1000.

[0070] If power noise reaches an unacceptable level, it could cause improper operation of one or more integrated circuit die (e.g., the first IC die 1002 and / or the second IC die 1004) in the 3DIC 1000.

[0071] In accordance with some aspects, a metal-insulator-metal (MiM) capacitor may be provided in the redistribution layer 1050 to reduce such power noise and improve power integrity to reduce the possibility of improper operation of 3DICs, and thereby improve the technology of 3DICs. This is accomplished without unacceptably reducing the density aspect of the performance of 3DICs.

[0072] In this regard, in accordance with some aspects, the redistribution layer 1050 may include an MiM capacitor 1080.

[0073] The MiM capacitor 1080 may include a first metal layer 1081, which may be a top metal layer of the MiM capacitor 1080, a second metal layer 1082, which may be a bottom metallayer of the MiM capacitor 1080, and a dielectric 1083 disposed between the first metal layer 1081 and the second metal layer 1082. The dielectric 1083 may have a high dielectric constant greater than a dielectric constant of one or more of the insulator layers (e.g., insulator layers 1055, 1057, 1059) of the redistribution layer 1050. In some aspects, the dielectric 1083 may have a high dielectric constant, for example greater than about 9, between about 9 and about 50, between about 9 and about 80, greater than about 75, or any suitable value of dielectric constant. Inputs to MiM capacitor 1080 may include power and ground and may function to reduce power supply instabilities and smooth out power transitions.

[0074] FIG. 2 is a simplified schematic of an electrical conduction path provided by the 3DIC of FIG. 1 for delivering power to one or more of the first integrated circuit(s) 1022 in the first IC die 1002 and one or more of the second integrated circuit(s) 1092 in the second IC die 1004.

[0075] Referring again to FIG. 1, the MiM capacitor 1080 may be disposed between two of the metal layers of the redistribution layer 1050 or otherwise. In some aspects, the MiM capacitor 1080 may be disposed between the first metal layer 1054 and the third metal layer 1058. The MiM capacitor 1080 may have a thickness that is approximately equal to a thickness of one of the metal layers of the redistribution layer 1050 or otherwise. In some aspects, the MiM capacitor 1080 may have a thickness that is approximately equal to a thickness of the second metal layer 1056 of the redistribution layer 1050. As used herein, the term "approximately equal to" means "within + / - 15 percent of' a stated value. In an aspect, a thickness of the second metal layer 1056 of the redistribution layer 1050 may be between about 10 KA and about 30 KA.

[0076] The redistribution layer 1050 may further include one or more electrical conductors (e.g., conductors 1084, 1085) that electrically connect the first metal layer 1081 of the MiM capacitor 1080 to one of the metal layers of the redistribution layer 1050. In some aspects, the one or more electrical conductors (e.g., conductors 1084, 1085) electrically connect the first metal layer 1081 of the MiM capacitor 1080 to the third metal layer 1058 of the redistribution layer 1050.

[0077] The redistribution layer 1050 may further include one or more electrical conductors (e.g., conductors 1086, 1087) that electrically connect the second metal layer 1082 of the MiM capacitor 1080 to one of the metal layers of the redistribution layer 1050. In some aspects, the one or more electrical conductors (e.g., conductors 1086, 1087) electrically connect the second metal layer 1082 of the MiM capacitor 1080 to the first metal layer 1054 of the redistributionlayer 1050. In an aspect, redistribution layer 1050 may include a plurality of capacitors connected in parallel.

[0078] The redistribution layer 1050, the plurality of through-substrate vias (e.g., through- substrate vias 1040, 1042, 1044, 1046), the plurality of metal layers (e.g., metal layers, 1024, 1026, 1028) and the plurality of vias (e.g., vias 1030, 1032, 1034, 1036, 1038, 1039) in the first IC die 1002 may be collectively configured to route output signals from one(s) of the integrated circuit(s) 1022 in the first IC die 1002 that are configured to supply such to one(s) of the plurality of bump (or other type) electrically conductive contacts (e.g., contacts 1070-1077) that are designated to receive such.

[0079] Further, the redistribution layer 1050, the plurality of through-substrate vias (e.g., through-substrate vias 1040, 1042, 1044, 1046), the plurality of metal layers (e.g., metal layers, 1024, 1026, 1028), the plurality of vias (e.g., vias 1030, 1032, 1034, 1036, 1038, 1039) and the plurality of conductors (e.g., conductors 1048, 1049) in the first IC die 1002, the plurality of through-hybrid bond vias (e.g., through-hybrid bond vias 1010-1019) and one or more metal layers in the second IC die 1004, may be collectively configured to route output signals from one(s) of the integrated circuit(s) in the second IC die 1004 that are configured to supply such to one(s) of the plurality of bump (or other type) electrically conductive contacts (e.g., contacts 1070-1077) that are designated to receive such.

[0080] The 3DIC 1000 may be mounted or otherwise disposed on laminate substrate 1095, which may be a PCB or other substrate. The 3DIC 1010 may be electrically coupled with one or more external components through traces, circuitry, or similar connections through laminate substrate 1095.

[0081] In some aspects, the first IC die 1002 may comprise a logic IC. A logic IC may include one or more circuit components including a processor, a microprocessor, a CPU, a GPU, a field-programmable gate array (FGPA), programmable logic controller (PLC), applicationspecific integrated circuit (ASIC), a digital signal processing (DSP) die, a high-bandwidth memory, a voltage regulator, random-access memory (RAM), read-only memory (ROM), one or more registers, a heat sink, a socket, an input, an output, one or more comparators, one or more registers, one or more temperature sensor circuits, one or more analog-to-digital converters (ADCs), one or more digital-to-analog converters (DACs), one or more thermal sensing elements (TSEs), and / or the like.

[0082] The first IC die 1002 may be communicatively coupled with the second IC die 1004 and laminate substrate 1095.

[0083] In some aspects, the first IC die 1002 may be fixedly attached to the second IC die 1004 and / or laminate substrate 1095 through a solder, a braise, an epoxy, a mechanical attachment mechanism such as a clip, screw, bolt, or similar mechanism, and the like.

[0084] In some aspects, the second IC die 1004 may be a memory module. A memory module may be an IC configured to store data and may include a dynamic random access memory (DRAM) module, a static random access memory (SRAM) module, a flash memory module, a solid-state drive (SSD), a non-volatile random access memory (NVRAM) module, a read-only memory (ROM) module (such as a floating-gate ROM, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), onetime programmable ROM (OTPROM), or the like), high-bandwidth memory (HBM), or any suitable type of memory module.

[0085] In some aspects, the first IC die 1002 or the second IC die 1004 comprises a logic die and the other comprises memory module that includes a dynamic random access memory (DRAM) module.

[0086] In some aspects, the first IC die 1002 and the second IC die 1004 each comprise a logic die.

[0087] In some aspects, a logic die may execute artificial intelligence (Al) instructions and / or may be configured for computationally intensive processes such as artificial intelligence (Al) training.

[0088] In some aspects, the first IC die 1002 and the second IC die 1004 each comprise a memory module.

[0089] In some aspects, the first IC die 1002 and the second IC die 1004 each comprise a memory module that includes a dynamic random access memory (DRAM) module.

[0090] In some of such aspects, the first IC die 1002 or the second IC die 1004 comprises an RF die. In some of such aspects, the first IC die 1002 or the second IC die 1004 comprises an RF die and the other of the first IC die 1002 and the second IC die 1004 comprises a logic die. In some aspects, the logic die may execute artificial intelligence (Al) instructions and / or may be configured for computationally intensive processes such as artificial intelligence (Al) training.

[0091] In some aspects, such logic die may execute artificial intelligence (Al) instructions and / or may be configured for computationally intensive processes such as artificial intelligence (Al) training.

[0092] In the 3DIC 1000 of FIG. 1, the first IC die 1002 and the second IC die 1004 is each arranged such that its integrated circuit(s) (e.g., first integrated circuit(s) 1022, second integrated circuit(s) 1092) is closer to the hybrid bond 1006 than is its respective substrate (e.g., substrate 1020, substrate 1090, respectively). Thus, the top metal layer of the first integrated circuit(s) 1022 and the top metal layer of the second integrated circuit(s) 1092 is each closer to the hybrid bond 1006 than is the substrate 1020 and the substrate 1090, respectively.

[0093] This configuration is sometimes referred to herein as "face to face."

[0094] In some aspects, the first IC die 1002 is arranged such that its substrate is closer to the hybrid bond 1006 than is its integrated circuit(s). Thus, the substrate is closer to the hybrid bond 1006 than is the top metal layer of its integrated circuit(s).

[0095] FIG. 3 is a schematic representation of a cross section of a 3DIC 1300, in accordance with some aspects. The 3DIC 1300 may be similar to the 3DIC 1000 of FIG. 1 except that it has a first IC die arranged such that its substrate is closer to the hybrid bond 1006 than is its integrated circuit(s). Thus, its substrate is closer to the hybrid bond 1006 than is the top metal layer of its integrated circuit(s).

[0096] This configuration is sometimes referred to herein as "face to back."

[0097] Referring to FIG 5, the 3DIC 1300 may include a first integrated circuit (IC) die 1302 and a second IC die 1004, which may be bonded to the first IC die 1302 by a hybrid bond 1006 disposed between the first IC die 1302 and the second IC die 1004. The 3DIC 1300 may further include the plurality of electrical conductors (e.g., conductors 1010-1019) that extend through the hybrid bond 1006, sometimes referred to herein as through-bond vias 1010-1019.

[0098] The first IC die 1302 may include a substrate 1320 and first integrated circuit(s) 1322 disposed (directly or indirectly) on the substrate 1320. The substrate 1320 may be a silicon or other type of substrate. The first integrated circuit(s) 1322 may include a plurality of alternating metal and insulating layers (e.g., metal layers 1324, 1326, 1328 and insulating layers 1323, 1325, 1327).

[0099] For example, a first insulting layer 1023 may be disposed between the substrate 1320 and a first metal layer 1324. A second insulating layer 1325 may be disposed between the firstmetal layer 1324 and a second metal layer 1326. The first integrated circuit(s) 1022 may further include a plurality of electrically conducting vias (e.g., via 1334) that extend between pairs of the metal layers (e.g., between pairs of metal layers 1024, 1026, 1028). For example, via 1334 may extend from the first metal layer 1324 to the second metal layer 1326.

[0100] The first IC die 1302 may further include a plurality of electrically conducting vias (e.g., vias 1340, 1342, 1344, 1346), sometimes referred to as through-substrate (or through- silicon) vias (TSVs) that extend from one or more of the metal layers (e.g., one or more of metal layers 1324, 1326, 1328) to and through the substrate 1320.

[0101] The 3DIC 1300 may further include a redistribution layer 1350 disposed (directly or indirectly) on the substrate 1320. The redistribution layer 1350 may include a plurality of alternating metal and insulating layers (e.g., metal layers 1354, 1356, 1358 and insulating layers 1355, 1357). For example, an insulting layer 1355 may be disposed between a first metal layer 1354 and a second metal layer 1356. The redistribution layer 1350 may further include a plurality of electrically conducting vias (e.g., vias 1361, 1362, 1363, 1364) that extend between pairs of the metal layers (e.g., pairs of metal layers 1354, 1356, 1358) and may further include a plurality of electrical conductors (not shown) that extend from one or more of the metal layers (e.g., one or more of metal layers 1354, 1356, 1358) to one or more of the through-substrate vias (e.g., one or more of through- substrate vias 1340, 1342, 1344, 1346). The redistribution layer 1350 may further include a plurality of electrical conductors (e.g., conductor 1349) that extend from one or more of the metal layers (e.g., one or more of metal layers 1354, 1356, 1358) to one or more of the through -bond vias (e.g., one or more of the through-bond vias 1010-1019). For example, conductor 1349 may extend from the metal layer 1358 to through- bond vias 1018, respectively.

[0102] The 3DIC 1300 may further include the plurality of bump (or other type) electrically conductive contacts (e.g., contacts 1070-1077) disposed (directly or indirectly) on the redistribution layer 1350.

[0103] The plurality of metal layers (e.g., metal layers, 1324, 1326, 1328) and the plurality of vias (e.g., via 1334) in the first IC die 1302 may be configured to: (1) route electrical power, ground and input signals from one(s) of the plurality of bump (or other type) electrically conductive contacts (e.g., contacts 1070-1077) that are designated to receive such to one(s) of the integrated circuit(s) 1322 in the first IC die 1302 that are configured to receive such.

[0104] The plurality of metal layers (e.g., metal layers, 1324, 1326, 1328) in the first IC die 1302, the plurality of vias (e.g., via 1334) in the first IC die 1302, the plurality of through- substrate vias (e.g., through- substrate vias 1340, 1342, 1344, 1346), the redistribution layer 1350, the plurality of through-hybrid bond vias (e.g., through-hybrid bond vias 1010-1019) and one or more metal layers in the second IC die 1004, may be collectively configured to route electrical power, ground and input signals from one(s) of the plurality of bump (or other type) electrically conductive contacts (e.g., contacts 1070-1077) that are designated to receive such to one(s) of the integrated circuit(s) in the second IC die 1004 that are configured to receive such.

[0105] The above structure of the 3DIC 1300 may make the providing of the power to the second IC die 1004 more complex as it may require that power to one or more of the integrated circuit(s) 1092 in the second IC die 1004 be delivered through an electrical path comprising the plurality of metal layers (e.g., metal layers, 1324, 1326, 1328) and the plurality of vias (e.g., via 1334) in the first IC die 1302, the plurality of through- substrate vias (e.g., through- substrate vias 1340, 1342, 1344, 1346), the redistribution layer 1350, one or more of the through-hybrid bond vias (e.g., one or more of through-hybrid bond vias 1010-1019) and one or more metal layers in the second IC die 1004, each of which may have inductance associated therewith.

[0106] The inductances mentioned above can result in voltage spikes, sometimes referred to as power noise, for example, as a result of changes in current drawn or returned on the poweror ground, respectively (for example, in accordance with the relation V = L ■ where V isvoltage, L is inductance, and is change in current with respect to time), on the part of one or more integrated circuit die (e.g., the second IC die 1004) in the 3DIC 1300.

[0107] If power noise reaches an unacceptable level, it could cause improper operation of one or more integrated circuit die (e.g., the second IC die 1004) in the 3DIC 1300.

[0108] In accordance with some aspects, the MiM capacitor 1080 may be provided in the redistribution layer 1350 to reduce such power noise and improve power integrity to reduce the possibility of improper operation of 3DICs, and thereby improve the technology of 3DICs. This is accomplished without unacceptably reducing the density aspect of the performance of 3DICs.

[0109] The redistribution layer 1350 may further include one or more electrical conductors (e.g., conductors 1384, 1385) that electrically connect the first metal layer 1081 of the MiMcapacitor 1080 to one of the metal layers of the redistribution layer 1350. In some aspects, the one or more electrical conductors (e.g., conductors 1384, 1385) electrically connect the first metal layer 1081 of the MiM capacitor 1080 to the third metal layer 1358 of the redistribution layer 1350.

[0110] The redistribution layer 1350 may further include one or more electrical conductors (e.g., conductors 1386, 1387) that electrically connect the second metal layer 1082 of the MiM capacitor 1080 to one of the metal layers of the redistribution layer 1350. In some aspects, the one or more electrical conductors (e.g., conductors 1386, 1387) electrically connect the second metal layer 1082 of the MiM capacitor 1080 to the first metal layer 1354 of the redistribution layer 1350.

[0111] FIG. 4 is a simplified schematic of an electrical conduction path provided by the 3DIC of FIG. 3 for delivering power to one or more of the first integrated circuit(s) 1322 in the first IC die 1302 and one or more of the second integrated circuit(s) 1092 in the second IC die 1004.

[0112] FIG. 5 is a schematic representation of a cross section of a 3DIC 1500, in accordance with some aspects. The 3DIC 1500 is analogous to the 3DIC 1300 of FIG. 3 except that the 3DIC 1500 has a redistribution layer 1550 that includes a passive filter network 1580 that does not include the MiM capacitor 1080 (FIGS. 1, 3).

[0113] FIG. 6 is a simplified schematic of an electrical conduction path defined by the 3DIC 1500 of FIG. 5 for delivering power to one or more of the first integrated circuit(s) 1322 in a first IC die 1502 and one or more of the second integrated circuit(s) 1092 in the second IC die 1004.

[0114] In any and / or all of the above aspects that include the 3DIC 1500 and redistribution layer 1550, the first IC die 1502 or the second IC die 1004 may comprise an RF die.

[0115] In any and / or all of the above aspects that include the 3DIC 1500 and redistribution layer 1550, the first IC die 1502 or the second IC die 1004 may comprise an RF die and the other of the first IC die 1502 or the second IC die 1004 may comprise a logic die.

[0116] In some aspects, such logic die may execute artificial intelligence (Al) instructions and / or may be configured for computationally intensive processes such as artificial intelligence (Al) training.

[0117] In some aspects, any one or more of the techniques disclosed herein may be used in association with a 3DIC having more than two IC wafers or die.

[0118] In some of such aspects, the IC wafers or die may be arranged face-to-face, face-to- back or combinations thereof.

[0119] In some of such aspects, a 3DIC having more than two IC wafers or die may have the following types of IC wafers or die: Logic(s) + Logic(s), Logic(s) + DRAM(s), Logic(+DRAMs) + Logic(+DRAMs) and DRAM(s)+DRAM(s).

[0120] Thus, in some of such aspects, a 3DIC having more than two IC wafers or die may have three logic IC wafers or die, four logic IC wafers or die, more than four logic IC wafers or die, one logic IC die and two or more DRAM IC wafers or die, two or more logic IC wafers or die and one DRAM IC wafers or die, two or more logic IC wafers or die and two or more DRAM IC wafers or die, two logic IC wafers or die each having two or more of its own DRAM IC wafers or die, three DRAM IC wafers or die, four DRAM IC wafers or die, or more than four DRAM IC wafers or die. Additional arrangements of 3DIC stacks, dies, and related bonding methods (including further examples of hybrid bonded and / or micro-bump bonded 3DIC stack arrangements having one or more logic ICs and / or one or more memory modules bonded to one or more additional logic ICs and / or memory modules) can be utilized in connection with U.S. Provisional Patent Application No. 63 / 405,198, filed December 1, 2023, and titled “3D DRAM Stacking on Al Accelerators,” the entirety of which is incorporated herein by reference.

[0121] FIGS. 7A-7F illustrate a method of fabricating the 3DIC 1000 and 3DIC 1300 in accordance with some aspects. Referring to FIG. 7A, the method may include fabricating the first integrated circuit die. Referring to FIG. 7B, the method may further include fabricating the second integrated circuit die. Referring to FIG. 7C, the method may further include hybrid bonding the first integrated circuit die to the second integrated circuit die. Referring to FIG. 7D, the method may further include thinning down the substrate of the first integrated circuit die. Referring to FIG. 7E, the method may further include opening a power contact and forming the metal redistribution layer. Referring to FIG. 7F, the method may further include forming the plurality of bump (or other type) electrically conductive contacts.

[0122] FIG. 8 illustrates a three-dimensional integrated circuit 1810 in accordance with the present technology. Three-dimensional integrated circuit (3DIC) 1810 may include logic IC 1812 and memory die 1814, where memory die 1814 may be bonded or otherwise attached to logic IC 1812. Integrated circuit 1810 may be mounted or otherwise disposed on laminate substrate 1830, which may be a PCB or other substrate. Integrated circuit 1810 may becommunicatively coupled with one or more external components through traces, circuitry, or similar connections through laminate substrate 1830. Integrated circuit 1810 may include an RDL in accordance with the present technology, through which a TSE disposed in memory die 1814 may be communicatively coupled to control logic disposed in logic IC 1812.

[0123] Logic IC 1812 may include one or more circuit components including a processor, a microprocessor, a CPU, a GPU, an FPGA, an PLC, an ASIC, a DSP die, a high-bandwidth memory, RAM, ROM, one or more ADCs, one or more DACs, one or more thermal sensing elements (TSEs), and the like. One or more TSEs used in accordance with the present technology may include a temperature diode, a Vt threshold current mirror, a thermistor, a thermocouple, or any suitable temperature sensor.

[0124] Logic IC 1812 may include circuitry configured to receive input from one or more TSEs and determine at least a temperature and / or a thermal flux within a material that the one or more TSEs are contacting. Logic IC 1812 may include one or more TSEs and / or may be communicatively coupled to one or more TSEs disposed externally to logic IC 1812. For example, logic IC 1812 may be communicatively coupled to one or more TSEs disposed within a memory die such as memory die 1814. Logic IC 1812 may be configured to control the operation of circuitry within logic IC 1812. Additionally or alternatively, logic IC 1812 may be configured to be controlled by one or more external control elements such as a processor, CPU head node, PLC, control plane, or the like.

[0125] Logic IC 1812 may be communicatively coupled with memory die 1814 and laminate substrate 1830. Logic IC 1812 may be fixedly attached to memory die 1814 and / or laminate substrate 1830 through a solder, a braise, an epoxy, a mechanical attachment mechanism such as a clip, screw, bolt, or similar mechanism, and the like. Integrated circuit 1810 may be part of a server, for example a GPU server. In an embodiment, logic IC 1812 may generate waste heat as a result of normal operation, which may exceed 100 W, 250 W, 500 W, 600 W, 700 W, or greater amounts of waste heat. A portion of this waste heat may flow into memory die 1814 and be subsequently emitted by convection, conduction, or radiation from memory die 1814 to a surrounding environment.

[0126] Memory die 1814 may include a dynamic random access memory (DRAM) module, a static random access memory die (SRAM), solid state memory, flash memory, or other suitable memory type. Memory die 1814 may include one or more TSEs configured to output signals indicating a temperature or heat flux at the location of the TSE. Memory die 1814 mayinclude logic circuitry configured to determine a temperature or heat flux from one or more TSE outputs or may only include the one or more TSEs. The one or more TSEs may be communicatively coupled to logic circuitry disposed externally to memory die 1814 (e.g., in logic IC 1812 or another processor) configured to determine a temperature of memory die 1814 based on the output from the one or more TSEs disposed within memory die 1814. Memory die 1814 may include one or more memory modules 1916a-b, each memory module 1916a-b communicatively coupled to one or more low-dropout regulators (LDOs) configured to provide energy efficient access to the respective memory module.

[0127] Co-location of memory die 1814 with logic IC 1812 may expose memory die 1814 to more heat than it is designed for. This heat may increase a temperature of memory die 1814 or junction between components of integrated circuit 1810 above a safe operating limit, which may damage or destroy the memory die. To prevent this, logic IC 1812 may read outputs from one or more temperature sensors or TSEs disposed within memory die 1814 and control a power consumption (and therefore waste heat) of logic IC 1812. For example, if logic IC 1812 receives an output from a TSE disposed within memory die 1814 indicating that a temperature of memory die 1814 is above a threshold (for example, above 125° C), logic IC 1812 or other controller may reduce a power drawn (and exhausted as waste heat) by logic IC 1812. Additionally or alternatively, logic IC 1812 may manage a DRAM voltage in response to a temperature of memory die 1814; for example, logic IC 1812 may lower a voltage in response to determining that a temperature of memory die 1814 is higher than a threshold temperature.

[0128] FIG. 9 illustrates a circuit diagram of a 3DIC stack including a memory die and logic IC. 3DIC stack 1910 may include logic IC 1912 and memory die 1914, which may be analogous to logic IC 1812 and memory die 1814 in FIG. 8. Memory die 1914 may include thermal sensing elements 1924a-b (TSEs 1924a-b). TSEs 1924a-b may include a temperature diode, a Vt threshold current mirror, a thermistor, a thermocouple, or any suitable temperature sensor. A Vt threshold current mirror may include one or more bi-directional N / P metal-oxide semiconductor field effect transistor (MOSFET) circuits including a current source. The threshold voltage for turn on current within the current mirror will change with temperature, allowing the voltage to be used as an indicator of temperature. Additionally or alternatively, TSEs 1924a-b may transmit a delta voltage from a band gap circuit (e.g., in units of volts or millivolts), which may correspond to temperature with a resolution of approximately 0.2 mV / K.

[0129] TSEs 1924a-b may be communicatively coupled with thermal monitoring circuitry 1940 disposed within logic IC 1912. Logic IC 1912 may additionally include TSEs 1922a-b to provide additional resolution of temperature sensors. TSEs 1924a-b may operate by generating a voltage proportional to temperature, which may then be read by thermal monitoring circuitry 1940 and converted into a temperature. Thermal monitoring circuitry 1940 may include one or more temperature sensor circuits 1942a-d, one or more analog-to-digital converters 1944a-d, and control logic 1946.

[0130] Control logic 1946 may include circuitry configured to multiplex individual sensor signals, store sensor values, provide output signals including signals indicating a temperature of memory die 1914 and / or a temperature of logic IC 1912, and provide serial output to allow system engineers to provide feedback control for temperature management. Control logic 1946 may include one or more registers for storing data and making the data accessible through control logic output 1948 and / or control logic input 1947. For example, a user may send a signal using control logic input 1947 causing control logic 1946 to transmit one or more data elements stored on the one or more registers of control logic 1946 using control logic output 1948. Control logic 1946 may utilize control logic output 1948 to output one or more temperatures of memory die 1914, one or more temperatures of logic IC 1912, one or more voltages from TSEs 1922a-b and / or 1924a-b, or any suitable output.

[0131] Control logic 1946 may control an operational parameter of logic IC 1912 and / or memory die 1914. For example, control logic 1946 may control a frequency, voltage, current, power, data transfer rate, computational speed, processing speed, clock speed, or any suitable operational parameter of logic IC 1912 and / or memory die 1914. Control logic 1946 may raise or lower an operational parameter of logic IC 1912 and / or memory die 1914 in response to a temperature of logic IC 1912 and / or memory die 1914. For example, control logic 1946 may lower a frequency, voltage, current, power, data transfer rate, computational speed, processing speed, clock speed, or any suitable operational parameter of logic IC 1912 and / or memory die 1914 in response to determining that a temperature of logic IC 1912 and / or memory die 1914 exceeds a threshold.

[0132] In an aspect, control logic 1946 may control the operational parameter of logic IC 1912 and / or memory die 1914 based on a temperature limit of a bond mechanically coupling the logic IC 1912 and memory die 1914. For example, control logic 1946 may reduce a computational speed of logic IC 1912 if a temperature measured by a TSE exceeds a threshold associated with the bond, such as a hybrid bond, a micro-bump bond, or the like. A thresholdmay be a temperature, such as a predetermined number of degrees (Fahrenheit, Celsius, or any suitable temperature scale) below a melting temperature (TM) or destabilization temperature (TD) of a bond.

[0133] For example, control logic 1946 may control the operational parameter of logic IC 1912 and / or memory die 1914 based on a temperature within memory die 1914 equaling or exceeding (Tm- 30° C).

[0134] 3DIC stack 1910 may be disposed in an immersion cooling system. Such an immersion cooling system may include an immersion cooling container or tank (e.g., tank 2120 as depicted in FIG. 11) at least partially filled with immersion cooling liquid. 3DIC stack 1910 may be at least partially submerged in the immersion cooling liquid. Control logic 1946 may control the operational parameter of logic IC 1912 and / or memory die 1914 based on a boiling temperature or fluid level of the immersion cooling liquid. For example, control logic 1946 may reduce an operational frequency of logic IC 1912 and / or memory die 1914 based on a temperature of logic IC 1912 and / or memory die 1914 exceeding a boiling temperature of the immersion cooling liquid by more than a predetermined threshold, such as 10° C, 15° C, 30° C, 50° C, 100° C, or the like.

[0135] TSEs 1922a-b and 1924a-b may be communicatively coupled to temperature sensor circuits 1942. Temperature sensor circuits 1942 may include circuitry or similar logic configured to receive a voltage, current, or other signal from any of TSEs 1922a-b and / or TSEs 1924a-b and transmit the voltage, current, or other signal to one or more of analog-to-digital converters 1944a-d (ADCs 1944a-d). One or more of ADCs 1944a-d may convert a voltage, current, or other signal from TSE 1922a-b and / or 1924a-b to a number representing a temperature at the location of the respective TSE. ADCs 1944a-d may convert analog voltage readings to digital temperature values with a suitable number of bits of resolution, for example 8 bits, 9 bits, 12 bits, 16 bits, or any suitable number of bits. TSEs 1922a-b and 1924a-b may be capable of determining temperatures between about -55° C and 155° C, between about - 100° C and about 250° C, between about -200° C and about 400° C, or any suitable temperature range. In an embodiment, one or more of ADCs 1944a-d may be communicatively coupled directly to one or more of TSEs 1922a-b and / or 1924a-b.

[0136] In an embodiment, TSEs may be disposed within memory die 1914 only, logic IC 1912 only, or both memory die 1914 and logic IC 1912. Thermal monitoring circuitry 1940 may be disposed within logic IC 1912 only, memory die 1914 only, or both logic IC 1912 andmemory die 1914. Temperature sensor circuits 1942a-d may substantially continuously receive signals from TSEs 1922a-b and / or 1924a-b. Additionally or alternatively, temperature sensor circuits 1942a-d may receive signals with a predetermined frequency such as about once every 0.0001 seconds, about once every 0.001 seconds, about once every 0.01 seconds, about once every 0.1 seconds, about once per second, about once every 2 seconds, about once every 5 seconds, about once every 10 seconds, about once every 30 seconds, about once every 60 seconds, or any suitable frequency.

[0137] Immersion cooling systems may provide particular advantage to 3DIC stacks due to the lower surface area to volume ratio of a 3DIC stack compared to the individual components of the 3DIC stack (e.g., a bonded logic IC and memory module will have a lower surface area to volume ratio than the combined surface area to volume ratio of the physically separated logic IC and memory module) as well as the additional heat generated by state of the art logic ICs. This lower surface area to volume ratio means waste heat generated by the 3DIC stack may not be as efficiently dissipated and may require better cooling performance than air cooling can provide. Two-phase immersion cooling in particular can provide this additional heat removal required by 3DIC stacks.

[0138] FIG. 10A illustrates a 3DIC 2010a in accordance with the present technology. 3DIC 2010a may include a logic IC 2012 and a memory die 2014. 3DIC 2010a may be mechanically and / or communicatively coupled to substrate 2090, which may be a printed circuit board (PCB), silicon wafer, or other suitable substrate. More particularly, 3DIC 2010a may be bonded to substrate 2090 through logic IC 2012. Logic IC 2012 and memory die 2014 may be communicatively coupled through RDL 2018.

[0139] Logic IC 2012 may include one or more control logic 2013a-d. Memory die 2014 may include memory modules 2015, each of which may be configured to store information used and / or produced by logic IC 2012 in operation. Memory modules 2015 may have a design or manufacturing operating temperature limit, above which the memory modules may not function properly or may be damaged. To help prevent damage to the memory modules 2015, memory die 2014 may include one or more TSEs 2024a-d. The one or more TSEs 2024a-d may be communicatively coupled to logic IC 2012 and control logic 2013a-d through RDL 2018 and / or through one or more through- substrate vias 2019.

[0140] RDL 2018 may be analogous to redistribution layer 1350, and may include analogous components. RDL 2018 may include a plurality of alternating metal and insulating layers. For example, an insulating layer may be disposed between a first metal layer and a second metallayer. RDL 2018 may further include a plurality of electrical conductors that extend from one or more of metal layers to one or more through-bond vias.

[0141] RDL 2018 may further provide a benefit of increasing a distance between memory die2014 and logic IC 2012. This increased distance (as compared to a 3DIC lacking an RDL) may reduce a heat flux into memory die 2014, which may accordingly reduce an overall temperature of memory die 2014 during operation of logic IC 2012. RDL 2018 may be bonded to memory die 2014 and / or logic IC 2012 through one or more bump bonds, one or more micro-bump bonds, one or more hybrid bonds, any suitable bond, or any combination thereof.

[0142] A 3DIC in accordance with the present technology may have any suitable orientation or combination of logic ICs and / or memory dies. For example, FIG. 10B illustrates a 3DIC 2010b having the same components as 3DIC 2010a, but being bonded to substrate 2090 via memory die 2014 (i.e., in an “upside down” configuration as compared to 3DIC 2010a). This may be preferable for heat transfer purposes, for example to place more surface area of logic IC 2012 in contact with immersion cooling liquid and provide improved heat transfer as compared to 3DIC 2010a.

[0143] Any dies may be combined to form a suitable 3DIC. For example, FIG. 10C illustrates a 3DIC 2010c including two memory dies 2014 and 2044 communicatively and mechanically coupled through RDL 2018. In an aspect, 3DIC 2010c may include control logic 2030, which may be disposed within memory die 2044 and configured to monitor the one or more TSEs 2024a-d, which may be disposed within memory die 2014. Memory die 2044 may have a reduced number of memory modules 2045 when compared to a number of memory modules2015 included in memory die 2014 due to the additional space required by control logic 2030.

[0144] Analogously, FIG. 10D illustrates a 3DIC 2010d including two logic IC dies 2012 and 2042, communicatively and mechanically coupled through RDL 2018. Logic IC 2042 may include TSEs 2024a-d, which may in turn be communicatively coupled with control logic 2013a-d through RDL 2018. Though not shown, TSEs 2024a-d may additionally or alternatively be communicatively coupled with control logic 2043a-d, which are disposed within logic IC 2042.

[0145] Each 3DIC 2010a-d may further include components analogous to those illustrated in FIGS. 1, 3, and 5, such as filter components including one or more MiM capacitors, one or more insulator layers, and one or more metal layers. The embodiments illustrated in FIGS. 1, 3, 5, and 10A-D may be combined as would be apparent to those skilled in the art in view of the description.

[0146] FIG. 11 depicts aspects of an immersion cooling system 2100 for dissipating heat from one or more heat-generating components such as semiconductor die packages 2105 via immersion cooling. Each package 2105 can include one or more semiconductor dies that produce heat when the system is in operation. The immersion cooling system 2100 in the illustrated example of FIG. 11 is a two-phase immersion cooling system, though the invention may also be implemented in a single-phase immersion cooling system, as well as a system employing direct liquid cooling (DLC).

[0147] Immersion cooling system 2100 includes a container such as tank 2120 filled, at least in part, with immersion cooling liquid 2164. The immersion cooling system 2100 can further include at least one chiller 2180 that flows a heat-transfer fluid through at least one condenser tube 2170 that is disposed in the tank 2120 and headspace 2108. Condenser tubes 2170 and chiller 2180 may be part of a heat exchanger. The packages 2105 can be mounted on one or more printed circuit boards (PCBs) 2157 that are immersed, at least in part, in the immersion cooling liquid 2164. Immersion-cooling system 2100 may further include a filter 2175 disposed adjacent to the tank 2120.

[0148] One or more semiconductor die packages 2105 may be 3DIC stacks in accordance with the present technology. For example, one or more semiconductor die packages 2105 may include a logic IC and at least one memory module bonded to the logic IC using a hybrid bond or micro-bump bond.

[0149] Filter 2175 may include a filtration media, a housing, and a pump configured to force immersion cooling liquid 2164 through filter 2175 to remove contaminants, particulates, or other impurities that may be added to immersion cooling liquid 2164 during use. Filter 2175 may be housed outside of tank 2120 while being in fluidic communication with immersion cooling liquid 2164 in tank 2120. Alternatively, filter 2175 may be submerged within immersion cooling liquid 2164 inside of tank 2120.

[0150] Immersion cooling liquid 2164 may be a hydrocarbon, a fluoroketone, an oil, or a similar dielectric liquid that will act as an insulator while simultaneously transferring heat from package 2105 more efficiently than air. Examples of immersion cooling liquid 2164 are Novec™ 649, Novec™ 7000, and Novec™ 7100 produced by 3M™. An exemplary immersion cooling liquid 2164 used in accordance with embodiments of the present invention may have a dielectric constant baseline value of about 1.8-2 at a frequency of about 1 kHz.

[0151] In an embodiment of the invention, immersion cooling liquid 2164 may be considered unacceptably contaminated if the dielectric constant and / or dielectric loss tangent of immersioncooling fluid being used in an immersion cooling system 2100 differs by a threshold amount as compared to unused or pure immersion cooling liquid 2164. For example, immersion cooling liquid 2164 may be considered unacceptably contaminated or degraded if the dielectric constant and / or dielectric loss tangent differs by a threshold of 10% or more as compared to unused or pure immersion cooling liquid 2164. In an embodiment, a dielectric constant and / or dielectric loss tangent variation threshold may be 20%, 15%, 5%, 3%, 1%, or any suitable threshold.

[0152] Contamination of the immersion cooling liquid 2164 and resulting changes to dielectric constant and / or dielectric loss tangent may alter or negatively impact operation of components within immersion cooling liquid 2164 including semiconductor die(s) 2150. An altered dielectric constant and / or dielectric loss tangent may result in undesirable cross-talk between components on a PCB, additional noise or reduction in signal strength transmitted along exposed wires of a PCB or semiconductor die(s) 2150 submerged in immersion fluid, and / or signal dissipation through the immersion cooling liquid 2164. Signal loss may be severe enough that two elements may be effectively represented as being separated by an open circuit despite being physically connected. In an embodiment, a dielectric constant and / or dielectric loss tangent variation threshold may be selected based on an observed or inferred effect on one or more submerged semiconductor die(s) 2150. For example, an increase in PCIe bit error rate above an error rate baseline may be correlated with an increase in dielectric constant and / or dielectric loss tangent above a dielectric constant and / or dielectric loss tangent baseline. Accordingly, operation of semiconductor die(s) 2150 may be throttled or suspended when a dielectric constant and / or dielectric loss tangent of immersion cooling liquid 2164 exceeds a predetermined threshold.

[0153] Changes to dielectric constant and / or dielectric loss tangent may be caused by contaminants within immersion cooling liquid 2164. In some cases, changes to dielectric constant and / or dielectric loss tangent may be reversed by filtering the contaminants from immersion cooling liquid 2164. In some embodiments, upon detecting an increase in dielectric constant and / or dielectric loss tangent of immersion cooling liquid 2164, controller 2102 may instruct filter 2175 to increase filtration throughput or notify a user that an immersion cooling liquid 2164 filtration media may need to be replaced. If a dielectric constant and / or dielectric loss tangent exceeds a predetermined threshold, controller 2102 may throttle or shut down one or more semiconductor die(s) 2150, generate a notification that immersion cooling liquid 2164 should be replaced, trigger an alarm, etc.

[0154] Further examples of sensors and methods for immersion cooling contamination monitoring may include probes for monitoring immersion cooling liquid parameters such as dielectric constant and dielectric loss tangent, and processors configured to identify trends in sensor data, model immersion cooling system behavior as a function of contamination, and alter operations of immersion cooling systems based on detected levels and / or states of contamination may be found in U.S. Provisional Patent Application 63 / 516,748, filed July 31, 2023 and entitled “Di-Electric Monitoring of Immersion Fluid During Cooling Operation,” the entirety of which is incorporated herein by reference.

[0155] The illustrated example of FIG. 11 is not intended to be to scale. The immersion cooling system 2100 may house and provide immersion cooling liquid 2164 to tens, hundreds, or even thousands of packages 2105. In some cases, the immersion cooling system 2100 can be small (e.g., the size of a floor unit air conditioner, approximately 1 meter high, 0.5 meter width, 0.5 meter depth or length). In some implementations, the immersion cooling system can be large (e.g., the size of a van or larger, approximately 2.5 meters high, 2.5 meters width, 4 meters depth or length).

[0156] The immersion cooling system 2100 can also include a controller 2102 (e.g., a microcontroller, programmable logic controller (PLC), microprocessor, field-programmable gate array, logic circuitry, memory, or some combination thereof) to manage system operation. Controller 2102 can perform various system functions such as monitoring temperatures of system components, cooling fluid level, tank access, chiller operation etc. The controller 2102 can further issue commands to control system operation such as executing a start-up sequence, executing a shut-down sequence, assigning workloads among the packages, changing cooling fluid level, changing the temperature of the heat-transfer fluid circulated by the chiller 2180, etc. In some implementations, controller 2102 can include (or itself be) a baseboard management controller (BMC) 2104. That is, the BMC 2104 may monitor and control all aspects of system operation for the immersion cooling system 2100 in addition to monitoring and controlling workloads of the semiconductor dies 2150 in the packages 2105 cooled by the system. The immersion cooling system 2100 can also include a network interface controller (NIC 2103) to allow the system to communicate over a network, such as a local area network or wide area network. The immersion cooling system 2100 can further include a fluid sensor array 2190 having a plurality of fluid sensors 2110. Fluid sensors 2110 may include one or more leak detection sensors at least partially submerged in immersion cooling liquid 2164.

[0157] The semiconductor die(s) 2150 and can be mounted on and attached to a printed circuitboard (PCB) 2155 (sometimes referred to as a substrate) in device package 2105. The package 2105 can be made commercially available as an off-the-shelf (OTS) product. The package 2105 can be used for single-phase or two-phase immersion cooling of at least one semiconductor die 2150, such as a microprocessor (e.g., a central processing unit (CPU) and / or graphics processing unit (GPU)), voltage regulator (VR), high bandwidth memory (HBM), a digital signal processing (DSP) die, an artificial intelligence (Al) accelerator, an application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), and / or other densely patterned semiconductor die.

[0158] In the two-phase immersion cooling system 2100 of FIG. 11, heat flows from the semiconductor die 2150 where it is generated into the heat spreader 2152. The heat spreader 2152 is in thermal contact with an immersion cooling liquid 2164 that can flow over and extract heat from the heat spreader 2152. The amount of heat delivered by the heat spreader 2152 to the immersion cooling liquid 2164 is enough to boil the immersion cooling liquid 2164 that contacts the heat spreader 2152 (creating bubbles 2165 and potentially creating froth 2167 when bubbles 2165 reach the surface of immersion cooling liquid 2164). The vapor 2166 from the boiled immersion cooling liquid 2164 can be cooled and condensed back to liquid droplets 2168, for example, by the condenser tube 2170. The heat-transfer fluid, such as chilled water, from the chiller 2180 can be circulated through the condenser tube 2170 to lower the temperature of the condenser tube 2170 below the condensation point in the headspace 2108 of the tank 2120. As a result, vapor 2166 condenses on exterior surfaces of the condenser tube 2170 and liquid droplets 2168 from the condensed vapor can drip and / or flow back to the immersion cooling liquid 2164. There may be a plurality of condenser tubes 2170 in tank 2120 to condense the vapor 2166 into droplets. Some or all of the condenser tubes 2170 may or may not be located directly over the PCBs 2157. Instead, the condenser tube(s) 2170 can be located near one or more walls of the tank 2120, such that the condenser tube(s) 2170 are not directly over the PCBs 2157 on which the packages 2105 are mounted.

[0159] To improve thermal performance in two-phase immersion cooling system 2100, the heat spreader 2152 can include a boiling enhancement coating (BEC) on at least one surface. The BEC can be formed from copper or a copper alloy and can be porous, for example, though BECs can take various forms. In some cases, the BEC is a micro porous copper coating having a thickness from approximately or exactly 50 microns to 500 microns thick (which may be produced by electroplating and / or etching). In some implementations, the BEC comprises a mesh copper layer bonded (e.g., via resistance heating) to at least an outer surface of the heatspreader 2152. In some cases, the BEC is applied as particulates to at least one smooth surface of the heat spreader 2152 and then subsequently sintered to adhere to one another and to the heat spreader 2152. The BEC provides an improved surface area to contact the immersion cooling liquid 2164 and can increase the heat transfer coefficient from the heat spreader 2152 to the immersion cooling liquid 2164 by up to a factor of 15 versus a smooth surface on the heat spreader 2152. Accordingly, BECs can increase thermal conductivity to, and accelerate the boiling of, the immersion cooling liquid 2164.

[0160] Further implementations of boiling enhancement coatings and enclosures are possible. Additional arrangements, applications, and methods of use of boiling enhancement coatings and enclosures, including with semiconductor dies and 3DIC stacks, are described in the below U.S. Patent Applications.

[0161] U.S. Patent Application No. 18 / 327,615, filed June 1, 2023 and entitled "Boiler Enhancement Coatings with Active Boiling Management,” discloses heat spreader and boiling enhancement enclosure architectures thermally and / or mechanically coupled to one or more semiconductor dies or logic ICs that may be used for passive and / or active management of immersion cooling fluid boiling, including through the use of valves to control pressure of boiling immersion cooling fluid within a boiling enhancement chamber, particularly in paragraphs

[0018] -

[0039] and FIGS. 3-5B. The entirety of U.S. Patent Application No. 18 / 327,615 is incorporated herein by reference.

[0162] U.S. Provisional Patent Application No. 63 / 500,167, filed May 4, 2023 and entitled “Direct to Chip Heat Spreader and Boiler Enhancement Coatings for Microelectronics,” discloses heat spreader and BECs thermally and / or mechanically coupled to one or more semiconductor dies, logic ICs, and / or 3DIC stacks, particularly in paragraphs

[0015] -

[0033] and FIGS. 2A-4. BEC form factors may include graphite heat spreader architectures, vapor chambers, heat pipes, copper plates, fins, and the like. BEC form factors may be thermally and / or mechanically coupled to the one or more semiconductor dies, logic ICs, and / or 3DIC stacks through a thermally conductive epoxy, and may have varying dimensions relative to a surface to which the semiconductor dies and / or logic ICs are mounted. The entirety of U.S. Provisional Patent Application No. 63 / 500,167 is incorporated herein by reference.

[0163] U.S. Patent Application No. 18 / 460,091, filed September 1, 2023 and entitled “Direct to Chip Application of Boiling Enhancement Coating,” discloses BECs and methods for applying BECs to semiconductor dies, logic ICs, and / or 3DIC stacks in accordance with thepresent technology. In particular, paragraphs

[0024] -

[0046] and FIGS. 2A-5 disclose embodiments of BEC layers, adhesives, solders, sintering, laser ablation, meshes, and other BECs and BEC application methods. The entirety of U.S. Patent Application No. 18 / 460,091 is incorporated herein by reference.

[0164] U.S. Provisional Patent Application No. 63 / 506,945, filed June 8, 2023 and entitled “Vapor- Shedding Structures for Boiler Plates in Two-Phase Immersion Cooling Systems,” discloses structures that may be thermally and / or mechanically coupled to computing hardware such as one or more semiconductor dies, logic ICs, and / or 3DIC stacks to enable the shedding of immersion cooling vapors generated from the boiling of immersion cooling fluid during operation of the computing hardware. In particular, paragraphs

[0021] -

[0039] and FIGS. 3A-5 disclose vapor-shedding structures including varying porosities, constituent materials, and geometries relative to the computing hardware on which they are mounted. The entirety of U.S. Provisional Patent Application No. 63 / 506,945 is incorporated herein by reference.

[0165] U.S. Provisional Application No. 63 / 513,828, filed July 14, 2023 and entitled “Grinding Apparatuses and Methods for Mechanically Modifying Surfaces of Processors to Promote Boiling of a Coolant Liquid,” discloses methods for creating boiling enhancement modifications to surfaces such as the surfaces of computing hardware such as one or more semiconductor dies, logic ICs, and / or 3DIC stacks, particularly in paragraphs

[0036] -

[0095] and FIGS. 2A-8. For example, grooves, patterns, gouges, trenches, or other structures may be added to a surface or lid of a processor, semiconductor die, logic IC, 3DIC stack component, and / or BEC to encourage nucleation sites for bubbles of immersion cooling vapor to form during a cooling process, thus decreasing the thermal resistance between the processor, semiconductor die, logic IC, and / or 3DIC stack component and the surrounding immersion cooling fluid. The entirety of U.S. Provisional Application No. 63 / 513,828 is incorporated herein by reference.

[0166] U.S. Provisional Patent Application No. 63 / 513,829, filed July 14, 2023 and entitled “Electrical Connector Having a Heater to Facilitate Boiling of a Coolant Liquid to Improve Signal Integrity in Immersion Cooling Environment,” discloses heaters for promoting boiling of immersion cooling fluid near electrical connectors such as connections between components of a 3DIC stack and enable improved impedances at those connectors, particularly in paragraphs

[0019] -

[0052] and FIGS. 1A-3B. The entirety of U.S. Provisional Patent Application No. 63 / 513,829 is incorporated herein by reference.

[0167] U.S. Provisional Patent Application No. 63 / 603,1942, filed November 28, 2023 and entitled “Woven Boiler Enhancement Coatings,” provides additional examples of BECs including woven BECs with variable weave patterns, densities, attachment mechanisms, and materials (including copper and tungsten) that may be attached to computing hardware such as one or more semiconductor dies, logic ICs, and / or 3DIC stacks in order to promote more efficient heat transfer and immersion cooling vapor nucleation, particularly in paragraphs

[0031] -

[0055] and FIGS. 3-7. The entirety of U.S. Provisional Patent Application No. 63 / 603,1942 is incorporated herein by reference.

[0168] FIG. 12 is a flowchart of an example method 2200 for thermal management in three- dimensional integrated circuits (3DICs). Method 2200 includes blocks 2210-2230.

[0169] Block 2210 includes receiving, by an analog-to-digital converter (ADC) disposed in a logic integrated circuit (IC), a first voltage of a temperature sensing element (TSE) disposed in a memory die. The ADC may receive the first voltage through an RDL disposed between the logic IC and the memory die. The ADC, logic IC, and memory die may be part of a 3DIC.

[0170] Block 2220 includes converting, by the ADC, the first voltage to a temperature, wherein the ADC is communicatively coupled to the first TSE.

[0171] Block 2230 includes controlling, by the logic IC, an operational parameter of the logic IC or the memory die based on the temperature. The operational parameter may include a frequency, a voltage, a current, a power, a data transfer rate, a computational speed, a processing speed, or a clock speed. The logic IC may be further configured to control an operational parameter of the logic IC or the memory die based on a temperature limit of a bond mechanically coupling the memory die and the logic IC. The logic IC may be further configured to control an operational parameter of the logic IC or the memory die based on a boiling temperature of an immersion cooling liquid in which the logic IC is disposed. The bond may include at least one of a hybrid bond, a bump bond, or a micro-bump bond.

[0172] Method 2200 may further include blocks 2240-2260. Block 2240 may include receiving, by the ADC, a second voltage of a second TSE, the second TSE disposed in the logic IC. Block 2250 may include converting, by the ADC, the second voltage to a second temperature. Block 2260 may include controlling, by the logic IC, the operational parameter of the logic IC or the memory die based on the second temperature.

[0173] Clause 1. A system for thermal management in three-dimensional integrated circuits (3DICs), the system comprising: a 3DIC comprising a logic integrated circuit (IC) and amemory die, the memory die bonded to the logic IC; a first thermal sensing element (TSE) disposed within the memory die and communicatively coupled to a control logic within the logic IC; wherein the control logic is configured to determine a temperature within the memory die using the first TSE.

[0174] Clause 2. The system of clause 1, wherein: the logic IC and the memory die are bonded through a redistribution layer (RDL); and the first TSE and the control logic are communicatively coupled through the RDL.

[0175] Clause 3. The system of clause 2, wherein the RDL comprises a through-substrate via (TSV); and the first TSE and the control logic are communicatively coupled through the TSV.

[0176] Clause 4. The system of clause 1, wherein the first TSE is disposed between at least one memory module of the memory die and the logic IC.

[0177] Clause 5. The system of clause 1, wherein the control logic is further configured to control an operational parameter of the logic IC or the memory die based on the temperature within the memory die.

[0178] Clause 6. The system of clause 5, wherein the operational parameter comprises a frequency, a voltage, a current, a power, a data transfer rate, a computational speed, a processing speed, or a clock speed.

[0179] Clause 7. The system of clause 1, wherein the control logic is further configured to control an operational parameter of the logic IC or the memory die based on a temperature limit of a bond mechanically coupling the memory die and the logic IC.

[0180] Clause 8. The system of clause 7, wherein the bond comprises at least one of a hybrid bond, a bump bond, or a micro-bump bond.

[0181] Clause 9. The system of clause 1, further comprising a second TSE disposed within the logic IC.

[0182] Clause 10. The system of clause 9, wherein the control logic is further configured to control an operational parameter of the logic IC or the memory die based on a temperature detected using the second TSE.

[0183] Clause 11. The system of clause 10, wherein the operational parameter comprises a frequency, a voltage, a current, a power, a data transfer rate, a computational speed, a processing speed, or a clock speed.

[0184] Clause 12. The system of clause 1, further comprising a container at least partially filled with immersion cooling liquid, wherein: the 3DIC is disposed within the immersion cooling liquid; and the control logic is further configured to control an operational parameter of the logic IC or the memory die based on a boiling temperature of the immersion cooling liquid.

[0185] Clause 13. A method for thermal management in three-dimensional integrated circuits (3DICs), the method comprising: receiving, by an analog-to-digital converter (ADC) disposed in a logic integrated circuit (IC), a first voltage of a temperature sensing element (TSE) disposed in a memory die; converting, by the ADC, the first voltage to a temperature, wherein the ADC is communicatively coupled to the first TSE; controlling, by the logic IC, an operational parameter of the logic IC or the memory die based on the temperature.

[0186] Clause 14. The method of clause 13, wherein the ADC receives the first voltage through a redistribution layer (RDL) disposed between the logic IC and the memory die.

[0187] Clause 15. The method of clause 13, wherein the operational parameter comprises a frequency, a voltage, a current, a power, a data transfer rate, a computational speed, a processing speed, or a clock speed.

[0188] Clause 16. The method of clause 13, further comprising: receiving, by the ADC, a second voltage of a second TSE, the second TSE disposed in the logic IC; converting, by the ADC, the second voltage to a second temperature; controlling, by the logic IC, the operational parameter of the logic IC or the memory die based on the second temperature.

[0189] Clause 17. The method of clause 16, wherein the operational parameter comprises a frequency, a voltage, a current, a power, a data transfer rate, a computational speed, a processing speed, or a clock speed.

[0190] Clause 18. The method of clause 16, wherein the logic IC is further configured to control an operational parameter of the logic IC or the memory die based on a temperature limit of a bond mechanically coupling the memory die and the logic IC.

[0191] Clause 19. The method of clause 18, wherein the bond comprises at least one of a hybrid bond, a bump bond, or a micro-bump bond.

[0192] Clause 20. A three-dimensional integrated circuit (3DIC) comprising: a first integrated circuit (IC) die including a first substrate and a first IC; a second IC die including a second substrate and a second IC; a hybrid bond disposed between the first IC die and the second ICdie; and a redistribution layer (RDL) disposed on the first IC die; wherein the first substrate of the first IC die is disposed between the RDL and the first IC of the first IC die; and wherein the RDL includes a passive filter component.

[0193] Clause 21. The 3DIC of clause 20, wherein the first IC comprises a logic IC and the second IC comprises a memory.

[0194] Clause 22. The 3DIC of clause 21, wherein: the second IC die comprises a thermal sensing element (TSE), the TSE communicatively coupled to the first IC through the RDL.

[0195] Clause 23. The 3DIC of clause 20, wherein the passive filter component comprises a metal-insulator-metal (MiM) capacitor.

[0196] Clause 24. The 3DIC of clause 23, wherein the 3DIC is configured to receive electrical power from an external source and the RDL is configured to electrically couple the electric power to the MiM capacitor.

[0197] Clause 25. The 3DIC of clause 20, wherein the first substrate of the first IC die is disposed between the hybrid bond and the RDL.

[0198] Clause 26. The 3DIC of clause 20, wherein the RDL is disposed between the hybrid bond and the first substrate of the first IC die.

[0199] Clause 27. The 3DIC of clause 23, wherein the RDL comprises an insulator layer and the MiM capacitor of the RDL comprises a dielectric having a dielectric constant greater than a dielectric constant of the insulator layer of the RDL.

[0200] Clause 28. The 3DIC of clause 23, wherein the MiM capacitor of the RDL comprises a dielectric having a dielectric constant greater than about 9.

[0201] Clause 29. The 3DIC of clause 23, wherein: the RDL includes a first metal layer, a second metal layer and a third metal layer; and the MiM capacitor is disposed between the first metal layer of the RDL and the third metal layer of the RDL.Conclusion

[0202] While various inventive embodiments have been described and illustrated herein, those of ordinary skill in the art will readily envision a variety of other means and / or structures for performing the function and / or obtaining the results and / or one or more of the advantages described herein, and each of such variations and / or modifications is deemed to be within the scope of the inventive embodiments described herein. More generally, those skilled in the artwill readily appreciate that all parameters, dimensions, materials, and configurations described herein are meant to be exemplary and that the actual parameters, dimensions, materials, and / or configurations will depend upon the specific application or applications for which the inventive teachings is / are used. Those skilled in the art will recognize, or be able to ascertain using no more than routine experimentation, many equivalents to the specific inventive embodiments described herein. It is, therefore, to be understood that the foregoing embodiments are presented by way of example only and that, within the scope of the appended claims and equivalents thereto, inventive embodiments may be practiced otherwise than as specifically described and claimed. Inventive embodiments of the present disclosure are directed to each individual feature, system, article, material, kit, and / or method described herein. In addition, any combination of two or more such features, systems, articles, materials, kits, and / or methods, if such features, systems, articles, materials, kits, and / or methods are not mutually inconsistent, is included within the inventive scope of the present disclosure.

[0203] Also, various inventive concepts may be embodied as one or more methods, of which an example has been provided. The acts performed as part of the method may be ordered in any suitable way. Accordingly, embodiments may be constructed in which acts are performed in an order different than illustrated, which may include performing some acts simultaneously, even though shown as sequential acts in illustrative embodiments.

[0204] All definitions, as defined and used herein, should be understood to control over dictionary definitions, definitions in documents incorporated by reference, and / or ordinary meanings of the defined terms.

[0205] The indefinite articles “a” and “an,” as used herein in the specification and in the claims, unless clearly indicated to the contrary, should be understood to mean “at least one.”

[0206] The phrase “and / or,” as used herein in the specification and in the claims, should be understood to mean “either or both” of the elements so conjoined, i.e., elements that are conjunctively present in some cases and disjunctively present in other cases. Multiple elements listed with “and / or” should be construed in the same fashion, i.e., “one or more” of the elements so conjoined. Other elements may optionally be present other than the elements specifically identified by the “and / or” clause, whether related or unrelated to those elements specifically identified. Thus, as a non-limiting example, a reference to “A and / or B”, when used in conjunction with open-ended language such as “comprising” can refer, in one embodiment, to A only (optionally including elements other than B); in another embodiment, to B only(optionally including elements other than A); in yet another embodiment, to both A and B (optionally including other elements); etc.

[0207] As used herein in the specification and in the claims, “or” should be understood to have the same meaning as “and / or” as defined above. For example, when separating items in a list, “or” or “and / or” shall be interpreted as being inclusive, i.e., the inclusion of at least one, but also including more than one, of a number or list of elements, and, optionally, additional unlisted items. Only terms clearly indicated to the contrary, such as “only one of’ or “exactly one of,” or, when used in the claims, “consisting of,” will refer to the inclusion of exactly one element of a number or list of elements. In general, the term “or” as used herein shall only be interpreted as indicating exclusive alternatives (i.e. “one or the other but not both”) when preceded by terms of exclusivity, such as “either,” “one of,” “only one of,” or “exactly one of.” “Consisting essentially of,” when used in the claims, shall have its ordinary meaning as used in the field of patent law.

[0208] As used herein in the specification and in the claims, the phrase “at least one,” in reference to a list of one or more elements, should be understood to mean at least one element selected from any one or more of the elements in the list of elements, but not necessarily including at least one of each and every element specifically listed within the list of elements and not excluding any combinations of elements in the list of elements. This definition also allows that elements may optionally be present other than the elements specifically identified within the list of elements to which the phrase “at least one” refers, whether related or unrelated to those elements specifically identified. Thus, as a non-limiting example, “at least one of A and B” (or, equivalently, “at least one of A or B,” or, equivalently “at least one of A and / or B”) can refer, in one embodiment, to at least one, optionally including more than one, A, with no B present (and optionally including elements other than B); in another embodiment, to at least one, optionally including more than one, B, with no A present (and optionally including elements other than A); in yet another embodiment, to at least one, optionally including more than one, A, and at least one, optionally including more than one, B (and optionally including other elements); etc.

[0209] In the claims, as well as in the specification above, all transitional phrases such as “comprising,” “including,” “carrying,” “having,” “containing,” “involving,” “holding,” “composed of,” and the like are to be understood to be open-ended, i.e., to mean including but not limited to. Only the transitional phrases “consisting of’ and “consisting essentially of’ shallbe closed or semi-closed transitional phrases, respectively, as set forth in the United States Patent Office Manual of Patent Examining Procedures, Section 2111.03.

Claims

CLAIMS1. A system for thermal management in three-dimensional integrated circuits (3DICs), the system comprising: a 3DIC comprising a logic integrated circuit (IC) and a memory die, the memory die bonded to the logic IC; and a first thermal sensing element (TSE) disposed within the memory die and communicatively coupled to a control logic within the logic IC; wherein the control logic is configured to determine a temperature within the memory die using the first TSE.

2. The system of claim 1, wherein: the logic IC and the memory die are bonded through a redistribution layer (RDL); and the first TSE and the control logic are communicatively coupled through the RDL.

3. The system of claim 2, wherein the RDL comprises a through- substrate via (TSV); and the first TSE and the control logic are communicatively coupled through the TSV.

4. The system of claim 1, wherein the first TSE is disposed between at least one memory module of the memory die and the logic IC.

5. The system of claim 1, wherein the control logic is further configured to control an operational parameter of the logic IC or the memory die based on the temperature within the memory die.

6. The system of claim 5, wherein the operational parameter comprises a frequency, a voltage, a current, a power, a data transfer rate, a computational speed, a processing speed, or a clock speed.

7. The system of claim 1, wherein the control logic is further configured to control an operational parameter of the logic IC or the memory die based on a temperature limit of a bond mechanically coupling the memory die and the logic IC.

8. The system of claim 7, wherein the bond comprises at least one of a hybrid bond, a bump bond, or a micro-bump bond.

9. The system of claim 1, further comprising a second TSE disposed within the logic IC.

10. The system of claim 9, wherein the control logic is further configured to control an operational parameter of the logic IC or the memory die based on a temperature detected using the second TSE.

11. The system of claim 10, wherein the operational parameter comprises a frequency, a voltage, a current, a power, a data transfer rate, a computational speed, a processing speed, or a clock speed.

12. The system of claim 1, further comprising a container at least partially filled with immersion cooling liquid, wherein: the 3DIC is disposed within the immersion cooling liquid; and the control logic is further configured to control an operational parameter of the logic IC or the memory die based on a boiling temperature of the immersion cooling liquid.

13. A method for thermal management in three-dimensional integrated circuits (3DICs), the method comprising: receiving, by an analog-to-digital converter (ADC) disposed in a logic integrated circuit (IC), a first voltage of a temperature sensing element (TSE) disposed in a memory die; converting, by the ADC, the first voltage to a temperature, wherein the ADC is communicatively coupled to the first TSE; and controlling, by the logic IC, an operational parameter of the logic IC or the memory die based on the temperature.

14. The method of claim 13, wherein the ADC receives the first voltage through a redistribution layer (RDL) disposed between the logic IC and the memory die.

15. The method of claim 13, wherein the operational parameter comprises a frequency, a voltage, a current, a power, a data transfer rate, a computational speed, a processing speed, ora clock speed.

16. The method of claim 13, further comprising: receiving, by the ADC, a second voltage of a second TSE, the second TSE disposed in the logic IC; converting, by the ADC, the second voltage to a second temperature; and controlling, by the logic IC, the operational parameter of the logic IC or the memory die based on the second temperature.

17. The method of claim 16, wherein the operational parameter comprises a frequency, a voltage, a current, a power, a data transfer rate, a computational speed, a processing speed, or a clock speed.

18. The method of claim 16, wherein the logic IC is further configured to control an operational parameter of the logic IC or the memory die based on a temperature limit of a bond mechanically coupling the memory die and the logic IC.

19. The method of claim 18, wherein the bond comprises at least one of a hybrid bond, a bump bond, or a micro-bump bond.

20. A three-dimensional integrated circuit (3DIC) comprising: a first integrated circuit (IC) die including a first substrate and a first IC; a second IC die including a second substrate and a second IC; a hybrid bond disposed between the first IC die and the second IC die; and a redistribution layer (RDL) disposed on the first IC die; wherein the first substrate of the first IC die is disposed between the RDL and the firstIC of the first IC die; and wherein the RDL includes a passive filter component.

21. The 3DIC of claim 20, wherein the first IC comprises a logic IC and the second IC comprises a memory.

22. The 3DIC of claim 21, wherein:the second IC die comprises a thermal sensing element (TSE), the TSE communicatively coupled to the first IC through the RDL.

23. The 3DIC of claim 20, wherein the passive filter component comprises a metalinsulator-metal (MiM) capacitor.

24. The 3DIC of claim 23, wherein the 3DIC is configured to receive electrical power from an external source and the RDL is configured to electrically couple the electric power to the MiM capacitor.

25. The 3DIC of claim 20, wherein the first substrate of the first IC die is disposed between the hybrid bond and the RDL.

26. The 3DIC of claim 20, wherein the RDL is disposed between the hybrid bond and the first substrate of the first IC die.

27. The 3DIC of claim 23, wherein the RDL comprises an insulator layer and the MiM capacitor of the RDL comprises a dielectric having a dielectric constant greater than a dielectric constant of the insulator layer of the RDL.

28. The 3DIC of claim 23, wherein the MiM capacitor of the RDL comprises a dielectric having a dielectric constant greater than about 9.

29. The 3DIC of claim 23, wherein: the RDL includes a first metal layer, a second metal layer and a third metal layer; and the MiM capacitor is disposed between the first metal layer of the RDL and the third metal layer of the RDL.

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