Integrated circuit design method and apparatus, and integrated circuit and storage system

Abstract

The present application provides an integrated circuit design method and apparatus, and an integrated circuit and a storage system. The method comprises: acquiring initial information of a chip, and on the basis of the initial information, dividing the chip into a plurality of logic modules; determining first areas and second areas in an integrated circuit that correspond to the logic modules, wherein the first areas corresponding to the logic modules satisfy axial or central symmetry; selecting one logic module as a reference logic module, carrying out circuit design on the first area of the integrated circuit that corresponds to the reference logic module, and on the basis of the axial or central symmetry, acquiring circuit designs of the first areas of the integrated circuit that correspond to the other logic modules; and respectively carrying out circuit design on the second areas of the integrated circuit that correspond to the logic modules, so as to obtain a target integrated circuit design.

Description

Integrated circuit design method, device, integrated circuit, and storage system Technical Field

[0001] The present application relates to the field of semiconductor technology, and more specifically, to a method, device, integrated circuit, and storage system for integrated circuit design. Background Art

[0002] With the development of semiconductor technology, three-dimensional memory has achieved vertical interconnection, which has the advantages of reducing the chip packaging size, reducing the length of interconnection lines, increasing the chip's operating speed, reducing latency, and reducing chip power consumption. It is becoming more and more widely used in the semiconductor field.

[0003] Three-dimensional memory can achieve hierarchical interconnection between multiple layers of dynamic random access memory (DRAM) chips and programmable logic devices (PLDs), also known as logic chips, through through silicon vias (TSVs), micro-bumping, and hybrid bonding (HB). Three-dimensional integrated circuits (3D ICs) are used in interconnected packaging structures for multiple chips. DRAM and PLDs are stacked face-to-face. After the two chips are positioned in a standard position, they are bonded using HB to interconnect them.

[0004] The complexity of the chip structure leads to a long design cycle and high cost for three-dimensional integrated circuits. Therefore, how to shorten the design cycle of three-dimensional integrated circuits and improve the design efficiency of circuits is an urgent problem to be solved. Technical Solutions

[0005] Some embodiments of the present application provide a method, an apparatus, an integrated circuit, and a storage system for designing an integrated circuit.

[0006] According to a first aspect of the present application, a method for integrated circuit design is provided, which may include: obtaining initial information of a chip, and dividing the chip into multiple logic modules based on the initial information; determining a first area and a second area in the integrated circuit corresponding to the logic module, wherein the first area of ​​the logic module satisfies axial symmetry or central symmetry; selecting the logic module as a reference logic module, performing circuit design on the first area of ​​the integrated circuit corresponding to the reference logic module, and obtaining circuit designs of the first areas of the integrated circuits corresponding to the remaining logic modules based on axial symmetry or central symmetry; performing circuit design on the second areas of the integrated circuit corresponding to the logic module respectively to obtain a target integrated circuit design.

[0007] In one embodiment of the present application, obtaining initial information of a chip and dividing the chip into multiple logic modules based on the initial information may include: obtaining the distribution and storage structure of the bonding interface of the chip based on the initial information; dividing the chip based on the distribution of the bonding interface and the storage structure to obtain multiple logic modules, wherein the overlap rate of the distribution of the bonding interfaces of different logic modules is greater than or equal to an overlap rate threshold, and the storage structure distribution of different logic modules satisfies axial symmetry or central symmetry.

[0008] In one embodiment of the present application, dividing the chip based on the distribution of the bonding interface and the storage structure to obtain a plurality of the logic modules may include: performing a first pre-processing on the chip based on the distribution of the bonding interface to obtain a first number of first pre-logic modules; performing a second pre-processing on the chip based on the storage structure to obtain a second number of second pre-logic modules; comparing the first number and the second number, if the first number is greater than the second number, dividing the chip based on the second pre-processing, and if the first number is less than the second number, dividing the chip based on the first pre-processing.

[0009] In one embodiment of the present application, the chip includes multiple storage units, and circuit design is performed on the second area of ​​the integrated circuit corresponding to the logic module to obtain a target integrated circuit design, which may include: determining the number of the bonding interfaces based on the distribution of the bonding interfaces, and determining multiple first sub-areas and second sub-areas in the second area based on the number of the bonding interfaces and the distribution of the bonding interfaces, wherein the first sub-areas and the second sub-areas are distributed at intervals; configuring the first sub-areas and the second sub-areas corresponding to the storage units and the bonding interfaces, wherein the first sub-areas and the second sub-areas both include a winding area and a unit placement area.

[0010] In one embodiment of the present application, the method may further include: obtaining a standard grid of the chip and determining the initial positions of standard components in the second area; comparing the initial positions of the standard components in the second area of ​​each logic module with the standard grid to obtain comparison results; determining the target positions of the standard components in the second area based on the comparison results, and placing the corresponding standard components in the second area based on the target positions.

[0011] According to a second aspect of the present application, there is provided an integrated circuit design device, which may include: a chip partitioning unit, configured to obtain initial information of a chip and, based on the initial information, divide the chip into a plurality of logic modules; an area confirmation unit, configured to determine a first area and a second area in the integrated circuit corresponding to the logic module, wherein the first area of ​​the logic module satisfies axial symmetry or central symmetry; a first circuit design unit, configured to select one of the logic modules as a reference logic module, perform circuit design on the first area of ​​the integrated circuit corresponding to the reference logic module, and obtain circuit designs of the first areas of the integrated circuits corresponding to the remaining logic modules based on axial symmetry or central symmetry; and a second circuit design unit, configured to perform circuit design on the second areas of the integrated circuit corresponding to the logic modules respectively to obtain a target integrated circuit design.

[0012] In one embodiment of the present application, the chip division unit can be used to obtain the distribution and storage structure of the bonding interface of the chip based on the initial information; divide the chip based on the distribution of the bonding interface and the storage structure to obtain multiple logic modules, wherein the overlap rate of the distribution of the bonding interfaces of different logic modules is greater than or equal to the overlap rate threshold, and the storage structure distribution of different logic modules satisfies axial symmetry or central symmetry.

[0013] In one embodiment of the present application, the chip division unit can also be used to perform a first pre-processing on the chip based on the distribution of the bonding interface to obtain a first number of first pre-logic modules; perform a second pre-processing on the chip based on the storage structure to obtain a second number of second pre-logic modules; compare the first number and the second number, if the first number is greater than the second number, divide the chip based on the second pre-processing, if the first number is less than the second number, divide the chip based on the first pre-processing.

[0014] In one embodiment of the present application, the second circuit design unit can be used to determine the number of the bonding interfaces based on the distribution of the bonding interfaces, and determine a plurality of first sub-regions and second sub-regions within the second region based on the number of the bonding interfaces and the distribution of the bonding interfaces, wherein the first sub-regions and the second sub-regions are spaced apart; and the first sub-regions and the second sub-regions corresponding to the storage unit and the bonding interface are configured, wherein the first sub-region and the second sub-region both include a winding area and a cell placement area.

[0015] In one embodiment of the present application, the second circuit design unit can also be used to obtain a standard grid of the chip and determine the initial positions of standard components in the second area; compare the initial positions of the standard components in the second area of ​​each logic module with the standard grid to obtain a comparison result; determine the target position of the standard components in the second area based on the comparison result, and place the corresponding standard components in the second area based on the target position.

[0016] A third aspect of the present application provides an integrated circuit, which is generated based on the above-mentioned integrated circuit design method or the above-mentioned integrated circuit design device.

[0017] A fourth aspect of the present application provides a chip, which may include a logic chip and a memory chip connected to the logic chip, wherein the logic chip includes the above-mentioned integrated circuit.

[0018] A fifth aspect of the present application provides a storage system, which may include: a chip as described above; and a controller coupled to the chip and controlling the chip to store data. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Other features, objects and advantages of the present application will become more apparent from the detailed description of non-limiting embodiments made with reference to the following drawings, in which:

[0020] FIG1 is a flowchart of a method 1000 for designing an integrated circuit according to an embodiment of the present application;

[0021] FIG2 is a flowchart of dividing a chip into multiple logic modules based on initial information according to an exemplary embodiment of the present application;

[0022] FIG3 is a flowchart of chip partitioning according to an exemplary embodiment of the present application;

[0023] FIG4 is a schematic diagram of a divided logic module according to an exemplary embodiment of the present application;

[0024] FIG5 is a schematic diagram of a partial region of an integrated circuit including a first region and a second region according to an exemplary embodiment of the present application;

[0025] FIG6 is a schematic diagram of a first region and a second region according to an exemplary embodiment of the present application;

[0026] FIG7 is a flow chart of a second region circuit design according to an exemplary embodiment of the present application;

[0027] FIG8 is a schematic diagram of a first sub-region and a second sub-region according to an exemplary embodiment of the present application;

[0028] FIG9 is a flow chart of placing filling components in the second area according to an exemplary embodiment of the present application;

[0029] FIG10 is a block diagram of an integrated circuit design apparatus 2000 according to an embodiment of the present application;

[0030] FIG11 is a block diagram of a storage system according to an exemplary embodiment of the present application;

[0031] FIG12A is a schematic diagram of a nonvolatile memory system according to an exemplary embodiment of the present application; and

[0032] FIG. 12B is a schematic diagram of a nonvolatile memory system according to another exemplary embodiment of the present application. DETAILED DESCRIPTION

[0033] For a better understanding of the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely descriptions of exemplary embodiments of the present application and are not intended to limit the scope of the present application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0034] In the accompanying drawings, the size, dimensions, and shapes of the elements have been slightly adjusted for ease of illustration. The accompanying drawings are for illustration only and are not drawn strictly to scale. As used herein, the terms "substantially," "approximately," and similar terms are used to indicate approximations, not degrees, and are intended to illustrate inherent deviations in measurements or calculations that would be recognized by a person of ordinary skill in the art. In addition, in this application, the order in which the steps are described does not necessarily represent the order in which these steps would occur in actual operation, unless otherwise specified or inferred from the context.

[0035] It should also be understood that expressions such as "comprises," "including," "having," "includes," and / or "comprising" are open rather than closed expressions in this specification, indicating the presence of the stated features, elements, and / or components, but do not exclude the presence of one or more other features, elements, components, and / or combinations thereof. In addition, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features rather than just the individual elements in the list. In addition, when describing embodiments of the present application, "may" is used to mean "one or more embodiments of the present application." And, the term "exemplary" is intended to refer to an example or illustration.

[0036] Unless otherwise defined, all words used herein (including engineering terms and scientific and technological terms) have the same meaning as commonly understood by those skilled in the art to which this application belongs. It should also be understood that, unless otherwise specified in this application, words defined in commonly used dictionaries should be interpreted as having the same meaning as they do in the context of the relevant technology, and should not be interpreted in an idealized or overly formal sense.

[0037] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in this application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0038] FIG1 is a flow chart of a method 1000 for designing an integrated circuit according to an embodiment of the present application. As shown in FIG1 , the method 1000 for designing an integrated circuit may include:

[0039] Step S100: obtaining initial information of the chip, and dividing the chip into multiple logic modules based on the initial information;

[0040] Step S200: determining a first region and a second region in the integrated circuit corresponding to the logic module, wherein the first region of the logic module satisfies axisymmetry or central symmetry;

[0041] Step S300: Selecting a logic module as a reference logic module, performing circuit design on a first region of the integrated circuit corresponding to the reference logic module, and obtaining circuit designs of the first regions of the integrated circuit corresponding to the remaining logic modules based on axial symmetry or central symmetry;

[0042] Step S400: performing circuit design on the second region of the integrated circuit corresponding to each logic module to obtain a target integrated circuit design.

[0043] The specific contents of each step of the above-mentioned integrated circuit design method 1000 will be described in detail below.

[0044] Step S100

[0045] In an exemplary embodiment of the present application, initial information of the chip is first obtained, and the chip is divided into multiple logic modules based on the initial information. Figure 2 is a flow chart of dividing the chip into multiple logic modules based on the initial information according to an exemplary embodiment of the present application. As shown in Figure 2, dividing the chip into multiple logic modules may include the following steps:

[0046] Step S110: obtaining the distribution and storage structure of the bonding interfaces of the chip based on the initial information;

[0047] Step S120: Divide the chip based on the distribution of bonding interfaces and the storage structure to obtain multiple logic modules, wherein the overlap rate of the distribution of bonding interfaces of different logic modules is greater than or equal to the overlap rate threshold, and the storage structures of different logic modules satisfy axial symmetry or central symmetry.

[0048] For example, a chip packaged in a 3D IC is used for example. Based on the design or manufacturing process of the chip, its initial information can be obtained, and then its bonding interface distribution and storage structure are obtained according to the initial information of the chip. For example, the storage capacity of the chip is 8GB, each chip includes 52 storage blocks (blocks), and the bonding interface may include a signal interface and a power network interface. Then, based on the distribution and storage structure of the bonding interface, the chip is divided into multiple logic modules (meshes), wherein the overlap rate of the distribution of the bonding interfaces of different logic modules is greater than or equal to the overlap rate threshold, and the storage structure of different logic modules satisfies axial symmetry or central symmetry. The overlap rate of the distribution of the bonding interfaces of different logic modules can determine the complexity of the subsequent integrated circuit, and the overlap rate threshold can be set according to the actual situation of the integrated circuit. For example, the overlap rate threshold can be set to 70%, 75%, 80%, etc. Figure 3 is a flowchart of dividing the chip according to an exemplary embodiment of the present application. Figure 4 is a schematic diagram of the divided logic module according to an exemplary embodiment of the present application. As shown in Figure 3, dividing the chip based on the distribution and storage structure of the bonding interface may include the following steps:

[0049] Step S111: performing a first pre-processing on the chip based on the distribution of the bonding interfaces to obtain a first number of first pre-logic modules;

[0050] Step S112: performing a second pre-processing on the chip based on the storage structure to obtain a second number of second pre-logic modules;

[0051] Step S113: Compare the first number and the second number. If the first number is greater than the second number, divide the chips based on the second pre-processing. If the first number is less than the second number, divide the chips based on the first pre-processing.

[0052] In conjunction with Figures 3 and 4, taking a chip with an 8GB storage capacity as an example, the chip can include 6144 storage cells and 256 arithmetic and logic units (ALUs). Based on the distribution of the bonding interfaces, the chip is first pre-processed to obtain a first number of first pre-logic modules, where the first pre-processing can be a first pre-division. Based on the first pre-division, the chip can be divided into 8 logic modules, each of which has a storage capacity of 0.996GB, approximately equal to 1GB. The bonding interfaces of the 8 0.996GB logic modules are symmetrical about points O1 and O2, respectively. Based on the storage structure, the chip is second pre-processed to obtain a second number of second pre-logic modules, where the second pre-processing can be a second pre-division. Based on the chip structure requirements, each logic module requires 2GB of storage capacity. Therefore, the chip needs to be divided into 4 logic modules, namely, the first logic module mesh01, the second logic module mesh02, the third logic module mesh03, and the fourth logic module mesh04. Mesh01, mesh02, mesh03, and mesh04 are symmetrical about point O. Each logic module has a storage capacity of 2GB and consists of 13 blocks, meaning that the 2GB storage capacity is evenly divided among the 13 sub-blocks. Compare the first and second numbers, and then select the preprocessing method corresponding to the smaller number as the final preprocessing method. For example, if the first preprocessing method divides the chip into 8 logic modules, and the second preprocessing method divides the chip into 4 logic modules, then 4 logic modules is selected as the final partitioning method.

[0053] According to the exemplary embodiment of the present application, the chip is divided based on the distribution of the bonding interface and the storage structure, and the final division method of the logic module is obtained, which makes the chip more reasonably divided, and is conducive to simplifying the design of the integrated circuit corresponding to the subsequent logic module.

[0054] Step S200

[0055] In an exemplary embodiment of the present application, after obtaining a plurality of logic modules, the first region and the second region in the integrated circuit corresponding to the logic module are determined, wherein the first region of the logic module satisfies axial symmetry or central symmetry. The first region is a similar region of the integrated circuit in each logic module, and the second region is a different region of the integrated circuit in each logic module. Figure 5 is a schematic diagram of a partial region of an integrated circuit according to the first region and the second region of an exemplary embodiment of the present application. As shown in Figure 5, the hybrid bonding area of ​​the integrated circuit may include a first region 210 and a second region 220, wherein a plurality of first regions 210 satisfy axial symmetry or central symmetry, and the portion of the logic module that cannot satisfy axial symmetry or central symmetry constitutes the second region 220. Among them, the second region 220 is the hybrid bonding area of ​​the chip, that is, the logic chip and the DRAM chip bond the bonding interface inside the hybrid bonding area together, and the bonding interfaces of the logic chip and the DRAM chip need to correspond one to one.

[0056] In an exemplary embodiment of the present application, the bonding interface may include a signal interface and a power network interface. According to the specific circumstances of the chip, the design process is divided into top-level design, mesh layer design and block layer design. For example, in the process of integrated circuit design, the power network interface and signal interface in the second area 220 are configured on the top layer of the logic chip for integrated circuit design, and are implemented with the top metal layer. The mesh layer power network interface uses the bottom metal routing and is connected to the top metal layer power network interface through a through hole to form a power network connection for the entire chip. The second area 220 in the mesh layer is covered by a routing blockage on the top metal layer to avoid a short circuit in the power network or signal link of the second area 220. For the signal interface, the signal interface needs to be connected to the inside of the logic chip. Therefore, an equal amount of built-in signal interfaces need to be configured inside the logic chip. The built-in signal interface is electrically connected to the signal interface on the top layer to realize the design of the entire signal circuit.

[0057] Furthermore, because the core voltages of the power network interfaces in memory chips and logic chips differ, a level shifter (LVL) is required to convert the voltage. During integrated circuit design, each bonding interface requires a corresponding level shifter, and the level shifter and bonding interface are directly electrically connected, without the presence of other components, such as buffers. If the level shifter is located in the layer structure corresponding to the logic module during integrated circuit design, due to the limitations of the level shifter's driving capability, the distance between the bonding interfaces driven by the level shifter generally exceeds the level shifter's driving range. Therefore, the level shifter is placed on the top layer of the logic chip during integrated circuit design. By placing the level shifter on the top layer during integrated circuit design, without using a buffer unit between the level shifter and the bonding interface, the required distance between the components driven by the level shifter's driving capability can be met while reducing the complexity of the circuit design.

[0058] In an exemplary embodiment of the present application, the second region can be distributed in multiple stacked layers of the logic module. The second region cannot be obtained through axial symmetry or central symmetry in the subsequent integrated circuit design. The circuit structure of the second region of each logic module is different. Therefore, it is necessary to determine the second region and design it separately in the subsequent circuit design process, which can improve the efficiency of the integrated circuit design to a certain extent.

[0059] Step S300 and Step S400

[0060] In an exemplary embodiment of the present application, after determining the first and second regions of the logic modules, one of the logic modules can be selected as a reference logic module, and a circuit design can be performed on the first region of the integrated circuit corresponding to the reference logic module. The circuit designs of the first regions of the integrated circuit corresponding to the remaining logic modules can then be obtained based on axial symmetry or centrosymmetry. Figure 6 is a schematic diagram of the first and second regions according to an exemplary embodiment of the present application. As shown in Figure 6, each logic module includes a first region 210 and a second region 220. Any one of the first logic module mesh01, the second logic module mesh02, the third logic module mesh03, and the fourth logic module mesh04 is selected as the reference logic module. For example, the first logic module mesh01 is selected as the reference logic module, and the circuit design of the first region 210 inside the first logic module is first completed. Then, the circuit designs of the first region 210 of the second logic module mesh02, the third logic module mesh03, and the fourth logic module mesh04 are obtained in an axially symmetric or centrosymmetric manner.

[0061] In the exemplary embodiment of the present application, the reference logic module may be further confirmed. If the same circuit layout exists inside the reference logic module, the circuit design process may also be optimized in an axially symmetrical or centrally symmetrical manner.

[0062] According to an exemplary embodiment of the present application, by selecting a reference logic module among the logic modules, completing the circuit design of the first area of ​​the reference logic module, and then completing the circuit design of the first area of ​​the remaining logic modules through axial symmetry or central symmetry, the circuit design process can be simplified, the design efficiency of the integrated circuit can be improved, and the design cycle and cost of the integrated circuit can be saved.

[0063] In an exemplary embodiment of the present application, after completing the circuit design of the first region of each logic module, the circuit design of the second region of the integrated circuit corresponding to the logic module can also be performed to obtain the target integrated circuit design. Figure 7 is a flow chart of the second region circuit design according to an exemplary embodiment of the present application. As shown in Figure 7, the second region circuit design may include the following steps:

[0064] Step S410: determining the number of bonding interfaces based on the distribution of the bonding interfaces, and determining a plurality of first sub-regions and second sub-regions within the second region based on the number of bonding interfaces and the distribution of the bonding interfaces, wherein the first sub-regions and the second sub-regions are spaced apart from each other;

[0065] Step S420: configuring a first sub-region and a second sub-region corresponding to the memory cell and the bonding interface, wherein the first sub-region and the second sub-region both include a wiring region and a cell placement region.

[0066] In conjunction with Figure 6, since the second area 220 cannot be designed in an axially symmetrical or centrally symmetrical manner, it is necessary to design the integrated circuit for the second area 220 of each logic module separately. The second area 220 may include four area units, namely the first area unit 220-1 and the second area unit 220-2. Among them, the first area unit 220-1 can be configured as a standard component unit circuit area, and the second area unit 220-2 can be configured as a filling unit circuit area. Among them, standard components may include buffers, level converters, etc. Each area unit may include a unit placement area and a winding area. The unit placement area can be used to configure the components corresponding to the logic module, and the winding area can provide a winding space for the bonding interface between the logic chip and the top layer. Taking the first area unit as an example, the number of bonding interfaces is determined according to the distribution of the bonding interfaces, and further based on the number of bonding interfaces, multiple first sub-areas and second sub-areas are determined within the area unit. Figure 8 is a schematic diagram of the first sub-area and the second sub-area according to an exemplary embodiment of the present application. As shown in Figure 8, the first area unit may include a plurality of first sub-areas 221 and second sub-areas 222 that are spaced apart, wherein the first sub-area 221 can be used to configure standard components and winding space for the memory unit of the chip, and the second sub-area 222 can first be set with winding obstacles to occupy the area, which is used to configure the corresponding standard components and winding space for the bonding interface in the subsequent integrated circuit design process. For example, 228 signal interfaces need to be connected to the logic module, and the number of first sub-areas and second sub-areas is evaluated based on the number of signal interfaces and the distribution of bonding interfaces. Among them, each first sub-area 221 can place 12 bonding interfaces, and the number of first sub-areas is determined to be 19. Then, the positions of the first sub-area 221 and the second sub-area 222 are confirmed based on the distribution of the bonding interfaces. This application takes the circuit design of the first area unit as an example for illustration, and the circuit design of the second area unit can also be completed based on the same or similar method.

[0067] According to an exemplary embodiment of the present application, the number and position of the first sub-region and the second sub-region are determined based on the distribution and number of bonding interfaces, wherein the first sub-region and the second sub-region are spaced apart, which can effectively solve the problem of winding congestion caused by uneven distribution of the winding area and the unit placement area, and to a certain extent, can improve the yield and safety of the integrated circuit. Although the present application uses the first sub-region and the second sub-region to space apart to avoid winding congestion, those skilled in the art will appreciate that the first sub-region and the second sub-region can also be arranged in other ways, and the present application is not limited thereto.

[0068] In an exemplary embodiment of the present application, after determining the first sub-region and the second sub-region, corresponding filling components may be placed in the first sub-region and the second sub-region. FIG9 is a flow chart of placing filling components in the second region according to an exemplary embodiment of the present application. As shown in FIG9 , placing filling components in the second region may include the following steps:

[0069] Step S430: obtaining a standard grid of the chip and determining the initial positions of standard components in the second area;

[0070] Step S440: comparing the initial positions of the standard components in the second area of ​​each logic module with the standard grid to obtain a comparison result;

[0071] Step S450: determining a target position of the standard component in the second area based on the comparison result, and placing the corresponding standard component in the second area based on the target position.

[0072] For example, in the process of chip design, a standard grid (row) is first set, and the chip is designed based on the standard grid. For example, the standard grid is set to 0.096*0.384. The initial positions of the standard components are determined in the second area, and the initial positions of the standard components in the second area of ​​each logic module are compared with the standard grid to obtain comparison results. In response to all the standard components being located on the standard grid, the initial positions of the standard components are used as the target positions. However, since the integrated circuits in the first area of ​​the remaining logic modules are obtained by axial symmetry or central symmetry of the integrated circuits in the first area of ​​the reference logic module, the standard components in the second area connected to the first area may not all be located on the standard grid. When it is detected that the standard components in the second area are not all located on the standard grid, the internal grid of the second area can be redefined, and the target positions of the standard components can be determined based on the internal grid of the second area. After obtaining the target positions of the standard components, the corresponding standard components are placed based on the target positions.

[0073] According to an exemplary embodiment of the present application, by comparing the initial positions of standard components in the second area of ​​each logic module with the standard grid, and determining whether to adjust the grid within the second area and obtain the target positions of the standard components based on the comparison results, placing the standard components based on the target positions, and completing the circuit design of the second area, it can be ensured that after the integrated circuit of the first area is obtained through axial symmetry or central symmetry, the integrated circuit of the second area is accurately spliced ​​with the integrated circuit of the first area, thereby improving the efficiency of chip integrated circuit design.

[0074] According to an exemplary embodiment of the present application, based on initial chip information, the chip is divided into multiple logic modules and the first and second regions of the logic modules are determined. A reference logic module is selected, and integrated circuit design is performed for the first region of the reference logic module. The integrated circuit design for the first region of the remaining logic modules is completed in an axially symmetrical or centrally symmetrical manner, and then the integrated circuit design for the second region of each logic module is completed separately. The integrated circuit design method of the present application completes the design of the first region of the logic module in an axially symmetrical or centrally symmetrical manner, and completes the design of the integrated circuit for the second region of each logic module separately, thereby improving circuit design efficiency and reducing circuit design cycle and cost.

[0075] The present application also provides an integrated circuit design apparatus 2000. FIG10 is a block diagram of the integrated circuit design apparatus 2000 according to an embodiment of the present application. As shown in FIG10 , the integrated circuit design apparatus 2000 may include a chip partitioning unit 2100, a region confirmation unit 2200, a first circuit design unit 2300, and a second circuit design unit 2400.

[0076] In an exemplary embodiment of the present application, the chip division unit 2100 can be used to obtain initial information of the chip and divide the chip into multiple logic modules based on the initial information; the area confirmation unit 2200 can be used to determine the first area and the second area in the integrated circuit corresponding to the logic module, wherein the first area of ​​the logic module satisfies axial symmetry or central symmetry; the first circuit design unit 2300 can be used to select a logic module as a reference logic module, perform circuit design on the first area of ​​the integrated circuit corresponding to the reference logic module, and obtain the circuit design of the first area of ​​the integrated circuit corresponding to the remaining logic modules based on axial symmetry or central symmetry; the second circuit design unit 2400 can be used to perform circuit design on the second area of ​​the integrated circuit corresponding to the logic module respectively to obtain the target integrated circuit design.

[0077] In an exemplary embodiment of the present application, the chip division unit 2100 can be specifically used to obtain the distribution and storage structure of the bonding interface of the chip based on the initial information; divide the chip based on the distribution and storage structure of the bonding interface to obtain multiple logic modules, wherein the overlap rate of the distribution of the bonding interfaces of different logic modules is greater than or equal to the overlap rate threshold, and the storage structures of different logic modules satisfy axial symmetry or central symmetry.

[0078] In an exemplary embodiment of the present application, the chip division unit 2100 can be specifically used to perform a first pre-processing on the chip based on the distribution of the bonding interface to obtain a first number of first pre-logic modules; perform a second pre-processing on the chip based on the storage structure to obtain a second number of second pre-logic modules; compare the first number and the second number, if the first number is greater than the second number, divide the chip based on the second pre-processing, if the first number is less than the second number, divide the chip based on the first pre-processing.

[0079] In an exemplary embodiment of the present application, the second circuit design unit 2400 can be used to determine the number of bonding interfaces based on the distribution of the bonding interfaces, and determine multiple first sub-regions and second sub-regions in the second region based on the number of bonding interfaces and the distribution of the bonding interfaces, wherein the first sub-regions and the second sub-regions are distributed at intervals; and configure corresponding first sub-regions and second sub-regions for storage cells and bonding interfaces, wherein the first sub-regions and the second sub-regions both include a winding area and a cell placement area.

[0080] In an exemplary embodiment of the present application, the second circuit design unit 2400 can also be used to obtain a standard grid of the chip and determine the initial positions of standard components in the second area; compare the initial positions of standard components in the second area of ​​each logic module with the standard grid to obtain comparison results; determine the target positions of standard components in the second area based on the comparison results, and place corresponding standard components in the second area based on the target positions.

[0081] According to an exemplary trial method of the present application, based on initial chip information, the chip is divided into multiple logic modules and the first and second regions of the logic modules are determined. A reference logic module is selected, and the integrated circuit design of the first region of the reference logic module is performed. The integrated circuit design of the first region of the remaining logic modules is completed in an axially symmetrical or centrally symmetrical manner, and then the integrated circuit design of the second region of each logic module is completed separately. The integrated circuit design device of the present application completes the design of the first region of the logic module in an axially symmetrical or centrally symmetrical manner, and completes the design of the integrated circuit of the second region of each logic module separately, thereby improving circuit design efficiency and reducing circuit design cycle and cost.

[0082] The functions of the integrated circuit design apparatus 2000 of the present application have been described in detail in the integrated circuit design method 1000 and will not be elaborated on here.

[0083] The present application may also provide an integrated circuit, wherein the integrated circuit of the present application is the integrated circuit generated based on the integrated circuit design method 1000 or the integrated circuit design apparatus 2000.

[0084] The present application may also provide a chip and a storage system. Figure 11 is a block diagram of a storage system according to an exemplary embodiment of the present application. The storage system may be a non-volatile storage system, wherein the non-volatile storage system may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having storage therein. As shown in Figure 11, the non-volatile storage system may include a host 30 and a memory system 40 having one or more chips 42 and a controller 41. The host 30 may be a processor of an electronic device, such as a central processing unit (CPU), or a system on a chip (SoC), such as an application processor (AP).

[0085] In an exemplary embodiment of the present application, the controller 41 is coupled to the chip 42 and the host 30, and is configured to control the chip 42 to perform operations, such as performing data erasing, data writing, or data reading operations. The controller 41 can manage the data stored in the chip 42 and communicate with the host 30. In some exemplary embodiments, the controller 41 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some exemplary embodiments, the controller 41 is designed to operate in a high duty cycle environment SSD or an embedded multimedia card (eMMC), which is used as data storage for mobile devices (such as smart phones, tablets, laptops, etc.) and enterprise storage arrays. The controller 41 can be configured to control the operations of the chip 42, such as reading, erasing, and programming operations. The controller 41 may also be configured to manage various functions related to data stored or to be stored in the chip 42, including bad block management, garbage collection, logical to physical address translation, wear leveling, and the like. In some exemplary embodiments, the controller 41 is also configured to process error correction code (ECC) for data read from or written to the chip 42. Any other suitable function may also be performed by the controller 41, such as formatting the chip. The controller 41 may communicate with an external device (e.g., the host 30) according to a specific communication protocol. For example, the controller 41 may communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a high-speed PCI (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a FireWire protocol, and the like.

[0086] The controller 41 and one or more chips 42 can be integrated into various types of storage devices, for example, included in the same package, such as a Universal Flash Storage (UFS) package or an eMMC package. That is, the memory system 40 can be implemented as and packaged into different types of terminal electronic products.

[0087] A nonvolatile memory system according to an exemplary embodiment of the present application is shown in FIG12A , in which a controller 41 and a single chip 42 may be integrated into a nonvolatile memory system 400 a. The controller 41 may control the chip 42 through, for example, a channel (not shown), and the chip 42 may perform operations based on the control of the controller 41. The chip 42 may receive commands and addresses from the controller 41 through the channel and access an area selected from the memory array in response to the address.

[0088] In some exemplary embodiments, the controller 41 and one or more chips 42 can be integrated into various types of memory systems. In other words, the memory systems 400a and 400b can be implemented and packaged into different types of final electronic products. In one example as shown in FIG12A , the controller 41 and the chip 42 can be integrated into a memory system 400a in the form of a memory card. The memory card may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a Compact Flash (CF) card, a Smart Media (SM) card, a memory stick, a MultiMedia Card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a Universal Flash Storage Card (UFS), etc. The memory system 400a in the form of a memory card may also include a memory card connector 43 for coupling it to a host (not shown).

[0089] A nonvolatile memory system according to an exemplary embodiment of the present application is shown in FIG12B . A controller 41 and a plurality of chips 42 may be integrated into a memory system 400 b. The controller 41 and the plurality of chips 42 may be integrated into a memory system 400 b formed as a solid-state drive (SSD). The solid-state drive (SSD) may further include an SSD connector 43 for coupling the SSD to a host. In some embodiments, the storage capacity and / or operating speed of the solid-state drive (SSD) may be higher than that of a memory card.

[0090] The above-described specific embodiments further illustrate the objectives, technical solutions, and beneficial effects of the present invention. It should be understood that the above description is merely a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

Claims

1. A method for designing an integrated circuit, the method include: Acquire initial information of a chip, and divide the chip into a plurality of logic modules based on the initial information; Determine a first region and a second region in the integrated circuit corresponding to the logic module, wherein the first region of the logic module satisfies axial symmetry or central symmetry; Selecting one of the logic modules as a reference logic module, performing circuit design on the first region of the integrated circuit corresponding to the reference logic module, and obtaining circuit designs of the first regions of the integrated circuit corresponding to the remaining logic modules based on axial symmetry or central symmetry; Circuit design is performed on the second regions of the integrated circuit corresponding to the logic modules to obtain a target integrated circuit design.

2. The integrated circuit design method according to claim 1, in, Acquiring initial information of a chip, and dividing the chip into a plurality of logic modules based on the initial information, including: Acquire the distribution and storage structure of the bonding interfaces of the chip based on the initial information; The chip is divided based on the distribution of the bonding interface and the storage structure to obtain a plurality of logic modules, wherein an overlap rate of the distribution of the bonding interfaces of different logic modules is greater than or equal to an overlap rate threshold, and the storage structure distribution of different logic modules satisfies axial symmetry or central symmetry.

3. The method for integrated circuit design according to claim 2, in, Dividing the chip based on the distribution of the bonding interface and the storage structure to obtain a plurality of logic modules includes: Performing a first preprocessing on the chip based on the distribution of the bonding interfaces to obtain a first number of first pre-logic modules; Performing a second preprocessing on the chip based on the storage structure to obtain a second number of second pre-logic modules; The first number is compared with the second number. If the first number is greater than the second number, the chips are divided based on the second preprocessing. If the first number is less than the second number, the chips are divided based on the first preprocessing.

4. The method for integrated circuit design according to claim 2, in, The chip includes a plurality of storage units, and circuit design is performed on the second area of ​​the integrated circuit corresponding to the logic module to obtain a target integrated circuit design, including: The number of the bonding interfaces is determined based on the distribution of the bonding interfaces, and the number of the bonding interfaces is determined based on the distribution of the bonding interfaces. The number of the ports and the distribution of the bonding interfaces determine a plurality of first sub-regions and second sub-regions in the second region, wherein the first sub-regions and the second sub-regions are distributed at intervals; The first sub-region and the second sub-region corresponding to the storage unit and the bonding interface are configured, wherein the first sub-region and the second sub-region both include a wiring region and a unit placement region.

5. The integrated circuit design method according to claim 4, in, The method further comprises: Acquire a standard grid of the chip and determine initial positions of standard components in the second area; Comparing the initial positions of the standard components in the second area of ​​each of the logic modules with the standard grid to obtain a comparison result; The target position of the standard component in the second area is determined based on the comparison result, and the corresponding standard component is placed in the second area based on the target position.

6. A device for integrated circuit design, the device include: A chip division unit, used for obtaining initial information of a chip and dividing the chip into a plurality of logic modules based on the initial information; A region confirmation unit, configured to determine a first region and a second region in the integrated circuit corresponding to the logic module, wherein the first region of the logic module satisfies axisymmetry or central symmetry; a first circuit design unit, configured to select one of the logic modules as a reference logic module, perform circuit design on the first region of the integrated circuit corresponding to the reference logic module, and obtain circuit designs of the first regions of the integrated circuit corresponding to the remaining logic modules based on axial symmetry or central symmetry; The second circuit design unit is used to perform circuit design on the second area of ​​the integrated circuit corresponding to the logic module to obtain a target integrated circuit design.

7. The integrated circuit design device according to claim 6, in, The chip partitioning unit is used for: Acquire the distribution and storage structure of the bonding interfaces of the chip based on the initial information; The chip is divided based on the distribution of the bonding interface and the storage structure to obtain a plurality of logic modules, wherein an overlap rate of the distribution of the bonding interfaces of different logic modules is greater than or equal to an overlap rate threshold, and the storage structure distribution of different logic modules satisfies axial symmetry or central symmetry.

8. An integrated circuit, wherein the integrated circuit is generated based on the integrated circuit design method according to any one of claims 1 to 5 or the integrated circuit design device according to claim 6 or 7.

9. A chip comprising a logic chip and a memory chip connected to the logic chip, in, The logic chip includes the integrated circuit as claimed in claim 8.

10. A storage system, the storage system include: The chip as claimed in claim 9; as well as The controller is coupled to the chip and controls the chip to store data.

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