Ferroelectric memory array, manufacturing method therefor, memory, and electronic device

Abstract

The present application relates to the technical field of semiconductors, provides a ferroelectric memory array, a manufacturing method therefor, a memory and an electronic device, and aims to expand data read-write windows of memories and reduce the power consumption of the memories. The ferroelectric memory array comprises a plurality of memory cells, each memory cell comprising a ferroelectric capacitor and a transistor. The ferroelectric capacitor comprises a first electrode and a second electrode which are arranged opposite to each other and, located between the first electrode and the second electrode, a ferroelectric layer and an intercalation layer. The intercalation layer can be arranged between the ferroelectric layer and the first electrode, the intercalation layer can also be arranged between the ferroelectric layer and the second electrode, or intercalation layers are provided between the ferroelectric layer and the first electrode and between the ferroelectric layer and the second electrode. The intercalation layer contains electric dipoles, the electric dipoles being distributed on two opposite surfaces of the intercalation layer in the direction from the first electrode to the second electrode. The ferroelectric memory array can be used in ferroelectric random access memories, so as to read and write data.

Description

Ferroelectric memory array and preparation method thereof, memory, and electronic device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on November 13, 2023, with application number 202311515181.7 and application name “Ferroelectric Memory Array and Preparation Method, Memory, and Electronic Device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of semiconductor technology, and in particular to a ferroelectric memory array and a preparation method thereof, a memory, and an electronic device. Background Art

[0003] Ferroelectric Random Access Memory (FeRAM), as a new type of memory, has attracted widespread attention due to its non-volatility of stored data, fast access rate, low read and write voltage, and low power consumption.

[0004] Typically, a ferroelectric random access memory includes a ferroelectric capacitor, which includes two electrodes disposed opposite to each other and a ferroelectric layer disposed between the two electrodes. Currently, the mainstream material of the ferroelectric layer includes hafnium oxide-based ferroelectric materials, which still have ferroelectric properties at a smaller thickness.

[0005] Based on the above architecture, how to increase the read and write data window of the memory and reduce the power consumption of the memory has become an urgent problem to be solved in the field.

[0006] Summary of the Invention

[0007] The embodiments of the present application provide a ferroelectric memory array and a preparation method thereof, a memory, and an electronic device, aiming to increase the read and write data window of the memory and reduce the power consumption of the memory.

[0008] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0009] In a first aspect, a ferroelectric memory array is provided. The ferroelectric memory array can have a two-dimensional or three-dimensional structure. Furthermore, the ferroelectric memory array can be applied to a ferroelectric random access memory, a ferroelectric field effect transistor memory, or a ferroelectric tunnel junction memory to enable data reading and writing.

[0010] The ferroelectric memory array includes a plurality of memory cells arranged in an array, each memory cell including a ferroelectric capacitor and a transistor. The ferroelectric capacitor includes a first electrode and a second electrode disposed opposite each other, and a ferroelectric layer and an intercalation layer located between the first and second electrodes. An intercalation layer may be disposed between the ferroelectric layer and the first electrode, an intercalation layer may also be disposed between the ferroelectric layer and the second electrode, or an intercalation layer may be disposed between the ferroelectric layer and the first electrode and between the ferroelectric layer and the second electrode. When the first and second electrodes do not receive a voltage signal, the intercalation layer includes an electric dipole. That is, in the absence of an external electric field, the intercalation layer can generate an electric dipole based on its material properties. The electric dipoles are distributed on two opposing surfaces of the intercalation layer along a direction from the first electrode to the second electrode.

[0011] In the above-described embodiments of the present application, an intercalation layer is provided between the ferroelectric layer and an electrode (a first electrode or a second electrode). Electric dipoles are distributed on two opposing surfaces of the intercalation layer in a direction directed from the first electrode toward the second electrode. These electric dipoles can generate an electric field. During the preparation of the ferroelectric layer, the electric field generated by the electric dipoles guides the polarization axis of the ferroelectric material in the ferroelectric layer to align along the electric field direction of the electric dipoles, thereby facilitating improved spontaneous polarization properties of the ferroelectric material.

[0012] Moreover, when the external electric field generated by the first electrode and the second electrode is reversed, the electric dipoles in the intercalation layer can undergo charge migration in response to the reversal of the external electric field, thereby increasing the amount of polarization charge. The total amount of polarization induced current is equal to the induced current generated by the polarization of the ferroelectric material and the induced current of the electric dipole, thereby increasing the residual polarization intensity of the ferroelectric material and the distinction between positive and negative polarization states, and increasing the read and write data window of the memory equipped with the ferroelectric capacitor.

[0013] In addition, ferroelectric materials undergo ferroelectric flipping under the action of an inverted external electric field. The electric field generated by the electric dipole can serve as a "depolarization electric field" to assist the ferroelectric flipping, thereby improving the efficiency of the ferroelectric flipping and reducing the coercive field of the ferroelectric material. The external electric field required for the ferroelectric flipping is reduced, thereby reducing the operating voltage of the ferroelectric capacitor, which is beneficial to reducing the power consumption of the memory.

[0014] In some embodiments, the intercalation layer includes at least one first sub-intercalation layer and at least one second sub-intercalation layer, and the first sub-intercalation layer and the second sub-intercalation layer are alternately arranged along a direction from the first electrode to the second electrode. The dielectric constant of the material of the first sub-intercalation layer is different from the dielectric constant of the material of the second sub-intercalation layer, and the dielectric constant of the material at the surface where the first sub-intercalation layer and the second sub-intercalation layer intersect changes. The first sub-intercalation layer and the second sub-intercalation layer are stacked in a superlattice manner, so that two opposing surfaces of the first sub-intercalation layer generate electric dipoles, and two opposing surfaces of the second sub-intercalation layer generate electric dipoles.

[0015] In some embodiments, the intercalation layer is doped with elements, and the doped elements include at least one of niobium, titanium, hafnium, zirconium, lanthanum, yttrium, strontium, silicon, germanium, tantalum, or tungsten. By doping the intercalation layer with elements, the intrinsic parameters of the material of the intercalation layer can be changed, and high-concentration, low-energy-level defects can be introduced into the material to generate electric dipoles in the intercalation layer.

[0016] In some embodiments, the material of the intercalation layer includes a piezoelectric material. According to the piezoelectric effect, when the intercalation layer is subjected to pressure, two opposite surfaces of the intercalation layer will generate electric dipoles.

[0017] In some embodiments, the material of the intercalation layer includes a pyroelectric material, which is also a piezoelectric material. Pyroelectric materials can generate electric dipoles when heated or pressurized.

[0018] In some embodiments, the intercalation layer material includes a ferroelectric material. Ferroelectric materials are a branch of pyroelectric materials. Therefore, ferroelectric materials can generate electric dipoles when heated or pressurized. Furthermore, during the deposition of the ferroelectric material to form the intercalation layer, electric dipoles may also be generated within the intercalation layer.

[0019] In addition, the above-mentioned piezoelectric materials, pyroelectric materials or ferroelectric materials all have a negative capacitance effect. These materials all belong to negative capacitance materials. According to the negative capacitance effect, when the first electrode and the second electrode receive a voltage signal and generate an external electric field, the electrons in the intercalation layer will migrate to the surface of the intercalation layer under the action of the external electric field. The surface is distributed with negative charge, and the other surface opposite to the surface is distributed with positive charge, thereby generating electric dipoles on the two opposite surfaces of the intercalation layer.

[0020] In some embodiments, the material of the intercalation layer may include at least one of a piezoelectric material, a pyroelectric material, a ferroelectric material, or a negative capacitance material. In the absence of an external electric field, the intercalation layer may generate an electric dipole according to the respective material properties.

[0021] In some embodiments, the material of the intercalation layer includes at least one of titanium oxide, niobium oxide, tantalum oxide, yttrium oxide, lanthanum oxide, barium oxide, cerium oxide, gadolinium oxide, aluminum oxide, hafnium oxide, zirconium oxide, silicon nitride, titanium nitride, niobium nitride, tantalum nitride, hafnium nitride, zirconium nitride, strontium titanate, barium titanate, lanthanum aluminate, lithium niobate, or lithium tantalate.

[0022] In some embodiments, the thickness of the intercalation layer ranges from 0.5 nm to 5 nm. Compared to the thickness of the ferroelectric layer, the thinner the intercalation layer is, the smaller the voltage divider effect of the intercalation layer is, and the higher the operating voltage of the ferroelectric capacitor is due to the intercalation layer.

[0023] In some embodiments, the first electrode and the second electrode are both planar electrodes, and the first electrode, the ferroelectric layer, the intercalation layer and the second electrode are stacked. The ferroelectric capacitor is a two-dimensional planar structure with a simple structure and is easy to prepare.

[0024] In some embodiments, the first electrode is a planar electrode, the second electrode is a columnar electrode, the second electrode passes through the first electrode, and the ferroelectric layer and the intercalation layer are arranged around the second electrode. The ferroelectric capacitor is a three-dimensional vertical structure, which can reduce its occupied area in the plane, thereby increasing the number of ferroelectric capacitors set per unit area in the plane, thereby increasing the number of storage units set per unit area, which is beneficial to improving the storage density of the ferroelectric memory.

[0025] In some embodiments, the thermal expansion coefficient of the material of the first electrode differs from the thermal expansion coefficient of the material of the second electrode. During the annealing and crystallization process of the ferroelectric layer, the high temperature causes the first and second electrodes to expand. Due to the different thermal expansion coefficients of the two materials, the deformations produced by the two electrodes differ, which can generate an interaction force. If the intercalation layer is made of a piezoelectric material, this interaction force is applied to the intercalation layer, which can generate an electric dipole within the intercalation layer.

[0026] In a second aspect, a method for fabricating a ferroelectric memory array is provided. The method comprises: sequentially forming a first electrode, a ferroelectric layer, and a second electrode, wherein the first electrode and the second electrode are disposed opposite each other, and the ferroelectric layer is located between the first electrode and the second electrode. Furthermore, an intercalation layer is formed after forming the first electrode and before forming the ferroelectric layer. Furthermore, an intercalation layer is formed after forming the ferroelectric layer and before forming the second electrode. The intercalation layer includes electric dipoles distributed on two opposing surfaces of the intercalation layer in a direction from the first electrode to the second electrode.

[0027] The preparation method provided in the above-described embodiments of the present application sequentially forms a first electrode, a ferroelectric layer, and a second electrode, and forms an intercalation layer between the first electrode and the ferroelectric layer, and between the ferroelectric layer and the second electrode. Electric dipoles are distributed on two opposing surfaces of the intercalation layer in a direction from the first electrode to the second electrode, and these electric dipoles can generate an electric field.

[0028] During the formation of the ferroelectric layer, under the guidance of the electric field generated by the electric dipole, the polarization axis of the ferroelectric material of the ferroelectric layer is arranged along the electric field direction of the electric dipole, which is beneficial to improving the spontaneous polarization characteristics of the ferroelectric material.

[0029] In a third aspect, a memory is provided, which includes the ferroelectric memory array according to any one of the above embodiments, and a controller electrically connected to the ferroelectric memory array.

[0030] In a fourth aspect, an electronic device is provided, such as a consumer electronic product, a home electronic product, an in-vehicle electronic product, a financial terminal product, or a communication electronic product. The electronic device includes a circuit board and the memory of the above embodiment, the memory being electrically connected to the circuit board.

[0031] It can be understood that the beneficial effects that can be achieved by the memory and electronic device provided by the above embodiments of the present application can refer to the beneficial effects of the ferroelectric memory array mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] To more clearly illustrate the technical solutions of this application, the following briefly introduces the drawings required for use in some embodiments of this application. Obviously, the drawings described below are only drawings of some embodiments of this application, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of this application.

[0033] FIG1 is a diagram illustrating an electronic device according to an embodiment of the present invention;

[0034] FIG2 is an exploded view of an electronic device provided in an embodiment of the present application;

[0035] FIG3 is an architectural diagram of a ferroelectric random access memory provided in an embodiment of the present application;

[0036] FIG4 is a circuit diagram of a memory cell provided in an embodiment of the present application;

[0037] FIG5 is a structural diagram of a ferroelectric capacitor in the related art;

[0038] 6 to 8 are structural diagrams of various ferroelectric capacitors provided in embodiments of the present application;

[0039] 9 and 10 are hysteresis loop diagrams of the ferroelectric capacitor provided in the embodiments of the present application;

[0040] 11 and 12 are structural diagrams of various ferroelectric capacitors provided in embodiments of the present application;

[0041] 13A to 13E are diagrams showing the steps of preparing a ferroelectric capacitor according to an embodiment of the present application;

[0042] 14A to 14E are diagrams showing the steps of preparing a ferroelectric capacitor according to an embodiment of the present application;

[0043] FIG15 is a three-dimensional structural diagram of a ferroelectric capacitor provided in an embodiment of the present application;

[0044] 16A to 16G are diagrams showing the steps of preparing a ferroelectric capacitor according to an embodiment of the present application. DETAILED DESCRIPTION

[0045] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the embodiments described are only some embodiments of the present application, not all embodiments. Based on the embodiments provided in this application, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of this application.

[0046] Some embodiments of the present application provide an electronic device, which may be, for example, a mobile phone, a tablet computer, a personal digital assistant (PDA), a television, a smart wearable product (e.g., a smart watch, a smart bracelet), a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a rechargeable small household appliance (e.g., a soymilk maker, a sweeping robot), a drone, a radar, aerospace equipment, and a vehicle-mounted device, etc.; the electronic device may also be a network device such as a base station. The embodiments of the present application do not impose any particular restrictions on the specific form of the electronic device.

[0047] FIG1 is an architecture diagram of an electronic device provided in an embodiment of the present application.

[0048] 1 , an electronic device 1 includes components such as a storage device 11, a processor 12, an input device 13, and an output device 14. Those skilled in the art will appreciate that the architecture of the electronic device 1 shown in FIG. 1 does not limit the electronic device 1 , and the electronic device 1 may include more or fewer components than those shown in FIG. 1 , or may combine some of the components shown in FIG. 1 , or may have a different arrangement of components than shown in FIG. 1 .

[0049] The storage device 11 is used to store software programs and modules. The storage device 11 primarily includes a program storage area and a data storage area. The program storage area can store and back up the operating system and at least one application required for a function (such as a sound playback function or an image playback function). The data storage area can store data generated based on the use of the electronic device 1 (such as audio data, image data, a phone book, etc.). Furthermore, the storage device 11 includes an external memory 111 and an internal memory 112. Data stored in the external memory 111 and the internal memory 112 can be transferred between them.

[0050] The external memory 111 may include, for example, a hard disk, a USB flash drive, a floppy disk, etc. The internal memory 112 may include, for example, dynamic random access memory (DRAM), static random access memory (SRAM), resistance random access memory (RRAM), phase change random access memory (PCRAM), ferroelectric random access memory (FeRAM), ferroelectric field-effect transistor (FeFET) memory, ferroelectric tunnel junction (FTJ) memory, NAND flash memory, etc.

[0051] The processor 12 is the control center of the electronic device 1. It connects the various components of the electronic device 1 using various interfaces and circuits. By running or executing software programs and / or modules stored in the storage device 11 and accessing data stored in the storage device 11, it performs various functions of the electronic device 1 and processes data, thereby providing overall monitoring of the electronic device 1. Optionally, the processor 12 may include one or more processing units. For example, the processor 12 may include an application processor (AP), a modem processor, a graphics processing unit (GPU), etc. These different processing units may be independent devices or integrated into one or more processors. For example, the processor 12 may integrate an application processor and a modem processor, where the application processor primarily processes the operating system, user interface, and application programs, while the modem processor primarily handles wireless communications. It is understood that the modem processor may not be integrated into the processor 12. For example, the application processor may be a central processing unit (CPU). In Figure 1 , the CPU is used as an example, and the CPU may include an arithmetic unit 121 and a controller 122. The arithmetic unit 121 obtains and processes the data stored in the internal memory 112, and the processed results are usually sent back to the internal memory 112. The controller 122 can control the arithmetic unit 121 to process the data, and the controller 122 can also control the external memory 111 and the internal memory 112 to read or write data.

[0052] The input device 13 is used to receive input digital or character information, and to generate key signal input related to the user settings and function control of the electronic device. For example, the input device 13 may include a touch screen and other input devices. The touch screen, also known as a touch panel, can collect user touch operations on or near the touch screen (such as operations performed by the user using a finger, stylus, or any other suitable object or accessory on or near the touch screen) and drive the corresponding connection device according to a pre-set program. The controller 122 in the above-mentioned processor 12 can also control the input device 13 to receive input signals or not. In addition, the input digital or character information received by the input device 13, and the key signal input related to the user settings and function control of the electronic device can be stored in the internal memory 112.

[0053] The output device 14 is used to output signals corresponding to the inputs of the input device 13 and the data stored in the internal memory 112. For example, the output device 14 outputs an audio signal or a video signal. The controller 122 in the processor 12 can also control the output device 14 to output a signal or not output a signal.

[0054] It should be noted that the thick arrows in Figure 1 are used to represent the transmission of data, and the direction of the thick arrows represents the direction of data transmission. For example, the single arrow between the input device 13 and the internal memory 112 represents that the data received by the input device 13 is transmitted to the internal memory 112. For another example, the double arrow between the operator 121 and the internal memory 112 represents that the data stored in the internal memory 112 can be transmitted to the operator 121, and the data processed by the operator 121 can be transmitted to the internal memory 112. The thin arrows in Figure 1 represent components that can be controlled by the controller 122. For example, the controller 122 can control the external memory 111, the internal memory 112, the operator 121, the input device 13, the output device 14, etc.

[0055] In order to facilitate further description of the structure of the electronic device 1 , the following description will be given by taking a mobile phone as an example.

[0056] FIG2 is an exploded view of an electronic device provided in an embodiment of the present application.

[0057] 2 , electronic device 1 may further include a middle frame 15, a rear housing 16, and a display screen 17. Rear housing 16 and display screen 17 are located on opposite sides of middle frame 15, and are disposed within rear housing 16. Middle frame 15 includes a carrier plate 150 for supporting display screen 17, and a frame 151 surrounding carrier plate 150.

[0058] Continuing to refer to Figure 2, the electronic device 1 may further include a circuit board 18, which is arranged on a side of the carrier plate 150 close to the rear shell 16. The storage device 11 in the electronic device 1 may be arranged on the circuit board 18, and the memory in the storage device 11 is electrically connected to the circuit board 18.

[0059] The following embodiments are described using a ferroelectric random access memory as an example. FIG3 is an architecture diagram of the ferroelectric random access memory provided in the embodiments of the present application.

[0060] 3 , the ferroelectric random access memory includes a ferroelectric memory array 210, a decoder 220, a driver 230, a timing controller 240, a buffer 250, and an input / output interface 260. The ferroelectric memory array 210 includes a plurality of memory cells 200 arranged in an array.

[0061] FIG4 is a circuit diagram of a storage unit provided in an embodiment of the present application.

[0062] Referring to Figure 4, the memory cell 200 includes a circuit architecture based on a ferroelectric capacitor. The memory cell 200 has a 1T1C (1-Transistor-1-Capacitor) structure, that is, the memory cell 200 includes a transistor T and a ferroelectric capacitor C. The source of the transistor T is electrically connected to the bit line (Bit Line, BL), the drain is electrically connected to one electrode of the ferroelectric capacitor C, the gate is electrically connected to the word line (Word Line, WL), and the other electrode of the ferroelectric capacitor C is electrically connected to the plate line (Plate Line, PL). The circuit architecture of the memory cell 200 in the embodiment of the present application is not limited to this.

[0063] Based on this, the decoder 220 can decode the received address to determine the memory cell 200 in the ferroelectric memory array 210 that needs to be accessed. The driver 230 is used to generate a control signal based on the decoding result output by the decoder 220. The control signal is transmitted to the gate of the transistor T in the memory cell 200 via the word line WL to control the conduction or cutoff of the transistor T, thereby enabling access to the specified memory cell 200. The buffer 250 receives the data signal output by the memory cell 200 and is used to cache the data signal. For example, a first-in first-out (FIFO) method can be used for caching. The timing controller 240 is used to control the timing of the buffer 250 and control the driver 230 to drive the ferroelectric memory array 210. The input / output interface 260 is used to transmit data signals, such as receiving data signals or sending data signals.

[0064] The ferroelectric memory array 210 , decoder 220 , driver 230 , timing controller 240 , buffer 250 , and input / output interface 260 may be integrated into one chip or may be integrated into multiple chips.

[0065] The working principle of ferroelectric random access memory is introduced below in combination with the structure of ferroelectric capacitors.

[0066] FIG. 5 is a structural diagram of a ferroelectric capacitor in the related art.

[0067] 5 , the ferroelectric capacitor C' includes a first electrode 01' and a second electrode 02' disposed opposite each other, and a ferroelectric film 03' disposed between the first electrode 01' and the second electrode 02'. The ferroelectric capacitor C' has a metal-insulator-metal (MIM) structure. The ferroelectric film 03' includes a ferroelectric material having spontaneous polarization characteristics.

[0068] Specifically, the ferroelectric material contains ferroelectric phase crystals. When a voltage signal is received by the first electrode 01' and the second electrode 02', generating an external electric field, this external electric field is applied to the ferroelectric film 03'. The central atoms of the orthorhombic phase unit cell in the ferroelectric material move along the external electric field and remain in a low-energy state, such as a "0" storage state. A large number of central atoms move and couple within the unit cell to form ferroelectric domains. Under the action of the external electric field, the ferroelectric domains generate polarized charges.

[0069] Ferroelectric materials have a coercive field (Ec). When the external electric field generated by the first electrode 01' and the second electrode 02' is reversed and greater than the coercive field, the central atom moves in the unit cell along the direction of the external electric field and stops at another low-energy state. This polarization state can be, for example, a "1" storage state, that is, the ferroelectric domain is directionally flipped under the action of the reversed external electric field.

[0070] The polarization charge energy formed by the ferroelectric domain before and after the external electric field is reversed is different. This positive and negative polarization state will cause the ferroelectric capacitor C' to charge and discharge and generate current, which can then be recognized by an external sensing amplifier to determine whether the memory cell 200 is in the storage state of "0" or "1", thereby realizing the reading or writing of data by the ferroelectric random access memory.

[0071] Moreover, when the external electric field is removed, the polarization state of the ferroelectric material can be maintained, making the ferroelectric random access memory non-volatile in storing data.

[0072] However, after multiple directional flips, the polarization strength of the ferroelectric domain decreases. Specifically, when reading and writing data, the ferroelectric random access memory performs a large number of edit / erase operations, and the ferroelectric domains in the ferroelectric layer 03' are constantly flipped. After multiple cycles, the remnant polarization (Pr) of the ferroelectric domains in the ferroelectric layer 03' decreases, and the coercive field increases. The smaller the remnant polarization, the smaller the amount of polarization charge, causing the two states of "0" and "1" to become closer and closer. The differentiation between the positive and negative polarization states of the ferroelectric layer 03' decreases, and eventually becomes difficult to distinguish, increasing the error rate of reading and writing data in the ferroelectric random access memory equipped with the ferroelectric capacitor C'. Moreover, the larger the coercive field, the larger the external electric field used for reversal, and the higher the operating voltage of the ferroelectric capacitor C', resulting in higher power consumption of the memory, shorter read / write life, and poor anti-interference ability.

[0073] To solve the above problems, an embodiment of the present application provides a ferroelectric capacitor. FIG. 6 to FIG. 8 are structural diagrams of various ferroelectric capacitors provided in the embodiments of the present application.

[0074] 6 , the ferroelectric capacitor C includes a first electrode 01 and a second electrode 02 that are opposite to each other, and a ferroelectric layer 03 and an intercalation layer 04 located between the first electrode 01 and the second electrode 02 .

[0075] The ferroelectric capacitor C can have a two-dimensional planar structure, with the first electrode 01 and the second electrode 02 both being planar electrodes, disposed opposite each other. The first electrode 01, the ferroelectric layer 03, the intercalation layer 04, and the second electrode 02 being stacked, the ferroelectric capacitor C has a simple structure and is easy to manufacture.

[0076] Exemplarily, the materials of the first electrode 01 and the second electrode 02 may include at least one of titanium nitride, tantalum nitride, and tungsten.

[0077] For example, the material of the ferroelectric layer 03 includes a hafnium oxide-based fluorspar material, which may include hafnium zirconium oxide (HZO), hafnium silicon oxide, hafnium aluminum oxide, hafnium lanthanum oxide, hafnium zirconium lanthanum oxide, hafnium zirconium cerium oxide, hafnium yttrium oxide, and hafnium zirconium gadolinium oxide. Compared with traditional ferroelectric materials, hafnium oxide-based materials have stable ferroelectric switching properties, which can improve the charge and discharge performance of the ferroelectric capacitor C.

[0078] Furthermore, the fabrication process for the ferroelectric layer 03 using hafnium oxide-based fluorite is highly compatible with the fabrication process for complementary metal oxide semiconductors (CMOS). This allows the thickness of the ferroelectric layer 03 to be reduced to ten nanometers or even less, while maintaining the spontaneous polarization characteristics of the ferroelectric layer 03, thus facilitating the miniaturization of the ferroelectric capacitor C.

[0079] 6 , the intercalation layer 04 may be disposed between the ferroelectric layer 03 and the first electrode 01 , which is equivalent to inserting the intercalation layer 04 between the ferroelectric layer 03 and the first electrode 01 . The number of the intercalation layers 04 is not limited and may be one or more.

[0080] 7 , the intercalation layer 04 may also be provided between the ferroelectric layer 03 and the second electrode 02 , which is equivalent to inserting the intercalation layer 04 between the ferroelectric layer 03 and the second electrode 02 . The number of the intercalation layers 04 is also not limited, and may be one or more.

[0081] 8 , the intercalation layer 04 can be disposed between the ferroelectric layer 03 and the first electrode 01, or between the ferroelectric layer 03 and the second electrode 02. This is equivalent to inserting the intercalation layer 04 between the ferroelectric layer 03 and the first electrode 01, or between the ferroelectric layer 03 and the second electrode 02.

[0082] When the first electrode 01 and the second electrode 02 are not receiving a voltage signal, the intercalation layer 04 includes an electric dipole. That is, in the absence of an external electric field, the intercalation layer 04 can generate an electric dipole based on its material properties (this will be discussed later based on the material selection for the intercalation layer 04). An electric dipole is a system consisting of two point charges of equal magnitude and opposite sign. For example, along the direction from the first electrode 01 to the second electrode 02, i.e., along direction Z, the intercalation layer 04 includes two opposing surfaces, with positive and negative point charges distributed near the two surfaces of the intercalation layer 04, respectively. An electric field can be generated between the positive and negative point charges, and the direction of the electric field can be, for example, along direction Z. Consequently, a potential difference exists between the opposing ends of the intercalation layer 04 along direction Z.

[0083] For example, referring to Figure 8, when an intercalation layer 04 is provided between the ferroelectric layer 03 and the first electrode 01, and between the ferroelectric layer 03 and the second electrode 02, the positive point charges in the upper intercalation layer 04 and the negative point charges in the lower intercalation layer 04 can be combined to form a "long-range" electric dipole. Similarly, the negative point charges in the upper intercalation layer 04 and the positive point charges in the lower intercalation layer 04 can also be combined to form a "long-range" electric dipole. The "long-range" electric dipole can generate an electric field. Therefore, there is also a potential difference between the upper intercalation layer 04 and the lower intercalation layer 04.

[0084] The ferroelectric capacitor C provided in the above-mentioned embodiment of the present application is formed by inserting an intercalation layer 04 between the ferroelectric layer 03 and the electrode (the first electrode 01 or the second electrode 02). The intercalation layer 04 can form an electric dipole at its interface, and the electric dipole can generate an electric field. In the process step (crystallization) of preparing the ferroelectric layer 03, under the guidance of the electric field generated by the electric dipole, the polarization axis of the ferroelectric material is arranged along the electric field direction of the electric dipole, which is beneficial to improving the spontaneous polarization characteristics of the ferroelectric material.

[0085] Moreover, when the external electric field generated by the first electrode 01 and the second electrode 02 is reversed, the electric dipoles in the intercalation layer 04 can undergo charge migration in response to the reversal of the external electric field, thereby increasing the amount of polarization charge. The total amount of polarization induced current is equal to the induced current generated by the polarization of the ferroelectric material and the induced current of the electric dipole, thereby increasing the residual polarization intensity, increasing the distinction between the positive and negative polarization states of the ferroelectric layer 03, and increasing the window for reading and writing data of the ferroelectric random access memory equipped with the ferroelectric capacitor C, which is particularly important for small-size devices with high-density integration.

[0086] In addition, the intercalation layer 04 can also generate more electric dipoles in response to an external electric field. The ferroelectric domain is directionally flipped under the action of the reversed external electric field. The electric field generated by the electric dipole can serve as a "depolarization electric field" to assist the ferroelectric domain flipping, which can improve the efficiency of the ferroelectric domain flipping and reduce the coercive field of the ferroelectric material. The external electric field required for the ferroelectric domain to flip is reduced, thereby reducing the operating voltage of the ferroelectric capacitor C, which is beneficial to reducing the power consumption of the memory.

[0087] To verify the above conclusion, the hysteresis loops of a ferroelectric capacitor without an intercalation layer and a ferroelectric capacitor with an intercalation layer can be tested and compared.

[0088] FIG9 and FIG10 are hysteresis loop diagrams of the ferroelectric capacitor provided in the embodiment of the present application, wherein the horizontal axis is the electric field strength generated by the first electrode 01 and the second electrode 02, the unit is "MV / cm"; the vertical axis is the residual polarization strength of the ferroelectric layer, the unit is "μC / cm 2 "; Curve "1" is the hysteresis loop of the ferroelectric capacitor without an intercalation layer; curve "2" is the hysteresis loop of the ferroelectric capacitor with an intercalation layer.

[0089] Referring to FIG9 , the maximum value of the residual polarization intensity corresponding to curve “2” is greater than the maximum value of the residual polarization intensity corresponding to curve “1”, indicating that the degree of differentiation between the positive and negative polarization states of the ferroelectric layer in the ferroelectric capacitor with an intercalation layer is greater than that in the ferroelectric capacitor without an intercalation layer, thereby indicating that the setting of the intercalation layer can increase the window for reading and writing data.

[0090] Referring to Figure 10, when the residual polarization intensity is 0, the maximum value of the electric field intensity corresponding to curve "2" is smaller than the maximum value of the electric field intensity corresponding to curve "2", indicating that the coercive field Ec of the ferroelectric layer in the ferroelectric capacitor with an intercalation layer is smaller than the coercive field Ec of the ferroelectric layer in the ferroelectric capacitor without an intercalation layer, thereby indicating that the setting of the intercalation layer can reduce the coercive field of the ferroelectric layer, and the electric field intensity of the external electric field required for ferroelectric switching is reduced.

[0091] Next, the configuration of the intercalation layer 04 and how to form an electric dipole are introduced.

[0092] The intercalation layer 04 may be a single film layer. Please continue to refer to Figures 6 to 8. The material of the intercalation layer 04 may include piezoelectric material. According to the piezoelectric effect, for example, along direction Z, when the intercalation layer 04 is subjected to pressure, electric dipoles will be generated on the two opposite surfaces of the intercalation layer 04.

[0093] Alternatively, the material of the intercalation layer 04 may include a pyroelectric material, whose crystal does not have central symmetry. The pyroelectric material is also a piezoelectric material. The pyroelectric material can generate an electric dipole when heated or pressurized.

[0094] Alternatively, the material of the intercalation layer 04 may include a ferroelectric material. Ferroelectric materials are a branch of pyroelectric materials. Therefore, ferroelectric materials can generate electric dipoles when heated or pressurized. Furthermore, during the process of depositing the ferroelectric material to form the intercalation layer 04, electric dipoles may also be generated within the intercalation layer 04.

[0095] In addition, the above-mentioned piezoelectric materials, pyroelectric materials or ferroelectric materials all have a negative capacitance effect. These materials are all negative capacitance materials. According to the negative capacitance effect, when the first electrode 01 and the second electrode 02 receive a voltage signal and generate an external electric field, the electrons in the intercalation layer 04 will migrate to the surface of the intercalation layer 04 under the action of the external electric field. The surface is distributed with negative charges, and the other surface opposite to the surface is distributed with positive charges, thereby generating electric dipoles on the two opposite surfaces of the intercalation layer 04.

[0096] In some embodiments, the material of the intercalation layer 04 may include one or more of piezoelectric materials, pyroelectric materials, ferroelectric materials, or negative capacitance materials. In the absence of an external electric field, the intercalation layer 04 may generate an electric dipole according to its respective material properties.

[0097] In some embodiments, the thermal expansion coefficient of the material of the first electrode 01 is different from the thermal expansion coefficient of the material of the second electrode 02. During the annealing and crystallization process of the ferroelectric layer 03, the high temperature will cause the first electrode 01 and the second electrode 02 to expand. Since the thermal expansion coefficients of the two materials are different, the deformations produced by the two are different, which can generate an interaction force along the direction Z. This interaction force can be applied to the intercalation layer 04, causing an electric dipole to be generated in the intercalation layer 04.

[0098] Exemplarily, the material of one of the first electrode 01 and the second electrode 02 includes titanium nitride, and the material of the other includes tungsten. Titanium nitride and tungsten have different thermal expansion coefficients.

[0099] Alternatively, in some embodiments, the main material of the intercalation layer 04 includes a piezoelectric material, a pyroelectric material, or a ferroelectric material. In this case, the intercalation layer 04 is further doped with elements, and the doped elements may include at least one of niobium, titanium, hafnium, zirconium, lanthanum, yttrium, strontium, silicon, germanium, tantalum, or tungsten. By doping elements into the intercalation layer 04, the intrinsic parameters of the material of the intercalation layer 04 can be changed, and high-concentration, low-energy-level defects can be introduced into the material to generate an electric dipole in the intercalation layer 04, thereby generating a potential difference between the opposite ends of the intercalation layer 04.

[0100] Exemplarily, the main material of the intercalation layer 04 may include one or more of titanium oxide, niobium oxide, tantalum oxide, yttrium oxide, lanthanum oxide, barium oxide, cerium oxide, gadolinium oxide, aluminum oxide, hafnium oxide, zirconium oxide, silicon nitride, titanium nitride, niobium nitride, tantalum nitride, hafnium nitride, zirconium nitride, strontium titanate, barium titanate, lanthanum aluminate, lithium niobate or lithium tantalate.

[0101] For example, the thickness of the intercalation layer 04 can range from 0.5 nm to 5 nm, for example, the thickness of the intercalation layer 04 is 0.5 nm, 1 nm, 2 nm, 2.5 nm, 3 nm, 4 nm, or 5 nm. Compared to the thickness of the ferroelectric layer 03, the thinner thickness of the intercalation layer 04 can reduce the voltage divider effect of the intercalation layer 04, thereby preventing the operating voltage of the ferroelectric capacitor C from being too high due to the provision of the intercalation layer 04.

[0102] The intercalation layer 04 may also be a composite film layer. FIG. 11 and FIG. 12 are structural diagrams of various ferroelectric capacitors provided in the embodiments of the present application.

[0103] 11 and 12 , the intercalation layer 04 includes at least one first sub-intercalation layer 04a and at least one second sub-intercalation layer 04b. Along the direction from the first electrode 01 to the second electrode 02, for example, along the direction Z, the first sub-intercalation layer 04a and the second sub-intercalation layer 04b are alternately arranged.

[0104] The thickness of the first sub-intercalation layer 04a and the thickness of the second sub-intercalation layer 04b can be the same or different. The figure shows a case where the thickness of the first sub-intercalation layer 04a and the second sub-intercalation layer 04b are the same. The number of the first sub-intercalation layer 04a and the number of the second sub-intercalation layer 04b can be the same or different. The figure shows a case where the number of the first sub-intercalation layer 04a and the second sub-intercalation layer 04b is the same, that is, the first sub-intercalation layer 04a and the second sub-intercalation layer 04b are arranged in pairs.

[0105] For example, referring to FIG. 11 , the intercalation layer 04 includes a first sub-intercalation layer 04 a and a second sub-intercalation layer 04 b , and the first sub-intercalation layer 04 a and the second sub-intercalation layer 04 b are stacked.

[0106] For example, referring to FIG. 12 , the intercalation layer 04 includes a plurality of first sub-intercalation layers 04 a and a plurality of second sub-intercalation layers 04 b , and the first sub-intercalation layers 04 a and the second sub-intercalation layers 04 b are alternately stacked.

[0107] Moreover, the dielectric constant of the material of the first sub-intercalation layer 04a is different from the dielectric constant of the material of the second sub-intercalation layer 04b. The dielectric constant of the material at the surface where the first sub-intercalation layer 04a contacts the second sub-intercalation layer 04b changes. The first sub-intercalation layer 04a and the second sub-intercalation layer 04b are stacked in a superlattice manner, and along the direction Z, electric dipoles are generated on the two opposite surfaces of the first sub-intercalation layer 04a, and electric dipoles are generated on the two opposite surfaces of the second sub-intercalation layer 04b.

[0108] The first sub-intercalation layer 04a and the second sub-intercalation layer 04b are arranged alternately. At the surface where the first sub-intercalation layer 04a and the second sub-intercalation layer 04b are in contact, positive charges and negative charges attract each other. The charges distributed on the surface of the first sub-intercalation layer 04a away from the second sub-intercalation layer 04b are opposite in positive and negative charge to the charges distributed on the surface of the second sub-intercalation layer 04b away from the first sub-intercalation layer 04a, and can be combined to form a "long-range" electric dipole.

[0109] From the overall perspective of the stacking structure of intercalation layer 04, the charges distributed on the top surface of the uppermost sub-intercalation layer in the stacking structure are opposite in positive and negative charge to the charges distributed on the bottom surface of the lowermost sub-intercalation layer in the stacking structure, and can be combined to form a "long-range" electric dipole, so that the top and bottom surfaces of intercalation layer 04 generate electric dipoles, thereby generating a potential difference at the opposite ends of intercalation layer 04.

[0110] For example, the material of the first sub-intercalation layer 04a may include titanium oxide, and the material of the second sub-intercalation layer 04b may include niobium oxide. The dielectric constants of titanium oxide and niobium oxide are different, so that the two are stacked in a superlattice manner, so that electric dipoles are generated on the two opposite surfaces of the first sub-intercalation layer 04a, and electric dipoles are generated on the two opposite surfaces of the second sub-intercalation layer 04b.

[0111] The embodiment of the present application provides a method for preparing the ferroelectric capacitor C shown in FIG8 , and FIG13A to FIG13E are diagrams of the steps of preparing the ferroelectric capacitor provided in the embodiment of the present application.

[0112] 13A , a first electrode 01 is formed.

[0113] For example, a chemical vapor deposition (CVD) process may be used to deposit a metal material on a substrate (silicon wafer). The metal material may include tungsten, for example, to form the first electrode 01. The thickness of the first electrode 01 may be 50 nm.

[0114] Since the first electrode 01 is located on the substrate and at the bottom of the ferroelectric capacitor C, the first electrode 01 may also be referred to as a “bottom electrode”.

[0115] 13B , an intercalation layer 04 is formed. The intercalation layer 04 includes an electric dipole. The electric dipole can generate an electric field. Therefore, along the direction Z, there is a potential difference between the opposite ends of the intercalation layer 04.

[0116] For example, a physical vapor deposition (PVD) process can be used to deposit a strontium titanate material above the first electrode 01. At the same time, niobium elements are doped into the strontium titanate material to change the intrinsic parameters of the strontium titanate material, thereby introducing high-concentration, low-energy-level defects into the material to generate electric dipoles in the intercalation layer 04. The thickness of the intercalation layer 04 can be 2 nm.

[0117] Referring to FIG. 13C , a ferroelectric layer 03 is formed.

[0118] For example, an atomic layer deposition (ALD) process can be used to deposit hafnium and zirconium on the intercalation layer 04, with a mass ratio of hafnium to zirconium being 1:1, so as to form a hafnium zirconium oxide (chemical formula: Hf 0.5 Zr 0.5 The ferroelectric layer O3 of O2) may have a thickness of 10 nm.

[0119] During the formation of the ferroelectric layer 03 , the material of the ferroelectric layer 03 will crystallize. Under the guidance of the electric field generated by the electric dipole, the polarization axis of the material can be arranged along the electric field direction of the electric dipole, which is beneficial to improving the spontaneous polarization characteristics of the material.

[0120] 13D , the same method can be used to form an intercalation layer 04 on the ferroelectric layer 03 .

[0121] 13E , the second electrode 02 is formed.

[0122] For example, a chemical vapor deposition process may be used to deposit tungsten on the substrate to form the second electrode 02 .

[0123] Alternatively, a physical vapor deposition process may be used to deposit titanium nitride material on the substrate to form the second electrode 02 .

[0124] The thickness of the second electrode 02 may be 50 nm. Since the second electrode 02 is located on the top of the ferroelectric capacitor C, the second electrode 02 may also be referred to as a “top electrode”.

[0125] Continuing with FIG13E , after the structure is formed, it is subjected to a rapid thermal annealing process to crystallize the material of the ferroelectric layer 03 into a ferroelectric phase crystal. During this process, the electric field generated by the electric dipole can also guide the polarization axis of the material to align along the direction of the electric field.

[0126] The preparation method provided in the above embodiment of the present application sequentially forms the first electrode 01, the ferroelectric layer 03 and the second electrode 02, and forms an intercalation layer 04 between the first electrode 01 and the ferroelectric layer 03, and forms an intercalation layer 04 between the ferroelectric layer 03 and the second electrode 02.

[0127] By doping elements into the intercalation layer 04, the intrinsic parameters of the material are changed, and high-concentration, low-energy-level defects are introduced into the material to generate electric dipoles in the intercalation layer 04. The electric dipoles can generate an electric field. During the crystallization process of the ferroelectric material in the ferroelectric layer 03, the electric field generated by the electric dipoles can guide the polarization axis of the ferroelectric material to align along the direction of the electric field, which is beneficial to improving the spontaneous polarization characteristics of the ferroelectric material.

[0128] The embodiment of the present application further provides a method for preparing the ferroelectric capacitor C shown in FIG. 12 , and FIG. 14A to FIG. 14E are diagrams of the steps for preparing the ferroelectric capacitor provided in the embodiment of the present application.

[0129] 14A , a first electrode 01 is formed using the same manufacturing method as described above.

[0130] 14B , an intercalation layer 04 is formed. The intercalation layer 04 includes an electric dipole. The electric dipole can generate an electric field. Therefore, along the direction Z, there is a potential difference between the opposite ends of the intercalation layer 04.

[0131] For example, an atomic layer deposition process can be used to deposit niobium oxide material on the first electrode 01 to form the second sub-intercalation layer 04b. Then, an atomic layer deposition process can be used to deposit titanium oxide material on the second sub-intercalation layer 04b to form the first sub-intercalation layer 04a. The second sub-intercalation layer 04b and the first sub-intercalation layer 04a are alternately formed in this manner. The second sub-intercalation layer 04b and the first sub-intercalation layer 04a are stacked to form the intercalation layer 04. The thickness of the intercalation layer 04 can be 2 nm.

[0132] Alternatively, the first sub-intercalation layer 04a may be formed on the first electrode 01 first, and then the second sub-intercalation layer 04b may be formed on the first sub-intercalation layer 04a, and the first sub-intercalation layer 04a and the second sub-intercalation layer 04b may be formed alternately in this way. The embodiments of the present application are not limited to this.

[0133] Titanium oxide and niobium oxide have different dielectric constants, which enables the second sub-intercalation layer 04b and the first sub-intercalation layer 04a to be stacked in a superlattice manner, so that electric dipoles are generated on the two opposite surfaces of the first sub-intercalation layer 04a and electric dipoles are generated on the two opposite surfaces of the second sub-intercalation layer 04b.

[0134] Referring to FIG. 14C , a ferroelectric layer 03 is formed using the same preparation method as described above. Similarly, during the formation of the ferroelectric layer 03, the material of the ferroelectric layer 03 will crystallize. Under the guidance of the electric field generated by the electric dipole, the polarization axis of the material can be arranged along the electric field direction of the electric dipole, which is beneficial to improving the spontaneous polarization characteristics of the material.

[0135] 14D , the same method may be used to alternately form second sub-intercalation layers 04 b and first sub-intercalation layers 04 a on the ferroelectric layer 03 to form an intercalation layer 04 .

[0136] 14E , a second electrode 02 is formed, and the preparation method is the same as above.

[0137] Continuing to refer to FIG14E , after the structure in the figure is formed, the structure is also subjected to rapid thermal annealing treatment so that the material of the ferroelectric layer 03 crystallizes to form ferroelectric phase crystals. During this process, the electric field generated by the electric dipole can also guide the polarization axis of the material to be arranged along the direction of the electric field.

[0138] The preparation method provided in the above embodiment of the present application sequentially forms the first electrode 01, the ferroelectric layer 03 and the second electrode 02, and forms an intercalation layer 04 between the first electrode 01 and the ferroelectric layer 03, and forms an intercalation layer 04 between the ferroelectric layer 03 and the second electrode 02.

[0139] Intercalation layer 04 is formed by alternating the formation of second sub-intercalation layers 04b and first sub-intercalation layers 04a. The dielectric constants of the materials of first sub-intercalation layer 04a and second sub-intercalation layer 04b differ, and the dielectric constant changes at the intersection of the first sub-intercalation layer 04a and second sub-intercalation layer 04b. This creates electric dipoles on two opposing surfaces of the first sub-intercalation layer 04a, and also on two opposing surfaces of the second sub-intercalation layer 04b. These electric dipoles generate an electric field. During the crystallization process of the ferroelectric material in ferroelectric layer 03, the electric field generated by the electric dipoles can guide the polarization axis of the ferroelectric material to align along the direction of the electric field, thereby improving the spontaneous polarization characteristics of the ferroelectric material.

[0140] The ferroelectric capacitor C provided in the embodiment of the present application may also have a three-dimensional vertical structure. FIG15 is a three-dimensional structural diagram of the ferroelectric capacitor provided in the embodiment of the present application.

[0141] Referring to FIG. 15 , the first electrode 01 of the ferroelectric capacitor C is a planar electrode, and the second electrode 02 is a columnar electrode. The first electrodes 01 and dielectric layers L alternate to form a stacked structure. Multiple first electrodes 01 form a step surface T, and the first electrodes 01 are connected to the outside through their step surfaces T. The second electrode 02 penetrates the first electrodes 01 and dielectric layers L in the stacked structure, with the side surface of the second electrode 02 facing the first electrode 01. The ferroelectric layer 03 and the intercalation layer 04 are arranged around the side surface of the second electrode 02 to separate the first electrode 01 from the second electrode 02.

[0142] Exemplarily, an intercalation layer 04 is provided between the ferroelectric layer 03 and the first electrode 01 , and between the ferroelectric layer 03 and the second electrode 02 . Each intercalation layer 04 may be the single film layer described above, or a composite film layer.

[0143] For example, the first electrode 01 and the second electrode 02 are both made of tungsten. The ferroelectric capacitor C further includes a third electrode 05 made of titanium nitride. The third electrode 05 can be located between the second electrode 02 and the intercalation layer 04, and the third electrode 05 and the second electrode 02 form a composite electrode.

[0144] The ferroelectric capacitor C adopts the above-mentioned three-dimensional vertical structural design, which can reduce its occupied area in the XY plane, thereby increasing the number of ferroelectric capacitors C set per unit area in the XY plane, thereby increasing the number of storage units 200 set per unit area, which is beneficial to improving the storage density of the ferroelectric memory.

[0145] Based on the 1T1C structure of the memory cell 200, the memory cell 200 includes a ferroelectric capacitor C and a transistor T. The first electrode 01 of the ferroelectric capacitor C is a planar electrode, and the second electrode 02 is a columnar electrode. In this case, the second electrode 02 is electrically connected to the transistor T through a contact column, that is, the columnar electrode of the ferroelectric capacitor C is electrically connected to the transistor T to form the memory cell 200.

[0146] The embodiment of the present application further provides a method for preparing a ferroelectric capacitor C as shown in FIG. 15 , and FIG. 16A to FIG. 16G are diagrams of the steps for preparing a ferroelectric capacitor provided in the embodiment of the present application.

[0147] 16A , dielectric layers L and first electrodes 01 are alternately formed. The total thickness of the dielectric layers L and the first electrodes 01 may be 100 nm. The dielectric layers L may separate two adjacent first electrodes 01 to insulate the two adjacent first electrodes 01 .

[0148] Illustratively, an etching process may be used to etch the dielectric layer L and the first electrodes 01 , so that the plurality of first electrodes 01 form step surfaces T.

[0149] 16B , a via hole H penetrating the first electrode 01 and the dielectric layer L is formed.

[0150] For example, an etching process may be used to etch the first electrode 01 and the dielectric layer L to form a via hole H penetrating the two. The diameter of the via hole H may be 50 nm.

[0151] 16B and 16C , an intercalation layer 04 is formed on the sidewall of the via hole H. Referring to FIG.

[0152] Exemplarily, the intercalation layer 04 is a single film layer, and tantalum oxide material can be deposited on the side wall of the via H. At the same time, niobium element is doped into the tantalum oxide material to change the intrinsic parameters of the tantalum oxide material, so that high-concentration, low-energy-level defects are introduced into the material to generate electric dipoles in the intercalation layer 04. The thickness of the intercalation layer 04 can be 2 nm.

[0153] The intercalation layer 04 can also be a composite membrane layer, and its preparation method is the same as described above.

[0154] 16D , a ferroelectric layer 03 is formed on the inner side of the intercalation layer 04 . The preparation method is the same as described above. The thickness of the ferroelectric layer 03 may be, for example, 10 nm.

[0155] 16E , an intercalation layer 04 is formed on the inner side of the ferroelectric layer 03 . The preparation method is the same as described above. The thickness of the intercalation layer 04 may also be 2 nm, for example.

[0156] 16F , a third electrode 05 is formed inside the insertion layer 04 .

[0157] For example, a titanium nitride material may be deposited on the inner side of the intercalation layer 04 to form the third electrode 05 . The thickness of the third electrode 05 may be 5 nm.

[0158] 16G , the second electrode 02 is formed inside the third electrode 05 .

[0159] The preparation method provided in the above-mentioned embodiment of the present application first forms a first electrode 01, then forms a via H penetrating the first electrode 01, forms a ferroelectric layer 03 and an intercalation layer 04 on the sidewall of the via H, and finally forms a second electrode 02 on the inner side of the ferroelectric layer 03. The second electrode 02 penetrates the first electrode 01 to form a three-dimensional ferroelectric capacitor C.

[0160] In addition, the intercalation layer 04 in the ferroelectric capacitor C provided in the embodiment of the present application can also be applied to various three-dimensional vertical opening structures, such as 3D DRAM, 3D RRAM, 3D PCRAM, 3D FeRAM, 3D NAND, etc., and can also be applied to field effect transistors with vertical channels.

[0161] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention are intended to be covered by the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope of protection of the claims.

Claims

1. A ferroelectric memory array, characterized in that: A plurality of memory cells are arranged in an array, wherein the memory cells include ferroelectric capacitors and transistors; The ferroelectric capacitor comprises: A first electrode and a second electrode arranged opposite to each other; a ferroelectric layer, disposed between the first electrode and the second electrode; at least one intercalation layer disposed between the ferroelectric layer and the first electrode, and / or between the ferroelectric layer and the second electrode; Wherein, when the first electrode and the second electrode do not receive voltage signals, the intercalation layer includes electric dipoles, and the electric dipoles are distributed on two opposite surfaces of the intercalation layer along the direction from the first electrode to the second electrode.

2. The ferroelectric memory array according to claim 1, characterized in that: The intercalation layer includes at least one first sub-intercalation layer and at least one second sub-intercalation layer; Along the direction from the first electrode to the second electrode, the first sub-intercalation layer and the second sub-intercalation layer are alternately arranged; The dielectric constant of the material of the first sub-intercalation layer is different from the dielectric constant of the material of the second sub-intercalation layer.

3. The ferroelectric memory array according to claim 1 or 2, characterized in that: The intercalation layer is doped with an element, and the element includes at least one of niobium, titanium, hafnium, zirconium, lanthanum, yttrium, strontium, silicon, germanium, tantalum or tungsten.

4. The ferroelectric memory array according to any one of claims 1 to 3, characterized in that: The material of the intercalation layer includes piezoelectric material.

5. The ferroelectric memory array according to any one of claims 1 to 4, characterized in that: The material of the intercalation layer includes pyroelectric material.

6. The ferroelectric memory array according to any one of claims 1 to 5, characterized in that: The material of the intercalation layer includes ferroelectric material.

7. The ferroelectric memory array according to any one of claims 1 to 6, characterized in that: The material of the intercalation layer includes at least one of titanium oxide, niobium oxide, tantalum oxide, yttrium oxide, lanthanum oxide, barium oxide, cerium oxide, gadolinium oxide, aluminum oxide, hafnium oxide, zirconium oxide, silicon nitride, titanium nitride, niobium nitride, tantalum nitride, hafnium nitride, zirconium nitride, strontium titanate, barium titanate, lanthanum aluminate, lithium niobate or lithium tantalate.

8. The ferroelectric memory array according to any one of claims 1 to 7, characterized in that: The thickness of the intercalation layer ranges from 0.5 nm to 5 nm.

9. The ferroelectric memory array according to any one of claims 1 to 8, characterized in that: The first electrode and the second electrode are both planar electrodes, and the first electrode, the ferroelectric layer, the insertion layer and the second electrode are stacked.

10. The ferroelectric memory array according to any one of claims 1 to 8, characterized in that: The first electrode is a planar electrode, and the second electrode is a columnar electrode; The second electrode penetrates the first electrode, and the ferroelectric layer and the insertion layer are both arranged around the second electrode.

11. The ferroelectric memory array according to any one of claims 1 to 10, characterized in that: The thermal expansion coefficient of the material of the first electrode is different from the thermal expansion coefficient of the material of the second electrode.

12. A method for preparing a ferroelectric memory array, characterized in that: include: forming a first electrode, a ferroelectric layer and a second electrode in sequence, wherein the first electrode and the second electrode are arranged opposite to each other, and the ferroelectric layer is located between the first electrode and the second electrode; Wherein, after forming the first electrode and before forming the ferroelectric layer, an intercalation layer is further formed; and / or, after forming the ferroelectric layer and before forming the second electrode, an intercalation layer is further formed; The intercalation layer includes electric dipoles, and along the direction from the first electrode to the second electrode, the electric dipoles are distributed on two opposite surfaces of the intercalation layer.

13. A memory, characterized in that: include: The ferroelectric memory array according to any one of claims 1 to 11; A controller is electrically connected to the ferroelectric memory array.

14. An electronic device, characterized in that: include: Circuit boards; The memory as claimed in claim 13, electrically connected to the circuit board.

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