Trench-type schottky barrier diode and manufacturing method therefor

Abstract

The present application relates to a trench-type Schottky barrier diode and a manufacturing method therefor. The trench-type Schottky barrier diode comprises: a substrate (170), having a first conductivity type; a first conductivity type layer (160), located on the substrate (170), the doping concentration of the first conductivity type layer (160) being less than the doping concentration of the substrate (170); a trench structure, extending from the front surface of the first conductivity type layer (160) to the substrate (170), the trench structure comprising a conductive material (140) and further comprising a dielectric layer (130) surrounding the conductive material (140) from the side surface and the bottom surface; a Schottky barrier layer (120), located on the first conductivity type layer (160) and on the trench structure; and a second conductivity type region (150), located below the trench structure, the top of the second conductivity type region (150) being in direct contact with the bottom of the dielectric layer (130), and the bottom of the second conductivity type region (150) being spaced apart from the substrate (170) by part of the first conductivity type layer (160). The present application can maintain reverse withstand voltage characteristics while reducing the on-state forward voltage drop of devices.

Description

Trench-type Schottky barrier diode and manufacturing method thereof

[0001] Related applications

[0002] This application claims priority to Chinese patent application No. 202311523884.4, filed on November 14, 2023, entitled “A Trench-Type Schottky Barrier Diode and Its Manufacturing Method,” the entire text of which is incorporated herein by reference. Technical Field

[0003] The present application relates to the field of semiconductor manufacturing, and in particular to a trench-type Schottky barrier diode, and also to a method for manufacturing a trench-type Schottky barrier diode. Background Art

[0004] A Schottky barrier diode (SBD) is a metal-semiconductor device typically constructed with a Schottky metal as the positive electrode and an N-type semiconductor as the negative electrode, leveraging the rectifying properties of the potential barrier formed at the interface between the two. N-type semiconductors contain a large number of electrons, while metals have only a very small number of free electrons. Therefore, electrons diffuse from the high-concentration N-type semiconductor to the low-concentration metal. However, the metal lacks holes, so there is no diffusion of holes from the metal to the N-type semiconductor. As electrons continue to diffuse from the N-type semiconductor to the metal, the electron concentration on the surface of the N-type semiconductor gradually decreases, disrupting surface neutrality and forming a potential barrier. The electric field is directed from the N-type semiconductor to the metal. However, under the influence of this electric field, electrons in the metal also drift from the metal to the N-type semiconductor, weakening the electric field created by diffusion. Once a space charge region of a certain width is established, the electron drift motion caused by the electric field and the electron diffusion motion caused by the varying concentrations reach a relative equilibrium, forming a Schottky barrier. The Schottky barrier diode is a low-power, ultra-high-speed semiconductor device. Its most notable features are extremely short reverse recovery time and reduced forward conduction voltage.

[0005] In recent years, trench structures have been used in the manufacture of Schottky barrier diodes. Trench Schottky barrier diodes offer two main advantages: First, they overcome the surface breakdown of conventional planar structures, which poses challenges to device reliability; second, they utilize the principle of charge balance to increase the device's breakdown voltage.

[0006] The forward conduction characteristics of trench Schottky diodes influence their performance as power devices. It's generally believed that lower forward voltage drop indicates better device performance. However, these two parameters, forward voltage drop and reverse withstand voltage, often have a conflicting relationship. Lowering the forward voltage drop typically results in a decrease in reverse withstand voltage, while increasing the reverse withstand voltage tends to increase the forward voltage drop.

[0007] Summary of the Invention

[0008] Based on this, it is necessary to provide a trench Schottky barrier diode and a manufacturing method thereof that can take into account both forward conduction voltage drop and reverse withstand voltage.

[0009] A trench-type Schottky barrier diode comprises: a substrate having a first conductivity type; a first conductivity type layer located on the substrate, the doping concentration of the first conductivity type layer being less than the doping concentration of the substrate; a trench structure extending from a first surface of the first conductivity type layer toward the substrate, the first surface being a side of the first conductivity type layer facing away from the substrate; the trench structure comprising a conductive material and also comprising a dielectric layer surrounding the conductive material from the side and bottom surfaces; a Schottky barrier layer located on the first conductivity type layer; a second conductivity type region located below the trench structure, with the top of the second conductivity type region directly contacting the bottom of the dielectric layer, and the bottom of the second conductivity type region being separated from the substrate by a portion of the first conductivity type layer; the first conductivity type and the second conductivity type being opposite conductivity types.

[0010] The trench-type Schottky barrier diode described above has a PN junction formed between the second conductivity type region and the first conductivity type layer that can withstand reverse voltage, thus having strong reverse voltage withstand capability. Furthermore, because the trench depth reaches the second conductivity type region, the drift region resistance is reduced to a certain extent during forward conduction, thereby reducing the forward voltage drop of the device.

[0011] In one embodiment, the distance between the bottom of the dielectric layer and the top of the substrate is no more than 20 microns.

[0012] In one embodiment, the thickness of the second conductive type region is less than 20 micrometers, and the thickness direction is the direction from the first conductive type layer to the substrate.

[0013] In one embodiment, it further includes: a front electrode located on the Schottky barrier layer; and a back electrode located on a side of the substrate away from the first conductive type layer.

[0014] In one embodiment, the first conductivity type is N-type, and the second conductivity type is P-type.

[0015] In one embodiment, the substrate is a silicon substrate.

[0016] In one embodiment, the first conductive type layer is a silicon epitaxial layer.

[0017] In one embodiment, the conductive material is polysilicon of a first conductivity type.

[0018] In one embodiment, the dielectric layer is made of silicon oxide.

[0019] In one embodiment, the doping concentration of the substrate is 10 18 ~10 21 / cm 3 .

[0020] In one embodiment, the doping concentration of the first conductive type layer is 10 14 ~10 17 / cm 3 .

[0021] In one embodiment, the depth of the trench structure is greater than 75% of the thickness of the first conductive type layer.

[0022] A method for manufacturing a trench-type Schottky barrier diode comprises: obtaining a wafer, the wafer being formed with a substrate of a first conductivity type and a first conductivity type layer on the substrate, the doping concentration of the first conductivity type layer being lower than the doping concentration of the substrate; forming a trench in the first conductivity type layer; doping the bottom of the trench to form a second conductivity type region below the trench, the bottom of the trench reaching the top of the second conductivity type region, the bottom of the second conductivity type region being separated from the substrate by a portion of the first conductivity type layer; forming a dielectric layer on the inner surface of the trench; filling the trench with the dielectric layer formed with a conductive material; and forming a Schottky barrier layer on the first conductivity type layer.

[0023] In the above-described method for manufacturing a trench-type Schottky barrier diode, the PN junction formed between the second conductivity type region and the first conductivity type layer can withstand reverse voltage, thereby having strong reverse voltage withstand capability. Furthermore, because the trench depth reaches the second conductivity type region, the drift region resistance is reduced to a certain extent during forward conduction, thereby reducing the forward voltage drop of the device.

[0024] In one embodiment, the step of forming a trench in the first conductive type layer has a depth of the trench that is greater than 75% of the thickness of the first conductive type layer.

[0025] In one embodiment, the step of doping the bottom of the trench comprises implanting ions of the second conductivity type into the bottom of the trench by ion implantation, with an implantation energy of 50 keV to 200 keV.

[0026] In one embodiment, after the step of injecting ions of the second conductive type into the bottom of the groove by ion implantation, the step of heat treating the wafer is also included. After the heat treatment, the thickness of the second conductive type region is less than 20 microns, and the thickness direction is the direction from the first conductive type layer to the substrate.

[0027] In one embodiment, the doping concentration of the substrate is 10 18 ~10 21 / cm 3 .

[0028] In one embodiment, the doping concentration of the first conductive type layer is 10 14 ~10 17 / cm 3 .

[0029] In one embodiment, the distance between the bottom of the trench and the top of the substrate is no more than 20 microns.

[0030] In one embodiment, forming a dielectric layer on the inner surface of the trench includes forming an oxide layer on the inner surface of the trench by thermal oxidation to serve as the dielectric layer.

[0031] In one embodiment, forming a Schottky barrier layer on the first conductive type layer includes:

[0032] depositing a Schottky metal layer on the first conductive type layer and the conductive material;

[0033] Through heat treatment, the Schottky metal layer reacts with the first conductive type layer to form a metal silicide as the Schottky barrier layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the following briefly introduces the drawings required for use in the embodiments or related technology descriptions. Obviously, the drawings described below are only some embodiments of this application. For those of ordinary skill in the art, other drawings can be derived from these drawings without inventive effort.

[0035] FIG1 is a schematic diagram of the cross-sectional structure of a trench Schottky barrier diode in one embodiment of the present application.

[0036] FIG2 is a simulation diagram of the electric field distribution of a trench Schottky barrier diode according to an embodiment of the present application.

[0037] FIG3 is a simulation diagram of the breakdown current trend of a trench Schottky barrier diode according to an embodiment of the present application.

[0038] FIG4 is a simulation diagram of the electric field distribution of a trench Schottky barrier diode of a comparative example.

[0039] FIG5 is a simulation diagram of the breakdown current trend of a trench Schottky barrier diode of a comparative example.

[0040] FIG6 is a flow chart of a method for manufacturing a trench Schottky barrier diode in one embodiment of the present application.

[0041] 7 to 10 are schematic cross-sectional views of devices during the process of manufacturing a trench Schottky barrier diode using the method shown in FIG6 . DETAILED DESCRIPTION

[0042] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide some embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the disclosure of the present application.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0044] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part.

[0045] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, then the elements or features described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both the upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0046] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present application. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0047] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic illustrations of ideal embodiments (and intermediate structures) of the present application. As such, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances are contemplated. Accordingly, embodiments of the present application should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Accordingly, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shape of the region of the device and are not intended to limit the scope of the present application.

[0048] The semiconductor field terms used in this article are technical terms commonly used by those skilled in the art. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents P-type with heavy doping concentration, P-type represents P-type with medium doping concentration, P-type represents P-type with light doping concentration, N+ type represents N-type with heavy doping concentration, N-type represents N-type with medium doping concentration, and N-type represents N-type with light doping concentration.

[0049] It is difficult to balance the forward conduction voltage drop and reverse withstand voltage of trench-type Schottky diodes. An exemplary trench-type Schottky diode adopts a deep trench structure, extending the trench to pass through the bottom of the drift region and contacting the substrate, thereby achieving the purpose of reducing body resistance and lowering forward conduction voltage drop. However, since the bottom of the trench is in contact with the high-concentration substrate, reverse breakdown is easily caused. Another exemplary trench-type Schottky diode introduces a P-type doped floating plate structure between the bottom of the trench and the substrate to improve the reverse breakdown characteristics. However, the forward conduction voltage drop of this trench-type Schottky diode is relatively high.

[0050] This application aims to reduce the forward conduction voltage drop of a trench Schottky diode while maintaining its reverse withstand voltage characteristics. Figure 1 is a schematic cross-sectional structure diagram of a trench Schottky barrier diode according to one embodiment of this application. The trench Schottky barrier diode comprises a substrate 170, a first conductivity type layer 160, at least one second conductivity type region 150, a Schottky barrier layer 120, and at least one trench structure.

[0051] The substrate 170 has a first conductivity type. A first conductivity type layer 160 is located on the substrate 170, and the doping concentration of the first conductivity type layer 160 is less than the doping concentration of the substrate 170. The first conductivity type layer 160 serves as the drift region of the device. A trench structure extends from the first surface of the first conductivity type layer 160 (i.e., the side facing away from the substrate 170) toward the substrate 170. The trench structure includes a conductive material 140 and a dielectric layer 130 surrounding the conductive material 140 from the side and bottom. In other words, the trench structure includes the dielectric layer 130 formed on the inner surface of the trench and the conductive material 140 filled in the trench. The dielectric layer 130 is used for insulation isolation. The second conductivity type region 150 is located directly below the trench, and the top of the second conductivity type region 150 is in direct contact with the bottom of the dielectric layer 130. The bottom of the second conductivity type region 150 is separated from the substrate 170 by a portion of the first conductivity type layer 160. Schottky barrier layer 120 is located on first conductivity type layer 160. In the embodiment shown in FIG1 , the first conductivity type is N-type and the second conductivity type is P-type. Furthermore, substrate 170 is an N+ silicon substrate, first conductivity type layer 160 is an N-silicon epitaxial layer, and second conductivity type region 150 is a P-type doped region.

[0052] In the trench-type Schottky barrier diode, the PN junction formed by the second conductivity type region 150 and the first conductivity type layer 160 can withstand reverse voltage, thus having strong reverse voltage withstand capability. Furthermore, because the trench extends to the second conductivity type region 150, the drift region resistance is reduced to a certain extent during forward conduction, thereby reducing the forward conduction voltage drop of the device.

[0053] In one embodiment of the present application, the distance between the bottom of the dielectric layer 130 and the top of the substrate 170 is no greater than 20 microns. The trench depth is set to be deeper, but a position for forming the second conductive type region 150 is left between the trench bottom and the top of the substrate 170.

[0054] In one embodiment of the present application, the thickness of the second conductive type region 150 is less than 20 microns, and the thickness direction is the direction from the first conductive type layer 160 to the substrate 170, that is, the longitudinal direction in Figure 1. Furthermore, the thickness of the second conductive type region 150 is not less than 0.1 microns.

[0055] In one embodiment of the present application, the trench structure is a deep trench structure, and the depth of the trench structure is greater than 75% of the thickness of the first conductive type layer 160 .

[0056] In the embodiment shown in FIG1 , the trench Schottky barrier diode further includes a front electrode 110 located on the Schottky barrier layer 120, and a back electrode 180 located on the bottom surface of the substrate 170. In one embodiment of the present application, the front electrode 110 is an anode, and the back electrode 180 is a cathode. In one embodiment of the present application, the front electrode 110 is a metal film composed of one or more of AlSiCu, Ti, Ni, and Ag. In one embodiment of the present application, the back electrode 180 is a metal film composed of one or more of Ti, Ni, and Ag.

[0057] In one embodiment of the present application, the conductive material 140 is polysilicon of the first conductivity type. In one embodiment of the present application, the material of the dielectric layer 130 is silicon oxide, such as silicon dioxide. In one embodiment of the present application, the Schottky barrier layer 120 is a metal silicide formed by reacting at least one metal of Ti, Pt, Ni, Cr, W, Mo, and Co (i.e., a Schottky metal layer) with the first conductivity type layer 160 through heat treatment. A Schottky metal layer is also formed on the trench structure. The Schottky barrier layer 120 forms a Schottky contact with the first conductivity type layer 160 below.

[0058] Figure 2 is a simulation diagram of the electric field distribution of a trench Schottky barrier diode according to an embodiment of the present application, and Figure 4 is a simulation diagram of the electric field distribution of a trench Schottky barrier diode according to a comparative example, namely, Abs(Electric Field(Electric Field-Vector)) [V*cm^-1]. The scales of the bottom two rows in Figure 2 are 6.0E+01 and 1.1E-07, and the scales of the bottom two rows in Figure 4 are 6.0E+01 and 2.3E-07. Figure 3 is a simulation diagram of the breakdown current trend of a trench Schottky barrier diode according to an embodiment of the present application. Figure 5 is a simulation diagram of the breakdown current trend of a trench Schottky barrier diode according to a comparative example, namely, Abs(Total Current Density(Total Current Density-Vector))[A*cm^-2]. The bottom of the trench of the comparative example is separated from the second conductive type region (P-type doped region) by a first conductive type layer (drift region). The simulated reverse breakdown voltage of the comparative example is 54.18V, while the reverse breakdown voltage obtained by the simulation of the embodiment of the present application is 57.89V. It can be seen that the structure of the top of the second conductivity type region 150 in the embodiment of the present application directly contacting the bottom of the dielectric layer 130 can improve the depletion capability of the device during reverse withstand voltage and increase the reverse breakdown voltage (reverse withstand voltage) of the device. In Figures 2, 3, 4, and 5, the X-axis represents the size in microns; the Y-axis represents the coordinate in the thickness direction in microns.

[0059] FIG6 is a flow chart of a method for manufacturing a trench Schottky barrier diode according to an embodiment of the present application, comprising the following steps:

[0060] S410 , obtaining a wafer having a substrate and a first conductive type layer formed thereon.

[0061] 7, a first conductive type layer 160 is formed on a substrate 170. In one embodiment of the present application, step S410 includes growing a lightly doped silicon epitaxial layer as the first conductive type layer 160 on the provided silicon substrate 170. In one embodiment of the present application, the doping concentration of the substrate is 10 18 ~10 21 / cm 3 In one embodiment of the present application, the doping concentration of the first conductive type layer 160 is 10 14 ~10 17 / cm 3 .

[0062] S420 , forming a trench in the first conductive type layer.

[0063] In one embodiment of the present application, a groove is formed in the first conductive type layer 160 by an etching process. Furthermore, before etching, an oxide layer (e.g., a silicon dioxide layer) can be first deposited on the first conductive type layer 160. Then, a hard mask layer 192, such as a silicon nitride layer, is formed on the oxide layer (not shown in FIG8 ). Forming the hard mask layer 192 before etching can protect the cleanliness of the upper surface of the first conductive type layer 160. The thickness of the hard mask layer 192 can be set according to the requirements of etching. Thereafter, a photoresist layer 194 is formed on the hard mask layer 192 by photolithography. Specifically, after photoresist is coated on the hard mask layer 192, the photoresist is exposed through a corresponding photomask, and after development, a photoresist layer 194 exposing an injection window is formed. Next, the hard mask layer 192 is etched using the photoresist layer 194 as an etch barrier, thereby removing the hard mask layer 192 below the implant window while retaining the hard mask layer 192 covering the photoresist layer 194. Finally, the oxide layer and the first conductive type layer 160 are further etched downward to form a trench 131, as shown in FIG8 .

[0064] In one embodiment of the present application, the distance between the bottom of the trench 131 and the top of the substrate 170 is no greater than 20 micrometers.

[0065] In one embodiment of the present application, the trench 131 is a deep trench, and the depth thereof is greater than 75% of the thickness of the first conductive type layer 160 .

[0066] S430 , doping the bottom of the trench to form a second conductive type region below the trench.

[0067] In one embodiment of the present application, as shown in FIG9 , step S430 is to inject ions of the second conductivity type into the bottom of the trench 131 through an ion implantation process to form a second conductivity type region 150. In one embodiment of the present application, the implantation energy is 50kev to 200kev. In one embodiment of the present application, after the second conductivity type ions are implanted, a step of heat treating the wafer is also included. After the thermal annealing treatment, the implanted second conductivity type ions further diffuse in the first conductivity type layer 160 to form a second conductivity type region 150. In one embodiment of the present application, the first conductivity type is N-type and the second conductivity type is P-type.

[0068] S440 , forming a dielectric layer on the inner surface of the trench.

[0069] In one embodiment of the present application, as shown in FIG. 9 , an oxide layer is formed on the inner surface of the trench 131 by thermal oxidation to serve as the dielectric layer 130 .

[0070] S450 , filling the trench with a conductive material.

[0071] In one embodiment of the present application, as shown in FIG. 9 , step S450 is to deposit polysilicon of the first conductivity type into the trench 131 as the conductive material 140 .

[0072] S460 , forming a Schottky barrier layer on the first conductive type layer.

[0073] In one embodiment of the present application, after step S450 and before step S460, a step of removing the conductive material 140 outside the trench 131 by chemical mechanical polishing (CMP) is further included. After the conductive material 140 is planarized, the structure shown in FIG9 is obtained.

[0074] In one embodiment of the present application, step S460 further includes:

[0075] S462 , depositing a Schottky metal layer on the first conductive type layer 160 and the conductive material 140 .

[0076] In one embodiment of the present application, the Schottky metal layer includes at least one metal selected from the group consisting of Ti, Pt, Ni, Cr, W, Mo, and Co.

[0077] S464 , through heat treatment, the Schottky metal layer and the first conductive type layer 160 react to form a metal silicide, which serves as the Schottky barrier layer 120 (as shown in FIG. 10 ).

[0078] In one embodiment of the present application, the heat treatment in step S464 is performed using a rapid thermal annealing process. The structure after step S464 is completed is shown in FIG10 .

[0079] In the above-described trench Schottky barrier diode manufacturing method, the PN junction formed by the second conductivity type region 150 and the first conductivity type layer 160 can withstand reverse voltage, thus having strong reverse voltage withstand capability. Furthermore, because the trench depth reaches the second conductivity type region 150, the drift region resistance is reduced to a certain extent during forward conduction of the device, thereby reducing the forward conduction voltage drop of the device.

[0080] In one embodiment of the present application, step S460 further includes forming a front electrode 110 on the Schottky barrier layer 120 and a back electrode 180 on the bottom surface (lower surface) of the substrate 170, see Figure 1. Specifically, metal can be sputtered on the lower surface of the substrate 170 and the upper surface of the Schottky barrier layer 120 to form a cathode and an anode, respectively. In one embodiment of the present application, the front electrode 110 is a metal film composed of one or more of AlSiCu, Ti, Ni, and Ag. In one embodiment of the present application, the back electrode 180 is a metal film composed of one or more of Ti, Ni, and Ag.

[0081] In one embodiment of the present application, the thickness of the second conductive type region 150 is less than 20 micrometers. Furthermore, the thickness of the second conductive type region 150 is not less than 0.1 micrometers.

[0082] The manufacturing method of the trench Schottky barrier diode of the present application is based on the same inventive concept as the trench Schottky barrier diode. For matters not specifically described in the manufacturing method of the trench Schottky barrier diode, please refer to the previous introduction to the trench Schottky barrier diode.

[0083] It should be understood that, although the various steps in the flowchart of the present application are shown in sequence as indicated by the arrows, these steps are not necessarily performed in sequence in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be performed in other orders. Moreover, at least a portion of the steps in the flowchart of the present application may include multiple steps or multiple stages, and these steps or stages are not necessarily performed at the same time, but can be performed at different times, and the execution order of these steps or stages is not necessarily performed in sequence, but can be performed in turn or alternately with other steps or at least a portion of steps or stages in other steps.

[0084] Throughout this specification, references to terms such as "some embodiments," "other embodiments," and "desired embodiments" indicate that a particular feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present application. The schematic descriptions of these terms throughout this specification do not necessarily refer to the same embodiment or example.

[0085] The technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0086] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A trench Schottky barrier diode, comprising: a substrate having a first conductivity type; A first conductive type layer, located on the substrate, wherein the doping concentration of the first conductive type layer is lower than the doping concentration of the substrate; A groove structure extending from a first surface of the first conductive type layer toward the substrate, the first surface being a side of the first conductive type layer facing away from the substrate; the groove structure comprises a conductive material and a dielectric layer surrounding the conductive material from the side and bottom surfaces; A Schottky barrier layer, located on the first conductive type layer; A second conductive type region, located below the trench structure, with a top of the second conductive type region directly contacting the bottom of the dielectric layer, and a bottom of the second conductive type region being separated from the substrate by a portion of the first conductive type layer; The first conductivity type and the second conductivity type are opposite conductivity types. 2 . The trench Schottky barrier diode according to claim 1 , wherein a distance between a bottom of the dielectric layer and a top of the substrate is no greater than 20 micrometers. 3 . The trench Schottky barrier diode according to claim 1 , wherein the thickness of the second conductive type region is less than 20 microns, and the thickness direction is the direction from the first conductive type layer to the substrate.

4. The trench Schottky barrier diode according to claim 1, further comprising: A front electrode, located on the Schottky barrier layer; The back electrode is located on a side of the substrate facing away from the first conductive type layer. 5 . The trench Schottky barrier diode according to claim 1 , wherein the first conductivity type is N-type, and the second conductivity type is P-type. The trench Schottky barrier diode according to claim 1 , wherein the substrate is a silicon substrate. The trench Schottky barrier diode according to claim 1 , wherein the first conductive type layer is a silicon epitaxial layer. 8 . The trench Schottky barrier diode according to claim 1 , wherein the conductive material is polysilicon of a first conductivity type. 9 . The trench Schottky barrier diode according to claim 1 , wherein the dielectric layer is made of silicon oxide.

10. The trench Schottky barrier diode according to claim 1, wherein the doping concentration of the substrate is 10 18 ~10 21 / cm 3 .

11. The trench Schottky barrier diode according to claim 1, wherein the doping concentration of the first conductive type layer is 10 14 ~10 17 / cm 3 . 12 . The trench Schottky barrier diode according to claim 1 , wherein a depth of the trench structure is greater than 75% of a thickness of the first conductive type layer.

13. A method for manufacturing a trench Schottky barrier diode, comprising: Obtaining a wafer, wherein the wafer is formed with a substrate of a first conductivity type and a first conductivity type layer on the substrate, wherein a doping concentration of the first conductivity type layer is less than a doping concentration of the substrate; forming a groove in the first conductive type layer; Doping the bottom of the trench to form a second conductive type region below the trench, wherein the bottom of the trench reaches the top of the second conductive type region, and the bottom of the second conductive type region is separated from the substrate by a portion of the first conductive type layer; forming a dielectric layer on an inner surface of the trench; Filling the trench where the dielectric layer has been formed with a conductive material; A Schottky barrier layer is formed on the first conductive type layer. 14 . The method for manufacturing a trench Schottky barrier diode according to claim 13 , wherein the trench is a deep trench, and a depth thereof is greater than 75% of a thickness of the first conductive type layer.

15. The method for manufacturing a trench Schottky barrier diode according to claim 13, wherein the step of doping the bottom of the trench comprises: Ions of the second conductivity type are implanted into the bottom of the trench by ion implantation, with an implantation energy of 50kev to 200kev.

16. The method for manufacturing a trench-type Schottky barrier diode according to claim 15, wherein after the step of injecting ions of the second conductive type into the bottom of the trench by ion implantation, the method further comprises heat treating the wafer, and after the heat treatment, the thickness of the second conductive type region is less than 20 microns, and the thickness direction is the direction from the first conductive type layer to the substrate.

17. The method for manufacturing a trench Schottky barrier diode according to claim 13, wherein the doping concentration of the substrate is 10 18 ~10 21 / cm 3 , and / or the doping concentration of the first conductive type layer is 10 14 ~10 17 / cm 3 . 18 . The method for manufacturing a trench Schottky barrier diode according to claim 13 , wherein the distance between the bottom of the trench and the top of the substrate is not greater than 20 micrometers.

19. The method for manufacturing a trench Schottky barrier diode according to claim 13, wherein forming a dielectric layer on an inner surface of the trench comprises: An oxide layer is formed on the inner surface of the trench by thermal oxidation to serve as the dielectric layer.

20. The method for manufacturing a trench Schottky barrier diode according to claim 13, wherein forming a Schottky barrier layer on the first conductive type layer comprises: depositing a Schottky metal layer on the first conductive type layer and on the conductive material; Through heat treatment, the Schottky metal layer reacts with the first conductive type layer to form a metal silicide as the Schottky barrier layer.

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