Multilayer circuit board, processing method therefor, chip system, and electronic device

Abstract

The present application provides a multilayer circuit board, a processing method therefor, a chip system, and an electronic device. The processing method comprises: processing on a first substrate a second via, a first conductive pattern and a second conductive pattern, and processing a third via on a second substrate; and stacking and laminating the first substrate, the second substrate and a first insulating layer to fix same. The processing method further comprises: performing via filling plating on the first substrate to form a second conductive channel. The processing method further comprises electroplating the second substrate to form a sixth conductive pattern and a third conductive channel. The first insulating layer comprises a first conductive part. The first conductive pattern, the second conductive pattern and the sixth conductive pattern are electrically connected to the second conductive channel by means of the third conductive channel and the first conductive part. The second and third vias are filled in a via filling plating mode, thereby improving the wiring density and the chip signal transmission capability of the multilayer circuit board and improving the electrical performance and the thermal performance of the multilayer circuit board. In addition, via filling plating is suitable for mass production and allows for stable process yields.

Description

Multilayer circuit board and processing method thereof, chip system and electronic equipment

[0001] This invention claims priority to the Chinese patent application filed with the China Patent Office on November 16, 2023, with application number 202311531991.1 and application name “Multi-layer circuit board and its processing method, chip system and electronic device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present invention relates to the field of chip technology, and in particular to a multi-layer circuit board and a processing method thereof, a chip system and an electronic device. Background Art

[0003] As transistor scaling becomes increasingly challenging, market demands for higher chip performance continue to rise. These demands not only increase chip processing speed but also demand large memory capacity and low latency between the processor and memory. To meet these requirements, multiple chips are typically packaged in a flip-chip ball grid array (FCBGA) format. In this chip system, multiple chips are attached to an interposer, which is attached to a package substrate, which is attached to a printed circuit board (PCB). Signals can be transmitted between the chips, interposer, package substrate, and PCB. The introduction of an interposer between the chip and the package substrate allows for the placement of multiple chips in close proximity, significantly improving bandwidth performance, thanks to the high-density redistribution layer (RDL) fabricated on the interposer, which can achieve line widths of up to 1µm. However, because the chips and interposer are typically silicon-based, the significant difference in coefficient of thermal expansion (CTE) between them and the organic-based package substrate and PCB makes it difficult to manufacture large-scale packages, limiting the continued evolution of FCBGA packaging.

[0004] The package substrate and PCB are a multi-layer stacked structure (hereinafter referred to as a multi-layer circuit board), primarily composed of multiple dielectric layers and metal layers. In existing technology, the dielectric layer of a multi-layer circuit board is primarily made of organic materials (hereinafter referred to as organic substrates). With the development of larger packaging, glass dielectric materials are gaining increasing attention. Glass and silicon have similar CTEs. Using glass as the dielectric layer (hereinafter referred to as a glass substrate) can reduce the CTE mismatch between the substrate, chip, and interposer, thereby supporting the realization of larger substrates and packages.

[0005] In the existing processing technology for multi-layer glass substrates, through holes are first processed on a single-layer glass substrate, and then the through holes and surface conductive patterns are electroplated. Subsequently, a layer of insulating film is laminated on the glass substrate and holes are punched in the film at the positions corresponding to the through-glass holes. Conductive paste is applied to the through-glass holes and the through-holes in the film layer. Finally, the stacked glass substrates are heat-pressed into shape in one step. The film acts as an interlayer bond, and electrical interconnection is achieved through the conductive paste in the holes.

[0006] However, in the processing of existing technologies, the electrical interconnection of conductive paste has problems such as poor electrical and thermal conductivity, which in turn affects the electrical and thermal performance of the chip system.

[0007] Summary of the Invention

[0008] In view of this, the present application provides a multi-layer circuit board and a processing method thereof, a chip system and an electronic device, so as to solve the problem of poor electrical conductivity and thermal conductivity of electrical interconnection in the prior art.

[0009] A first aspect of an embodiment of the present application provides a method for processing a multilayer circuit board, which includes: making a core board, the core board including a first conductive channel extending along the thickness direction of the core board; making a first sub-board, the first sub-board including a second channel extending along the thickness direction of the core board, the first sub-board including a first surface and a second surface arranged opposite to each other along the thickness direction of the core board, a first conductive pattern arranged on the first surface, a second conductive pattern arranged on the second surface, and a difference between an area ratio of the first conductive pattern on the first surface and an area ratio of the second conductive pattern on the second surface is less than or equal to 50%; making a second sub-board, the second sub-board including a third channel extending along the thickness direction of the core board, the second sub-board including a third surface and a fourth surface arranged opposite to each other along the thickness direction of the core board, a third conductive pattern arranged on the third surface, a fourth conductive pattern arranged on the fourth surface, and a difference between an area ratio of the third conductive pattern on the third surface and an area ratio of the fourth conductive pattern on the fourth surface is less than or equal to 50%; taking a first insulating layer and a second insulating layer, and forming a plurality of insulating layers along the thickness direction of the multilayer circuit board; direction, stacking the first sub-board, the first insulating layer, the core board, the second insulating layer and the second sub-board, with the first insulating layer located between the first sub-board and the core board, the second insulating layer located between the core board and the second sub-board, the first conductive pattern located on the side of the first sub-board away from the core board, and the fourth conductive pattern located on the side of the second sub-board away from the core board; pressing and fixing the first sub-board, the first insulating layer, the core board, the second insulating layer and the second sub-board; removing the first conductive pattern and the fourth conductive pattern; electroplating the first sub-board to form a fifth conductive pattern on the first surface, filling the second hole with the second conductive medium to form a second conductive channel, and the fifth conductive pattern, the second conductive channel and the second conductive pattern constitute a signal transmission line structure; electroplating the second sub-board to form a sixth conductive pattern on the fourth surface, filling the third hole with the third conductive medium to form a third conductive channel, and the sixth conductive pattern, the third conductive channel and the third conductive pattern constitute a signal transmission line structure; the first sub-board, the core board and the second sub-board are electrically connected through the second conductive channel, the first conductive portion, the first conductive channel, the second conductive portion and the third conductive channel. In the present application, the area ratio difference between the first conductive pattern and the second conductive pattern, and the area ratio difference between the third conductive pattern and the fourth conductive pattern are both no more than 50%, so that the first conductive pattern is similar to the second conductive pattern, and the third conductive pattern is similar to the fourth conductive pattern, so that the mechanical characteristics of the first sub-board and the second sub-board on both sides along the thickness direction are similar, thereby reducing the risk of warping and deformation of the first sub-board and the second sub-board during subsequent processing, thereby reducing the difficulty of stacking the first sub-board, the second sub-board, and the core board, and improving the accuracy and reliability of the electrical connection between the first sub-board, the core board, the second sub-board and other components or substrates.During the production of the first daughter board, the first conductive pattern is first removed, and then the fifth conductive pattern and the second conductive channel are produced, so that the fifth conductive pattern, the second conductive channel and the second conductive pattern constitute a signal transmission line structure, thereby reducing the loss during signal transmission of the multilayer circuit board; similarly, during the production of the second daughter board, the fourth conductive pattern is first removed, and then the sixth conductive pattern and the third conductive channel are produced on the metal layer, so that the sixth conductive pattern, the third conductive channel and the third conductive pattern constitute a signal transmission line structure, thereby reducing the loss during signal transmission of the multilayer circuit board.

[0010] In some embodiments, the step of stacking the first sub-board, the first insulating layer, the core board, the second insulating layer and the second sub-board includes: placing the first insulating layer and the second insulating layer on both sides of the core board along the thickness direction of the core board; placing the first sub-board on the side of the first insulating layer away from the core board and the second sub-board on the side of the second insulating layer away from the core board along the thickness direction of the core board; after the step of pressing and fixing the first sub-board, the first insulating layer, the core board, the second insulating layer and the second sub-board, the processing method of the multilayer circuit board includes: processing a first through hole on the first insulating layer and processing a second through hole on the second insulating layer, the first through hole passing through the first insulating layer along the thickness direction of the first insulating layer and the second through hole passing through the second insulating layer along the thickness direction of the second insulating layer; sputtering a metal layer on the side walls of the first through hole and the second through hole; then electroplating and filling the first through hole to form a first conductive part, and electroplating and filling the second through hole to form a second conductive part. In the present application, the first conductive part and the second conductive part are processed by electroplating hole filling, which reduces the required radial dimensions of the first conductive part and the second conductive part, is beneficial to improving the wiring density of the multi-layer circuit board and the chip signal transmission capability, and at the same time, is beneficial to improving the electrical conductivity and thermal conductivity of the first conductive part and the second conductive part, thereby improving the electrical performance and thermal performance of the multi-layer circuit board and the chip system; electroplating hole filling is suitable for mass production, and the process yield is stable.

[0011] In some embodiments, the steps of stacking the first sub-board, the first insulating layer, the core board, the second insulating layer, and the second sub-board include: placing the first insulating layer and the second insulating layer on both sides of the core board along the thickness direction of the core board; processing a first through-hole in the first insulating layer and a second through-hole in the second insulating layer, the first through-hole penetrating the first insulating layer along the thickness direction of the first insulating layer, and the second through-hole penetrating the second insulating layer along the thickness direction of the second insulating layer; placing a fourth conductive medium into the first through-hole and a fifth conductive medium into the second through-hole, the fourth conductive medium being solder or conductive paste, and the fifth conductive medium being solder or conductive paste; and placing the first sub-board on the side of the first insulating layer away from the core board and the second sub-board on the side of the second insulating layer away from the core board along the thickness direction of the core board. In the present application, by filling the first through-hole and the second through-hole with solder or conductive paste, the processing method of the first through-hole and the second through-hole is simplified, thereby reducing the processing cost of the multi-layer circuit board and the chip system.

[0012] In some embodiments, the steps of making a core board include: taking a core substrate, laser inducing the core substrate to form a first phase change channel, wherein the extension direction of the first phase change channel is parallel to the thickness direction of the core substrate; etching the core substrate having a phase change channel to form a first channel; sputtering a metal layer on the exposed surface of the core substrate and the sidewall of the first channel; covering the exposed surface of the core substrate with photoresist; electroplating and filling the first channel to form a first conductive channel, wherein conductor patterns are formed at both ends of the first conductive channel; and removing the photoresist and the sputtered metal layer. In the present application, the first channel is processed by laser induction and etching, which improves the accuracy of the processing position and processing size of the first channel, improves the accuracy of the electrical connection position between the core board and the first sub-board and the second sub-board, and reduces the difficulty of stacking and compounding the core board, the first sub-board and the second sub-board. Filling the first channel with the first conductive medium by electroplating hole filling reduces the required radial size of the first channel, which is beneficial to improving the wiring density of the multi-layer circuit board and the chip signal transmission capability. At the same time, it is beneficial to improving the electrical conductivity and thermal conductivity of the first conductive channel, thereby improving the electrical and thermal performance of the multi-layer circuit board and the chip system. Electroplating hole filling is suitable for mass production and has a stable process yield.

[0013] In some embodiments, the steps of making a first sub-board include: taking a first substrate, the first substrate including a first surface and a second surface arranged opposite to each other along its own thickness direction, sputtering a metal layer on the first surface and the second surface; covering the first surface with a first photoresist, and covering the second surface with a second photoresist; photoetching the first surface to form a first pattern, and photoetching the second surface to form a second pattern; electroplating the first pattern and the second pattern to form a first conductive pattern and a second conductive pattern; removing the first photoresist, the second photoresist and the metal layer; the steps of making a second sub-board include: taking a second substrate, covering the third surface and the fourth surface with a metal layer; covering the third surface with a third photoresist, and covering the fourth surface with a fourth photoresist; photoetching the third surface to form a third pattern, and photoetching the fourth surface to form a fourth pattern; electroplating the third pattern and the fourth pattern to form a third conductive pattern and a fourth conductive pattern; removing the third photoresist, the fourth photoresist and the metal layer. In the present application, the first conductive pattern, the second conductive pattern, the third conductive pattern and the fourth conductive pattern are processed by photolithography and electroplating, thereby increasing the accuracy of parameters such as shape, position, and size of the first conductive pattern, the second conductive pattern, the third conductive pattern and the fourth conductive pattern, thereby improving the processing yield of the first sub-board and the second sub-board.

[0014] In some embodiments, the steps of making the first sub-plate include: laser inducing the first substrate to form a second phase change channel, wherein the extension direction of the second phase change channel is parallel to the thickness direction of the first substrate; etching the first substrate having the second phase change channel to form a second channel; and making the second sub-plate include: laser inducing the second substrate to form a third phase change channel, wherein the extension direction of the third phase change channel is parallel to the thickness direction of the second substrate; etching the second substrate having the third phase change channel to form a third channel. In the present application, the second channel and the third channel are processed by laser induction and etching, which improves the accuracy of the processing position and processing size of the second channel and the third channel, thereby improving the accuracy of the electrical connection position between the first substrate and the second substrate, and further reducing the difficulty of laminating and compounding the first substrate and the second substrate.

[0015] In some embodiments, the step of electroplating the first sub-board includes: sputtering a metal layer on the first surface and the side walls of the second channel; covering the first surface with a fifth photoresist; photoetching the first surface to form a fifth pattern; electroplating the fifth pattern and the second channel to form a fifth conductive pattern and a second conductive channel; removing the fifth photoresist and the metal layer; the step of electroplating the second sub-board includes: covering the fourth surface and the side walls of the third channel with a metal layer; covering the fourth surface with a sixth photoresist; photoetching the fourth surface to form a sixth pattern; electroplating the sixth pattern and the third channel to form a sixth conductive pattern and a third conductive channel; removing the sixth photoresist and the metal layer. In this application, the second and third vias are processed by electroplating and filling, which reduces the required radial dimensions of the second and third vias. This helps improve the wiring density of the first and second daughter boards, thereby improving the wiring density of the multilayer circuit board and the chip signal transmission capability. It also helps improve the electrical and thermal conductivity of the first, second, and third conductive channels, thereby improving the electrical and thermal performance of the multilayer circuit board and chip system. Electroplating and filling are suitable for mass production and have a stable process yield. The fifth conductive pattern and the second conductive channel are electroplated simultaneously, and the sixth conductive pattern and the third conductive channel are electroplated simultaneously, simplifying the processing operations and processing cycle of the first and second daughter boards.

[0016] In some embodiments, the processing method of the multilayer circuit board further includes: making a third sub-board, the third sub-board including a fourth channel extending along its own thickness direction, the third sub-board including a fifth surface and a sixth surface arranged opposite to each other along its own thickness direction, a seventh conductive pattern being provided on the fifth surface, an eighth conductive pattern being provided on the sixth surface, and the difference between the area ratio of the seventh conductive pattern on the fifth surface and the area ratio of the eighth conductive pattern on the sixth surface is less than or equal to 50%; taking a third insulating layer, and placing the third insulating layer and the third sub-board on the side of the second sub-board away from the core board along the thickness direction of the second sub-board, and the third The insulating layer is located between the second sub-board and the third sub-board, and the eighth conductive pattern is located on the side of the third sub-board away from the third insulating layer; the second sub-board and the third sub-board are pressed and fixed; the eighth conductive pattern is removed; the third sub-board is electroplated to form an eleventh conductive pattern on the sixth surface, and the fourth conductive medium is filled in the fourth channel to form a fourth conductive channel, and the eleventh conductive pattern, the fourth conductive channel, and the seventh conductive pattern constitute a signal transmission line structure; the third insulating layer includes a third conductive portion, and the third sub-board is electrically connected to the second sub-board through the fourth conductive channel and the third conductive portion; and / or, the processing method of the multi-layer circuit board further includes: making a fourth The fourth sub-board includes a fifth channel extending along the thickness direction of the fourth sub-board, the fourth sub-board includes a seventh surface and an eighth surface arranged opposite to each other along the thickness direction of the fourth sub-board, a ninth conductive pattern is arranged on the seventh surface, and a tenth conductive pattern is arranged on the eighth surface, and the difference between the area ratio of the ninth conductive pattern on the seventh surface and the area ratio of the tenth conductive pattern on the eighth surface is less than or equal to 50%; after the steps of pressing and fixing the first sub-board, the first insulating layer, the core board, the second insulating layer and the second sub-board, the processing method of the multi-layer circuit board includes: taking the fourth insulating layer, and extending the fourth insulating layer along the thickness direction of the first sub-board. The fourth sub-board is placed on the side of the first sub-board away from the core board, the fourth insulating layer is located between the fourth sub-board and the first sub-board, and the ninth conductive pattern is located on the side of the fourth sub-board away from the fourth insulating layer; the fourth sub-board is pressed and fixed to the first sub-board; the ninth conductive pattern is removed; the fourth sub-board is electroplated to form a twelfth conductive pattern on the seventh surface, and a fifth conductive medium is filled in the fifth channel to form a fifth conductive channel. The twelfth conductive pattern, the fifth conductive channel, and the tenth conductive pattern constitute a signal transmission line structure; the fourth insulating layer includes a fourth conductive portion, and the fourth sub-board is electrically connected to the first sub-board via the fifth conductive channel and the fourth conductive portion. In this application, the multi-layer circuit board also includes a third sub-board and a fourth sub-board, increasing the number of substrate layers on the multi-layer circuit board to meet the signal transmission requirements of higher-performance chip systems. The difference between the area ratio of the seventh conductive pattern and the eighth conductive pattern, and the area ratio of the ninth conductive pattern and the tenth conductive pattern is less than or equal to 50%, so that the mechanical characteristics on both sides of the third and fourth sub-boards are similar, reducing the risk of deformation of the third and fourth sub-boards.

[0017] The second aspect of the present application provides a method for processing a multilayer circuit board, which comprises: taking a first substrate, processing a first conductive pattern, a second conductive pattern, and a second channel on the first substrate, wherein the extension direction of the second channel is parallel to the thickness direction of the first substrate, and the first substrate comprises a first surface and a second surface arranged opposite to each other along its own thickness direction, the first conductive pattern is located on the first surface, and the second conductive pattern is located on the second surface; taking a second substrate, processing a third channel on the second substrate, wherein the extension direction of the third channel is parallel to the thickness direction of the second substrate; taking a first insulating layer, and stacking the second substrate and the first insulating layer on the first substrate along the thickness direction of the first sub-board, wherein the first insulating layer is located between the second substrate and the first substrate; and pressing and fixing the second substrate and the first insulating layer. and the first substrate; before the step of stacking the second substrate and the first insulating layer on the first substrate, or after the step of pressing and fixing the second substrate, the first insulating layer and the first substrate, the processing method of the multilayer circuit board includes: electroplating and filling the first substrate so that the second conductive medium fills the second channel to form a second conductive channel; after the step of pressing and fixing the second substrate, the first insulating layer and the first substrate, the processing method of the multilayer circuit board includes: electroplating the second substrate so that a sixth conductive pattern is formed on the side of the second substrate away from the first substrate, and the third channel is filled with the third conductive medium to form a third conductive channel; the first insulating layer includes a first conductive portion, and the first conductive pattern, the second conductive pattern and the sixth conductive pattern are electrically connected to the second conductive channel through the third conductive channel and the first conductive portion. In the present application, the second and third channels are filled by electroplating, which reduces the required radial dimensions of the second and third channels, and is beneficial to improving the wiring density of the multi-layer circuit board and the chip signal transmission capability. At the same time, it is beneficial to improve the electrical conductivity and thermal conductivity of the second and third conductive channels, thereby improving the electrical and thermal performance of the multi-layer circuit board and the chip system. Electroplating filling is suitable for mass production, and the process yield is stable.

[0018] In some embodiments, when the difference between the area ratio of the first conductive pattern on the first surface and the area ratio of the second conductive pattern on the second surface is less than or equal to 50%, the processing method of the multilayer circuit board includes: making a core board, the core board including a first conductive channel extending along its own thickness direction; processing the first conductive pattern and the second conductive pattern on the first substrate; processing the second channel on the first substrate having the first conductive pattern and the second conductive pattern; the step of stacking the second substrate and the first insulating layer on the first substrate includes: taking the second insulating layer, stacking the first substrate, the first insulating layer, the core board, the second insulating layer and the second substrate, the first insulating layer is located between the first substrate and the core board, the second insulating layer is located between the core board and the second substrate, and the first conductive pattern is located on the side of the first substrate away from the core board; pressing and fixing the second substrate and the first insulating layer The steps of pressing and fixing the first substrate, the first insulating layer, the core board, the second insulating layer and the second substrate include: pressing and fixing the first substrate, the first insulating layer, the core board, the second insulating layer and the second substrate; after the steps of pressing and fixing the first substrate, the first insulating layer, the core board, the second insulating layer and the second substrate, the processing method of the multilayer circuit board includes: removing the first conductive pattern; electroplating the first substrate to form a fifth conductive pattern on the first surface, filling the second channel with a second conductive medium to form a second conductive channel, forming a first sub-board, the fifth conductive pattern and the second conductive channel, and the second conductive pattern constitute a signal transmission line structure; the second insulating layer includes a second conductive portion, and after the step of electroplating the second substrate to form a sixth conductive pattern and a third conductive channel, the fifth conductive pattern, the second conductive pattern and the sixth conductive pattern are electrically connected through the second conductive channel, the first conductive portion, the first conductive channel, the second conductive portion and the third conductive channel. In the present application, the difference between the area ratio of the first conductive pattern on the first surface and the area ratio of the second conductive pattern on the second surface is less than or equal to 50%, so that the first conductive pattern is similar to the second conductive pattern, so that the mechanical characteristics of the two sides of the first sub-board along the thickness direction are similar, thereby reducing the risk of warping and deformation of the first sub-board during subsequent processing, thereby reducing the difficulty of stacking the first sub-board, the second sub-board, and the core board, and improving the accuracy and reliability of the electrical connection between the first sub-board, the core board, the second sub-board and other components or substrates. In the process of making the first sub-board, the first conductive pattern is first removed, and then the fifth conductive pattern and the second conductive channel are made, so that the fifth conductive pattern, the second conductive channel and the second conductive pattern constitute a signal transmission line structure, reducing the signal transmission loss of the multi-layer circuit board.

[0019] In some embodiments, the steps of making a core board include: taking a core substrate, laser inducing the core substrate to form a first phase change channel, wherein the extension direction of the first phase change channel is parallel to the thickness direction of the core substrate; etching the core substrate having a phase change channel to form a first channel; sputtering a metal layer on the exposed surface of the core substrate; electroplating and filling the first channel to form a first conductive channel; and removing the metal layer on the surface of the core substrate. In the present application, the first channel is processed by laser induction and laser etching, which improves the accuracy of the processing position and processing size of the first channel, improves the accuracy of the electrical connection position between the core board and the first sub-board and the second sub-board, and reduces the difficulty of stacking and compounding the core board, the first sub-board and the second sub-board. Filling the first channel with the first conductive medium by electroplating hole filling reduces the required radial size of the first channel, which is beneficial to improving the wiring density of the multi-layer circuit board and the chip signal transmission capability. At the same time, it is beneficial to improving the electrical conductivity and thermal conductivity of the first conductive channel, thereby improving the electrical and thermal performance of the multi-layer circuit board and the chip system. Electroplating hole filling is suitable for mass production and has a stable process yield.

[0020] In some embodiments, before the step of processing the third channel on the second substrate, the processing method of the multilayer circuit board includes: taking the second substrate, the second substrate including a third surface and a fourth surface arranged opposite to each other along the thickness direction of the second substrate, processing the third conductive pattern on the third surface, and processing the fourth conductive pattern on the fourth surface to form a second sub-board, and the difference between the area ratio of the third conductive pattern on the third surface and the area ratio of the fourth conductive pattern on the fourth surface is less than or equal to 50%; after the step of pressing and fixing the first substrate, the first insulating layer, the core board, the second insulating layer and the second substrate, the fourth conductive pattern is located on the side of the second substrate away from the first substrate, and the processing method of the multilayer circuit board includes: removing the fourth conductive pattern. In the present application, the difference between the area ratio of the third conductive pattern on the third surface and the area ratio of the fourth conductive pattern on the fourth surface is less than or equal to 50%, so that the third conductive pattern is similar to the fourth conductive pattern, thereby making the mechanical characteristics of both sides of the second sub-board along the thickness direction similar, reducing the risk of warping and deformation of the second sub-board during subsequent processing, reducing the difficulty of stacking the second sub-board with the core board, and improving the accuracy and reliability of the electrical connection between the second sub-board and the core board, and the second sub-board and the components or substrates on the second sub-board, thereby improving the production yield of the multi-layer circuit board and chip system. In the process of the second sub-board, the fourth conductive pattern is first removed, and then the sixth conductive pattern and the third conductive channel are made, so that the sixth conductive pattern, the third conductive channel and the third conductive pattern constitute a signal transmission line structure, reducing the signal transmission loss of the multi-layer circuit board.

[0021] In some embodiments, the steps of processing the first conductive pattern and the second conductive pattern on the first substrate include: taking the first substrate, sputtering a metal layer on the first surface and the second surface; covering the first surface with a first photoresist, and covering the second surface with a second photoresist; photoetching the first surface to form a first pattern, and photoetching the second surface to form a second pattern; electroplating the first pattern and the second pattern to form the first conductive pattern and the second conductive pattern; removing the first photoresist, the second photoresist and the metal layer; the steps of processing the third conductive pattern on the third surface and processing the fourth conductive pattern on the fourth surface include: taking the second substrate, sputtering a metal layer on the third surface and the fourth surface; covering the third surface with a third photoresist, and covering the fourth surface with a fourth photoresist; photoetching the third surface to form a third pattern, and photoetching the fourth surface to form a fourth pattern; electroplating the third pattern and the fourth pattern to form a third conductive pattern and a fourth conductive pattern; and removing the third photoresist, the fourth photoresist and the metal layer. In the present application, the first conductive pattern, the second conductive pattern, the third conductive pattern and the fourth conductive pattern are processed by photolithography and electroplating, thereby increasing the accuracy of parameters such as shape, position, and size of the first conductive pattern, the second conductive pattern, the third conductive pattern and the fourth conductive pattern, thereby improving the processing yield of the first sub-board and the second sub-board.

[0022] In some embodiments, the step of electroplating the first substrate includes: sputtering a metal layer on the first surface and the sidewalls of the second channel; covering the first surface with a fifth photoresist; performing photolithography on the first surface to form a fifth pattern; electroplating the fifth pattern and the second channel to form a fifth conductive pattern and a second conductive channel; removing the fifth photoresist and the metal layer; and the step of electroplating the second substrate includes: sputtering a metal layer on the fourth surface and the sidewalls of the third channel; covering the fourth surface with a sixth photoresist; performing photolithography on the fourth surface to form a sixth pattern; electroplating the sixth pattern and the third channel to form a sixth conductive pattern and a third conductive channel; and removing the sixth photoresist and the metal layer. In the present application, the fifth and sixth conductive patterns are processed by photolithography and electroplating, which increases the accuracy of parameters such as the shape, position, and size of the fifth and sixth conductive patterns, thereby improving the processing yield of the first and second sub-boards. By processing the second conductive channel and the third conductive channel by electroplating, the radial dimensions of the required second and third channels are reduced, which is beneficial to improving the wiring density of the multi-layer circuit board and the chip signal transmission capability. At the same time, it is beneficial to improve the electrical conductivity and thermal conductivity of the second and third conductive channels, thereby improving the electrical and thermal performance of the multi-layer circuit board and the chip system. Electroplating filling is suitable for mass production and has a stable process yield.

[0023] In some embodiments, the processing method of the multilayer circuit board further includes: making a third sub-board, the third sub-board including a fourth channel extending along the thickness direction of itself, the third sub-board including a fifth surface and a sixth surface arranged opposite to each other along the thickness direction of itself, a seventh conductive pattern being provided on the fifth surface, an eighth conductive pattern being provided on the sixth surface, and the difference between the area ratio of the seventh conductive pattern on the fifth surface and the area ratio of the eighth conductive pattern on the sixth surface is less than or equal to 50%; after the steps of pressing and fixing the first substrate, the first insulating layer, the core board, the second insulating layer and the second substrate, the processing method of the multilayer circuit board includes: taking the third insulating layer, extending along the second In the thickness direction of the sub-board, the third insulating layer and the third sub-board are placed on the side of the second sub-board away from the core board, the third insulating layer is located between the second sub-board and the third sub-board, and the eighth conductive pattern is located on the side of the third sub-board away from the third insulating layer; the second sub-board and the third sub-board are pressed and fixed; the eighth conductive pattern is removed; the third sub-board is electroplated to form an eleventh conductive pattern on the sixth surface, and the fourth conductive medium is filled in the fourth channel to form a fourth conductive channel. The eleventh conductive pattern, the fourth conductive channel, and the seventh conductive pattern constitute a signal transmission line structure; the third insulating layer includes a third conductive portion, and the third sub-board is electrically connected to the second sub-board through the fourth conductive channel and the third conductive portion. and / or, the processing method of the multi-layer circuit board further comprises: making a fourth sub-board, the fourth sub-board comprising a fifth channel extending along the thickness direction thereof, the fourth sub-board comprising a seventh surface and an eighth surface arranged opposite to each other along the thickness direction thereof, a ninth conductive pattern being arranged on the seventh surface, a tenth conductive pattern being arranged on the eighth surface, and the difference between the area ratio of the ninth conductive pattern on the seventh surface and the area ratio of the tenth conductive pattern on the eighth surface is less than or equal to 50%; after the steps of pressing and fixing the first sub-board, the first insulating layer, the core board, the second insulating layer and the second sub-board, the processing method of the multi-layer circuit board comprises: taking the fourth insulating layer, extending along the first sub-board, In the thickness direction, the fourth insulating layer and the fourth sub-board are placed on the side of the first sub-board away from the core board, the fourth insulating layer is located between the fourth sub-board and the first sub-board, and the ninth conductive pattern is located on the side of the fourth sub-board away from the fourth insulating layer; the fourth sub-board and the first sub-board are pressed and fixed; the ninth conductive pattern is removed; the fourth sub-board is electroplated to form a twelfth conductive pattern on the seventh surface, and the fifth conductive medium is filled in the fifth channel to form a fifth conductive channel. The twelfth conductive pattern, the fifth conductive channel, and the tenth conductive pattern constitute a signal transmission line structure; the fourth insulating layer includes a fourth conductive portion, and the fourth sub-board is electrically connected to the first sub-board through the fifth conductive channel and the fourth conductive portion. In the present application, the multi-layer circuit board also includes a third sub-board and a fourth sub-board, which increases the number of stacked substrates on the multi-layer circuit board to meet the signal transmission requirements of higher-performance chip systems.

[0024] In some embodiments, when the first conductive pattern, the second conductive pattern, and the second conductive channel form a signal transmission line structure, the step of electroplating and filling holes on the first substrate is performed simultaneously with the step of processing the first conductive pattern and the second conductive pattern; the step of processing the first conductive pattern, the second conductive pattern, and the second channel on the first substrate includes: processing the second channel on the first substrate; sputtering a metal layer on the first surface and the second surface of the first substrate having the second channel; covering the first surface with a first photoresist and covering the second surface with a second photoresist; photoetching the first surface to form a first pattern and photoetching the second surface to form a second pattern; electroplating the first pattern, the second pattern, and the second channel to form the first conductive pattern, the second conductive pattern, and the second conductive channel. In the present application, the first conductive pattern, the second conductive pattern, and the second conductive channel form a signal transmission line structure, so that the above-mentioned core board can be omitted, which is conducive to reducing the overall thickness of the multi-layer circuit board.

[0025] In some embodiments, the processing method of the multilayer circuit board also includes: making a third sub-board, the third sub-board including a fourth channel extending along the thickness direction of the third sub-board; after the step of pressing and fixing the second substrate, the first insulating layer and the first substrate, the processing method of the multilayer circuit board includes: taking the third insulating layer, and placing the third insulating layer and the third sub-board on the side of the second substrate away from the first substrate along the thickness direction of the second substrate, and the third insulating layer is located between the second substrate and the third sub-board; pressing and fixing the third sub-board and the second substrate; electroplating the third sub-board so that the side of the third sub-board away from the second substrate forms an eleventh conductive pattern, and the fourth channel is filled with a fourth conductive medium to form a fourth conductive channel; the third insulating layer includes a third conductive portion, and the eleventh conductive pattern is electrically connected to the sixth conductive pattern through the fourth conductive channel and the third conductive portion. and / or, the processing method of the multilayer circuit board further includes: making a fourth sub-board, the fourth sub-board including a fifth channel extending along its own thickness direction; after the step of pressing and fixing the second substrate, the first insulating layer, and the first substrate, the processing method of the multilayer circuit board includes: taking the fourth insulating layer, and placing the fourth insulating layer and the fourth sub-board on the side of the first substrate away from the second substrate along the thickness direction of the first substrate, with the fourth insulating layer located between the first substrate and the fourth sub-board; pressing and fixing the first substrate and the fourth sub-board; electroplating the fourth sub-board so that a twelfth conductive pattern is formed on the side of the fourth sub-board away from the first substrate, and a fifth conductive medium is filled in the fifth channel to form a fifth conductive channel; the fourth insulating layer includes a fourth conductive portion, and the twelfth conductive pattern is electrically connected to the first conductive pattern through the fifth conductive channel and the fourth conductive portion. In the present application, the multilayer circuit board further includes a third sub-board and a fourth sub-board, which increases the number of substrate stacking layers on the multilayer circuit board to meet the signal transmission requirements of higher-performance chip systems.

[0026] In some embodiments, the step of processing the second channel on the first substrate includes: laser induction on the first substrate to form a second phase change channel, the extension direction of the second phase change channel is parallel to the thickness direction of the first substrate; etching the first substrate having two phase change channels to form a second channel; the step of processing the third channel on the second substrate includes: laser induction on the second substrate to form a third phase change channel, the extension direction of the third phase change channel is parallel to the thickness direction of the second substrate; etching the second substrate having three phase change channels to form a third channel. In the present application, the second and third channels are processed by laser induction and etching, which improves the accuracy of the processing position and processing size of the second and third channels, thereby improving the accuracy of the electrical connection position of the first substrate and the second substrate, and further reducing the difficulty of stacking and compounding the first and second substrates.

[0027] In some embodiments, the step of stacking the second substrate and the first insulating layer on the first substrate includes: placing the first insulating layer on the first substrate along the thickness direction of the first sub-board; placing the second substrate on a side of the first insulating layer away from the first substrate along the thickness direction of the first sub-board; after the step of pressing and fixing the second substrate, the first insulating layer, and the first substrate, the method for processing the multilayer circuit board includes: processing a first through hole in the first insulating layer, the first through hole penetrating the first insulating layer along the thickness direction of the first insulating layer; sputtering a metal layer on the sidewall of the first through hole; and electroplating and filling the first through hole to form a first conductive portion. In the present application, processing the first and second conductive portions by electroplating and filling reduces the required radial dimensions of the first and second conductive portions, which is beneficial to improving the wiring density of the multilayer circuit board and the chip signal transmission capability. At the same time, it is beneficial to improve the electrical conductivity and thermal conductivity of the first and second conductive portions, thereby improving the electrical and thermal performance of the multilayer circuit board and the chip system. Electroplating and filling are suitable for mass production and have a stable process yield.

[0028] In some embodiments, the step of stacking the second substrate and the first insulating layer on the first sub-board includes: placing the first insulating layer on the first substrate along the thickness direction of the first substrate; machining a first through-hole in the first insulating layer, the first through-hole penetrating the first insulating layer along the thickness direction of the first insulating layer; placing a fourth conductive medium, such as solder or conductive paste, into the first through-hole; and placing the second substrate on a side of the first insulating layer away from the first sub-board along the thickness direction of the first sub-board. In the present application, the first and second through-holes are filled with melted solder or conductive paste to simplify the processing method of the first and second through-holes, thereby reducing the processing cost of the first and second insulating layers, and thereby reducing the processing cost of the multi-layer circuit board and chip system.

[0029] In a third aspect, the present application provides a multilayer circuit board, which is formed by processing the multilayer circuit board using any of the above-described processing methods. In the present application, when the first conductive pattern is similar to the second conductive pattern, and the third conductive pattern is similar to the fourth conductive pattern, the mechanical characteristics of the first and second sub-boards along the thickness direction are similar, thereby reducing the risk of warping and deformation of the first and second sub-boards during subsequent processing. This reduces the difficulty of stacking the first, second, and core boards, and improves the accuracy and reliability of the electrical connections between the first and second sub-boards, the core board, the second sub-board, and other components or substrates, thereby improving the production yield of the multilayer circuit board. When the second and third vias are filled by electroplating, the required radial dimensions of the second and third vias are reduced, which is beneficial for improving the wiring density of the multilayer circuit board and the chip signal transmission capability. At the same time, it is beneficial for improving the electrical conductivity and thermal conductivity of the second and third conductive channels, thereby improving the electrical and thermal performance of the multilayer circuit board and the chip system. Electroplating via filling is suitable for mass production and has a stable process yield.

[0030] The fourth aspect of the present application provides a chip system, which includes: a printed circuit board and a packaging substrate, the packaging substrate is mounted on the printed circuit board, and the packaging substrate is electrically connected to the printed circuit board; an interposer, the interposer is mounted on the packaging substrate, and the interposer is electrically connected to the packaging substrate; a plurality of chip monomers, the chip monomers are mounted on the interposer, and the plurality of chip monomers are electrically connected to the interposer respectively; the printed circuit board is a multi-layer circuit board as described in any one of the above items, and / or the packaging substrate is a multi-layer circuit board as described in any one of the above items. In the present application, since the line width of the redistribution layer on the interposer is relatively small, the plurality of chip monomers can be closely arranged on the surface of the interposer, which reduces the gap between adjacent chip monomers and increases the number of chip monomers that can be set in the chip system, thereby improving the bandwidth performance of the chip system. When the first conductive pattern is similar to the second conductive pattern, and the third conductive pattern is similar to the fourth conductive pattern, the mechanical characteristics of both sides of the first and second sub-boards along the thickness direction are similar, thereby reducing the risk of warping and deformation of the first and second sub-boards during subsequent processing, thereby reducing the difficulty of stacking the first, second, and core boards, and improving the accuracy and reliability of the electrical connections between the first, core, and second sub-boards and other components or substrates, thereby improving the production yield of the chip system. When the second and third vias are filled by electroplating, it is beneficial to improve the wiring density of the multi-layer circuit board and the signal transmission capability of the chip system. At the same time, it is beneficial to improve the electrical conductivity and thermal conductivity of the second and third conductive channels, thereby improving the electrical and thermal performance of the multi-layer circuit board and the chip system. Electroplating via filling is suitable for mass production and has a stable process yield. The substrate material includes but is not limited to glass, ceramic, sapphire, resin material, composite organic material, composite inorganic material, etc. Taking glass as an example, glass substrate replaces organic substrate, reducing signal transmission loss during the operation of the chip system.

[0031] The fifth aspect of the present application provides an electronic device, which includes a device body and a chip system installed on the device body, and the chip system is the above-mentioned chip system. In the present application, the chip system is provided with an intermediate layer, which improves the bandwidth performance of the chip system, thereby improving the working performance of the electronic device. During the processing of the multi-layer circuit board, when the first conductive pattern is similar to the second conductive pattern, and the third conductive pattern is similar to the fourth conductive pattern, the accuracy and reliability of the electrical connection of the first sub-board, the core board, the second sub-board and other components or substrates are improved, thereby improving the working stability of the chip system and the electronic device; when the second channel and the third channel are filled by electroplating, it is beneficial to improve the signal transmission capability of the chip system and the electronic device, and at the same time, it is beneficial to improve the electrical performance and thermal performance of the chip system and the electronic device; and electroplating filling is suitable for mass production, and the process yield is stable, which is beneficial to reducing the cost of electronic equipment. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0033] FIG1 is a cross-sectional view of a local structure of a chip system provided by the present application in one embodiment;

[0034] FIG2 is a cross-sectional view of a multi-layer circuit board provided in the present application in one embodiment;

[0035] FIG3 is a cross-sectional view of another embodiment of the multi-layer circuit board provided by the present application;

[0036] FIG4 is a cross-sectional view of another embodiment of the multi-layer circuit board provided by the present application;

[0037] FIG5(a) to FIG5(d) are process flow charts of a core plate provided by the present application in one embodiment;

[0038] FIG6(a) to FIG6(d) are flowcharts of a process for manufacturing the first sub-board according to an embodiment of the present application;

[0039] FIG7 (a) to FIG7 (d) are process flow charts of the second daughter board provided by the present application in one embodiment;

[0040] 8( a ) to 8 ( j ) are flowcharts of a process for manufacturing the multilayer circuit board in FIG. 3 in one embodiment;

[0041] 9( a ) to 9 ( j ) are flowcharts of a process for manufacturing the multilayer circuit board in FIG. 3 in another embodiment;

[0042] 10( a ) to 10 ( f ) are flowcharts of processing the first sub-board in another embodiment provided by the present application;

[0043] FIG11( a ) to FIG11 ( b ) are flowcharts of the processing of the second daughter board in another embodiment provided by the present application;

[0044] 12( a ) to 12 ( g ) are flowcharts of a process for manufacturing the multilayer circuit board in FIG. 4 in one embodiment;

[0045] 13( a ) to 13 ( h ) are flowcharts of the processing of the multilayer circuit board in FIG. 4 in another embodiment.

[0046] Reference Signs: 01-circuit board; 02-package substrate; 03-interposer; 04-chip unit; 041-first chip; 042-second chip; 043-third chip; 05-first pin; 06-second pin; 07-third pin; 1-core board; 11-core substrate; 111-first phase change channel; 12-first conductive channel; 121-first via; 122-first conductive medium; 2-first daughter board; 21-first conductive pattern; 22-second conductive pattern; 23-first substrate; 231-first surface; 232-second surface; 233-first photoresist; 234-second photoresist; 235-second phase change channel; 236-fifth photoresist; 24-second conductive channel; 241-second via; 242-second conductive medium; 3-second daughter board; 31 - conductive layer; 311 - third conductive pattern; 312 - fourth conductive pattern; 32 - second substrate; 321 - third surface; 322 - fourth surface; 323 - third photoresist; 324 - fourth photoresist; 325 - third phase change channel; 326 - sixth photoresist; 33 - third conductive channel; 331 - third via; 332 - third conductive medium; 4 - first insulating layer; 41 - first conductive portion; 411 - first through-hole; 412 - fourth conductive medium; 5 - second insulating layer; 51 - second conductive portion; 511 - second through-hole; 512 - fifth conductive medium; 6 - metal layer; 7 - third sub-board; 71 - seventh conductive pattern; 72 - eighth conductive pattern; 8 - third insulating layer; 9 - fourth sub-board; 91 - ninth conductive pattern; 92 - tenth conductive pattern; 1a-fourth insulating layer; 1b-substrate; 1b1-conductive path; 1c-conductive pattern; 1d-insulating layer; 1d1-conductive portion. DETAILED DESCRIPTION

[0047] In order to better understand the technical solution of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0048] It should be clear that the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0049] The terms used in the embodiments of the present application are for the purpose of describing specific embodiments only and are not intended to limit the present application. The singular forms "a", "an", "the" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise.

[0050] It should be understood that the term "and / or" as used herein simply describes a relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A alone, A and B together, or B alone. Furthermore, the character " / " in this document generally indicates an "or" relationship between the associated objects.

[0051] A first aspect of an embodiment of the present application provides an electronic device, which includes but is not limited to mobile phones, computers, tablets, headphones, helmets, and other devices capable of signal transmission. The electronic device includes a device body and a chip system installed on the device body. The chip system is used to realize signal transmission between electronic components inside the electronic device and between the electronic device and the outside world.

[0052] As shown in FIG1 , the chip system includes a printed circuit board 01, a package substrate 02, an interposer 03, and a plurality of chip monomers 04 stacked along its thickness direction. The package substrate 02 is mounted on the printed circuit board 01, and the package substrate 02 is electrically connected to the printed circuit board 01 through a first pin 05. The interposer 03 is mounted on the package substrate 02, and the interposer 03 is electrically connected to the package substrate 02 through a second pin 06. The chip monomer 04 is mounted on the interposer 03, and the plurality of chip monomers 04 are electrically connected to the interposer 03 through a third pin 07. As shown in FIG1 , the number of chip monomers 04 is at least two, and the number of chip monomers 04 is at least three. Taking the chip body 04 as an example, the chip body 04 includes a first chip 041, a second chip 042 and a third chip 043. The first chip 041, the second chip 042 and the third chip 043 are all installed on the interposer 03. Since the line width of the redistribution layer (RDL) on the interposer 03 is relatively small, the first chip 041, the second chip 042 and the third chip 043 can be closely arranged on the surface of the interposer 03, reducing the gap between adjacent chip bodies 04 and increasing the number of chip bodies 04 that can be set in the chip system, thereby improving the bandwidth performance of the chip system and further improving the working performance of the electronic device.

[0053] According to a second aspect of an embodiment of the present application, there is provided a multi-layer circuit board, which can be used as a packaging substrate 02 of a chip system, or as a printed circuit board 01 of a chip system. In one embodiment, the stacking structure of the multi-layer circuit board is shown in FIG2 , and the multi-layer circuit board includes a substrate 1b, and along the thickness direction of the substrate 1b, a multi-layer structure of a conductive pattern 1c-insulating layer 1d-conductive pattern 1c is provided on one or both sides of the substrate 1b, and a conductive portion 1d1 made of conductive paste or solder is provided on the insulating layer 1d, and the conductive pattern 1c is electrically connected to the conductive channel 1b1 on the substrate 1b, and the conductive pattern 1c is electrically connected to the conductive pattern 1c on the other side through the conductive portion 1d1 on the insulating layer 1d, that is, the multi-layer circuit board is a multi-layer composite structure of a substrate 1b-conductive pattern 1c-insulating layer 1d-conductive pattern 1c; in another embodiment, the stacking structure of the multi-layer circuit board is As shown in FIG3 , a multilayer circuit board includes multiple substrates 1b stacked along its thickness. Conductive patterns 1c are provided on the substrates 1b. The multilayer circuit board is electrically connected to components mounted on the multilayer circuit board via the conductive patterns 1c. Adjacent substrates 1b are bonded together via insulating layers 1d and electrically connected via conductive paths 1b1 extending along its thickness. In other words, the multilayer circuit board comprises a multilayer composite structure of substrate 1b - conductive pattern 1c - insulating layer 1d - substrate 1b - conductive pattern 1c. In another embodiment, the stacked structure of the multilayer circuit board is shown in FIG4 . The multilayer circuit board can simultaneously include the multilayer composite structures of the above two embodiments to increase the structural flexibility of the multilayer circuit board. For ease of description, the following example uses a multilayer composite structure of substrate 1b - conductive pattern 1c - insulating layer 1d - substrate 1b - conductive pattern 1c. In this case, the insulating layer 1d is an insulating adhesive film used to bond and secure adjacent substrates 1b.

[0054] The thermal expansion coefficient of substrate 1b matches that of interposer 03. This reduces the risk of different degrees of deformation of interposer 03 and substrate 1b due to different thermal expansion coefficients during the processing, installation, transportation, and use of the chip system. This reduces the risk of warping, cracking, or even connection failure between interposer 03 and substrate 1b, thereby improving the operational stability of the chip system. Specifically, the material of substrate 1b includes, but is not limited to, glass, ceramic, sapphire, resin, composite organic materials, composite inorganic materials, etc. It only needs to ensure that the thermal expansion coefficient of substrate 1b matches that of interposer 03. For example, using a glass substrate instead of an organic substrate reduces signal transmission loss during chip system operation.

[0055] In view of the above-mentioned multi-layer circuit board, a third aspect of the embodiments of the present application provides a method for processing the multi-layer circuit board. The method for processing the multi-layer circuit board includes:

[0056] As shown in FIG5(a) to FIG5(d), a core plate 1 is manufactured. As shown in FIG5(d), the core plate 1 includes a first conductive path 12 extending along its thickness direction;

[0057] As shown in Figures 6(a) to 6(d), a first sub-board 2 is manufactured. As shown in Figure 6(d), the first sub-board 2 includes a first substrate 23. The first substrate 23 is provided with a second channel 241 extending along its thickness direction. The first substrate 23 includes a first surface 231 and a second surface 232 arranged opposite to each other along its thickness direction. The first surface 231 is provided with a first conductive pattern 21, and the second surface 232 is provided with a second conductive pattern 22. The difference between the area ratio of the first conductive pattern 21 on the first surface 231 and the area ratio of the second conductive pattern 22 on the second surface 232 is less than or equal to 50%. The difference can be 0%, 5%, 15%, 20%, 25%, 30%, 35%, 40%, 45%, 50%, etc. For example, the first conductive pattern 21 and the second conductive pattern 22 are both ground layers or power layers. The ground layer is used to achieve grounding of the multi-layer circuit board, and the power layer is used to support power distribution and management of electrical components.

[0058] As shown in FIG7(a) to FIG7(d), a second sub-board 3 is manufactured. As shown in FIG7(d), the second sub-board 3 includes a second substrate 32. A conductive layer 31 and a third channel 331 extending along the thickness direction of the second substrate 32 are provided on the second substrate 32. The second substrate 32 includes a third surface 321 and a fourth surface 322 arranged opposite to each other along the thickness direction of the second substrate 32. The third surface 321 is provided with a third conductive pattern 311, and the fourth surface 322 is provided with a fourth conductive pattern 312. The difference between the area ratio of the third conductive pattern 311 on the third surface 321 and the area ratio of the fourth conductive pattern 312 on the fourth surface 322 is less than or equal to 50%. The difference can be 0%, 5%, 15%, 20%, 25%, 30%, 35%, 40%, 45%, 50%, etc. For example, the third conductive pattern 311 and the fourth conductive pattern 312 are both signal layers for arranging wires.

[0059] As shown in FIG8( a), take the first insulating layer 4 and the second insulating layer 5, and stack the first daughter board 2, the first insulating layer 4, the core board 1, the second insulating layer 5 and the second daughter board 3 along the thickness direction of the multilayer circuit board. The first insulating layer 4 is located between the first daughter board 2 and the core board 1, and the second insulating layer 5 is located between the core board 1 and the second daughter board 3. The first conductive pattern 21 is located on the side of the first daughter board 2 away from the core board 1, and the fourth conductive pattern 312 is located on the side of the second daughter board 3 away from the core board 1;

[0060] As shown in FIG8( b ), the first daughter board 2, the first insulating layer 4, the core board 1, the second insulating layer 5 and the second daughter board 3 are pressed and fixed, and the first daughter board 2 and the second daughter board 3 are electrically connected through the first conductive portion 41, the first conductive channel 12 and the second conductive portion 51; the first conductive pattern 21 and the fourth conductive pattern 312 are removed;

[0061] The first sub-board 2 is electroplated to form a fifth conductive pattern on the first surface 231, and the second conductive medium 242 is filled in the second hole 241 to form a second conductive channel 24. The fifth conductive pattern, the second conductive channel 24, and the second conductive pattern 22 constitute a signal transmission line structure. The second sub-board 3 is electroplated to form a sixth conductive pattern on the fourth surface 322, and the third conductive medium 332 is filled in the third hole 331 to form a third conductive channel 33. The sixth conductive pattern, the third conductive channel 33, and the third conductive pattern 311 constitute a signal transmission line structure. The first insulating layer 4 includes a first conductive portion 41, and the second insulating layer 5 includes a second conductive portion 51. The first conductive channel 12 is electrically connected to the second conductive channel 24 via the first conductive portion 41, and the first conductive channel 12 is electrically connected to the third conductive channel 33 via the second conductive portion 51.

[0062] In this embodiment, the difference between the area ratio of the first conductive pattern 21 on the first surface 231 and the area ratio of the second conductive pattern 22 on the second surface 232 is less than or equal to 50%, so that the first conductive pattern 21 is similar to the second conductive pattern 22. Preferably, the first conductive pattern 21 and the second conductive pattern 22 are symmetrically designed with respect to a plane perpendicular to the thickness direction of the multi-layer circuit board, so that the mechanical characteristics of the first sub-board 2 on both sides along the thickness direction are similar, thereby reducing the risk of warping and deformation of the first sub-board 2 during subsequent processing, thereby reducing the difficulty of stacking the first sub-board 2 and the core board 1, and improving the accuracy and reliability of the electrical connection between the first sub-board 2 and the core board 1, and the first sub-board 2 and the components or substrate 1b on the first sub-board 2, thereby improving the working stability and reliability of the chip system and electronic equipment.

[0063] The difference between the area ratio of the third conductive pattern 311 on the third surface 321 and the area ratio of the fourth conductive pattern 312 on the fourth surface 322 is less than or equal to 50%, so that the third conductive pattern 311 is similar to the fourth conductive pattern 312. Preferably, the third conductive pattern 311 and the fourth conductive pattern 312 are symmetrically designed relative to the plane perpendicular to the thickness direction of the multi-layer circuit board, so that the mechanical characteristics of the second sub-board 3 on both sides along the thickness direction are similar, thereby reducing the risk of warping and deformation of the second sub-board 3 during subsequent processing, thereby reducing the difficulty of stacking the second sub-board 3 and the core board 1, and improving the accuracy and reliability of the electrical connection between the second sub-board 3 and the core board 1, and the second sub-board 3 and the components or substrate 1b on the second sub-board 3, thereby improving the production yield of the multi-layer circuit board and the chip system, and further improving the working stability and reliability of the chip system and electronic equipment. During the production of the first daughter board 2, the first conductive pattern 21 is first removed, and then the fifth conductive pattern and second conductive channel 24 are produced. The fifth conductive pattern, second conductive channel 24, and second conductive pattern 22 form a signal transmission line structure, thereby reducing signal transmission losses in the multilayer circuit board. Similarly, during the production of the second daughter board 3, the fourth conductive pattern 312 is first removed, and then the sixth conductive pattern and third conductive channel 33 are produced. The sixth conductive pattern, third conductive channel 33, and third conductive pattern 311 form a signal transmission line structure, thereby reducing signal transmission losses in the multilayer circuit board.

[0064] In this embodiment, there is no particular limitation on the order of the steps of making the core board 1 , the steps of making the first sub-board 2 , and the steps of making the second sub-board 3 . They can be performed simultaneously or sequentially. In addition, the step of filling the second conductive medium 242 in the second channel 241 can be performed before the step of stacking the first sub-board 2, the first insulating layer 4, the core board 1, the second insulating layer 5 and the second sub-board 3, or after the step of pressing and fixing the first sub-board 2, the first insulating layer 4, the core board 1, the second insulating layer 5 and the second sub-board 3. Similarly, the step of filling the third conductive medium 332 in the third channel 331 can be performed before the step of stacking the first sub-board 2, the first insulating layer 4, the core board 1, the second insulating layer 5 and the second sub-board 3, or after the step of pressing and fixing the first sub-board 2, the first insulating layer 4, the core board 1, the second insulating layer 5 and the second sub-board 3. In addition, this embodiment has no special restriction on the order of the steps of filling the second conductive medium 242 in the second channel 241 and filling the third conductive medium 332 in the third channel 331, so as to increase the flexibility of the processing sequence of the multi-layer circuit board, which can be reasonably adjusted according to the actual processing conditions.

[0065] Specifically, during the manufacturing process of the core board 1, the first conductive channel 12 can be formed by drilling a through hole through machining and filling the hole with a conductive medium to reduce processing costs; it can also be formed by laser etching a through hole through machining and filling the hole with a conductive medium to improve processing accuracy.

[0066] In this embodiment, as shown in FIG. 5( a ) to FIG. 5 ( d ), the steps of making the core plate 1 include:

[0067] As shown in FIG5(a), a core substrate 11 is taken and laser induced on the core substrate 11 to form a first phase change channel 111. The extension direction of the first phase change channel 111 is parallel to the thickness direction of the substrate 1b.

[0068] As shown in FIG5(b), the core substrate 11 having a phase change channel is etched to form a first channel 121;

[0069] The first hole 121 is filled with a first conductive medium 122 to form a first conductive channel 12 .

[0070] In this embodiment, the first channels 121 are processed through laser induction and etching, which improves the accuracy of the processing position and processing size of the first channels 121, thereby improving the accuracy of the electrical connection position between the core board 1 and the first and second daughter boards 2 and 3, and further reducing the difficulty of laminating the core board 1, the first and second daughter boards 2 and 3. The thickness of the core substrate 11 is 4-6 times the diameter of the first channels 121, and the thickness of the core substrate 11 is between 100μm and 200μm. This increases the number and density of the first channels 121, thereby improving the bandwidth performance of the multi-layer circuit board.

[0071] In one embodiment, the step of filling the first channel 121 with the first conductive medium 122 includes: placing the first conductive medium 122 into the first channel 121, the first conductive medium 122 is solder or conductive paste, and filling the first channel 121 by melting the solder or conductive paste to simplify the processing method of the first conductive channel 12, thereby reducing the processing cost of the first conductive channel 12.

[0072] In another embodiment, as shown in FIG. 5( c ) and FIG. 5 ( d ), the step of filling the first conductive medium 122 in the first channel 121 includes:

[0073] Sputtering a metal layer 6 on the exposed surface of the core substrate 11 and the sidewalls of the first channel 121;

[0074] Covering the exposed surface of the core substrate 11 with photoresist;

[0075] The core substrate 11 is electroplated and filled with holes to form a first conductive channel 12, with conductor patterns formed at both ends of the first conductive channel 12;

[0076] The photoresist and the metal layer 6 on the surface of the core substrate 11 are removed.

[0077] In this embodiment, the first conductive medium 122 is filled into the first channel 121 by electroplating hole filling, which reduces the required radial size of the first channel 121, which is beneficial to improving the wiring density of the multi-layer circuit board and the chip signal transmission capability, thereby improving the bandwidth performance of the multi-layer circuit board and the chip system. At the same time, it is beneficial to improve the electrical conductivity, thermal conductivity, and flow capacity of the first conductive channel 12, thereby improving the signal transmission efficiency, electrical performance, and thermal performance of the multi-layer circuit board, chip system, and electronic equipment. In addition, electroplating hole filling is suitable for mass production and has a stable process yield. In addition, conductor patterns are formed at both ends of the first conductive channel 12, which can facilitate the control of the end size of the first conductive channel 12 to improve the processing accuracy of the end of the first conductive channel 12, thereby improving the processing yield of the core board 1, wherein the end size of the first conductive channel 12 includes but is not limited to radial size, thickness, etc.

[0078] Specifically, in one embodiment, the steps of manufacturing the first sub-board 2 include:

[0079] Take the first substrate 23, which includes a first surface 231 and a second surface 232 arranged opposite to each other along its thickness direction;

[0080] The first conductive pattern 21 is printed on the first surface 231 , and the second conductive pattern 22 is printed on the second surface 232 .

[0081] In this embodiment, the first conductive pattern 21 and the second conductive pattern 22 are processed by printing, which simplifies the processing method of the first sub-board 2 and helps reduce the processing cost of the first sub-board 2.

[0082] In another embodiment, as shown in FIG6( a ) and FIG6 ( b ), the steps of manufacturing the first sub-board 2 include:

[0083] Take the first substrate 23 and sputter a metal layer 6 on the first surface 231 and the second surface 232;

[0084] The first surface 231 is covered with a first photoresist 233 , and the second surface 232 is covered with a second photoresist 234 ;

[0085] Performing photolithography on the first surface 231 to form a first pattern, and performing photolithography on the second surface 232 to form a second pattern;

[0086] Electroplating the first pattern and the second pattern to form a first conductive pattern 21 and a second conductive pattern 22;

[0087] The first photoresist 233 , the second photoresist 234 and the metal layer 6 are removed.

[0088] In this embodiment, the first conductive pattern 21 and the second conductive pattern 22 are processed by photolithography and electroplating, which increases the accuracy of parameters such as shape, position, and size of the first conductive pattern 21 and the second conductive pattern 22, thereby improving the processing yield of the first sub-board 2.

[0089] More specifically, the step of making the first sub-board 2 also includes: processing the second channel 241 on the first sub-board 2. The step of processing the second channel 241 on the first sub-board 2 can be before the step of processing the first conductive pattern 21 and the second conductive pattern 22, or after the step of processing the first conductive pattern 21 and the second conductive pattern 22.

[0090] In one embodiment, the second channel 241 is formed by drilling a hole on the first sub-board 2 by machining, thereby simplifying the processing method of the first sub-board 2 and reducing the processing cost.

[0091] In another embodiment, as shown in FIG. 6( c ) and FIG. 6( d ), the step of machining the second channel 241 on the first sub-plate 2 includes:

[0092] Laser induction is performed on the first substrate 23 to form a second phase change channel 235, where the extension direction of the second phase change channel 235 is parallel to the thickness direction of the substrate 1b;

[0093] The first substrate 23 having the two phase change channels is etched to form the second channel 241 .

[0094] In this embodiment, the second channels 241 are processed through laser induction and etching, which improves the accuracy of the processing position and processing size of the second channels 241, thereby improving the accuracy of the electrical connection position between the first daughter board 2 and the core board 1, and further reducing the difficulty of laminating the first daughter board 2 and the core board 1. The thickness of the first substrate 23 is 4-6 times the diameter of the second channels 241, and the thickness of the first substrate 23 is between 100μm and 200μm. This increases the number and density of the second channels 241, thereby improving the bandwidth performance of the multi-layer circuit board.

[0095] More specifically, the step of electroplating the first sub-board 2 includes:

[0096] As shown in FIG8( e ), a metal 6 is sputter-plated on the first surface 231 and the sidewalls of the second channel 241 ;

[0097] As shown in FIG8( f ), a fifth photoresist 236 is covered on the first surface 231 ;

[0098] performing photolithography on the first surface 231 to form a fifth pattern;

[0099] As shown in FIG8( g ), the fifth pattern and the second channel 241 are electroplated so that the second conductive medium 242 covers the fifth pattern and fills the second channel 241 to form a fifth conductive pattern and a second conductive channel 24;

[0100] As shown in FIG. 8( h ), the fifth photoresist 236 and the metal layer 6 on the surface of the first substrate 23 are removed.

[0101] In this embodiment, the second conductive medium 242 is filled completely into the second channel 241 through electroplating, reducing the required radial dimension of the second channel 241. This improves the wiring density of the multilayer circuit board and the chip signal transmission capability. It also improves the electrical and thermal conductivity of the second conductive channel 24, thereby enhancing the electrical and thermal performance of the multilayer circuit board, chip system, and electronic device. Furthermore, electroplating is suitable for mass production and provides a stable process yield. The fifth conductive pattern and the second conductive channel 24 are electroplated simultaneously, simplifying the processing operations and cycle time of the first daughter board 2.

[0102] Specifically, in one embodiment, the steps of manufacturing the second sub-board 3 include:

[0103] Take the second substrate 32, which includes a third surface 321 and a fourth surface 322 arranged opposite to each other along its thickness direction;

[0104] A third conductive pattern 311 is printed on the third surface 321 , and a fourth conductive pattern 312 is printed on the fourth surface 322 .

[0105] In this embodiment, the third conductive pattern 311 and the fourth conductive pattern 312 are processed by printing, which simplifies the processing method of the second sub-board 3 and helps reduce the processing cost of the second sub-board 3.

[0106] In another embodiment, as shown in FIG. 7( a ) and FIG. 7 ( b ), the steps of manufacturing the second sub-board 3 include:

[0107] Take the second substrate 32 and sputter a metal layer 6 on the third surface 321 and the fourth surface 322;

[0108] The third surface 321 is covered with a third photoresist 323 , and the fourth surface 322 is covered with a fourth photoresist 324 ;

[0109] Performing photolithography on the third surface 321 to form a third pattern, and performing photolithography on the fourth surface 322 to form a fourth pattern;

[0110] Electroplating the third pattern and the fourth pattern to form a third conductive pattern 311 and a fourth conductive pattern 312;

[0111] The third photoresist 323 , the fourth photoresist 324 and the metal layer 6 are removed.

[0112] In this embodiment, the third conductive pattern 311 and the fourth conductive pattern 312 are processed by photolithography and electroplating, which increases the accuracy of parameters such as shape, position, and size of the third conductive pattern 311 and the fourth conductive pattern 312, thereby improving the processing yield of the second sub-board 3.

[0113] More specifically, the step of making the second sub-board 3 also includes: processing the third channel 331 on the second sub-board 3. The step of processing the third channel 331 on the second sub-board 3 can be before the step of processing the third conductive pattern 311 and the fourth conductive pattern 312, or after the step of processing the third conductive pattern 311 and the fourth conductive pattern 312.

[0114] In one embodiment, a hole is drilled on the second sub-plate 3 by machining to form the third channel 331 , thereby simplifying the processing method of the second sub-plate 3 and reducing the processing cost.

[0115] In another embodiment, as shown in FIG. 7( c ) and FIG. 7 ( d ), the steps of manufacturing the second sub-board 3 include:

[0116] Laser induction is performed on the second substrate 32 to form a third phase change channel 325 , wherein the extension direction of the third phase change channel 325 is parallel to the thickness direction of the substrate 1 b ;

[0117] The second substrate 32 having the three-phase change channel is etched to form a third channel 331 .

[0118] In this embodiment, the third channels 331 are processed through laser induction and etching, which improves the accuracy of the processing position and processing size of the third channels 331, thereby improving the accuracy of the electrical connection position between the second daughter board 3 and the core board 1, and further reducing the difficulty of laminating the second daughter board 3 and the core board 1. The thickness of the second substrate 32 is 4-6 times the diameter of the third channels 331, and the thickness of the second substrate 32 is between 100μm and 200μm. This increases the number and density of the third channels 331, thereby improving the bandwidth performance of the multilayer circuit board.

[0119] More specifically, the step of electroplating the second sub-board 3 includes:

[0120] As shown in FIG8( e ), a metal layer 6 is sputtered on the fourth surface 322 and the sidewalls of the third channel 331 ;

[0121] As shown in FIG8( f ), a sixth photoresist 326 is covered on the fourth surface 322 ;

[0122] performing photolithography on the fourth surface 322 to form a sixth pattern;

[0123] As shown in FIG8( g ), the sixth pattern and the third channel 331 are electroplated so that the third conductive medium 332 covers the sixth pattern and fills the third channel 331 to form a sixth conductive pattern 1c and a third conductive channel 33;

[0124] As shown in FIG. 8( h ), the sixth photoresist 326 and the metal layer 6 are removed.

[0125] In this embodiment, the third conductive medium 332 is filled completely through the third channel 331 via electroplating, reducing the required radial dimension of the third channel 331. This improves the wiring density of the multilayer circuit board and the chip signal transmission capability, thereby enhancing the bandwidth performance of the multilayer circuit board and the chip system. Furthermore, it improves the electrical conductivity, thermal conductivity, and flow capacity of the third conductive channel 33, thereby improving the signal transmission efficiency, electrical performance, and thermal performance of the multilayer circuit board and the chip system. Electroplating is suitable for mass production and provides a stable process yield. The sixth conductive pattern 1c and the third conductive channel 33 are electroplated simultaneously, simplifying the processing operations and cycle time of the first daughter board 2.

[0126] In any of the above embodiments, the first conductive portion 41 on the first insulating layer 4 and the second conductive portion 51 on the second insulating layer 5 are processed by the above-mentioned electroplating hole filling process, that is, as shown in Figures 8(a) to 8(g), the steps of stacking the first sub-board 2, the first insulating layer 4, the core board 1, the second insulating layer 5 and the second sub-board 3 include:

[0127] As shown in FIG8(a), along the thickness direction of the core plate 1, the first insulating layer 4 and the second insulating layer 5 are respectively placed on both sides of the core plate 1, along the thickness direction of the core plate 1, the first sub-plate 2 is placed on the side of the first insulating layer 4 away from the core plate 1, and the second sub-plate 3 is placed on the side of the second insulating layer 5 away from the core plate 1;

[0128] After the steps of pressing and fixing the first sub-board 2, the first insulating layer 4, the core board 1, the second insulating layer 5, and the second sub-board 3, the method for processing the multi-layer circuit board includes:

[0129] As shown in FIG8( d ), a first through hole 411 is processed on the first insulating layer 4, and a second through hole 511 is processed on the second insulating layer 5. The first through hole 411 penetrates the first insulating layer 4 along the thickness direction of the first insulating layer 4, and the second through hole 511 penetrates the second insulating layer 5 along the thickness direction of the second insulating layer 5;

[0130] sputtering a metal layer 6 on the sidewalls of the first through hole 411 and the second through hole 511;

[0131] The first through hole 411 is filled with electroplating to form the first conductive portion 41 , and the second through hole 511 is filled with electroplating to form the second conductive portion 51 .

[0132] In this embodiment, the first conductive part 41 and the second conductive part 51 are processed by electroplating hole filling, which reduces the required radial dimensions of the first conductive part 41 and the second conductive part 51, and is beneficial to improving the wiring density of the multi-layer circuit board and the chip signal transmission capability. At the same time, it is beneficial to improve the electrical conductivity and thermal conductivity of the first conductive part and the second conductive part, and further helps to improve the electrical performance and thermal performance of the multi-layer circuit board, chip system and electronic equipment; electroplating hole filling is suitable for mass production, and the process yield is stable.

[0133] In another embodiment, the first conductive portion 41 on the first insulating layer 4 and the second conductive portion 51 on the second insulating layer 5 are formed by filling the above-mentioned solder or conductive paste, that is, as shown in Figures 9(a) to 9(d), the steps of stacking the first sub-board 2, the first insulating layer 4, the core board 1, the second insulating layer 5 and the second sub-board 3 include:

[0134] As shown in FIG9(a), the first insulating layer 4 and the second insulating layer 5 are respectively placed on both sides of the core plate 1 along the thickness direction of the core plate 1; as shown in FIG9(b), a first through hole 411 is processed on the first insulating layer 4, and a second through hole 511 is processed on the second insulating layer 5. The first through hole 411 penetrates the first insulating layer 4 along the thickness direction of the first insulating layer 4, and the second through hole 511 penetrates the second insulating layer 5 along the thickness direction of the second insulating layer 5;

[0135] As shown in FIG9( c ), the fourth conductive medium 412 is placed in the first through hole 411 , and the fifth conductive medium 512 is placed in the second through hole 511 . The fourth conductive medium 412 is solder or conductive paste, and the fifth conductive medium 512 is solder or conductive paste.

[0136] As shown in FIG9 (d), along the thickness direction of the core board 1, the first sub-board 2 is placed on the side of the first insulating layer 4 away from the core board 1, and the second sub-board 3 is placed on the side of the second insulating layer 5 away from the core board 1.

[0137] In this embodiment, the first through hole 411 and the second through hole 511 are filled by melting solder or conductive paste to simplify the processing method of the first through hole 411 and the second through hole 511, thereby reducing the processing cost of the first insulating layer 4 and the second insulating layer 5, and further reducing the processing cost of the multi-layer circuit board, chip system and electronic equipment.

[0138] When the multilayer circuit board further includes a stacked third sub-board 7, the processing method of the multilayer circuit board further includes:

[0139] According to the above steps of making the first sub-board 2 and the second sub-board 3, a third sub-board 7 as shown in FIG8(i) is made. The third sub-board 7 includes a third substrate, the third substrate includes a fourth channel extending along the thickness direction of the third sub-board 7, and the third sub-board 7 includes a fifth surface and a sixth surface arranged opposite to each other along the thickness direction of the third sub-board 7. A seventh conductive pattern 71 is provided on the fifth surface, and an eighth conductive pattern 72 is provided on the sixth surface. The difference between the area ratio of the seventh conductive pattern 71 on the fifth surface and the area ratio of the eighth conductive pattern 72 on the sixth surface is less than or equal to 50%. The difference can be 0%, 5%, 15%, 20%, 25%, 30%, 35%, 40%, 45%, 50%, etc. For example, the seventh conductive pattern 71 and the eighth conductive pattern 72 are both ground layers or power layers, that is, the seventh conductive pattern 71 and the eighth conductive pattern 72 are similar. Preferably, the seventh conductive pattern 71 and the eighth conductive pattern 72 are designed symmetrically with respect to a plane perpendicular to the thickness direction of the multilayer circuit board.

[0140] The third insulating layer 8 is placed along the thickness direction of the second sub-board 3, and the third insulating layer 8 and the third sub-board 7 are placed on the side of the second sub-board 3 away from the core board 1, and the third insulating layer 8 is located between the second sub-board 3 and the third sub-board 7;

[0141] Press and fix the second sub-board 3 and the third sub-board 7;

[0142] removing the eighth conductive pattern 72;

[0143] Electroplating the third sub-board 7 to form an eleventh conductive pattern on the sixth surface and fill the fourth channel with a sixth conductive medium to form a fourth conductive channel 1b1. The eleventh conductive pattern, the fourth conductive channel 1b1, and the seventh conductive pattern 71 form a signal transmission line structure. The third sub-board 7 is electrically connected to the second sub-board 3 via the fourth conductive channel 1b1 and the third conductive portion on the third insulating layer 8.

[0144] And / or, when the multilayer circuit board further includes a fourth sub-board 9 that is stacked, the method for processing the multilayer circuit board further includes:

[0145] According to the above steps of making the first sub-board 2 and the second sub-board 3, a fourth sub-board 9 as shown in FIG8(i) is made. The fourth sub-board 9 comprises a fourth substrate. The fourth substrate includes a fifth channel extending along the thickness direction thereof. The fourth substrate includes a seventh surface and an eighth surface arranged opposite to each other along the thickness direction thereof. A ninth conductive pattern 91 is provided on the seventh surface, and a tenth conductive pattern 92 is provided on the eighth surface. The difference between the area ratio of the ninth conductive pattern 91 on the seventh surface and the area ratio of the tenth conductive pattern 92 on the eighth surface is less than or equal to 50%. The difference can be 0%, 5%, 15%, 20%, 25%, 30%, 35%, 40%, 45%, 50%, etc. For example, both are signal layers, that is, the ninth conductive pattern 91 and the tenth conductive pattern 92 are similar. Preferably, the ninth conductive pattern 91 and the tenth conductive pattern 92 are designed symmetrically with respect to a plane perpendicular to the thickness direction of the multilayer circuit board.

[0146] Take the fourth insulating layer 1a and place the fourth insulating layer 1a and the fourth sub-board 9 on the side of the first sub-board 2 away from the core board 1 along the thickness direction of the first sub-board 2, with the fourth insulating layer 1a located between the fourth sub-board 9 and the first sub-board 2;

[0147] Press and fix the fourth sub-board 9 and the first sub-board 2;

[0148] removing the ninth conductive pattern 91;

[0149] The fourth sub-board 9 is electroplated to form a twelfth conductive pattern on the seventh surface, and the fifth channel is filled with the seventh conductive medium to form a fifth conductive channel 1b1. The twelfth conductive pattern, the fifth conductive channel 1b1, and the tenth conductive pattern 92 constitute a signal transmission line structure. The fourth sub-board 9 is electrically connected to the first sub-board 2 through the fifth conductive channel 1b1, the fourth conductive portion on the fourth insulating layer 1a, and the second conductive channel 24.

[0150] In this embodiment, the multilayer circuit board also includes a third sub-board 7 and a fourth sub-board 9, increasing the number of layers of substrate 1b within the multilayer circuit board to meet the signal transmission requirements of higher-performance chip systems. The difference between the area ratios of the seventh conductive pattern 71 and the eighth conductive pattern 72, and the area ratios of the ninth conductive pattern 91 and the tenth conductive pattern 92, is less than or equal to 50%. This ensures that the mechanical characteristics of the third and fourth sub-boards 9 are similar, reducing the risk of deformation of the third and fourth sub-boards 7 and 9.

[0151] In addition, the multi-layer circuit board may also have a fifth sub-board, a sixth sub-board, a seventh sub-board, etc. The present application does not impose any special limitation on the number of stacked layers of the substrate 1b on the multi-layer circuit board.

[0152] The core substrate 11, first substrate 23, second substrate 32, third substrate, fourth substrate and other substrates 1b in any of the above embodiments are all processed from a plate-like substrate, that is, the plate-like substrate is cut so that the length, width and thickness dimensions of the cut plate-like substrate meet the use requirements of the multi-layer circuit board.

[0153] In summary, in one embodiment, a method for processing a multilayer circuit board includes:

[0154] As shown in FIG5(a), a core substrate 11 is taken and laser induced on the core substrate 11 to form a first phase change channel 111. The extension direction of the first phase change channel 111 is parallel to the thickness direction of the substrate 1b.

[0155] As shown in FIG5(b), the core substrate 11 having a phase change channel is etched to form a first channel 121;

[0156] As shown in FIG5(c), the metal 6 is sputter-plated on the exposed surface of the core substrate 11 and the sidewalls of the first channel 121;

[0157] Covering the exposed surface of the core substrate 11 with photoresist;

[0158] As shown in FIG5(d), the core substrate 11 is electroplated and filled to form a first conductive channel 12, and conductor patterns are formed at both ends of the first conductive channel 12;

[0159] removing the photoresist and the metal layer 6 on the surface of the core substrate 11;

[0160] As shown in FIG6( a ), a first substrate 23 is taken, and a metal layer 6 is sputtered on the first surface 231 and the second surface 232 ;

[0161] The first surface 231 is covered with a first photoresist 233 , and the second surface 232 is covered with a second photoresist 234 ;

[0162] Performing photolithography on the first surface 231 to form a first pattern, and performing photolithography on the second surface to form a second pattern;

[0163] Electroplating the first pattern and the second pattern to form a first conductive pattern 21 and a second conductive pattern 22, wherein the difference between the area occupied by the first conductive pattern 21 on the first surface 231 and the area occupied by the second conductive pattern 22 on the second surface 232 is less than or equal to 50%;

[0164] removing the first photoresist 233 , the second photoresist 234 and the metal layer 6 ;

[0165] As shown in FIG6(c), the first substrate 23 is laser induced to form a second phase change channel 235, and the extension direction of the second phase change channel 235 is parallel to the thickness direction of the substrate 1b;

[0166] As shown in FIG6(d), the first substrate 23 having two phase change channels is etched to form a second channel 241;

[0167] As shown in FIG7( a ), a second substrate 32 is taken, and a metal layer 6 is electroplated on the third surface 321 and the fourth surface 322 ;

[0168] The third surface 321 is covered with a third photoresist 323 , and the fourth surface 322 is covered with a fourth photoresist 324 ;

[0169] Performing photolithography on the third surface 321 to form a third pattern, and performing photolithography on the second surface 232 to form a fourth pattern;

[0170] Electroplating the third pattern and the fourth pattern to form a third conductive pattern 311 and a fourth conductive pattern 312, wherein the difference between the area ratio of the third conductive pattern 311 on the third surface 321 and the area ratio of the fourth conductive pattern 312 on the fourth surface 322 is less than or equal to 50%;

[0171] removing the third photoresist 323 , the fourth photoresist 324 and the metal layer 6 ;

[0172] As shown in FIG. 7( c ), the second substrate 32 is laser-induced to form a third phase change channel 325 , and the extension direction of the third phase change channel 325 is parallel to the thickness direction of the substrate 1 b ;

[0173] As shown in FIG. 7( d ), the second substrate 32 having the three-phase change channel is etched to form a third channel 331 ;

[0174] As shown in FIG8( a), take the first insulating layer 4 and the second insulating layer 5, and stack the first daughter board 2, the first insulating layer 4, the core board 1, the second insulating layer 5 and the second daughter board 3 along the thickness direction of the multilayer circuit board. The first insulating layer 4 is located between the first daughter board 2 and the core board 1, and the second insulating layer 5 is located between the core board 1 and the second daughter board 3. The first conductive pattern 21 is located on the side of the first daughter board 2 away from the core board 1, and the fourth conductive pattern 312 is located on the side of the second daughter board 3 away from the core board 1;

[0175] As shown in FIG8( b ), the first sub-board 2 , the first insulating layer 4 , the core board 1 , the second insulating layer 5 and the second sub-board 3 are pressed and fixed;

[0176] As shown in FIG8( c ), the first conductive pattern 21 and the fourth conductive pattern 312 are removed;

[0177] As shown in FIG8( d ), a first through hole 411 is processed on the first insulating layer 4, and a second through hole 511 is processed on the second insulating layer 5. The first through hole 411 penetrates the first insulating layer 4 along the thickness direction of the first insulating layer 4, and the second through hole 511 penetrates the second insulating layer 5 along the thickness direction of the second insulating layer 5;

[0178] As shown in FIG8( e ), a metal layer 6 is sputtered on the sidewalls of the first surface 231 , the second channel 241 , the first through hole 411 , the fourth surface 322 , the third channel 331 and the second through hole 511 ;

[0179] As shown in FIG. 8( f ), the first surface 231 is covered with a fifth photoresist 236 , and the fourth surface 322 is covered with a sixth photoresist 326 ;

[0180] Performing photolithography on the first surface 231 to form a fifth pattern, and performing photolithography on the fourth surface 322 to form a sixth pattern;

[0181] As shown in Figure 8(g), the first sub-board 2 and the first insulating layer 4 are electroplated to form a fifth conductive pattern, a second conductive channel 24 and a first conductive portion 41. The fifth conductive pattern, the second conductive channel 24 and the second conductive pattern 22 form a signal transmission line structure; the second sub-board 3 and the second insulating layer 5 are electroplated to form a sixth conductive pattern, a third conductive channel 33 and a second conductive portion 51. The sixth conductive pattern, the third conductive channel 33 and the third conductive pattern 311 form a signal transmission line structure; the fifth conductive pattern, the second conductive channel 24 and the second conductive pattern 22 form a signal transmission line structure, and the sixth conductive pattern, the third conductive channel 33 and the third conductive pattern 311 form a signal transmission line structure.

[0182] As shown in FIG8(h), the fifth photoresist 236, the sixth photoresist 326 and the metal layer 6 are removed;

[0183] A third sub-board 7 and a fourth sub-board 9 are manufactured according to the steps of manufacturing the first sub-board 2 and the second sub-board 3. The third sub-board 7 includes a fourth channel extending along the thickness direction of the third sub-board 7. The third sub-board 7 includes a seventh conductive pattern 71 and an eighth conductive pattern 72 arranged opposite to each other along the thickness direction of the third sub-board 7. The difference between the area ratio of the seventh conductive pattern 71 on the fifth surface and the area ratio of the eighth conductive pattern 72 on the sixth surface is less than or equal to 50%. The fourth sub-board 9 includes a fifth channel extending along the thickness direction of the fourth sub-board 9. The fourth sub-board 9 includes a ninth conductive pattern 91 and a tenth conductive pattern 92 arranged opposite to each other along the thickness direction of the fourth sub-board 9. The difference between the area ratio of the ninth conductive pattern 91 on the seventh surface and the area ratio of the tenth conductive pattern 92 on the eighth surface is less than or equal to 50%.

[0184] As shown in FIG8(i), take the third insulating layer 8, and place the third insulating layer 8 and the third sub-board 7 on the side of the second sub-board 3 away from the core board 1 along the thickness direction of the second sub-board 3, and the third insulating layer 8 is located between the second sub-board 3 and the third sub-board 7;

[0185] Take the fourth insulating layer 1a and place the fourth insulating layer 1a and the fourth sub-board 9 on the side of the first sub-board 2 away from the core board 1 along the thickness direction of the first sub-board 2, with the fourth insulating layer 1a located between the fourth sub-board 9 and the first sub-board 2;

[0186] Press and fix the third sub-board 7, the third insulating layer 8 and the second sub-board 3, and press and fix the fourth sub-board 9, the fourth insulating layer 1a and the first sub-board 2;

[0187] The steps as shown in FIG. 8( c ) to FIG. 8( h ) are followed to form a multi-layer circuit board having five layers of substrates 1 b stacked together as shown in FIG. 8( j ).

[0188] In summary, in another embodiment, a method for processing a multi-layer circuit board includes:

[0189] As shown in FIG5(a), a core substrate 11 is taken and laser induced on the core substrate 11 to form a first phase change channel 111. The extension direction of the first phase change channel 111 is parallel to the thickness direction of the substrate 1b.

[0190] As shown in FIG5(b), the core substrate 11 having a phase change channel is etched to form a first channel 121;

[0191] As shown in FIG5( c ), a metal layer 6 is sputtered on the exposed surface of the core substrate 11 and the sidewalls of the first channel 121 ;

[0192] Covering the exposed surface of the core substrate 11 with photoresist;

[0193] As shown in FIG5(d), the core substrate 11 is electroplated and filled to form a first conductive channel 12, and conductor patterns are formed at both ends of the first conductive channel 12;

[0194] removing the photoresist and the metal layer 6 on the surface of the core substrate 11;

[0195] As shown in FIG6( a ), a first substrate 23 is taken, and a metal layer 6 is sputtered on the first surface 231 and the second surface 232 ;

[0196] The first surface 231 is covered with a first photoresist 233 , and the second surface 232 is covered with a second photoresist 234 ;

[0197] Performing photolithography on the first surface 231 to form a first pattern, and performing photolithography on the second surface to form a second pattern;

[0198] Electroplating the first pattern and the second pattern to form a first conductive pattern 21 and a second conductive pattern 22, wherein the difference between the area occupied by the first conductive pattern 21 on the first surface 231 and the area occupied by the second conductive pattern 22 on the second surface 232 is less than or equal to 50%;

[0199] removing the first photoresist 233 , the second photoresist 234 and the metal layer 6 ;

[0200] As shown in FIG6(c), the first substrate 23 is laser induced to form a second phase change channel 235, and the extension direction of the second phase change channel 235 is parallel to the thickness direction of the substrate 1b;

[0201] As shown in FIG6(d), the first substrate 23 having two phase change channels is etched to form a second channel 241;

[0202] As shown in FIG7( a ), a second substrate 32 is taken, and a metal layer 6 is sputtered on the third surface 321 and the fourth surface 322 ;

[0203] The third surface 321 is covered with a third photoresist 323 , and the fourth surface 322 is covered with a fourth photoresist 324 ;

[0204] Performing photolithography on the third surface 321 to form a third pattern, and performing photolithography on the second surface 232 to form a fourth pattern;

[0205] Electroplating the third pattern and the fourth pattern to form a third conductive pattern 311 and a fourth conductive pattern 312, wherein the difference between the area ratio of the third conductive pattern 311 on the third surface 321 and the area ratio of the fourth conductive pattern 312 on the fourth surface 322 is less than or equal to 50%;

[0206] removing the third photoresist 323 , the fourth photoresist 324 and the metal layer 6 ;

[0207] As shown in FIG. 7( c ), the second substrate 32 is laser-induced to form a third phase change channel 325 , and the extension direction of the third phase change channel 325 is parallel to the thickness direction of the substrate 1 b ;

[0208] As shown in FIG. 7( d ), the second substrate 32 having the three-phase change channel is etched to form a third channel 331 ;

[0209] As shown in FIG9 (a), take the first insulating layer 4 and the second insulating layer 5, and stack the first insulating layer 4, the core board 1 and the second insulating layer 5 along the thickness direction of the multilayer circuit;

[0210] As shown in FIG9( b ), a first through hole 411 is processed on the first insulating layer 4 and a second through hole 511 is processed on the second insulating layer 5 ;

[0211] As shown in FIG9( c ), solder or conductive paste is placed in the first through hole 411 and the second through hole 511 ;

[0212] As shown in Figure 9 (d), the first sub-board 2 is placed on the side of the first insulating layer 4 away from the core board 1, and the second sub-board 3 is placed on the side of the second insulating layer 5 away from the core board 1, and the first sub-board 2, the first insulating layer 4, the core board 1, the second insulating layer 5 and the second sub-board 3 are pressed and fixed;

[0213] As shown in FIG. 9( e ), the first conductive pattern 21 and the fourth conductive pattern 312 are removed;

[0214] As shown in FIG9( f ), a metal layer 6 is sputtered on the first surface 231 , the second channel 241 , the fourth surface 322 and the sidewalls of the third channel 331 ;

[0215] As shown in FIG. 9( g ), the first surface 231 is covered with a fifth photoresist 236 , and the fourth surface 322 is covered with a sixth photoresist 326 ;

[0216] Performing photolithography on the first surface 231 to form a fifth pattern, and performing photolithography on the fourth surface 322 to form a sixth pattern;

[0217] As shown in Figure 9(h), the first sub-board 2 is electroplated to form a fifth conductive pattern and a second conductive channel 24. The fifth conductive pattern, the second conductive channel 24, and the second conductive pattern 22 constitute a signal transmission line structure. The second sub-board 3 is electroplated to form a sixth conductive pattern and a third conductive channel 33. The sixth conductive pattern, the third conductive channel 33, and the second conductive pattern 22 constitute a signal transmission line structure.

[0218] removing the fifth photoresist 236 , the sixth photoresist 326 and the metal layer 6 ;

[0219] A third sub-board 7 and a fourth sub-board 9 are manufactured according to the steps of manufacturing the first sub-board 2 and the second sub-board 3. The third sub-board 7 includes a fourth channel extending along the thickness direction of the third sub-board 7. The third sub-board 7 includes a seventh conductive pattern 71 and an eighth conductive pattern 72 arranged opposite to each other along the thickness direction of the third sub-board 7. The difference between the area ratio of the seventh conductive pattern 71 on the fifth surface and the area ratio of the eighth conductive pattern 72 on the sixth surface is less than or equal to 50%. The fourth sub-board 9 includes a fifth channel extending along the thickness direction of the fourth sub-board 9. The fourth sub-board 9 includes a ninth conductive pattern 91 and a tenth conductive pattern 92 arranged opposite to each other along the thickness direction of the fourth sub-board 9. The difference between the area ratio of the ninth conductive pattern 91 on the seventh surface and the area ratio of the tenth conductive pattern 92 on the eighth surface is less than or equal to 50%.

[0220] As shown in FIG9 (i), take the third insulating layer 8, along the thickness direction of the second sub-board 3, place the third insulating layer 8 and the third sub-board 7 on the side of the second sub-board 3 away from the core board 1, and the third insulating layer 8 is located between the second sub-board 3 and the third sub-board 7;

[0221] Take the fourth insulating layer 1a and place the fourth insulating layer 1a and the fourth sub-board 9 on the side of the first sub-board 2 away from the core board 1 along the thickness direction of the first sub-board 2, with the fourth insulating layer 1a located between the fourth sub-board 9 and the first sub-board 2;

[0222] The steps as shown in FIG. 9( b ) to FIG. 9( h ) are followed to form a multi-layer circuit board having five layers of substrates 1 b stacked together as shown in FIG. 9( j ).

[0223] A fourth aspect of an embodiment of the present application provides a method for processing a multi-layer circuit board. The method for processing a multi-layer circuit board includes:

[0224] A first sub-board 2 is fabricated as shown in FIG6(a) to FIG6(d), or as shown in FIG10(a) to FIG10(d). A first substrate 23 is prepared, and a first conductive pattern 21, a second conductive pattern 22, and a second channel 241 are processed on the first substrate 23. The second channel 241 extends in a direction parallel to the thickness of the first substrate 23. The first substrate 23 includes a first surface 231 and a second surface 232 that are oppositely disposed along its thickness. The first conductive pattern 21 is located on the first surface 231, and the second conductive pattern 22 is located on the second surface 232.

[0225] The second sub-plate 3 is manufactured as shown in FIG7(c) and FIG7(d), or as shown in FIG11(a) to FIG11(b), by taking a second substrate 32 and processing a third channel 331 on the second substrate 32. The extension direction of the third channel 331 is parallel to the thickness direction of the second substrate 32.

[0226] As shown in FIG8( a ), or as shown in FIG12( a ), take the first insulating layer 4 , and stack the second substrate 32 and the first insulating layer 4 on the first substrate 23 along the thickness direction of the first substrate 23 , with the first insulating layer 4 being located between the second substrate 32 and the first substrate 23 ;

[0227] As shown in FIG8( b ), or as shown in FIG12( b ), the second substrate 32 , the first insulating layer 4 and the first substrate 23 are pressed and fixed;

[0228] Before the step of stacking the second substrate 32 and the first insulating layer 4 on the first substrate 23, or after the step of pressing and fixing the second substrate 32, the first insulating layer 4 and the first substrate 23, the method for processing the multilayer circuit board includes:

[0229] As shown in FIG. 8( g ), or as shown in FIG. 10( e ) and FIG. 10( f ), the first substrate 23 is electroplated and filled with holes so that the second conductive medium 242 fills the second channel 241 to form a second conductive channel 24 ;

[0230] Before the step of stacking the second substrate 32 and the first insulating layer 4 on the first substrate 23, or after the step of pressing and fixing the second substrate 32, the first insulating layer 4 and the first substrate 23, the method for processing the multilayer circuit board includes:

[0231] As shown in FIG7(a) and FIG7(b), or as shown in FIG12(e) and FIG12(f), a conductive layer 31 is processed on the second substrate 32 along the thickness direction of the second substrate 32, and at least a portion of the conductive layer 31 is located on a side of the second substrate 32 away from the first substrate 23;

[0232] As shown in Figure 8(g), or as shown in Figures 12(e) and 12(f), the second substrate 32 includes a third surface 321 and a fourth surface 322 arranged opposite to each other along its own thickness direction, and the second substrate 32 is electroplated to form a sixth conductive pattern on the fourth surface 322, and the third channel 331 is filled with a third conductive medium 332 to form a third conductive channel 33; the first insulating layer 4 includes a first conductive portion 41, and the sixth conductive pattern is electrically connected to the second conductive channel 24 through the third conductive channel 33 and the first conductive portion 41.

[0233] In this embodiment, the second hole 241 and the third hole 331 are filled by electroplating, which reduces the required radial dimensions of the second hole 241 and the third hole 331, thereby improving the wiring density of the multi-layer circuit board and the chip signal transmission capability. At the same time, it is beneficial to improve the electrical conductivity and thermal conductivity of the second conductive channel 24 and the third conductive channel 33, thereby improving the electrical and thermal properties of the multi-layer circuit board, the chip system and the electronic equipment. Electroplating filling is suitable for mass production, and the process yield is stable, which is beneficial to reducing the processing cost of the chip system and electronic equipment.

[0234] In this embodiment, there is no special limitation on the order of the steps of making the first sub-board 2 and the steps of making the second sub-board 3 , and they can be performed simultaneously or sequentially.

[0235] When the difference between the area ratio of the first conductive pattern 21 on the first surface 231 and the area ratio of the second conductive pattern 22 on the second surface 232 is less than or equal to 50%, that is, when the first conductive pattern 21 is similar to the second conductive pattern 22, the processing method of the multilayer circuit board includes:

[0236] As shown in FIG5(a) to FIG5(d), a core plate 1 is manufactured. As shown in FIG5(d), the core plate 1 includes a first conductive path 12 extending along its thickness direction;

[0237] As shown in FIG6( a ) and FIG6 ( b ), a first conductive pattern 21 and a second conductive pattern 22 are processed on a first substrate 23. The difference between the area ratio of the first conductive pattern 21 on the first surface 231 and the area ratio of the second conductive pattern 22 on the second surface 232 is less than or equal to 50%. The difference can be 0%, 5%, 15%, 20%, 25%, 30%, 35%, 40%, 45%, 50%, etc. For example, the first conductive pattern 21 and the second conductive pattern 22 are both ground layers or power layers. The ground layer is used to achieve grounding of the multi-layer circuit board, and the power layer is used to support power distribution and management of electrical components.

[0238] Processing a second channel 241 on the first substrate 23 having the first conductive pattern 21 and the second conductive pattern 22;

[0239] The steps of stacking the second substrate 32 and the first insulating layer 4 on the first substrate 23 include:

[0240] As shown in FIG8( a), take the second insulating layer 5, and stack the first sub-board 2, the first insulating layer 4, the core board 1, the second insulating layer 5, and the second sub-board 3 along the thickness direction of the multilayer circuit board. The first insulating layer 4 is located between the first sub-board 2 and the core board 1, and the second insulating layer 5 is located between the core board 1 and the second sub-board 3. The first conductive pattern 21 is located on the side of the first sub-board 2 away from the core board 1, and the fourth conductive pattern 312 is located on the side of the second sub-board 3 away from the core board 1;

[0241] The steps of pressing and fixing the second substrate 32, the first insulating layer 4 and the first substrate 23 include:

[0242] As shown in FIG8( b ), the first sub-board 2 , the first insulating layer 4 , the core board 1 , the second insulating layer 5 and the second sub-board 3 are pressed and fixed;

[0243] After the steps of pressing and fixing the first sub-board 2, the first insulating layer 4, the core board 1, the second insulating layer 5, and the second sub-board 3, the method for processing the multi-layer circuit board includes:

[0244] removing the first conductive pattern 21;

[0245] Electroplating the first sub-board 2 to form a fifth conductive pattern on the first surface 231 and filling the second hole 241 with a second conductive medium 242 to form a second conductive channel 24. The fifth conductive pattern, the second conductive channel 24, and the second conductive pattern 22 form a signal transmission line structure.

[0246] The second insulating layer 5 includes a second conductive portion 51. After the step of electroplating the first sub-board 2 to form the fifth conductive pattern and the second conductive path 24, the fifth conductive pattern, the second conductive pattern 22, and the sixth conductive pattern are electrically connected through the second conductive path 24, the first conductive portion 41, the first conductive path 12, the second conductive portion 51, and the third conductive path 33.

[0247] In this embodiment, the difference between the area ratio of the first conductive pattern 21 on the first surface 231 and the area ratio of the second conductive pattern 22 on the second surface 232 is less than or equal to 50%, making the first conductive pattern 21 similar to the second conductive pattern 22. Preferably, the first conductive pattern 21 and the second conductive pattern 22 are designed symmetrically with respect to a plane perpendicular to the thickness direction of the multilayer circuit board, so that the mechanical characteristics of the two sides of the first sub-board 2 along the thickness direction are similar, thereby reducing the risk of warping and deformation of the first sub-board 2 during subsequent processing, thereby reducing the difficulty of laminating the first sub-board 2 with the core board 1, and improving the accuracy and reliability of the electrical connection between the first sub-board 2 and the core board 1, and between the first sub-board 2 and the components or substrate 1b on the first sub-board 2, thereby facilitating improved operational stability and reliability of chip systems and electronic devices. Specifically, during the process of manufacturing the first sub-board 2, the first conductive pattern 21 is first removed, and then the fifth conductive pattern and the second conductive path 24 are formed. The fifth conductive pattern, the second conductive path 24, and the second conductive pattern 22 form a signal transmission line structure, thereby reducing signal transmission loss in the multilayer circuit board.

[0248] In this embodiment, there is no particular limitation on the order of the steps of making the core board 1 , the steps of making the first sub-board 2 , and the steps of making the second sub-board 3 . They can be performed simultaneously or sequentially.

[0249] Specifically, during the manufacturing process of the core board 1, the first conductive channel 12 can be formed by drilling a through hole through machining and filling the hole with a conductive medium to reduce processing costs; it can also be formed by laser etching a through hole through machining and filling the hole with a conductive medium to improve processing accuracy.

[0250] In this embodiment, as shown in FIG. 5( a ) to FIG. 5 ( d ), the steps of making the core plate 1 include:

[0251] As shown in FIG5(a), a core substrate 11 is taken and laser induced on the core substrate 11 to form a first phase change channel 111. The extension direction of the first phase change channel 111 is parallel to the thickness direction of the substrate 1b.

[0252] As shown in FIG5(b), the core substrate 11 having a phase change channel is etched to form a first channel 121;

[0253] The first hole 121 is filled with a first conductive medium 122 to form a first conductive channel 12 .

[0254] In this embodiment, the first channels 121 are processed through laser induction and laser etching, which improves the accuracy of the processing position and processing size of the first channels 121, thereby improving the accuracy of the electrical connection position between the core board 1 and the first sub-board 2 and the second sub-board 3, and further reducing the difficulty of laminating the core board 1, the first sub-board 2 and the second sub-board 3. The thickness of the core substrate 11 is 4-6 times the diameter of the first channels 121, and the thickness of the core substrate 11 is between 100μm and 200μm. This increases the number and density of the first channels 121, thereby improving the bandwidth performance of the multi-layer circuit board.

[0255] In one embodiment, the step of filling the first channel 121 with the first conductive medium 122 includes: placing the first conductive medium 122 into the first channel 121, the first conductive medium 122 is solder or conductive paste, and filling the first channel 121 by melting the solder or conductive paste to simplify the processing method of the first conductive channel 12, thereby reducing the processing cost of the first conductive channel 12.

[0256] In another embodiment, as shown in FIG. 5( c ) and FIG. 5 ( d ), the step of filling the first conductive medium 122 in the first channel 121 includes:

[0257] Sputtering a metal layer 6 on the exposed surface of the core substrate 11 and the sidewalls of the first channel 121;

[0258] Covering the exposed surface of the core substrate 11 with photoresist;

[0259] The core substrate 11 is electroplated and filled with holes to form a first conductive channel 12, with conductor patterns formed at both ends of the first conductive channel 12;

[0260] The photoresist and the metal layer 6 on the surface of the core substrate 11 are removed.

[0261] In this embodiment, the first conductive medium 122 is filled into the first channel 121 by electroplating, which reduces the required radial dimension of the first channel 121, which is beneficial to improving the wiring density of the multi-layer circuit board and the chip signal transmission capability. At the same time, it is beneficial to improve the electrical conductivity and thermal conductivity of the first conductive channel 12, thereby improving the electrical performance and thermal performance of the multi-layer circuit board, chip system and electronic equipment. Electroplating filling is suitable for mass production and has a stable process yield. In addition, conductor patterns are formed at both ends of the first conductive channel 12, which can facilitate the control of the end size of the first conductive channel 12 to improve the processing accuracy of the end of the first conductive channel 12, thereby improving the processing yield of the core board 1, wherein the end size of the first conductive channel 12 includes but is not limited to radial size, thickness, etc.

[0262] Specifically, before the step of machining the third via 331 on the second substrate 32, the method for machining the multilayer circuit board includes:

[0263] Take the second substrate 32, which includes a third surface 321 and a fourth surface 322 arranged opposite to each other along its thickness direction, process a third conductive pattern 311 on the third surface 321, and process a fourth conductive pattern 312 on the fourth surface 322 to form a second sub-board 3. In one embodiment, the third conductive pattern 311 and the fourth conductive pattern 312 can form a signal transmission line structure through a conductive medium. For example, the third conductive pattern 311 and the fourth conductive pattern 312 are asymmetrically designed, with one of the third conductive pattern 311 and the fourth conductive pattern 312 being a signal layer and the other being a ground layer or a power layer. In another embodiment, the difference between the area ratio of the third conductive pattern 311 on the third surface 321 and the area ratio of the fourth conductive pattern 312 on the fourth surface 322 is less than or equal to 50%. Specifically, the difference can be 0%, 5%, 15%, 20%, 25%, 30%, 35%, 40%, 45%, 50%, etc. For example, the third conductive pattern 311 and the fourth conductive pattern 312 are both signal layers, that is, the third conductive pattern 311 and the fourth conductive pattern 312 are similar. Preferably, the third conductive pattern 311 and the fourth conductive pattern 312 are symmetrically designed with respect to a plane perpendicular to the thickness direction of the multilayer circuit board.

[0264] When the difference between the area ratio of the third conductive pattern 311 on the third surface 321 and the area ratio of the fourth conductive pattern 312 on the fourth surface 322 is less than or equal to 50%, after the steps of pressing and fixing the first sub-board 2, the first insulating layer 4, the core board 1, the second insulating layer 5, and the second sub-board 3, the fourth conductive pattern 312 is located on a side of the second substrate 32 away from the first substrate 23, and the processing method of the multilayer circuit board includes:

[0265] The fourth conductive pattern 312 is removed.

[0266] In this embodiment, the third conductive pattern 311 is similar to the fourth conductive pattern 312, so that the mechanical characteristics of both sides of the second sub-board 3 along the thickness direction are similar, thereby reducing the risk of warping and deformation of the second sub-board 3 during subsequent processing, thereby reducing the difficulty of stacking the second sub-board 3 with the core board 1, and improving the accuracy and reliability of the electrical connection between the second sub-board 3 and the core board 1, and between the second sub-board 3 and the components or substrate 1b on the second sub-board 3, thereby improving the production yield of multi-layer circuit boards, chip systems, and electronic devices. During the process of the second sub-board 3, the fourth conductive pattern 312 is first removed, and then the sixth conductive pattern and the third conductive channel 33 are formed, so that the sixth conductive pattern, the third conductive channel 33, and the third conductive pattern 311 form a signal transmission line structure, reducing signal transmission loss in the multi-layer circuit board.

[0267] Specifically, in one embodiment, the steps of manufacturing the first sub-board 2 include:

[0268] Take the first substrate 23, which includes a first surface 231 and a second surface 232 arranged opposite to each other along its thickness direction;

[0269] The first conductive pattern 21 is printed on the first surface 231 , and the second conductive pattern 22 is printed on the second surface 232 .

[0270] In this embodiment, the first conductive pattern 21 and the second conductive pattern 22 are processed by printing, which simplifies the processing method of the first sub-board 2 and helps reduce the processing cost of the first sub-board 2.

[0271] In another embodiment, as shown in FIG6( a ) and FIG6 ( b ), the steps of manufacturing the first sub-board 2 include:

[0272] Take the first substrate 23 and sputter a metal layer 6 on the first surface 231 and the second surface 232;

[0273] The first surface 231 is covered with a first photoresist 233 , and the second surface 232 is covered with a second photoresist 234 ;

[0274] Performing photolithography on the first surface 231 to form a first pattern, and performing photolithography on the second surface 232 to form a second pattern;

[0275] Electroplating the first pattern and the second pattern to form a first conductive pattern 21 and a second conductive pattern 22;

[0276] The first photoresist 233 , the second photoresist 234 and the metal layer 6 are removed.

[0277] In this embodiment, the first conductive pattern 21 and the second conductive pattern 22 are processed by photolithography and electroplating, which increases the accuracy of parameters such as shape, position, and size of the first conductive pattern 21 and the second conductive pattern 22, thereby improving the processing yield of the first sub-board 2.

[0278] More specifically, the step of making the first sub-board 2 also includes: processing the second channel 241 on the first sub-board 2. The step of processing the second channel 241 on the first sub-board 2 can be before the step of processing the first conductive pattern 21 and the second conductive pattern 22, or after the step of processing the first conductive pattern 21 and the second conductive pattern 22.

[0279] In one embodiment, the second channel 241 is formed by drilling a hole on the first sub-board 2 by machining, thereby simplifying the processing method of the first sub-board 2 and reducing the processing cost.

[0280] In another embodiment, as shown in FIG. 6( c ) and FIG. 6( d ), the step of machining the second channel 241 on the first sub-plate 2 includes:

[0281] Laser induction is performed on the first substrate 23 to form a second phase change channel 235, where the extension direction of the second phase change channel 235 is parallel to the thickness direction of the substrate 1b;

[0282] The first substrate 23 having the two phase change channels is etched to form the second channel 241 .

[0283] In this embodiment, the second channels 241 are processed through laser induction and etching, which improves the accuracy of the processing position and processing size of the second channels 241, thereby improving the accuracy of the electrical connection position between the first daughter board 2 and the core board 1, and further reducing the difficulty of laminating the first daughter board 2 and the core board 1. The thickness of the first substrate 23 is 4-6 times the diameter of the second channels 241, and the thickness of the first substrate 23 is between 100μm and 200μm. This increases the number and density of the second channels 241, thereby improving the bandwidth performance of the multi-layer circuit board.

[0284] More specifically, the step of electroplating the first sub-board 2 includes:

[0285] As shown in FIG8( e ), a metal layer 6 is sputtered on the first surface 231 and the sidewalls of the second channel 241 ;

[0286] As shown in FIG8( f ), a fifth photoresist 236 is covered on the first surface 231 ;

[0287] performing photolithography on the first surface 231 to form a fifth pattern;

[0288] As shown in FIG8( g ), the fifth pattern and the second channel 241 are electroplated so that the second conductive medium 242 covers the fifth pattern and fills the second channel 241 to form a fifth conductive pattern and a second conductive channel 24;

[0289] As shown in FIG. 8( h ), the fifth photoresist 236 and the metal layer 6 on the surface of the first substrate 23 are removed.

[0290] In this embodiment, the second conductive medium 242 is filled completely through the second channel 241 via electroplating. This reduces the required radial dimension of the second channel 241, improving the wiring density of the multilayer circuit board and the chip's signal transmission capabilities. This also helps improve the electrical and thermal conductivity of the second conductive channel 24, thereby enhancing the electrical and thermal performance of the multilayer circuit board and chip system. Electroplating is suitable for mass production and provides a stable process yield. The fifth conductive pattern and the second conductive channel 24 are electroplated simultaneously, simplifying the processing operations and cycle time of the first daughter board 2.

[0291] Specifically, in one embodiment, the steps of manufacturing the second sub-board 3 include:

[0292] Take the second substrate 32, which includes a third surface 321 and a fourth surface 322 arranged opposite to each other along its thickness direction;

[0293] A third conductive pattern 311 is printed on the third surface 321 , and a fourth conductive pattern 312 is printed on the fourth surface 322 .

[0294] In this embodiment, the third conductive pattern 311 and the fourth conductive pattern 312 are processed by printing, which simplifies the processing method of the second sub-board 3 and helps reduce the processing cost of the second sub-board 3.

[0295] In another embodiment, as shown in FIG. 7( a ) and FIG. 7 ( b ), the steps of manufacturing the second sub-board 3 include:

[0296] Take the second substrate 32 and sputter a metal layer 6 on the third surface 321 and the fourth surface 322;

[0297] The third surface 321 is covered with a third photoresist 323 , and the fourth surface 322 is covered with a fourth photoresist 324 ;

[0298] Performing photolithography on the third surface 321 to form a third pattern, and performing photolithography on the fourth surface 322 to form a fourth pattern;

[0299] Electroplating the third pattern and the fourth pattern to form a third conductive pattern 311 and a fourth conductive pattern 312;

[0300] The third photoresist 323 , the fourth photoresist 324 and the metal layer 6 are removed.

[0301] In this embodiment, the third conductive pattern 311 and the fourth conductive pattern 312 are processed by photolithography and electroplating, which increases the accuracy of parameters such as shape, position, and size of the third conductive pattern 311 and the fourth conductive pattern 312, thereby improving the processing yield of the second sub-board 3.

[0302] More specifically, the step of making the second sub-board 3 also includes: processing the third channel 331 on the second sub-board 3. The step of processing the third channel 331 on the second sub-board 3 can be before the step of processing the third conductive pattern 311 and the fourth conductive pattern 312, or after the step of processing the third conductive pattern 311 and the fourth conductive pattern 312.

[0303] In one embodiment, a hole is drilled on the second sub-plate 3 by machining to form the third channel 331 , thereby simplifying the processing method of the second sub-plate 3 and reducing the processing cost.

[0304] In another embodiment, as shown in FIG. 7( c ) and FIG. 7 ( d ), the steps of manufacturing the second sub-board 3 include:

[0305] Laser induction is performed on the second substrate 32 to form a third phase change channel 325 , wherein the extension direction of the third phase change channel 325 is parallel to the thickness direction of the substrate 1 b ;

[0306] The second substrate 32 having the three-phase change channel is etched to form a third channel 331 .

[0307] In this embodiment, the third channels 331 are processed through laser induction and etching, which improves the accuracy of the processing position and processing size of the third channels 331, thereby improving the accuracy of the electrical connection position between the second daughter board 3 and the core board 1, and further reducing the difficulty of laminating the second daughter board 3 and the core board 1. The thickness of the second substrate 32 is 4-6 times the diameter of the third channels 331, and the thickness of the second substrate 32 is between 100μm and 200μm. This increases the number and density of the third channels 331, thereby improving the bandwidth performance of the multilayer circuit board.

[0308] More specifically, the step of electroplating the second sub-board 3 includes:

[0309] As shown in FIG8( e ), a metal layer 6 is sputtered on the fourth surface 322 and the sidewalls of the third channel 331 ;

[0310] As shown in FIG8( f ), a sixth photoresist 326 is covered on the fourth surface 322 ;

[0311] performing photolithography on the fourth surface 322 to form a sixth pattern;

[0312] As shown in FIG8( g ), the sixth pattern and the third channel 331 are electroplated so that the third conductive medium 332 covers the sixth pattern and fills the third channel 331 to form a sixth conductive pattern 1c and a third conductive channel 33;

[0313] As shown in FIG. 8( h ), the sixth photoresist 326 and the metal layer 6 are removed.

[0314] In this embodiment, the third conductive medium 332 is filled completely through the third via 331 via electroplating. This reduces the required radial dimension of the third via 331, thereby improving the wiring density of the multilayer circuit board and the signal transmission capability of the chip. It also improves the electrical and thermal conductivity of the third conductive channel 33, thereby enhancing the electrical and thermal performance of the multilayer circuit board and chip system. Electroplating via filling is suitable for mass production and provides a stable process yield. The sixth conductive pattern 1c and the third conductive channel 33 are electroplated simultaneously, simplifying the processing operations and cycle time of the first daughter board 2.

[0315] When the multilayer circuit board further includes a stacked third sub-board 7, the processing method of the multilayer circuit board further includes:

[0316] According to the above steps of making the first sub-board 2 and the second sub-board 3, a third sub-board 7 as shown in FIG8(i) is made. The third sub-board 7 includes a third substrate, the third substrate includes a fourth channel extending along the thickness direction of the third sub-board 7, and the third sub-board 7 includes a fifth surface and a sixth surface arranged opposite to each other along the thickness direction of the third sub-board 7. A seventh conductive pattern 71 is provided on the fifth surface, and an eighth conductive pattern 72 is provided on the sixth surface. The difference between the area ratio of the seventh conductive pattern 71 on the fifth surface and the area ratio of the eighth conductive pattern 72 on the sixth surface is less than or equal to 50%. The difference can be 0%, 5%, 15%, 20%, 25%, 30%, 35%, 40%, 45%, 50%, etc. For example, the seventh conductive pattern 71 and the eighth conductive pattern 72 are both ground layers or power layers, that is, the seventh conductive pattern 71 and the eighth conductive pattern 72 are similar. Preferably, the seventh conductive pattern 71 and the eighth conductive pattern 72 are designed symmetrically with respect to a plane perpendicular to the thickness direction of the multilayer circuit board.

[0317] Take the third insulating layer 8 and place the third insulating layer 8 and the third sub-board 7 along the thickness direction of the second sub-board 3 on the side of the second sub-board 3 away from the core board 1, with the third insulating layer 8 located between the second sub-board 3 and the third sub-board 7;

[0318] Press and fix the second sub-board 3 and the third sub-board 7;

[0319] removing the eighth conductive pattern 72;

[0320] Electroplating the third sub-board 7 to form an eleventh conductive pattern on the sixth surface and fill the fourth channel with a sixth conductive medium to form a fourth conductive channel 1b1. The eleventh conductive pattern, the fourth conductive channel 1b1, and the seventh conductive pattern 71 form a signal transmission line structure. The third sub-board 7 is electrically connected to the second sub-board 3 via the fourth conductive channel 1b1 and the third conductive portion on the third insulating layer 8.

[0321] And / or, when the multilayer circuit board further includes a fourth sub-board 9 that is stacked, the method for processing the multilayer circuit board further includes:

[0322] According to the above steps of making the first sub-board 2 and the second sub-board 3, a fourth sub-board 9 as shown in FIG8(i) is made. The fourth sub-board 9 comprises a fourth substrate. The fourth substrate includes a fifth channel extending along its thickness direction. The fourth substrate includes a seventh surface and an eighth surface arranged opposite to each other along its thickness direction. A ninth conductive pattern 91 is provided on the seventh surface, and a tenth conductive pattern 92 is provided on the eighth surface. The difference between the area ratio of the ninth conductive pattern 91 on the seventh surface and the area ratio of the tenth conductive pattern 92 on the eighth surface is less than or equal to 50%. The difference can be 0%, 5%, 15%, 20%, 25%, 30%, 35%, 40%, 45%, 50%, etc. For example, the ninth conductive pattern 91 and the tenth conductive pattern 92 are both signal layers, that is, the ninth conductive pattern 91 and the tenth conductive pattern 92 are similar. Preferably, the ninth conductive pattern 91 and the tenth conductive pattern 92 are designed symmetrically with respect to a plane perpendicular to the thickness direction of the multilayer circuit board.

[0323] Take the fourth insulating layer 1a and place the fourth insulating layer 1a and the fourth sub-board 9 on the side of the first sub-board 2 away from the core board 1 along the thickness direction of the first sub-board 2, with the fourth insulating layer 1a located between the fourth sub-board 9 and the first sub-board 2;

[0324] Press and fix the fourth sub-board 9 and the first sub-board 2;

[0325] removing the ninth conductive pattern 91;

[0326] The fourth sub-board 9 is electroplated to form an eleventh conductive pattern on the seventh surface, and the fifth channel is filled with the seventh conductive medium to form a fifth conductive channel 1b1. The fourth sub-board 9 is electrically connected to the first sub-board 2 through the fifth conductive channel 1b1, the fourth conductive portion on the fourth insulating layer 1a, and the second conductive channel 24.

[0327] In this embodiment, the multilayer circuit board also includes a third sub-board 7 and a fourth sub-board 9, increasing the number of substrate layers within the multilayer circuit board to meet the signal transmission requirements of higher-performance chip systems. The difference between the area ratios of the seventh conductive pattern 71 and the eighth conductive pattern 72, and the area ratios of the ninth conductive pattern 91 and the tenth conductive pattern 92, is less than or equal to 50%. This ensures that the mechanical characteristics of the third and fourth sub-boards 9 are similar, reducing the risk of deformation of the third and fourth sub-boards 9.

[0328] In addition, the multi-layer circuit board may also have a fifth sub-board, a sixth sub-board, a seventh sub-board, etc. The present application does not impose any special limitation on the number of stacked layers of the substrate 1b on the multi-layer circuit board.

[0329] When the first conductive pattern 21, the second conductive pattern 22, and the second conductive channel 24 form a signal transmission line structure, for example, when the first conductive pattern 21 is a signal layer and the second conductive pattern 22 is a ground layer or a power layer, the first conductive pattern 21 and the second conductive pattern 22 are asymmetrically designed, and the step of plating and filling the first substrate 23 to form the second conductive channel 24 is performed simultaneously with the step of processing the first conductive pattern 21 and the second conductive pattern 22 on the first substrate 23;

[0330] The steps of processing the first conductive pattern 21, the second conductive pattern 22 and the second conductive path 24 on the first substrate 23 include:

[0331] Processing a second channel 241 on the first substrate 23;

[0332] sputtering a metal layer 6 on the first surface 231 and the second surface 232 of the first substrate 23 having the second hole 241;

[0333] The first surface 231 is covered with a first photoresist 233 , and the second surface 232 is covered with a second photoresist 234 ;

[0334] Performing photolithography on the first surface 231 to form a first pattern, and performing photolithography on the second surface to form a second pattern;

[0335] The first pattern, the second pattern, and the second channel 241 are electroplated to form a first conductive pattern 21 , a second conductive pattern 22 , and a second conductive channel 24 .

[0336] In an embodiment of the present application, the first conductive pattern 21, the second conductive channel 24 and the second conductive pattern 22 can constitute a signal transmission line structure, thereby eliminating the above-mentioned core board 1, which is beneficial to reducing the overall thickness of the multi-layer circuit board, and is beneficial to reducing the overall size of the chip system, improving the space utilization of the device body, and thus helping to reduce the overall size of the electronic device and reduce the cost of the electronic device.

[0337] When the multilayer circuit board further includes a stacked third sub-board 7, the processing method of the multilayer circuit board further includes:

[0338] Producing a third sub-plate 7, wherein the third sub-plate 7 includes a fourth channel extending along the thickness direction of the third sub-plate 7;

[0339] After the steps of pressing and fixing the second substrate 32, the first insulating layer 4, and the first substrate 23, the method for processing the multilayer circuit board includes:

[0340] Take the third insulating layer 8 and place the third insulating layer 8 and the third sub-board 7 on the side of the second substrate 32 away from the first substrate 23 along the thickness direction of the second substrate 32, with the third insulating layer 8 located between the third sub-board 7 and the second substrate 32;

[0341] Press and fix the third sub-board 7 and the second substrate 32;

[0342] The third sub-board 7 is electroplated so that an eleventh conductive pattern is formed on a surface of the third sub-board 7 facing away from the second substrate 32, and a fourth conductive medium is filled in the fourth channel to form a fourth conductive path. The third insulating layer 8 includes a third conductive portion, and the eleventh conductive pattern is electrically connected to the sixth conductive pattern via the fourth conductive path and the third conductive portion.

[0343] And / or, when the multilayer circuit board further includes a fourth sub-board 9 that is stacked, the method for processing the multilayer circuit board further includes:

[0344] A fourth sub-plate 9 is manufactured, wherein the fourth sub-plate 9 includes a fifth channel extending along the thickness direction thereof;

[0345] After the steps of pressing and fixing the second substrate 32, the first insulating layer 4, and the first substrate 23, the method for processing the multilayer circuit board includes:

[0346] Take the fourth insulating layer 1a, and place the fourth sub-board 9 and the fourth insulating layer 1a along the thickness direction of the first substrate 23 on the side of the first substrate 23 away from the second substrate 32, with the fourth insulating layer 1a located between the first substrate 23 and the fourth sub-board 9;

[0347] Pressing and fixing the first substrate 23 and the fourth sub-board 9;

[0348] The fourth sub-board 9 is electroplated so that a twelfth conductive pattern is formed on the surface of the fourth sub-board 9 away from the first substrate 23, and a fifth conductive medium is filled in the fifth channel to form a fifth conductive channel; the fourth insulating layer 1a includes a fourth conductive portion, and the twelfth conductive pattern is electrically connected to the first conductive pattern 21 through the fifth conductive channel and the fourth conductive portion.

[0349] In this embodiment, the multi-layer circuit board also includes a third sub-board 7 and a fourth sub-board 9, which increases the number of stacking layers of the substrate 1b on the multi-layer circuit board, so as to improve the bandwidth performance of the multi-layer circuit board, so that the multi-layer circuit board can be applied to chip systems with higher bandwidth requirements, thereby improving the applicability scenarios of the multi-layer circuit board and helping to improve the working performance of the chip system.

[0350] In addition, the multi-layer circuit board may also have a fifth sub-board, a sixth sub-board, a seventh sub-board, etc. The present application does not impose any special limitation on the number of stacked layers of the substrate 1b on the multi-layer circuit board.

[0351] In any of the above embodiments, the first conductive portion 41 on the first insulating layer 4 and the second conductive portion 51 on the second insulating layer 5 are processed by the above-mentioned electroplating hole filling process, that is, as shown in Figures 8(a) to 8(g), the steps of stacking the first sub-board 2, the first insulating layer 4, the core board 1, the second insulating layer 5 and the second sub-board 3 include:

[0352] As shown in FIG8(a), along the thickness direction of the core plate 1, the first insulating layer 4 and the second insulating layer 5 are respectively placed on both sides of the core plate 1, along the thickness direction of the core plate 1, the first sub-plate 2 is placed on the side of the first insulating layer 4 away from the core plate 1, and the second sub-plate 3 is placed on the side of the second insulating layer 5 away from the core plate 1;

[0353] After the steps of pressing and fixing the first sub-board 2, the first insulating layer 4, the core board 1, the second insulating layer 5, and the second sub-board 3, the method for processing the multi-layer circuit board includes:

[0354] As shown in FIG8( d ), a first through hole 411 is processed on the first insulating layer 4, and a second through hole 511 is processed on the second insulating layer 5. The first through hole 411 penetrates the first insulating layer 4 along the thickness direction of the first insulating layer 4, and the second through hole 511 penetrates the second insulating layer 5 along the thickness direction of the second insulating layer 5;

[0355] Sputtering the metal layer 6 on the sidewalls of the first through hole 411 and the second through hole 511;

[0356] The first through hole 411 is filled with electroplating to form the first conductive portion 41 , and the second through hole 511 is filled with electroplating to form the second conductive portion 51 .

[0357] In this embodiment, the first conductive part 41 and the second conductive part 51 are processed by electroplating hole filling, which reduces the required radial dimensions of the first conductive part 41 and the second conductive part 51, and is beneficial to improving the wiring density of the multi-layer circuit board and the chip signal transmission capability. At the same time, it is beneficial to improve the electrical conductivity and thermal conductivity of the first conductive part and the second conductive part, and further helps to improve the electrical performance and thermal performance of the multi-layer circuit board, chip system and electronic equipment; electroplating hole filling is suitable for mass production, and the process yield is stable.

[0358] In another embodiment, the first conductive portion 41 on the first insulating layer 4 and the second conductive portion 51 on the second insulating layer 5 are formed by filling the above-mentioned solder or conductive paste, that is, as shown in Figures 9(a) to 9(d), the steps of stacking the first sub-board 2, the first insulating layer 4, the core board 1, the second insulating layer 5 and the second sub-board 3 include:

[0359] As shown in FIG9 (a), along the thickness direction of the core plate 1, the first insulating layer 4 and the second insulating layer 5 are respectively placed on both sides of the core plate 1;

[0360] As shown in FIG9( b ), a first through hole 411 is processed on the first insulating layer 4, and a second through hole 511 is processed on the second insulating layer 5. The first through hole 411 penetrates the first insulating layer 4 along the thickness direction of the first insulating layer 4, and the second through hole 511 penetrates the second insulating layer 5 along the thickness direction of the second insulating layer 5;

[0361] As shown in FIG9( c ), the fourth conductive medium 412 is placed in the first through hole 411 , and the fifth conductive medium 512 is placed in the second through hole 511 . The fourth conductive medium 412 is solder or conductive paste, and the fifth conductive medium 512 is solder or conductive paste.

[0362] As shown in FIG9 (d), along the thickness direction of the core board 1, the first sub-board 2 is placed on the side of the first insulating layer 4 away from the core board 1, and the second sub-board 3 is placed on the side of the second insulating layer 5 away from the core board 1.

[0363] In this embodiment, the first through hole 411 and the second through hole 511 are filled by melting solder or conductive paste to simplify the processing method of the first through hole 411 and the second through hole 511, thereby reducing the processing cost of the first insulating layer 4 and the second insulating layer 5, and further reducing the processing cost of the multi-layer circuit board and the chip system.

[0364] The core substrate 11, first substrate 23, second substrate 32, third substrate, fourth substrate and other substrates 1b in any of the above embodiments are all processed from a plate-like substrate, that is, the plate-like substrate is cut so that the length, width and thickness dimensions of the cut plate-like substrate meet the use requirements of the multi-layer circuit board.

[0365] In summary, in one embodiment, a method for processing a multilayer circuit board includes:

[0366] As shown in FIG5(a), a core substrate 11 is taken and laser induced on the core substrate 11 to form a first phase change channel 111. The extension direction of the first phase change channel 111 is parallel to the thickness direction of the substrate 1b.

[0367] As shown in FIG5(b), the core substrate 11 having a phase change channel is etched to form a first channel 121;

[0368] As shown in FIG5(c), the metal layer 6 is sputtered on the exposed surface of the core substrate 11 and the sidewalls of the first channel 121;

[0369] Covering the exposed surface of the core substrate 11 with photoresist;

[0370] As shown in FIG5(d), the core substrate 11 is electroplated and filled to form a first conductive channel 12, and conductor patterns are formed at both ends of the first conductive channel 12;

[0371] removing the photoresist and the metal layer 6 on the surface of the core substrate 11;

[0372] As shown in FIG6( a ), a first substrate 23 is taken, and a metal layer 6 is covered on the first surface 231 and the second surface 232 ;

[0373] The first surface 231 is covered with a first photoresist 233 , and the second surface 232 is covered with a second photoresist 234 ;

[0374] Performing photolithography on the first surface 231 to form a first pattern, and performing photolithography on the second surface to form a second pattern;

[0375] Electroplating the first pattern and the second pattern to form a first conductive pattern 21 and a second conductive pattern 22, wherein the difference between the area occupied by the first conductive pattern 21 on the first surface 231 and the area occupied by the second conductive pattern 22 on the second surface 232 is less than or equal to 50%;

[0376] removing the first photoresist 233 , the second photoresist 234 and the metal layer 6 ;

[0377] As shown in FIG6(c), the first substrate 23 is laser induced to form a second phase change channel 235, and the extension direction of the second phase change channel 235 is parallel to the thickness direction of the substrate 1b;

[0378] As shown in FIG6(d), the first substrate 23 having two phase change channels is etched to form a second channel 241;

[0379] As shown in FIG7( a ), a second substrate 32 is taken, and a metal layer 6 is sputtered on the third surface 321 and the fourth surface 322 ;

[0380] The third surface 321 is covered with a third photoresist 323 , and the fourth surface 322 is covered with a fourth photoresist 324 ;

[0381] Performing photolithography on the third surface 321 to form a third pattern, and performing photolithography on the second surface 232 to form a fourth pattern;

[0382] Electroplating the third pattern and the fourth pattern to form a third conductive pattern 311 and a fourth conductive pattern 312. The third conductive pattern 311 and the fourth conductive pattern 312 are both signal layers. That is, the third conductive pattern 311 is similar to the fourth conductive pattern 312. The difference between the area ratio of the third conductive pattern 311 on the third surface 321 and the area ratio of the fourth conductive pattern 312 on the fourth surface 322 is less than or equal to 50%.

[0383] removing the third photoresist 323 , the fourth photoresist 324 and the metal layer 6 ;

[0384] As shown in FIG. 7( c ), the second substrate 32 is laser-induced to form a third phase change channel 325 , and the extension direction of the third phase change channel 325 is parallel to the thickness direction of the substrate 1 b ;

[0385] As shown in FIG. 7( d ), the second substrate 32 having the three-phase change channel is etched to form a third channel 331 ;

[0386] As shown in FIG8( a), take the first insulating layer 4 and the second insulating layer 5, and stack the first daughter board 2, the first insulating layer 4, the core board 1, the second insulating layer 5 and the second daughter board 3 along the thickness direction of the multilayer circuit board. The first insulating layer 4 is located between the first daughter board 2 and the core board 1, and the second insulating layer 5 is located between the core board 1 and the second daughter board 3. The first conductive pattern 21 is located on the side of the first daughter board 2 away from the core board 1, and the fourth conductive pattern 312 is located on the side of the second daughter board 3 away from the core board 1;

[0387] As shown in FIG8( b ), the first sub-board 2 , the first insulating layer 4 , the core board 1 , the second insulating layer 5 and the second sub-board 3 are pressed and fixed;

[0388] As shown in FIG8( c ), the first conductive pattern 21 and the fourth conductive pattern 312 are removed;

[0389] As shown in FIG8( d ), a first through hole 411 is processed on the first insulating layer 4, and a second through hole 511 is processed on the second insulating layer 5. The first through hole 411 penetrates the first insulating layer 4 along the thickness direction of the first insulating layer 4, and the second through hole 511 penetrates the second insulating layer 5 along the thickness direction of the second insulating layer 5;

[0390] As shown in FIG8(e), the metal layer 6 is sputtered on the first surface 231, the second channel 241, the first through-hole 411, the fourth surface 322, the third channel 331 and the sidewall of the second through-hole 511;

[0391] As shown in FIG. 8( f ), the first surface 231 is covered with a fifth photoresist 236 , and the fourth surface 322 is covered with a sixth photoresist 326 ;

[0392] Performing photolithography on the first surface 231 to form a fifth pattern, and performing photolithography on the fourth surface 322 to form a sixth pattern;

[0393] As shown in Figure 8(g), the first sub-board 2 and the first insulating layer 4 are electroplated to form a fifth conductive pattern, a second conductive channel 24 and a first conductive portion 41. The fifth conductive pattern, the second conductive channel 24 and the second conductive pattern 22 constitute a signal transmission line structure; the second sub-board 3 and the second insulating layer 5 are electroplated to form a sixth conductive pattern, a third conductive channel 33 and a second conductive portion 51. The sixth conductive pattern, the third conductive channel 33 and the third conductive pattern 311 constitute a signal transmission line structure.

[0394] As shown in FIG8(h), the fifth photoresist 236, the sixth photoresist 326 and the metal layer 6 are removed;

[0395] A third sub-board 7 and a fourth sub-board 9 are manufactured according to the steps of manufacturing the first sub-board 2 and the second sub-board 3. The third sub-board 7 includes a fourth channel extending along the thickness direction of the third sub-board 7. The third sub-board 7 includes a seventh conductive pattern 71 and an eighth conductive pattern 72 arranged opposite to each other along the thickness direction of the third sub-board 7. The difference between the area ratio of the seventh conductive pattern 71 on the fifth surface and the area ratio of the eighth conductive pattern 72 on the sixth surface is less than or equal to 50%. The fourth sub-board 9 includes a fifth channel extending along the thickness direction of the fourth sub-board 9. The fourth sub-board 9 includes a ninth conductive pattern 91 and a tenth conductive pattern 92 arranged opposite to each other along the thickness direction of the fourth sub-board 9. The difference between the area ratio of the ninth conductive pattern 91 on the seventh surface and the area ratio of the tenth conductive pattern 92 on the eighth surface is less than or equal to 50%.

[0396] As shown in FIG8(i), take the third insulating layer 8, and place the third insulating layer 8 and the third sub-board 7 on the side of the second sub-board 3 away from the core board 1 along the thickness direction of the second sub-board 3, and the third insulating layer 8 is located between the second sub-board 3 and the third sub-board 7;

[0397] Take the fourth insulating layer 1a and place the fourth insulating layer 1a and the fourth sub-board 9 on the side of the first sub-board 2 away from the core board 1 along the thickness direction of the first sub-board 2, with the fourth insulating layer 1a located between the fourth sub-board 9 and the first sub-board 2;

[0398] Press and fix the third sub-board 7, the third insulating layer 8 and the second sub-board 3, and press and fix the fourth sub-board 9, the fourth insulating layer 1a and the first sub-board 2;

[0399] The steps as shown in FIG. 8( c ) to FIG. 8( h ) are followed to form a multi-layer circuit board having five layers of substrates 1 b stacked together as shown in FIG. 8( j ).

[0400] In summary, in another embodiment, a method for processing a multi-layer circuit board includes:

[0401] As shown in FIG5(a), a core substrate 11 is taken and laser induced on the core substrate 11 to form a first phase change channel 111. The extension direction of the first phase change channel 111 is parallel to the thickness direction of the substrate 1b.

[0402] As shown in FIG5(b), the core substrate 11 having a phase change channel is etched to form a first channel 121;

[0403] As shown in FIG5(c), the metal layer 6 is sputtered on the exposed surface of the core substrate 11 and the sidewalls of the first channel 121;

[0404] Covering the exposed surface of the core substrate 11 with photoresist;

[0405] As shown in FIG5(d), the core substrate 11 is electroplated and filled to form a first conductive channel 12, and conductor patterns are formed at both ends of the first conductive channel 12;

[0406] removing the photoresist and the metal layer 6 on the surface of the core substrate 11;

[0407] As shown in FIG6( a ), a first substrate 23 is taken, and a metal layer 6 is sputtered on the first surface 231 and the second surface 232 ;

[0408] The first surface 231 is covered with a first photoresist 233 , and the second surface 232 is covered with a second photoresist 234 ;

[0409] Performing photolithography on the first surface 231 to form a first pattern, and performing photolithography on the second surface to form a second pattern;

[0410] Electroplating the first pattern and the second pattern to form a first conductive pattern 21 and a second conductive pattern 22, wherein the difference between the area occupied by the first conductive pattern 21 on the first surface 231 and the area occupied by the second conductive pattern 22 on the second surface 232 is less than or equal to 50%;

[0411] removing the first photoresist 233 , the second photoresist 234 and the metal layer 6 ;

[0412] As shown in FIG6(c), the first substrate 23 is laser induced to form a second phase change channel 235, and the extension direction of the second phase change channel 235 is parallel to the thickness direction of the substrate 1b;

[0413] As shown in FIG6(d), the first substrate 23 having two phase change channels is etched to form a second channel 241;

[0414] As shown in FIG7( a ), a second substrate 32 is taken, and a metal layer 6 is sputtered on the third surface 321 and the fourth surface 322 ;

[0415] The third surface 321 is covered with a third photoresist 323 , and the fourth surface 322 is covered with a fourth photoresist 324 ;

[0416] Performing photolithography on the third surface 321 to form a third pattern, and performing photolithography on the second surface 232 to form a fourth pattern;

[0417] Electroplating the third pattern and the fourth pattern to form a third conductive pattern 311 and a fourth conductive pattern 312, wherein the difference between the area ratio of the third conductive pattern 311 on the third surface 321 and the area ratio of the fourth conductive pattern 312 on the fourth surface 322 is less than or equal to 50%;

[0418] removing the third photoresist 323 , the fourth photoresist 324 and the metal layer 6 ;

[0419] As shown in FIG. 7( c ), the second substrate 32 is laser-induced to form a third phase change channel 325 , and the extension direction of the third phase change channel 325 is parallel to the thickness direction of the substrate 1 b ;

[0420] As shown in FIG. 7( d ), the second substrate 32 having the three-phase change channel is etched to form a third channel 331 ;

[0421] As shown in FIG9 (a), take the first insulating layer 4 and the second insulating layer 5, and stack the first insulating layer 4, the core board 1 and the second insulating layer 5 along the thickness direction of the multilayer circuit board;

[0422] As shown in FIG9( b ), a first through hole 411 is processed on the first insulating layer 4 and a second through hole 511 is processed on the second insulating layer 5 ;

[0423] As shown in FIG9( c ), solder or conductive paste is placed in the first through hole 411 and the second through hole 511 ;

[0424] As shown in Figure 9 (d), the first sub-board 2 is placed on the side of the first insulating layer 4 away from the core board 1, and the second sub-board 3 is placed on the side of the second insulating layer 5 away from the core board 1, and the first sub-board 2, the first insulating layer 4, the core board 1, the second insulating layer 5 and the second sub-board 3 are pressed and fixed;

[0425] As shown in FIG. 9( e ), the first conductive pattern 21 and the fourth conductive pattern 312 are removed;

[0426] As shown in FIG9( f ), the metal layer 6 is sputtered on the first surface 231 , the second channel 241 , the fourth surface 322 and the sidewall of the third channel 331 ;

[0427] As shown in FIG. 9( g ), the first surface 231 is covered with a fifth photoresist 236 , and the fourth surface 322 is covered with a sixth photoresist 326 ;

[0428] Performing photolithography on the first surface 231 to form a fifth pattern, and performing photolithography on the fourth surface 322 to form a sixth pattern;

[0429] As shown in Figure 9(h), the first sub-board 2 is electroplated to form a fifth conductive pattern and a second conductive channel 24. The fifth conductive pattern, the second conductive channel 24, and the second conductive pattern 22 constitute a signal transmission line structure. The second sub-board 3 is electroplated to form a sixth conductive pattern and a third conductive channel 33. The sixth conductive pattern, the third conductive channel 33, and the third conductive pattern 311 constitute a signal transmission line structure.

[0430] removing the fifth photoresist 236 , the sixth photoresist 326 and the metal layer 6 ;

[0431] A third sub-board 7 and a fourth sub-board 9 are manufactured according to the steps of manufacturing the first sub-board 2 and the second sub-board 3. The third sub-board 7 includes a fourth channel extending along the thickness direction of the third sub-board 7. The third sub-board 7 includes a seventh conductive pattern 71 and an eighth conductive pattern 72 arranged opposite to each other along the thickness direction of the third sub-board 7. The difference between the area ratio of the seventh conductive pattern 71 on the fifth surface and the area ratio of the eighth conductive pattern 72 on the sixth surface is less than or equal to 50%. The fourth sub-board 9 includes a fifth channel extending along the thickness direction of the fourth sub-board 9. The fourth sub-board 9 includes a ninth conductive pattern 91 and a tenth conductive pattern 92 arranged opposite to each other along the thickness direction of the fourth sub-board 9. The difference between the area ratio of the ninth conductive pattern 91 on the seventh surface and the area ratio of the tenth conductive pattern 92 on the eighth surface is less than or equal to 50%.

[0432] As shown in FIG9 (i), take the third insulating layer 8, along the thickness direction of the second sub-board 3, place the third insulating layer 8 and the third sub-board 7 on the side of the second sub-board 3 away from the core board 1, and the third insulating layer 8 is located between the second sub-board 3 and the third sub-board 7;

[0433] Take the fourth insulating layer 1a and place the fourth insulating layer 1a and the fourth sub-board 9 on the side of the first sub-board 2 away from the core board 1 along the thickness direction of the first sub-board 2, with the fourth insulating layer 1a located between the fourth sub-board 9 and the first sub-board 2;

[0434] The steps as shown in FIG. 9( b ) to FIG. 9( h ) are followed to form a multi-layer circuit board having five layers of substrates 1 b stacked together as shown in FIG. 9( j ).

[0435] In summary, in another embodiment, a method for processing a multi-layer circuit board includes:

[0436] As shown in FIG10( a ), the first substrate 23 is taken and laser induced on the first substrate 23 to form a second phase change channel 235 , wherein the extension direction of the second phase change channel 235 is parallel to the thickness direction of the substrate 1 b ;

[0437] As shown in FIG10( b ), the first substrate 23 having two phase change channels is etched to form a second channel 241 ;

[0438] As shown in FIG10( c ), the first substrate 23 includes a first surface 231 and a second surface 232 disposed opposite to each other along its thickness direction, and a metal layer 6 is sputtered on the first surface 231 and the second surface 232 ;

[0439] As shown in FIG. 10( d ), a first photoresist 233 is covered on the first surface 231 , and a second photoresist 234 is covered on the second surface 232 ;

[0440] Performing photolithography on the first surface 231 to form a first pattern, and performing photolithography on the second surface to form a second pattern;

[0441] As shown in FIG10( e ), the first pattern, the second pattern, and the second channel 241 are electroplated to form a first conductive pattern 21, a second conductive pattern 22, and a second conductive channel 24. The first conductive pattern 21, the second conductive channel 24, and the second conductive pattern 22 constitute a signal transmission line structure. For example, the first conductive pattern 21 is a signal layer, and the second conductive pattern 22 is a ground layer or a power layer.

[0442] As shown in FIG10( f ), the metal layer 6 on the first surface 231 and the second surface 232 is removed to complete the processing of the first sub-board 2 ;

[0443] As shown in FIG11( a ), the second substrate 32 is taken and laser induced on the second substrate 32 to form a third phase change channel 325 , wherein the extension direction of the third phase change channel 325 is parallel to the thickness direction of the second substrate 32 ;

[0444] As shown in FIG11( b ), the second substrate 32 having the three-phase change channel is etched to form a third channel 331 ;

[0445] As shown in FIG12( a ), take the first insulating layer 4 and place the first insulating layer 4 on one side of the first substrate 23 along the thickness direction of the first substrate 23 , and place the second substrate 32 on the side of the first insulating layer 4 away from the first substrate 23 ;

[0446] As shown in FIG12( b ), the first substrate 23 , the first insulating layer 4 and the second substrate 32 are laminated and fixed;

[0447] As shown in FIG12( c ), the excess first insulating layer 4 in the third channel 331 is removed, and a first through hole 411 is processed on the first insulating layer 4. The first through hole 411 passes through the first insulating layer 4 along the thickness direction of the first insulating layer 4.

[0448] As shown in FIG12( d ), a metal layer 6 is sputtered on the surface of the second substrate 32 , the sidewalls of the third channel 331 , and the sidewalls of the first through hole 411 ;

[0449] As shown in FIG. 12( e ), the surface of the second substrate 32 is covered with a fourth photoresist 324 ;

[0450] Performing photolithography on the second substrate 32 to form a sixth pattern;

[0451] As shown in FIG12( f ), the sixth pattern, the third via 331 and the first through-hole 411 are electroplated and filled to form a conductive layer 31 (i.e., the sixth conductive pattern), a third conductive channel 33 and a first conductive portion 41 . The sixth conductive pattern, the third conductive channel 33 and the first conductive pattern 21 constitute a signal transmission line structure.

[0452] As shown in FIG. 12( g ), the fourth photoresist 324 and the metal layer 6 on the surface of the second substrate 32 are removed;

[0453] The third sub-board 7 is processed according to the steps shown in Figures 11(a) and 11(b) above, and is processed according to the steps shown in Figures 12(a) to 12(g) above to form a multi-layer circuit board composed of a stacked multi-layer substrate 1b.

[0454] In summary, in another embodiment, a method for processing a multi-layer circuit board includes:

[0455] As shown in FIG10( a ), the first substrate 23 is taken and laser induced on the first substrate 23 to form a second phase change channel 235 , wherein the extension direction of the second phase change channel 235 is parallel to the thickness direction of the substrate 1 b ;

[0456] As shown in FIG10( b ), the first substrate 23 having two phase change channels is etched to form a second channel 241 ;

[0457] As shown in FIG10( c ), the first substrate 23 includes a first surface 231 and a second surface 232 disposed opposite to each other along its thickness direction, and a metal layer 6 is sputtered on the first surface 231 and the second surface 232 ;

[0458] As shown in FIG. 10( d ), a first photoresist 233 is covered on the first surface 231 , and a second photoresist 234 is covered on the second surface 232 ;

[0459] Performing photolithography on the first surface 231 to form a first pattern, and performing photolithography on the second surface to form a second pattern;

[0460] As shown in FIG10( e ), the first pattern, the second pattern, and the second channel 241 are electroplated to form a first conductive pattern 21, a second conductive pattern 22, and a second conductive channel 24. The conductive pattern 21, the second conductive channel 24, and the second conductive pattern 22 constitute a signal transmission line structure. For example, the first conductive pattern 21 is a signal layer, and the second conductive pattern 22 is a ground layer or a power layer.

[0461] As shown in FIG10( f ), the metal layer 6 on the first surface 231 and the second surface 232 is removed to complete the processing of the first sub-board 2 ;

[0462] As shown in FIG11( a ), the second substrate 32 is taken and laser induced on the second substrate 32 to form a third phase change channel 325 , wherein the extension direction of the third phase change channel 325 is parallel to the thickness direction of the second substrate 32 ;

[0463] As shown in FIG11( b ), the second substrate 32 having the three-phase change channel is etched to form a third channel 331 ;

[0464] As shown in FIG13( a ), take the first insulating layer 4 and place the first insulating layer 4 on one side of the first substrate 23 ;

[0465] As shown in FIG13( b ), a first through hole 411 is processed on the first insulating layer 4 ;

[0466] As shown in FIG. 13( c ), a fourth conductive medium 412 is placed into the first through hole 411 . The fourth conductive medium 412 is solder or conductive paste to form the first conductive portion 41 .

[0467] As shown in FIG13( d ), along the thickness direction of the first substrate 23 , the second substrate 32 is placed on the side of the first insulating layer 4 away from the first substrate 23 ;

[0468] Laminating and fixing the first substrate 23, the first insulating layer 4 and the second substrate 32;

[0469] As shown in FIG13( e ), a metal layer 6 is sputtered on the surface of the second substrate 32 and the sidewalls of the third channel 331 ;

[0470] As shown in FIG. 13( f ), the surface of the second substrate 32 is covered with a fourth photoresist 324 ;

[0471] Performing photolithography on the second substrate 32 to form a sixth pattern;

[0472] As shown in FIG13( g ), the sixth pattern and the third via 331 are electroplated and filled to form a conductive layer 31 (i.e., the sixth conductive pattern) and a third conductive channel 33. The sixth conductive pattern, the third conductive channel 33, and the first conductive pattern 21 constitute a signal transmission line structure.

[0473] As shown in FIG. 13( h ), the fourth photoresist 324 and the metal layer 6 on the surface of the second substrate 32 are removed;

[0474] The third sub-board 7 is processed according to the steps shown in Figures 11(a) and 11(b) above, and is processed according to the steps shown in Figures 13(a) to 13(h) above to form a multi-layer circuit board composed of a stacked multi-layer substrate 1b.

[0475] In this specification, reference can be made to the same or similar parts between the various embodiments. In particular, for the device embodiment and the terminal embodiment, since they are basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the description in the method embodiment.

Claims

1. A method for processing a multi-layer circuit board, characterized in that: The processing method of the multi-layer circuit board comprises: Taking a first substrate, processing a first conductive pattern, a second conductive pattern and a second channel on the first substrate, wherein the extension direction of the second channel is parallel to the thickness direction of the first substrate, the first substrate comprises a first surface and a second surface arranged opposite to each other along the thickness direction thereof, the first conductive pattern is located on the first surface, and the second conductive pattern is located on the second surface; Taking a second substrate, processing a third channel on the second substrate, wherein an extension direction of the third channel is parallel to a thickness direction of the second substrate; Take the first insulating layer, and stack the second substrate and the first insulating layer on the first substrate along the thickness direction of the first sub-board, with the first insulating layer being located between the second substrate and the first substrate; Pressing and fixing the second substrate, the first insulating layer and the first substrate; Before the step of stacking the second substrate and the first insulating layer on the first substrate, or after the step of pressing and fixing the second substrate, the first insulating layer and the first substrate, the processing method of the multilayer circuit board includes: Performing electroplating and filling holes on the first substrate so that the second conductive medium fills the second hole to form a second conductive channel; After the step of pressing and fixing the second substrate, the first insulating layer and the first substrate, the processing method of the multilayer circuit board includes: The second substrate is electroplated to form a sixth conductive pattern on a side of the second substrate away from the first substrate, and a third conductive medium is filled in the third channel to form a third conductive channel, the first insulating layer includes a first conductive portion, and the first conductive pattern, the second conductive pattern and the sixth conductive pattern are electrically connected to the second conductive channel through the third conductive channel and the first conductive portion.

2. The method for processing a multi-layer circuit board according to claim 1, characterized in that: When the difference between the area ratio of the first conductive pattern on the first surface and the area ratio of the second conductive pattern on the second surface is less than or equal to 50%, the processing method of the multilayer circuit board includes: Making a core board, wherein the core board includes a first conductive path extending along the thickness direction of the core board; Processing the first conductive pattern and the second conductive pattern on the first substrate; Processing the second channel on the first substrate having the first conductive pattern and the second conductive pattern; The step of stacking the second substrate and the first insulating layer on the first substrate comprises: Take the second insulating layer, stack the first substrate, the first insulating layer, the core board, the second insulating layer and the second substrate, the first insulating layer is located between the first substrate and the core board, the second insulating layer is located between the core board and the second substrate, and the first conductive pattern is located on a side of the first substrate away from the core board; The step of pressing and fixing the second substrate, the first insulating layer and the first substrate comprises: Pressing and fixing the first substrate, the first insulating layer, the core plate, the second insulating layer and the second substrate; After the step of pressing and fixing the first substrate, the first insulating layer, the core board, the second insulating layer and the second substrate, the processing method of the multilayer circuit board includes: removing the first conductive pattern; Electroplating the first substrate to form a fifth conductive pattern on the first surface, fill the second channel with a second conductive medium to form a second conductive channel, and form a first sub-board, wherein the fifth conductive pattern, the second conductive channel, and the second conductive pattern constitute a signal transmission line structure; The second insulating layer includes a second conductive portion, and after the step of electroplating the second substrate to form the sixth conductive pattern and the third conductive path, the fifth conductive pattern, the second conductive pattern, and the sixth conductive pattern are electrically connected through the second conductive path, the first conductive portion, the first conductive path, the second conductive portion, and the third conductive path.

3. The method for processing a multi-layer circuit board according to claim 2, characterized in that: The steps of making the core plate include: Taking a core substrate, and performing laser induction on the core substrate to form a first phase change channel, wherein an extension direction of the first phase change channel is parallel to a thickness direction of the core substrate; Etching the core substrate having the phase change channel to form a first channel; sputtering a metal layer on the exposed surface of the core substrate; Performing electroplating to fill the first hole to form the first conductive channel; The metal layer on the surface of the core substrate is removed.

4. The method for processing a multi-layer circuit board according to claim 2, characterized in that: Before the step of processing the third via on the second substrate, the method for processing the multilayer circuit board includes: Take the second substrate, the second substrate includes a third surface and a fourth surface arranged opposite to each other along the thickness direction of the second substrate, process a third conductive pattern on the third surface, and process a fourth conductive pattern on the fourth surface to form a second sub-board, and the difference between the area ratio of the third conductive pattern on the third surface and the area ratio of the fourth conductive pattern on the fourth surface is less than or equal to 50%; After the step of pressing and fixing the first substrate, the first insulating layer, the core board, the second insulating layer and the second substrate, the fourth conductive pattern is located on a side of the second substrate away from the first substrate. The processing method of the multilayer circuit board includes: The fourth conductive pattern is removed.

5. The method for processing a multi-layer circuit board according to claim 4, characterized in that: The step of processing the first conductive pattern and the second conductive pattern on the first substrate comprises: Taking the first substrate, and sputtering a metal layer on the first surface and the second surface; Covering the first surface with a first photoresist, and covering the second surface with a second photoresist; Performing photolithography on the first surface to form a first pattern, and performing photolithography on the second surface to form a second pattern; Electroplating the first pattern and the second pattern to form the first conductive pattern and the second conductive pattern; removing the first photoresist, the second photoresist and the metal layer; The steps of processing the third conductive pattern on the third surface and processing the fourth conductive pattern on the fourth surface include: Take the second substrate, and sputter a metal layer on the third surface and the fourth surface; Covering the third surface with a third photoresist, and covering the fourth surface with a fourth photoresist; Performing photolithography on the third surface to form a third pattern, and performing photolithography on the fourth surface to form a fourth pattern; Electroplating the third pattern and the fourth pattern to form the third conductive pattern and the fourth conductive pattern; The third photoresist, the fourth photoresist and the metal layer are removed.

6. The method for processing a multi-layer circuit board according to claim 4, characterized in that: The step of electroplating the first substrate comprises: sputtering a metal layer on the first surface and the sidewalls of the second hole; Covering the first surface with a fifth photoresist; performing photolithography on the first surface to form a fifth pattern; Electroplating the fifth pattern and the second channel to form the fifth conductive pattern and the second conductive channel; removing the fifth photoresist and the metal layer; The step of electroplating the second substrate comprises: sputtering a metal layer on the fourth surface and the sidewalls of the third channel; Covering the fourth surface with a sixth photoresist; performing photolithography on the fourth surface to form a sixth pattern; Electroplating the sixth pattern and the third channel to form the sixth conductive pattern and the third conductive channel; The sixth photoresist and the metal layer are removed.

7. The method for processing a multi-layer circuit board according to claim 4, characterized in that: The processing method of the multi-layer circuit board also includes: A third sub-board is manufactured, wherein the third sub-board includes a fourth channel extending along the thickness direction of the third sub-board, the third sub-board includes a fifth surface and a sixth surface arranged opposite to each other along the thickness direction of the third sub-board, a seventh conductive pattern is arranged on the fifth surface, an eighth conductive pattern is arranged on the sixth surface, and a difference between an area ratio of the seventh conductive pattern on the fifth surface and an area ratio of the eighth conductive pattern on the sixth surface is less than or equal to 50%; After the step of pressing and fixing the first substrate, the first insulating layer, the core board, the second insulating layer and the second substrate, the processing method of the multilayer circuit board includes: Take the third insulating layer, and place the third insulating layer and the third sub-board on the side of the second sub-board away from the core board along the thickness direction of the second sub-board, the third insulating layer is located between the second sub-board and the third sub-board, and the eighth conductive pattern is located on a side of the third sub-board away from the third insulating layer; Pressing and fixing the second sub-board and the third sub-board; removing the eighth conductive pattern; The third sub-board is electroplated to form an eleventh conductive pattern on the sixth surface, and a fourth conductive medium is filled in the fourth channel to form a fourth conductive channel, and the eleventh conductive pattern, the fourth conductive channel, and the seventh conductive pattern constitute a signal transmission line structure; the third insulating layer includes a third conductive portion, and the third sub-board is electrically connected to the second sub-board through the fourth conductive channel and the third conductive portion; And / or, the method for processing the multilayer circuit board further includes: Manufacturing a fourth sub-board, the fourth sub-board comprising a fifth channel extending in the thickness direction thereof, the fourth sub-board comprising a seventh surface and an eighth surface arranged opposite to each other in the thickness direction thereof, the seventh surface being provided with a ninth conductive pattern, the eighth surface being provided with a tenth conductive pattern, and the difference between the area ratio of the ninth conductive pattern on the seventh surface and the area ratio of the tenth conductive pattern on the eighth surface being less than or equal to 50%; After the step of pressing and fixing the first sub-board, the first insulating layer, the core board, the second insulating layer and the second sub-board, the processing method of the multi-layer circuit board includes: Take the fourth insulating layer, and place the fourth insulating layer and the fourth sub-board on a side of the first sub-board away from the core board along the thickness direction of the first sub-board, the fourth insulating layer is located between the fourth sub-board and the first sub-board, and the ninth conductive pattern is located on a side of the fourth sub-board away from the fourth insulating layer; Pressing and fixing the fourth sub-board and the first sub-board; removing the ninth conductive pattern; The fourth sub-board is electroplated to form a twelfth conductive pattern on the seventh surface, and a fifth conductive medium is filled in the fifth channel to form a fifth conductive channel, and the twelfth conductive pattern, the fifth conductive channel, and the tenth conductive pattern constitute a signal transmission line structure; the fourth insulating layer includes a fourth conductive portion, and the fourth sub-board is electrically connected to the first sub-board through the fifth conductive channel and the fourth conductive portion.

8. The method for processing a multi-layer circuit board according to claim 1, characterized in that: When the first conductive pattern, the second conductive pattern, and the second conductive channel form a signal transmission line structure, the step of electroplating and filling holes on the first substrate is performed simultaneously with the step of processing the first conductive pattern and the second conductive pattern; The step of processing the first conductive pattern, the second conductive pattern and the second via on the first substrate comprises: Processing the second channel on the first substrate; sputtering a metal layer on the first surface and the second surface of the first substrate having the second hole; Covering the first surface with a first photoresist, and covering the second surface with a second photoresist; Performing photolithography on the first surface to form a first pattern, and performing photolithography on the second surface to form a second pattern; The first pattern, the second pattern, and the second channel are electroplated to form the first conductive pattern, the second conductive pattern, and the second conductive channel.

9. The method for processing a multi-layer circuit board according to claim 8, characterized in that: The processing method of the multi-layer circuit board also includes: Manufacturing a third sub-plate, wherein the third sub-plate includes a fourth channel extending along the thickness direction of the third sub-plate; After the step of pressing and fixing the second substrate, the first insulating layer and the first substrate, the processing method of the multilayer circuit board includes: Taking a third insulating layer, and placing the third insulating layer and the third sub-board on a side of the second substrate away from the first substrate along the thickness direction of the second substrate, wherein the third insulating layer is located between the second substrate and the third sub-board; Pressing and fixing the third sub-board and the second substrate; The third sub-board is electroplated so that an eleventh conductive pattern is formed on a side of the third sub-board away from the second substrate, and a fourth conductive medium is filled in the fourth channel to form a fourth conductive channel; the third insulating layer includes a third conductive portion, and the eleventh conductive pattern is electrically connected to the sixth conductive pattern through the fourth conductive channel and the third conductive portion; And / or, the method for processing the multilayer circuit board further includes: Manufacturing a fourth sub-plate, wherein the fourth sub-plate includes a fifth channel extending along the thickness direction of the fourth sub-plate; After the step of pressing and fixing the second substrate, the first insulating layer and the first substrate, the processing method of the multilayer circuit board includes: Taking a fourth insulating layer, and placing the fourth insulating layer and the fourth sub-board on a side of the first substrate away from the second substrate along the thickness direction of the first substrate, wherein the fourth insulating layer is located between the first substrate and the fourth sub-board; Pressing and fixing the first substrate and the fourth sub-board; The fourth sub-board is electroplated so that a twelfth conductive pattern is formed on a side of the fourth sub-board away from the first substrate, and a fifth conductive medium is filled in the fifth channel to form a fifth conductive channel; the fourth insulating layer includes a fourth conductive portion, and the twelfth conductive pattern is electrically connected to the first conductive pattern through the fifth conductive channel and the fourth conductive portion.

10. The method for processing a multi-layer circuit board according to any one of claims 1 to 9, characterized in that: The step of processing the second channel on the first substrate comprises: Performing laser induction on the first substrate to form a second phase change channel, wherein an extension direction of the second phase change channel is parallel to a thickness direction of the first substrate; Etching the first substrate having the two phase change channels to form a second channel; The step of processing the third channel on the second substrate comprises: Performing laser induction on the second substrate to form a third phase change channel, wherein an extension direction of the third phase change channel is parallel to a thickness direction of the second substrate; The second substrate having the three-phase change channel is etched to form a third channel.

11. The method for processing a multi-layer circuit board according to any one of claims 1 to 9, characterized in that: The step of stacking the second substrate and the first insulating layer on the first substrate comprises: Placing the first insulating layer on the first substrate along the thickness direction of the first sub-board; Placing the second substrate on a side of the first insulating layer away from the first substrate along the thickness direction of the first sub-board; After the step of pressing and fixing the second substrate, the first insulating layer and the first substrate, the processing method of the multilayer circuit board includes: Processing a first through hole on the first insulating layer, wherein the first through hole penetrates the first insulating layer along a thickness direction of the first insulating layer; sputtering a metal layer on the sidewall of the first through hole; The first through hole is filled with electroplating to form the first conductive portion.

12. The method for processing a multi-layer circuit board according to any one of claims 1 to 9, characterized in that: The step of stacking the second substrate and the first insulating layer on the first sub-board comprises: placing the first insulating layer on the first substrate along a thickness direction of the first substrate; Processing a first through hole on the first insulating layer, wherein the first through hole penetrates the first insulating layer along a thickness direction of the first insulating layer; Putting a fourth conductive medium into the first through hole, wherein the fourth conductive medium is solder or conductive paste; Along the thickness direction of the first sub-board, the second substrate is placed on a side of the first insulating layer away from the first sub-board.

13. A multi-layer circuit board, characterized in that: The multilayer circuit board is formed by processing based on the multilayer circuit board processing method according to any one of claims 1 to 12.

14. A chip system, characterized in that: The chip system comprises: Printed circuit boards; A packaging substrate, the packaging substrate is mounted on the printed circuit board, and the packaging substrate is electrically connected to the printed circuit board; An intermediary layer, the intermediary layer is mounted on the packaging substrate, and the intermediary layer is electrically connected to the packaging substrate; A plurality of chip monomers, wherein the chip monomers are mounted on the intermediary layer, and the plurality of chip monomers are electrically connected to the intermediary layer respectively; The printed circuit board is the multi-layer circuit board according to claim 13, and / or the packaging substrate is the multi-layer circuit board according to claim 13.

15. An electronic device, characterized in that: The electronic device comprises: Equipment body; The chip system as described in claim 14 is installed on the device body.

Images