Compression attached memory module and device

Abstract

The present disclosure relates to the technical field of semiconductors, and provides a compression attached memory module and a device. The compression attached memory module comprises: a compression attached memory circuit board; a plurality of memory chips, arranged on the compression attached memory circuit board; and a power management apparatus, arranged on the compression attached memory circuit board and electrically connected to the plurality of memory chips. The power management apparatus comprises a preset number of power management chips, and is used for supplying to the plurality of memory chips electric energy generated by the preset number of power management chips as power supply, wherein the preset number of the power management chips in the power management apparatus is preset according to the power requirements of the plurality of memory chips.

Description

Press-fit memory modules and equipment

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on the Chinese patent application with application number 202311525966.2 and application date of November 13, 2023, and claims the priority of the Chinese patent application. The entire content of the Chinese patent application is hereby introduced into this application as a reference. Technical Field

[0003] The present disclosure relates to the field of semiconductor technology, and more particularly to press-fit memory modules and devices. Background Art

[0004] With the development of semiconductor technology, Compressed Attached Memory Module (CAMM) has become one of the important research directions of semiconductor technology due to its thinner thickness, better heat dissipation and lower power consumption.

[0005] However, current press-fit memory modules lack a suitable power supply solution.

[0006] Therefore, how to provide a press-fit memory module with a power supply solution suitable for itself has become a technical problem that needs to be solved urgently.

[0007] Summary of the Invention

[0008] The present disclosure provides a press-fit memory module and device, which at least to some extent overcomes the problem that the memory module lacks a power supply solution that is suitable for its own power supply needs.

[0009] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by practice of the present disclosure.

[0010] According to one aspect of the present disclosure, a press-fit memory module is provided, comprising:

[0011] Press-fit memory circuit boards;

[0012] A plurality of memory chips are disposed on a press-fit memory circuit board;

[0013] A power management device is arranged on a press-fit memory circuit board and is electrically connected to multiple memory chips. The power management device includes a preset number of power management chips, which are used to provide the electric energy generated by the preset number of power management chips as power supply energy to the multiple memory chips. The preset number of power management chips in the power management device is preset based on the power requirements of the multiple memory chips.

[0014] In one embodiment, the power management device includes multiple power management chips, wherein the power management chip includes a first power supply pin, and the first power supply pins of the multiple power management chips are connected to provide the electric energy generated by the multiple power management chips to the multiple memory chips through the connected first power supply pins.

[0015] In one embodiment, the first power supply pin includes N power transmission pins, each power transmission pin is used to output a power supply voltage, wherein the i-th power transmission pins of multiple power management chips are connected to provide the power supply voltage output by the connected i-th power transmission pin to multiple memory chips, wherein N is an integer greater than or equal to 1, and i is any integer less than or equal to N.

[0016] In one embodiment, the module further includes: a serial detection chip configured to store preset power quantity information, wherein the preset power quantity information is used to indicate the quantity of power management chips in the power management device.

[0017] In one embodiment, the power management chip further includes a mode register, which is used to store preset power configuration information of the power management chip to which it belongs, wherein the preset power configuration information is configured by the chip control device based on the preset power quantity information in the configuration serial detection chip.

[0018] In one embodiment, the configuration serial detection chip includes a first communication pin, and each power management chip includes a second communication pin, wherein the first communication pin is respectively connected to the second communication pin of each power management chip to establish a communication connection between the configuration serial detection chip and each power management chip.

[0019] In one embodiment, the serial detection chip is configured to include a first power supply pin, and each power management chip further includes a second power supply pin;

[0020] In which, when the power management device includes multiple power management chips, the second power supply pin of the target power management chip in the power management device is connected to the first power supply pin, and the second power supply pins of other power management chips in the power management device except the target power management chip are left vacant, so that the electric energy output by the second power supply pin of the target power management chip can be provided to the configured serial detection chip as the power supply energy for the configured serial detection chip.

[0021] In one embodiment, each power management chip includes a status signal pin, which is used to output a first level indicating that each power management chip is normal or a second level indicating that each power management chip is faulty. When the power management device includes multiple power management chips, the status signal pins of the multiple power management chips are connected to a status signal transmission line. When the status signal pins of one or more power management chips output the second level, the level on the status signal transmission line is adjusted to the second level, and the second level on the status signal transmission line indicates a fault in the power management device.

[0022] In one embodiment, each power management chip includes an enable pin, which is used to start or shut down each power management chip, wherein the enable pin of each power management chip is used to receive a control instruction sent by the chip control device, and the control instruction is used to start or shut down each power management chip.

[0023] In one embodiment, each power management chip includes a communication address pin, which is used to indicate the communication address of each power management chip. The communication address pins of multiple power management chips correspond to different voltages, and different voltages represent different communication addresses.

[0024] In one embodiment, the first power supply pin of one of the multiple power management chips is directly connected to the first conductive line, and the first power supply pins of other power management chips among the multiple power management chips are connected to the first conductive line or the first power supply pin of one of the power management chips through a connector.

[0025] In one embodiment, the connecting member includes: one or more of a resistor with a preset resistance, a connecting line, a switching element, and a fuse device.

[0026] In one embodiment, the connector includes a fuse device, which is a fuse or an antifuse;

[0027] Among them, for each other power management chip, when the fuse device corresponding to each other power management chip is in a low-resistance state, each other power management chip supplies power to multiple memory chips; when the fuse device is in a high-resistance state, each other power management chip does not supply power to multiple memory chips.

[0028] In one embodiment, the resistance state of the fuse device is adjusted by a tester when the actual number of the power management chips supplied is incorrect.

[0029] In one embodiment, a test machine determines whether there is an error in the actual quantity based on preset power quantity information, wherein the preset power quantity information is stored in a configuration serial detection chip and is used to indicate the number of power management chips in a power management device; wherein, when the actual quantity is wrong and the actual quantity is greater than the quantity indicated by the preset power quantity information, the test machine adjusts the first target fuse device to a high impedance state to disconnect the power management chip corresponding to the first target fuse device from the power management device; wherein, when the actual quantity is wrong and the actual quantity is less than the quantity indicated by the preset power quantity information, the test machine adjusts the fuse device to a low impedance state to connect the power management chip corresponding to the second target fuse device to the power management device.

[0030] In one embodiment, each power management chip is used to provide power to some of the memory chips.

[0031] In one embodiment, multiple memory chips can be divided into multiple groups, each group of memory chips belongs to a memory channel, each power management chip corresponds to at least one memory channel, and each power management chip is used to provide power to the memory chips in the corresponding memory channel.

[0032] According to yet another aspect of the present disclosure, there is provided an electronic device comprising the above-mentioned press-fit memory module.

[0033] The press-fit memory module and device provided by the embodiments of the present disclosure can flexibly set the preset number of power management chips in the power management device according to the power requirements of the memory chips, so that the electricity generated by the preset number of power management chips can flexibly meet the power requirements of a variety of press-fit memory modules, avoiding the occurrence of voltage drops caused by insufficient power supply. Furthermore, the technical solution provided by the embodiments of the present disclosure can achieve flexible power supply to the press-fit memory module while ensuring power supply stability, thereby enabling the press-fit memory module to have a power supply solution that suits itself.

[0034] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0036] FIG1 shows a schematic structural diagram of a press-fit memory module provided by an embodiment of the present disclosure;

[0037] FIG2 shows a schematic structural diagram of a press-fit memory module provided by an embodiment of the present disclosure;

[0038] FIG3 shows a schematic structural diagram of an exemplary press-fit memory module provided by an embodiment of the present disclosure;

[0039] FIG4 shows a schematic structural diagram of an exemplary power management chip provided by an embodiment of the present disclosure;

[0040] FIG5 shows a schematic structural diagram of another exemplary press-fit memory module provided by an embodiment of the present disclosure;

[0041] FIG6 shows a schematic structural diagram of another exemplary press-fit memory module provided by an embodiment of the present disclosure;

[0042] FIG7 shows a schematic structural diagram of another press-fit memory module provided by an embodiment of the present disclosure;

[0043] FIG8 shows a schematic structural diagram of another exemplary power management chip provided by an embodiment of the present disclosure;

[0044] FIG9 shows a schematic structural diagram of another exemplary power management chip provided by an embodiment of the present disclosure;

[0045] FIG10 shows a schematic structural diagram of another exemplary power management chip provided by an embodiment of the present disclosure;

[0046] FIG11 shows a schematic structural diagram of another exemplary power management chip provided by an embodiment of the present disclosure;

[0047] FIG12 shows a schematic structural diagram of another exemplary power management chip provided by an embodiment of the present disclosure;

[0048] FIG13 shows a schematic structural diagram of another exemplary power management chip provided by an embodiment of the present disclosure;

[0049] FIG14 shows a schematic structural diagram of another exemplary power management chip provided by an embodiment of the present disclosure;

[0050] FIG15 shows a schematic structural diagram of an exemplary first power management chip provided by an embodiment of the present disclosure;

[0051] FIG16 shows a schematic structural diagram of an exemplary second power management chip provided by an embodiment of the present disclosure;

[0052] FIG17 shows a schematic structural diagram of an exemplary serial detection chip configuration provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0053] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be embodied in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0054] As mentioned in the background art, Compressed Attached Memory Module (CAMM) has become one of the important research directions of semiconductor technology.

[0055] FIG1 shows a schematic structural diagram of a compression memory module provided by an embodiment of the present disclosure. As shown in FIG1 , the compression memory module 10 and the system main board (Main Board) 20 can be arranged between a top pressure plate (Top Bolster Plate) 30 and a bottom pressure plate (Bottom Bolster Plate) 40, and the compression memory module 10 can be fixed to the compression connector (Compression Connector) 50 of the system main board 20 using screws. In some embodiments, the external connection end of the compression memory module 10 can be a contact. Accordingly, the compression memory module 10 can be connected to and fixed to the system main board by combining contacts and screws.

[0056] However, the standard for press-fit memory modules has not yet been finalized. The inventors discovered through research that, in an exemplary scenario, a small outline dual in-line memory module (Small outline Dual In-line Memory Module, SoDIMM) has only one memory channel (channel), while a press-fit memory module can have two independent memory channels. Therefore, in theory, the load of a press-fit memory module is twice that of a small outline dual in-line memory module. Therefore, if the power supply design of the small outline dual in-line memory module is borrowed, that is, if a power management chip (Power Management Integrated Circuit, PMIC) is used to power the memory chip in the press-fit memory module, then in extreme cases, the power demand of the press-fit memory module may not be met, resulting in voltage drops and the like.

[0057] Therefore, how to provide a press-fit memory module with a power supply solution suitable for itself has become a technical solution that needs to be solved urgently.

[0058] Based on this, the disclosed embodiments provide a press-fit memory module and device that can be applied in semiconductor storage scenarios, such as module design scenarios, particularly the power supply design scenarios of CAMM modules. The technical solutions provided by the disclosed embodiments ensure power supply stability while enabling flexible power supply for press-fit memory modules, enabling press-fit memory modules to have a power supply solution that suits them.

[0059] Before describing the technical solutions provided by the embodiments of the present disclosure, the technical terms involved in the embodiments of the present disclosure are first described.

[0060] (1) Power Management Integrated Circuit (PMIC), an integrated circuit used for voltage conversion, voltage regulation, and battery management. For example, in the field of semiconductor technology, its important role can be to provide power support for other chips on the memory module (such as memory chips).

[0061] (2) Configuring a serial presence detect chip (Serial Presence Detect, SPD), that is, a chip for storing the SPD information of the module. Exemplarily, the SPD information includes important information of the storage module, such as chip information of the memory mode, module manufacturer information, operating frequency, operating voltage, speed, capacity, voltage, row and column address bandwidth and other information. Exemplarily, the configured serial detection chip can be an electrically erasable programmable read-only memory (EEPROM). Exemplarily, the chip control device can access the SPD information in the configured serial detection chip through the Inter-Integrated Circuit (I2C) bus or the System Management Bus (SMBus).

[0062] After introducing the above technical terms, the technical solutions provided by the embodiments of the present disclosure are described below.

[0063] Figure 2 shows a schematic diagram of the structure of a press-fit memory module provided by an embodiment of the present disclosure. As shown in Figure 2, the press-fit memory module 20 may include a press-fit memory circuit board 21, multiple memory chips 22, and a power management device 23. The press-fit memory module may have two independent memory channels. The following describes each component of the press-fit memory module in turn.

[0064] The press-fit memory circuit board 21 may be a circuit board used to realize electrical connection between devices in the press-fit memory module 20, such as a printed circuit board (PCB). There is no restriction on the specific form of the press-fit memory circuit board 21.

[0065] The memory chip 22 may be disposed on the compression memory circuit board 10 .

[0066] In terms of the arrangement, in some embodiments, the memory chip 22 can be arranged on one side of the press-fit memory circuit board 10 . In other embodiments, the memory chip 22 can be arranged on both sides of the press-fit memory circuit board 10 .

[0067] In terms of specific form, in some embodiments, the memory chip 22 can be a chip for data storage. For example, the memory chip 22 can be a dynamic random access memory chip (DRAM), a static random access memory chip (SRAM), or a flash memory chip. For example, the memory chip 22 can be a double data rate synchronous dynamic random access memory (Dual Data Rate SDRAM, DDR SDRAM) or a low power double data rate synchronous dynamic random access memory (Low Power Dual Data Rate SDRAM, LPDDR SDRAM). For example, the semiconductor memory can be DDR5, DDR6, LPDDR4, LPDDR5, LPDDR6, etc. The present disclosure does not limit the specific form of the memory chip 22.

[0068] After introducing the memory chip 22 , the power management device 23 will be described next.

[0069] The power management device 23 can be disposed on the press-fit memory circuit board 21 and electrically connected to the plurality of memory chips 22. The power management device 23 includes a predetermined number (e.g., K) of power management chips 2311 to 231K, and is configured to provide power generated by the predetermined number of power management chips 2311 to 231K as power supply energy to the plurality of memory chips 20. The number of power management chips (i.e., K) in the power management device 23 is determined based on the power requirements of the plurality of memory chips 20.

[0070] Next, the power management device 23 will be described in detail from aspects such as the installation location, specific structure, number of power management chips, and power supply method.

[0071] In terms of the installation location, in some embodiments, the power management chips 2311 to 231K can be installed on a memory card (raw card) of a press-fit memory module.

[0072] In terms of specific structure, in some embodiments, in order to provide power supply energy to the memory chip, when the power management device 23 includes multiple power management chips 2311 to 231K, each power management chip includes a first power supply pin A1, wherein the first power supply pin A1 can be a pin for providing power supply energy to the memory chip.

[0073] Specifically, the first power supply pins A1 of the plurality of power management chips are connected to provide the power generated by the plurality of power management chips 2311 to 231K to the plurality of memory chips via the connected first power supply pins A1. For example, the first power supply pins of the plurality of power management chips 2311 to 231K can be connected to the same first conductive line to provide the power generated by the plurality of power management chips to the plurality of memory chips 22 via the first conductive line.

[0074] In one example, FIG3 shows a schematic structural diagram of an exemplary press-fit memory module provided by an embodiment of the present disclosure. As shown in FIG3, when the power management device 23 includes two power management chips, namely a first power management chip 23111 and a second power management chip 2312, the first power management chip 23111 and the second power management chip 2312 are connected to each other with their respective first power supply pins A1, so as to provide the electrical energy generated by the first power management chip 2311 and the second power management chip 2312 to the memory chip through the connected first power supply pins A1. For example, the power supply voltage V0 output after the first power supply pins A1 of the first power management chip 2311 and the second power management chip 2312 are connected can be provided to the memory chip as the power supply voltage of the memory chip.

[0075] Through the embodiment of the present disclosure, multiple power management chips can jointly power multiple memory chips through the first power supply pin, thereby meeting the power needs of multiple memory chips, avoiding the occurrence of voltage drops caused by insufficient power supply, and ensuring power supply stability.

[0076] In one embodiment, to provide multiple power supply voltages to the memory chip, each first power supply pin A1 includes N power transmission pins, each of which is used to output a power supply voltage. N is an integer greater than or equal to 1. For example, FIG4 shows a schematic diagram of the structure of an exemplary power management chip provided in an embodiment of the present disclosure. As shown in FIG4 , the first power management chip 2311 may include multiple power transmission pins, such as power transmission pins A111, A112, and A113. The second power management chip 2312 may include multiple power transmission pins, such as power transmission pins A121, A122, and A123. In a specific example, to ensure stable voltage output, each power transmission pin may include a switching voltage pin, a startup voltage pin, and a feedback voltage pin. For example, using power transmission pins A111 and A121 as an example, they may include a switching voltage pin SWA, a startup voltage pin SWA_BOOT, and a feedback voltage pin SWA_FB_P. Taking the power transmission pins A112 and A122 as an example, they may include a switch voltage pin SWB, a startup voltage pin SWB_BOOT, and a feedback voltage pin SWB_FB_P. Taking the power transmission pins A113 and A123 as an example, they may include a switch voltage pin SWC, a startup voltage pin SWC_BOOT, and a feedback voltage pin SWC_FB_P.

[0077] Specifically, the i-th power transmission pins of the multiple power management chips are connected to provide the supply voltage output by the connected i-th power transmission pins to the multiple memory chips. Here, i is any integer less than or equal to N. Exemplarily, the i-th power transmission pin can be connected to the i-th first conductive line to provide the supply voltage output by the i-th power transmission pin to the multiple memory chips via the i-th first conductive line.

[0078] In one example, referring to Figure 4, the first power transmission pin A111 of the first power management chip 2311 is connected to the first power transmission pin A121 of the second power management chip 2312 to output the first power supply voltage VDD; the second power transmission pin A112 of the first power management chip 2311 is connected to the second power transmission pin A122 of the second power management chip 2312 to output the second power supply voltage VDDQ; the third power transmission pin A113 of the first power management chip 2311 is connected to the third power transmission pin A123 of the second power management chip 2312 to output the third power supply voltage VPP.

[0079] Through the embodiments of the present disclosure, N power transmission pins of multiple power management chips can be connected separately to provide N power transmission voltages to the memory chip through N power transmission pins, so that the power management device can achieve stable output of multiple power transmission voltages, thereby improving the power supply capacity of the power management device.

[0080] In some embodiments, FIG5 shows a schematic structural diagram of another exemplary press-fit memory module provided by an embodiment of the present disclosure. As shown in FIG5 , the first power supply pin A1 of one of the multiple power management chips 2311 to 231K (e.g., the first power management chip 2311) is directly connected to the first conductive line L1, and the first power supply pin A1 of the other power management chips 2311 to 231K (e.g., the second power management chips 2312 to 231K) is connected to the first conductive line L1 or the first power supply pin A1 of one of the power management chips (e.g., the first power management chip 2311) via a connector 232.

[0081] Through this embodiment, multiple power management chips 2311 to 231K can be connected to the first conductive line L1 through the connector 232, so that the power supply voltage that can meet the power requirements of the press-fit memory module can be output through the first conductive line L1, thereby ensuring the power supply quality of the power management device 23.

[0082] In one embodiment, the connector 232 may be an electrical element for electrical connection. For example, the connector 232 may include one or more of a resistor with a preset resistance, a connecting wire, a switch element, and a fuse.

[0083] Among them, for the resistor, it can be an electrical component with ohmic characteristics. For example, referring to Figure 3, the connector 232 can be the resistor R1 in Figure 3. For example, in order to improve the power supply quality, the preset resistance value of the resistor R1 can be 0ohm (ohm). It should be noted that the preset resistance value can also be selected from other resistance values ​​according to actual conditions and specific scenarios, and there is no specific limitation on this. And, it should also be noted that the 0ohm resistor in the embodiment of the present disclosure can refer to a resistor with a very small resistance value.

[0084] The connecting line may be a line that can electrically connect devices, such as a wire.

[0085] The switching element may be an electrical device that performs a switching function, for example, a semiconductor switch such as a metal-oxide semiconductor field-effect transistor (MOS), and is not specifically limited thereto. It should be noted that other electrical components capable of performing a switching function may also be used, and are not specifically limited thereto.

[0086] The fuse device may be an electrical component that switches between a low-resistance state and a high-resistance state through a fusing operation. For example, the fuse device may be a one-time programmable (OTP) device such as a fuse or an antifuse, without specific limitation.

[0087] This embodiment utilizes components such as resistors with preset resistance values, connecting wires, switching elements, and fuses to electrically connect multiple power management chips, thereby ensuring the power supply capability of the power management device 23. Alternatively, if the connector 232 includes a switching element and / or a fuse, flexible power supply for the power management device 20 can be achieved.

[0088] In one example, for each other power management chip, when the fuse device corresponding to each other power management chip is in a low-resistance state, each other power management chip supplies power to the multiple memory chips, and when the fuse device is in a high-resistance state, each other power management chip does not supply power to the multiple memory chips.

[0089] Through this example, flexible power supply of multiple power management chips can be achieved by controlling the resistance state of the fuse device.

[0090] In one specific example, the resistance state of the fuse components is adjusted by the tester when the actual number of power management chips being supplied is incorrect. For example, if, during chip testing, the actual number of power management chips is found to be inconsistent with the pre-designed number, the resistance state of each fuse component can be adjusted to bring the actual number of power management chips being supplied into line with the pre-designed number.

[0091] For example, referring to Figure 3, if the resistor R1 is a fuse device in a low-resistance state, the actual number of power management chips currently supplying power is 2. If the pre-designed number is 1, the fuse device can be adjusted to a high-resistance state through fusing. At this time, the second power management chip 2312 is disconnected from the power supply line. At this time, only the first power management chip 2311 supplies power to the memory. The actual number of power management chips currently supplying power is adjusted to 1, which is consistent with the pre-designed number.

[0092] For example, the test machine can determine whether there is an error in the actual quantity based on preset power quantity information, wherein the preset power quantity information is stored in the configuration serial detection chip and is used to indicate the number of power management chips in the power management device.

[0093] Among them, when the actual number is incorrect and the actual number is greater than the number indicated by the preset power quantity information, the test machine adjusts the first target fuse device to a high-impedance state to disconnect the power management chip corresponding to the first target fuse device from the power management device. Exemplarily, the power management chip corresponding to the first target fuse device can be selected arbitrarily from multiple power management chips, or selected according to a preset method, and there is no specific limitation on this. For example, if the actual number is 5 and the number indicated by the preset power quantity information is 3, then 2 power management chips can be selected from the 5 power management chips connected to the power management device as the power management chips corresponding to the first target fuse device, and disconnected from the power management device, so that the remaining 3 power management chips can supply power to the press-fit memory module.

[0094] When the actual number is incorrect and the actual number is less than the number indicated by the preset power quantity information, the test machine adjusts the fuse device to a low-resistance state to connect the power management chip corresponding to the second target fuse device to the power management device. Exemplarily, the power management chip corresponding to the second target fuse device can be selected arbitrarily from a plurality of power management chips, or selected according to a preset method, and there is no specific restriction on this. For example, if the actual number is 2 and the number indicated by the preset power quantity information is 3, then one power management chip can be selected from the power management chips that are not connected to the power management device as the power management chip corresponding to the second target fuse device to connect to the power management device, so that the two previously connected power management chips and the newly connected power management chip can jointly power the press-fit memory module.

[0095] Through the above example, when the actual number of power management chips supplied by the power management device is incorrect, the number of power management chips connected to the power management device can be adjusted according to the relationship between the preset power quantity information and the actual quantity. Therefore, when the power management device cannot normally supply power to the memory chip, the high and low resistance states of the fuse device are adjusted to enable the power management device to meet the power supply requirements of the memory chip, thereby improving the yield of the memory module.

[0096] Through this example, when the actual number of power management chips powered by the power management device is wrong, the error can be corrected through fuse processing in stages such as chip testing, thereby improving the power supply reliability of the power management device and further improving the yield of the press-fit memory module.

[0097] After introducing the specific structure of the power management device 23 through the above embodiment, the number of power management chips will be described next.

[0098] In terms of specific quantity, in some embodiments, the preset number of power management chips in the power management device 23 (i.e., the number N) can be any positive integer greater than or equal to 1, for example, 1 or 2. It should be noted that the preset number of power management chips in the embodiments of the present disclosure can be the number of power management chips on the power supply line connected to the power management device, that is, the number of power management chips used to power the memory chips.

[0099] In some embodiments, the preset number of power management chips in the power management device 23 may be determined by the module manufacturer. For example, the number of power management chips may be determined based on the power requirements of the memory chips.

[0100] In one embodiment, the module information of the press-fit memory module can be input into a preset chip quantity prediction model, and the prediction result output by the preset chip quantity prediction model can be determined as the preset number of power management chips. Exemplarily, the module information can be the configuration information of the module, such as the chip model of the module, the module model, the memory column (rank) information, the current parameters of the press-fit memory module, and the module capacity. It should be noted that other information can also be selected as configuration information according to the actual setting situation and the specific setting scenario, and there is no specific limitation on this. Exemplarily, the preset chip quantity prediction model can be a neural network model, a mathematical model, etc., and there is no specific limitation on it.

[0101] In another embodiment, the actual value of the module information of the press-fit memory module can be obtained. If the actual value of the module information is within a preset numerical range, the number of chips corresponding to the preset numerical range is determined as the preset number of power management chips. In one example, the current required for the press-fit memory module can be obtained. When the required current is less than or equal to a preset current threshold, the preset number of power management chips is 1. When the required current is greater than the preset current threshold, the preset number of power management chips is 2. For example, continuing with Figure 3 as an example, when the required current is less than or equal to the preset current threshold, that is, when the current required for the press-fit memory module is relatively small, only one current management chip is required for power supply. In this case, there is no need to weld resistor R1, nor is there a need to provide a second power management chip 2312. Furthermore, when the required current is greater than the preset current threshold, that is, when the current required for the press-fit memory module is relatively large, two current management chips are required for power supply. In this case, the first power management chip 2311 and the second power management chip 2312 can be welded together via resistor R1.

[0102] Through this embodiment, the preset number of power management chips can be accurately set, thereby improving the power supply accuracy and flexibility of the power management chips.

[0103] After introducing the number of power management chips in the power management device, the power supply method of the power management device will be specifically described.

[0104] In some embodiments, each power management chip is used to provide power to a portion of the plurality of memory chips. For example, the plurality of memory chips can be divided into M groups, with N power management chips corresponding one to each of the N groups of memory chips, and each power management chip is used to provide power to the corresponding group of memory chips.

[0105] For example, Figure 6 shows a schematic structural diagram of another exemplary press-fit memory module provided by an embodiment of the present disclosure. As shown in Figure 6, the first power management chip 2311 can provide power to the memory chips 22 in the first row, and the second power management chip 2312 can provide power to the memory chips 22 in the second row.

[0106] In one embodiment, multiple memory chips can be divided into multiple groups, and each group of memory chips belongs to a memory channel. Each power management chip corresponds to at least one memory channel, and each power management chip is used to provide power supply energy to the memory chips in the corresponding memory channel. For example, continuing with Figure 6 as an example, if the memory chips 22 in the first row belong to the first memory channel and the memory chips 22 in the second row belong to the second memory channel, the first power management chip 2311 can provide power supply energy for each memory chip 22 in the first memory channel, and the second power management chip 2312 can provide power supply energy for each memory chip in the second memory channel.

[0107] Since press-fit memory modules often have multiple independent memory channels, such as two independent DDR5 memory channels, through this embodiment, the memory chips in each memory channel of the press-fit memory module can be independently powered by one or more power management chips, thereby ensuring the power supply requirements of the press-fit memory module.

[0108] Through the embodiments of the present disclosure, each power management chip can be used to provide power to some of the multiple memory chips, thereby achieving accurate power supply to the press-fit memory module and improving power supply stability and reliability.

[0109] In other embodiments, the output terminals (such as the first power supply pin A1 ) of each power management chip of the plurality of power management chips may be connected together to supply power to each memory chip using the power of the plurality of power management chips.

[0110] The press-fit memory module provided by the embodiments of the present disclosure can flexibly set the preset number of power management chips in the power management device according to the power requirements of the memory chips, so that the electricity generated by the preset number of power management chips can flexibly meet the power requirements of a variety of press-fit memory modules, avoiding the occurrence of voltage drops caused by insufficient power supply. Furthermore, the technical solution provided by the embodiments of the present disclosure can achieve flexible power supply to the press-fit memory module while ensuring power supply stability, thereby enabling the press-fit memory module to have a power supply solution that suits itself.

[0111] Also, it should be noted that, considering that the press-fit memory module has two independent memory channels, its load is theoretically twice that of the small-outline dual in-line memory module. The power supply requirements of the press-fit memory module can be met by two memory management chips, avoiding the risk of voltage drop when the press-fit memory module is powered by the small-outline dual in-line memory module power supply solution, and achieving stable power supply to the press-fit memory module.

[0112] Also, it should be noted that, through the embodiments of the present disclosure, different flexible power supply schemes can be selected according to the module information of the press-fit memory module (such as the configuration information of the press-fit memory module, the capacity of the press-fit memory module), such as the optional power supply scheme of choosing whether to use 1 power management chip or 2 power management chips for power supply. For example, when there are fewer memory particles on the press-fit memory module, 1 power management chip can be used for power supply to reduce the cost of the press-fit memory module while meeting the power supply requirements. And, when there are more memory particles on the press-fit memory module, 2 power management chips can be used to reduce the voltage drop in extreme cases to improve the stability of the power supply.

[0113] FIG7 shows a schematic structural diagram of another compression-bonded memory module provided by an embodiment of the present disclosure. FIG7 differs from FIG2 in that the compression-bonded memory module may further include a serial detection chip 24 .

[0114] The serial detection chip 24 is configured to store preset power quantity information X1. The preset power quantity information X1 indicates the number of power management chips in the power management device 23. It should be noted that the preset power quantity information X1 may also include other power configuration information of the power management device 23, and this is not specifically limited.

[0115] Exemplarily, the configuration serial detection chip 24 may include at least one field for storing the preset power quantity information X1. Each field may include one or more bits. In the disclosed embodiment, the preset power quantity information X1 may be written into the at least one field. For example, the preset power quantity information X1 may be written into one bit of the configuration serial detection chip 24.

[0116] For example, if the preset power quantity information X1 is written into one bit, the first value of the bit indicates quantity 1 (i.e., the press-fit memory module is powered by one power management chip), and the second value of the bit indicates quantity 2 (i.e., the press-fit memory module is powered by two power management chips). One of the first value and the second value is 0, and the other is 1.

[0117] Through this embodiment, after the power configuration is performed, the number of power management chips in the power management device 23 can be stored in the preset power quantity information X1 of the configured serial detection chip 24 to accurately record the quantity information of the power management chips, which is convenient for subsequent power management.

[0118] In one embodiment, the preset power quantity information X1 can be written by the module manufacturer into the preset power quantity information X1 after the module manufacturer configures the power management chip of the power management device 23. For example, if the module manufacturer determines that the press-fit memory module requires one power management chip for power supply, one power management chip is set on the press-fit memory module (or multiple power management chips are set but only one power management chip is used for power supply), and 0 is written to the bit corresponding to the preset power quantity information X1; for another example, if the module manufacturer determines that the press-fit memory module requires two power management chips for power supply, two power management chips are set on the press-fit memory module, and the first power supply pins of the two power management chips are connected through a connector, and 1 is written to the bit corresponding to the preset power quantity information X1.

[0119] Through this embodiment, after the module manufacturer completes the configuration of the power management chip, the number of power management chips can be written into the preset power quantity information of the configuration serial detection chip, so that in the subsequent process of pressing the memory module, the accurate number of power management chips in the pressed memory module can be obtained based on the preset power quantity information, so that the pressed memory module can be accurately subsequently configured and tested, thereby improving the convenience and accuracy of the pressed memory module process.

[0120] In some embodiments, the power management chip includes a mode register, which is used to store the preset power configuration information of the power management chip to which it belongs. The preset power configuration information is obtained by the chip control device based on the preset power quantity information configured in the serial detection chip. For example, Figure 8 shows a structural schematic diagram of another exemplary power management chip provided by an embodiment of the present disclosure. As shown in Figure 8, the first power management chip 2311 may include a first mode register MR1, and the first mode register MR1 stores the preset power configuration information X21 of the first power management chip 2311. The second power management chip 2312 may include a second mode register MR2, and the second mode register MR2 stores the preset power configuration information X22 of the second power management chip 2312.

[0121] The preset power configuration information may refer to the power configuration information of the power management chip. For example, the preset power configuration information may include one or more of the following configuration information: overvoltage, overcurrent, overtemperature, power-on sequence, power-off sequence, etc. It should be noted that the preset power configuration information may also include other power information that needs to be configured, depending on the actual chip conditions and specific chip scenarios, and this is not specifically limited.

[0122] Exemplarily, the mode register may include at least one field for storing preset power configuration information. Each field may include one or more bits. In an embodiment of the present disclosure, the preset power configuration information may be written into the at least one field.

[0123] The chip control device may refer to a device having chip control functions. For example, the chip control device may be a host device, such as a system on a chip (SOC). It should be noted that the chip controller may also be other host devices such as a processor (Central Processing Unit, CPU), and this is not specifically limited.

[0124] In one embodiment, the chip control device may configure the preset power configuration information according to the provisions of a preset standard protocol and the quantity indicated by the preset power quantity information. The preset standard protocol may be a protocol that specifies a power management chip. For example, the preset standard protocol may be a Joint Electron Device Engineering Council (JEDEC) standard protocol.

[0125] It should be noted that, in the embodiment of the present disclosure, when there are multiple power management chips, the configuration information of the multiple power management chips may be the same or different, and there is no specific limitation on this.

[0126] In one embodiment, the chip management device can access the power management chip via a communication bus such as I2C and configure various information in the power management chip. Alternatively, the chip management device can configure a serial detection chip to achieve I2C communication with the power management chip and configure the power management chip by configuring the serial detection chip.

[0127] Through this embodiment, the chip control device configures the preset power configuration information of the power management chip based on the preset power quantity information in the configuration serial detection chip, thereby realizing accurate and flexible power configuration of the power management chip according to the number of power management chips, thereby improving the power supply reliability and power supply flexibility of the press-fit memory module.

[0128] In some embodiments, in order to realize the communication connection between the configuration serial detection chip and each power management chip, the configuration serial detection chip includes a first communication pin, and each power management chip includes a second communication pin. The first communication pin is respectively connected to the second communication pin of each power management chip to realize the communication connection between the serial detection chip and each power management chip. Exemplarily, the communication connection can be an I2C communication connection. It should be noted that other communication technologies that can realize communication between the power management chip and the configuration serial detection chip can also be selected according to the actual communication situation and specific communication scenario, such as I3C, SMBus and other serial communication connections, etc., and there is no specific limitation on this.

[0129] In one embodiment, continuing with Figure 3 as an example, the first communication pin B1 of the serial detection chip 24 can be connected to the second communication pin B2 of the first power management chip 2311 and the second communication pin B2 of the second power management chip 2312, respectively, to realize the local I2C communication connection between the serial detection chip 24 and the first power management chip 2311 and the second power management chip 2312.

[0130] In one example, Figure 9 shows a schematic diagram of the structure of another exemplary power management chip provided by an embodiment of the present disclosure. As shown in Figure 9, the first communication pin B1 of the serial detection chip 24 can include a first clock line pin LSCL and a first bidirectional data line pin LSDA; the second communication pin B2 of the first power management chip 2311 can include a second clock line pin SCL1 and a second bidirectional data line pin SDA1; and the second power management chip 2312 can include a third clock line pin SCL2 and a third bidirectional data line pin SDA2.

[0131] Specifically, the first clock line pin LSCL of the serial detection chip 24 can be connected to the second clock line pin SCL1 and the third clock line pin SCL2 respectively, and the first bidirectional data line pin LSDA can be connected to the second bidirectional data line pin SDA1 and the third bidirectional data line pin SDA2 respectively.

[0132] Through this embodiment, by configuring the first communication pin of the serial detection chip to be connected to the second communication pin of each power management chip, the communication connection between the serial detection chip and the power management chip can be configured, thereby facilitating various management operations such as power configuration on the power management chip.

[0133] In one embodiment, referring to FIG3 , the serial detection chip 24 may further include a third communication pin B0 to enable communication with the chip control device via the third communication pin B0 . For example, host I2C communication with the chip control device may be achieved.

[0134] Exemplarily, referring to FIG9 , the third communication pin B0 includes a fourth clock line pin HSCL and a fourth bidirectional data line pin HSDA, so as to implement I2C communication with the chip control device through the fourth clock line pin HSCL and the fourth bidirectional data line pin HSDA.

[0135] Through this embodiment, the communication connection between the chip control device and the configuration serial detection chip 24 can be realized through the third communication pin B0, so that the chip control device can communicate with each power management chip through the configuration serial detection chip 24, so that external devices such as the chip control device can perform power management operations such as chip configuration on each power management device.

[0136] After introducing the communication method of the press-fit memory module, the power supply method of the press-fit memory module will be introduced.

[0137] In some embodiments, the power management chip can also supply power to the configuration serial detection chip. Accordingly, the configuration serial detection chip 24 includes a first power pin, and each power management chip also includes a second power pin.

[0138] In the case where the power management device includes multiple power management chips, the second power supply pin of the target power management chip in the power management device is connected to the first power supply pin, and the second power supply pins of other power management chips in the power management device except the target power management chip are left vacant, so that the power output from the second power supply pin of the target power management chip is provided to the configured serial detection chip as the power supply power for the configured serial detection chip. Exemplarily, the target power management chip can be one or more of the power management devices. It should be noted that the target power management device can be selected according to the actual power supply situation and specific scenario, and there is no specific limitation on this.

[0139] In one example, FIG10 shows a schematic diagram of the structure of another exemplary power management chip provided by an embodiment of the present disclosure. As shown in FIG10 , the first power pin of the serial detection chip 24 may include an SPD power pin VDDSPD and an input / output power pin VIO, the second power pin of the first power management chip 2311 may include a power pin VOUT1 and a power pin VOUT2, and the second power pin of the second power management chip 2312 may include a power pin VOUT1 and a power pin VOUT2.

[0140] For example, when the first power management chip 2311 serves as the target power management chip and the second power management chip 2312 serves as the other power management chip, the power supply pin VOUT1 of the first power management chip 2311 is connected to the SPD power supply pin VDDSPD of the configuration serial detection chip 24 to provide the first power supply voltage Vddspd to the configuration serial detection chip 24. The power supply pin VOUT2 of the first power management chip 2311 is connected to the input / output power supply pin VIO of the configuration serial detection chip 24 to provide the second power supply voltage VDDIO to the configuration serial detection chip 24. Furthermore, the power supply pins VOUT1 and VOUT2 of the second power management chip 2312 remain unconnected. In this manner, the first power management chip 2311 can provide power to the configuration serial detection chip 24. The first power supply voltage Vddspd and the second power supply voltage VDDIO can be the power supply voltages required by the serial detection chip 24. For example, the first power supply voltage Vddspd can be 1.8V (volts), and the second power supply voltage VDDIO can be 1V. It should be noted that the first power supply voltage Vddspd and the second power supply voltage VDDIO may also be set to other voltage values ​​according to specific scenarios and actual requirements, and there is no specific limitation on this.

[0141] In this embodiment, the target power management chip can be used to power the configuration serial detection chip, thereby ensuring the normal operation of the configuration serial detection chip without an additional external power supply, thereby ensuring the normal operation of the entire press-fit memory module. Furthermore, by keeping other power management chips idle, energy waste in other power management chips is avoided, thereby improving the energy utilization efficiency of the power management chips.

[0142] In some embodiments, each power management chip includes a status signal pin. The status signal pin can indicate whether the working status of the power management chip is normal. Specifically, the status chip pin is used to output a first level indicating that each power management chip is normal or a second level indicating that each power management chip is faulty. One of the first level and the second level is a high level, and the other of the first level and the second level is a low level. For example, the first level can be a high level and the second level can be a low level. That is, when the power management chip is normal, its status signal pin is pulled high to a high level; when the power management chip fails, its status signal pin is pulled low to a low level. In one example, Figure 11 shows a schematic structural diagram of another exemplary power management chip provided in an embodiment of the present disclosure. As shown in Figure 11, the first power management chip 2311 may include a first status signal pin PWR_GOOD1, and the second power management chip 2312 may include a second status signal pin PWR_GOOD2. Taking the first power management chip 2311 as an example, when the first power management chip 2311 is normal, the first state signal pin PWR_GOOD1 outputs a high level; when the first power management chip 2311 fails, the first state signal pin PWR_GOOD1 outputs a low level.

[0143] In the case where the power management device includes multiple power management chips, the status signal pins of the multiple power management chips are connected to the status signal transmission line. In the case where the status signal pins of one or more power management chips output the second level, the level on the status signal transmission line is adjusted to the second level, and the second level on the status signal transmission line indicates a failure of the power management device. In one example, referring to Figure 11, the first status signal pin PWR_GOOD1 of the first power management chip 2311 and the second status signal pin PWR_GOOD2 of the second power management chip 2312 are both connected to the status signal transmission line L2. When the first power management chip 2311 and / or the second power management chip 2312 fails, the level on the status signal transmission line L2 is a low level; when the first power management chip 2311 and the second power management chip 2312 are both normal, the level on the status signal transmission line L2 is a high level.

[0144] In this embodiment, the status signal transmission line is adjusted to the first level when the status signal pins of each power management chip are at the first level; and the status signal transmission line is adjusted to the second level when the status signal pins of any one or more power management chips are at the second level. Since the first level indicates that the power management chip is normal and the second level indicates that the power management chip is faulty, accordingly, in the disclosed embodiment, when all the power management chips in the power management device are normal, the status signal transmission line can output the first level indicating that the power management device is normal; and when any one or more power management chips in the power management device are faulty, the status signal transmission line can output the second level indicating that the power management device is faulty. Thus, the output level of the status signal transmission line can accurately indicate the operating status of the power management device, facilitating accurate and rapid detection of fault conditions in the power management device. Furthermore, this can facilitate management and maintenance of the power management device during subsequent use, testing, and other processes when abnormalities are detected in the power management device.

[0145] In some embodiments, in order to facilitate the control of the power management chip, each power management chip includes an enable pin, which is used to turn on or off each power management chip. The enable pin of each power management chip is used to receive a control instruction sent by the chip control device. The control instruction is used to turn on or off each power management chip. It should be noted that the control instructions received by each power management chip may be the same or different, and there is no specific limitation on this. It should also be noted that in the embodiment of the present disclosure, the chip control device may send a control instruction directly to the enable pin, or send a control instruction to the enable pin under the forwarding of other devices or equipment, and there is no specific limitation on this.

[0146] In one example, FIG12 shows a schematic diagram of the structure of another exemplary power management chip provided by an embodiment of the present disclosure. As shown in FIG12, the first power management chip 2311 may include a first enable pin VR_EN1, and the second power management chip 2312 may include a second enable pin VR_EN2. The first enable pin VR_EN1 and the second enable pin VR_EN2 may receive a control instruction PWR_EN. For example, the control instruction PWR_EN may be a level signal, such as a high level indicating that the power management chip is turned on, and a low level indicating that the power management chip is turned off.

[0147] Through this embodiment, the chip control device can flexibly and accurately control the opening or closing of each power management chip through the enable pin of each power management chip, so that the power management device can be accurately controlled with the power management chip as the granularity, thereby improving the control accuracy. Furthermore, when the power supply requirements of some chips on the press-fit memory module change, the number of power management chips can be changed. For example, some power management chips can be turned off and the remaining power management chips can be used to power the press-fit memory module, taking into account the power supply accuracy and the rational use of electric energy, and improving the power supply flexibility. And, further, when the power management chip fails, each power management chip or the failed power management chip can be quickly turned off, thereby improving the safety of the power management device.

[0148] In some embodiments, to ensure proper communication of the power management device, each power management chip includes a communication address pin, which is used to indicate the communication address of each power management chip. The communication address pins of multiple power management chips correspond to different voltages, with different voltages representing different communication addresses. For example, different voltages can be applied to the communication address pins of different power management chips to represent different communication addresses of the power management chips.

[0149] In one example, Figure 13 shows a schematic diagram of the structure of another exemplary power management chip provided by an embodiment of the present disclosure. As shown in Figure 13, the first power management chip 2311 may include a first communication address pin PID1, and the second power management chip 2312 may include a second communication address pin PID2. The first communication address pin PID1 is grounded, and a preset power supply voltage is applied to the second communication address pin PID2. For example, the preset power supply voltage may be the second power supply voltage VDDIO.

[0150] Through this embodiment, by configuring different voltages for the communication address pins of the power management chip, different communication addresses can be configured for different power management chips in the same power management device, thereby enabling communication between the power management chips of the power management device.

[0151] In some embodiments, in addition to the pins described in conjunction with the above embodiments, the power management chip may further include one or more other pins. FIG14 shows a schematic diagram of the structure of another exemplary power management chip provided by an embodiment of the present disclosure. As shown in FIG14 , the power management chip may further include at least one of the following pins 1-8.

[0152] Pin 1, the power ground pin PGND, is used to form a discharge path for dangerous current in a high-power circuit. For example, referring to FIG14 , the power ground pin PGND is grounded.

[0153] Pin 2, analog ground pin AGND, is used to form a discharge path for the current of the analog signal. For example, referring to FIG14 , the analog ground pin AGND is grounded.

[0154] Pin 3, dummy pins NC, NC1-3, which are not connected to the internal functional circuit of the device. For example, referring to FIG14 , dummy pins NC, NC1-3 are grounded.

[0155] Pin 4, general status interrupt signal output pin GSI_n, which is used to output a general status interrupt signal. As shown in Figure 14, the general status interrupt signal output pin GSI_n may not be connected to the outside of the power management device. For example, the general status interrupt signal output pin GSI_n may be connected to a reference position point of a voltage divider structure. Exemplarily, the voltage divider structure may include a first voltage divider resistor Ra and a second voltage divider resistor Rb. One end of the first voltage divider resistor Ra is applied with a first power supply voltage Vddspd, the other end of the voltage divider Ra and one end of the second voltage divider resistor Rb are both connected to the reference position point, and the other end of the second voltage divider resistor Rb is grounded.

[0156] Pins 5-8, the first voltage input pin VIN_BULK_A, the second voltage input pin VIN_BULK_B, the third voltage input pin VIN_BULK_C, and the fourth voltage input pin VIN are respectively used to receive the input voltage VIN_BULK, so that the power management chip can generate supply voltages such as the first supply voltage VDD, the second supply voltage VDDQ, and the third supply voltage VPP based on the input voltage VIN_BULK.

[0157] In some embodiments, in addition to the pins shown in conjunction with the above embodiments, the serial detection chip may further include one or more other pins. Continuing to refer to FIG14 , the serial detection chip may further include at least one of pins 9-11.

[0158] Pin 9, address pin HSA.

[0159] Pin 10, ground pin Gnd.

[0160] Pin 11, Gnd / Thermal Pad. Still referring to FIG14 , Gnd / Thermal Pad is connected to ground.

[0161] To facilitate an overall understanding of the technical solutions provided by the embodiments of the present disclosure, Figure 15 shows a schematic diagram of the structure of an exemplary first power management chip provided by the embodiments of the present disclosure; Figure 16 shows a schematic diagram of the structure of an exemplary second power management chip provided by the embodiments of the present disclosure; and Figure 17 shows a schematic diagram of the structure of an exemplary serial detection chip provided by the embodiments of the present disclosure. The technical solutions provided by the embodiments of the present disclosure will now be described in conjunction with Figures 15-17.

[0162] As shown in Figures 15 and 16, in order to improve the quality of the input voltage VIN_BULK, the first power management chip also includes a first filtering unit Q1, and the second power management chip also includes a second filtering unit Q2. Exemplarily, the first filtering unit Q1 may include a plurality of capacitors in parallel, such as capacitors C3-C5 and capacitors C7-C14. For example, and again exemplarily, the second filtering unit Q2 may include a plurality of capacitors in parallel, such as capacitors C41-C51. Among them, for any one of the first filtering unit Q1 and the second filtering unit Q2, there are at least two types of capacitors with different capacitance in any one of the filtering units to achieve filtering of different frequencies such as high frequency and low frequency. It should be noted that each capacitor can also be selected as other parameters according to actual scenarios and specific requirements, and there is no specific restriction on its device parameters.

[0163] The first enable pin VR_EN1 of the first power management chip and the second enable pin VR_EN2 of the second power management chip can be connected together via resistor R111 to receive the control instruction PWR_EN_0. For example, to avoid power loss, resistor R111 can be 0 ohm. It should be noted that the resistance value of resistor R111 can also be selected as other parameters based on actual scenarios and specific requirements, and there is no specific limitation on its device parameters.

[0164] The first status signal pin PWR_GOOD1 of the first power management chip and the second status signal pin PWR_GOOD2 of the second power management chip can be connected together through a resistor R112 to output a status signal PWR_GOOD_0. For example, when the level signal on the first status signal pin PWR_GOOD1 and / or the level signal PWR_GOOD2_01 on the second status signal pin PWR_GOOD2 is low, the output status signal PWR_GOOD_0 is low. For example, in order to avoid power loss, the resistor R112 can be 0 ohm. It should be noted that the resistance value of the resistor R112 can also be selected as other parameters according to actual scenarios and specific requirements, and there is no specific restriction on its device parameters.

[0165] For the first power management chip and the second power management chip, their switching voltage pin SWA is connected to the startup voltage pin SWA_BOOT through capacitor C6 (or capacitor C36. It should be noted that for the sake of simplicity, different devices of the second power management chip and the first power management chip at the same position are output in brackets). The switching voltage pin SWA is connected to inductor L1 (or inductor L4), and the other end of inductor L1 (or inductor L4) is connected to the feedback voltage pin SWA_FB_P. For example, in order to improve the power transmission quality of the first power supply voltage V_MEM_VDD, the other end of inductor L1 (or inductor L4) is connected to capacitor C1, capacitor C2, capacitor C27, capacitor C28 (or capacitors C37-C40), respectively, and the other ends of capacitors C1, capacitor C2, capacitor C27, capacitor C28 (or capacitors C37-C40) are all grounded.

[0166] Furthermore, the switch voltage pin SWB is connected to the startup voltage pin SWB_BOOT via capacitor C15 (or capacitor C52). The switch voltage pin SWB is connected to inductor L2 (or inductor L5). The other end of inductor L2 (or inductor L5) is connected to the feedback voltage pin SWB_FB_P. For example, to improve the power transmission quality of the second supply voltage V_MEM_VDDQ, the other end of inductor L2 (or inductor L5) is connected to capacitors C16, C17, C29, and C30 (or capacitors C53-C56), respectively. The other ends of capacitors C16, C17, C29, and C30 (or capacitors C53-C56) are all grounded.

[0167] In addition, the switch voltage pin SWC is connected to the startup voltage pin SWC_BOOT through the capacitor C18 (or capacitor C57), the switch voltage pin SWC is connected to the inductor L3 (or inductor L6), and the other end of the inductor L3 (or inductor L6) is connected to the feedback voltage pin SWC_FB_P. For example, in order to improve the transmission quality of the third power supply voltage V_MEM_VPP, the other end of the inductor L3 (or inductor L6) is connected to the capacitor C19 and the capacitor C20 (or capacitor C58, capacitor C59), respectively, and the other ends of the capacitor C19 and the capacitor C20 (or capacitor C58, capacitor C59) are all grounded. It should be noted that each capacitor and inductor can also be selected as other parameters according to the actual scenario and specific requirements, and there is no specific limitation on its device parameters.

[0168] In addition, the general status interrupt signal output pin GSI_n of the first power management chip can be connected to one end of the resistor R105 and one end of the resistor R106 respectively, one end of the resistor R105 is used to receive the first power supply voltage Vddspd_1P8V, and the other end of the resistor R106 is grounded. The general status interrupt signal output pin GSI_n of the second power management chip can be connected to one end of the resistor R109 and one end of the resistor R110 respectively, one end of the resistor R109 is used to receive the first power supply voltage Vddspd_1P8V, and the other end of the resistor R110 is grounded. In one example, the resistance of the resistor R105 and the resistor R109 can be 1K (kilo ohm). In another example, the resistance of the resistor R106 and the resistor R110 can be 0ohm. It should be noted that each capacitor and capacitor can also be selected as other parameters according to actual scenarios and specific requirements, and there is no specific limitation on its device parameters.

[0169] Furthermore, for either the first power management chip or the second power management chip, its power supply pin VOUT_1.8V (also referred to as power supply pin VOUT1) can be grounded via capacitors C22 (capacitor C62) and C25 (capacitor C63), respectively; and its power supply pin VOUT_1.0V (also referred to as power supply pin VOUT2) can be grounded via capacitors C21 (capacitor C60) and C23 (capacitor C61), respectively. It should be noted that other parameters can be selected for each capacitor based on actual scenarios and specific requirements, and there is no specific limitation on their device parameters.

[0170] Also, referring to Figure 17 , the SPD power pin VDDSPD of the serial detection chip can be grounded via capacitor C26, and the input / output power pin VIO can be grounded via capacitor C24. It should be noted that the capacitors can also be selected to other parameters based on actual scenarios and specific requirements, and there are no specific restrictions on their device parameters.

[0171] It should be noted that, for other contents of the first power management chip, the second power management chip and the configuration serial detection chip, reference can be made to the relevant description of the above part of the embodiment of the present disclosure, which will not be repeated here.

[0172] Based on the same inventive concept, an embodiment of the present disclosure further provides a power management device, which is disposed on a press-fit memory circuit board of a press-fit memory module and is connected to a plurality of memory chips of the press-fit memory module.

[0173] Specifically, the power management device includes: a preset number of power management chips, which are used to provide the electric energy generated by the preset number of power management chips as power supply energy to the plurality of memory chips.

[0174] The preset number of power management chips in the power management device is related to the power requirements of the multiple memory chips.

[0175] In one embodiment, the power management device includes a plurality of power management chips.

[0176] The power management chip includes a first power supply pin, and the first power supply pins of the plurality of power management chips are connected to provide the power generated by the plurality of power management chips to the plurality of memory chips through the connected first power supply pins.

[0177] In one embodiment, the first power supply pin includes N power transmission pins, each power transmission pin is configured to output a power supply voltage.

[0178] The i-th power transmission pins of the plurality of power management chips are connected to provide the power supply voltage output by the connected i-th power transmission pins to the plurality of memory chips. N is an integer greater than or equal to 1, and i is any integer less than or equal to N.

[0179] In one embodiment, the power management chip further includes a mode register.

[0180] The mode register is used to store the preset power configuration information of the power management chip to which it belongs.

[0181] The preset power configuration information is obtained by the chip control device based on the preset power quantity information configured in the serial detection chip.

[0182] In one embodiment, when the serial detection chip is configured to include a first communication pin, each power management chip includes a second communication pin.

[0183] The first communication pin is connected to the second communication pin of each power management chip respectively, so as to configure the communication connection between the serial detection chip and each power management chip.

[0184] In one embodiment, the serial detection chip is configured to include a first power supply pin, and each power management chip further includes a second power supply pin.

[0185] In which, when the power management device includes multiple power management chips, the second power supply pin of the target power management chip in the power management device is connected to the first power supply pin, and the second power supply pins of other power management chips in the power management device except the target power management chip are left vacant, so that the electric energy output by the second power supply pin of the target power management chip can be provided to the configured serial detection chip as the power supply energy for the configured serial detection chip.

[0186] In one embodiment, each power management chip includes a status signal pin, and the status signal pin is used to output a first level indicating that each power management chip is normal or a second level indicating that each power management chip is faulty.

[0187] In which, when the power management device includes multiple power management chips, the status signal pins of the multiple power management chips are connected to the status signal transmission line. In which, when the status signal pins of one or more power management chips output the second level, the level on the status signal transmission line is adjusted to the second level, and the second level on the status signal transmission line indicates a failure of the power management device.

[0188] In one embodiment, each power management chip includes an enable pin, and the enable pin is used to start or shut down each power management chip.

[0189] The enable pin of each power management chip is used to receive a control instruction sent by the chip control device, and the control instruction is used to turn on or off each power management chip.

[0190] In one embodiment, each power management chip includes a communication address pin, which is used to indicate the communication address of each power management chip. The communication address pins of multiple power management chips correspond to different voltages, and different voltages represent different communication addresses.

[0191] In one embodiment, the first power supply pin of one of the multiple power management chips is directly connected to the first conductive line, and the first power supply pins of other power management chips among the multiple power management chips are connected to the first conductive line or the first power supply pin of one of the power management chips through a connector.

[0192] In one embodiment, the connecting member includes: one or more of a resistor with a preset resistance, a connecting line, a switching element, and a fuse device.

[0193] In one embodiment, the connector includes a fuse device, which is a fuse or an antifuse; wherein, for each other power management chip, when the fuse device corresponding to each other power management chip is in a low-resistance state, each other power management chip supplies power to multiple memory chips; when the fuse device is in a high-resistance state, each other power management chip does not supply power to multiple memory chips.

[0194] In one embodiment, the resistance state of the fuse device is adjusted by a tester when the actual number of the power management chips supplied is incorrect.

[0195] In one embodiment, a test machine determines whether there is an error in the actual quantity based on preset power quantity information, wherein the preset power quantity information is stored in a configuration serial detection chip and is used to indicate the number of power management chips in a power management device; wherein, when the actual quantity is wrong and the actual quantity is greater than the quantity indicated by the preset power quantity information, the test machine adjusts the first target fuse device to a high impedance state to disconnect the power management chip corresponding to the first target fuse device from the power management device; wherein, when the actual quantity is wrong and the actual quantity is less than the quantity indicated by the preset power quantity information, the test machine adjusts the fuse device to a low impedance state to connect the power management chip corresponding to the second target fuse device to the power management device.

[0196] In one embodiment, each power management chip is used to provide power to some of the memory chips.

[0197] In one embodiment, multiple memory chips can be divided into multiple groups, each group of memory chips belongs to a memory channel, each power management chip corresponds to at least one memory channel, and each power management chip is used to provide power to the memory chips in the corresponding memory channel.

[0198] The power management device provided by the embodiments of the present disclosure can flexibly set the preset number of power management chips in the power management device according to the power requirements of the memory chips, so that the electricity generated by the preset number of power management chips can flexibly meet the power requirements of a variety of press-fit memory modules, avoiding the occurrence of voltage drops due to insufficient power supply. Furthermore, the technical solution provided by the embodiments of the present disclosure can achieve flexible power supply to press-fit memory modules while ensuring power supply stability, thereby enabling press-fit memory modules to have a power supply solution that suits them.

[0199] It should be noted that the specific content of the power management device can be found in the above part of the embodiment of the present disclosure combined with the relevant description of Figures 2 to 17, and will not be repeated here.

[0200] Based on the same inventive concept, an embodiment of the present disclosure further provides a serial detection chip.

[0201] The serial detection chip is configured to store preset power quantity information, which is used to indicate the number of power management chips in the power management device, wherein the power management device is arranged on the press-fit memory circuit board of the press-fit memory module and is connected to multiple memory chips of the press-fit memory module. The power management device includes a preset number of power management chips, which are used to provide the electric energy generated by the preset number of power management chips as power supply energy to multiple memory chips, wherein the preset number of power management chips in the power management device is related to the power consumption requirements of multiple memory chips.

[0202] In one embodiment, the configuration serial detection chip includes a first communication pin, and each power management chip includes a second communication pin, wherein the first communication pin is respectively connected to the second communication pin of each power management chip to establish a communication connection between the configuration serial detection chip and each power management chip.

[0203] In one embodiment, the configuration serial detection chip includes a first power pin, and each power management chip also includes a second power pin; wherein, when the power management device includes multiple power management chips, the second power pin of the target power management chip in the power management device is connected to the first power pin, and the second power pins of other power management chips in the power management device except the target power management chip are left vacant, so that the electric energy output by the second power pin of the target power management chip is provided to the configuration serial detection chip as the power supply energy of the configuration serial detection chip.

[0204] The configuration serial detection chip provided in the embodiment of the present disclosure can flexibly set the preset number of power management chips in the power management device according to the power demand of the memory chip, so that the electric energy generated by the preset number of power management chips can flexibly meet the power demand of various press-fit memory modules, avoiding the occurrence of voltage drops due to insufficient power supply. Furthermore, the technical solution provided in the embodiment of the present disclosure can achieve flexible power supply to the press-fit memory module while ensuring power supply stability, so that the press-fit memory module can have a power supply solution suitable for itself. In addition, after the power supply configuration is performed, the number of power management chips in the power management device 23 can be stored in the preset power quantity information X1 of the configuration serial detection chip 24 to accurately record the quantity information of the power management chips, which is convenient for subsequent power management.

[0205] It should be noted that the specific content of configuring the serial detection chip can be found in the above part of the embodiment of the present disclosure in combination with the relevant description of Figures 2 to 17, and will not be repeated here.

[0206] Based on the same inventive concept, the present disclosure also provides an electronic device that can include the press-fit memory module provided by any of the above-mentioned embodiments of the present disclosure. The details of the press-fit memory module can be found in the description of the embodiments of the present disclosure in conjunction with Figures 2-17 , and will not be further elaborated.

[0207] Among them, the electronic device of the embodiment of the present disclosure can be an electronic device equipped with a memory. For example, the electronic device can be a mobile terminal, a computer, a server, a virtual reality device, an Internet of Things device, etc.

[0208] The electronic device provided by the embodiments of the present disclosure can flexibly set the preset number of power management chips in the power management device according to the power requirements of the memory chips, so that the electricity generated by the preset number of power management chips can flexibly meet the power requirements of a variety of press-fit memory modules, avoiding the occurrence of voltage drops due to insufficient power supply. Furthermore, the technical solution provided by the embodiments of the present disclosure can achieve flexible power supply to the press-fit memory modules while ensuring power supply stability, thereby enabling the press-fit memory modules to have a power supply solution that suits them.

[0209] In the description of this specification, the reference terms "some embodiments", "exemplarily", etc. mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0210] Although the embodiments of the present disclosure have been shown and described above, it is understood that the above embodiments are illustrative and cannot be understood as limitations on the present disclosure. A person skilled in the art may change, modify, replace and modify the above embodiments within the scope of the present disclosure. Therefore, any changes or modifications made in accordance with the claims and description of the present disclosure shall fall within the scope of the patent of the present disclosure.

Claims

1. A crimped memory module, the module comprising: Pressing the memory circuit board (21); A plurality of memory chips (22) are arranged on the compression memory circuit board; A power management device (23) is arranged on the crimped memory circuit board and is electrically connected to the multiple memory chips. The power management device includes a preset number of power management chips, which are used to provide the electric energy generated by the preset number of power management chips (2311...231K) as power supply energy to the multiple memory chips, wherein the preset number of power management chips in the power management device is preset according to the power consumption requirements of the multiple memory chips.

2. The module according to claim 1, wherein: The power management device includes multiple power management chips, wherein the power management chip includes a first power supply pin (A1), and the first power supply pins of the multiple power management chips are connected to provide the electric energy generated by the multiple power management chips to the multiple memory chips through the connected first power supply pins.

3. The module according to claim 2, wherein: The first power supply pin includes N power transmission pins, each power transmission pin (A111, A112, A113, A121, A122, A123) is used to output a power supply voltage, wherein the i-th power transmission pins of the multiple power management chips are connected to provide the power supply voltage output by the connected i-th power transmission pin to the multiple memory chips, wherein N is an integer greater than or equal to 1, and i is any integer less than or equal to N.

4. The module according to any one of claims 1 to 3, wherein: The module also includes: A serial detection chip (24) is configured to store preset power quantity information, wherein the preset power quantity information is used to indicate the quantity of power management chips in the power management device.

5. The module according to claim 4, wherein: The power management chip also includes mode registers (MR1, MR2), which are used to store preset power configuration information of the power management chip to which it belongs, wherein the preset power configuration information is configured by the chip control device based on preset power quantity information in the configuration serial detection chip.

6. The module according to claim 4, wherein: The configuration serial detection chip includes a first communication pin (B1), and each power management chip includes a second communication pin (B2), wherein the first communication pin is respectively connected to the second communication pin of each power management chip to establish a communication connection between the configuration serial detection chip and each power management chip.

7. The module according to claim 4, wherein: The configured serial detection chip includes a first power pin, and each power management chip also includes a second power pin; wherein, when the power management device includes multiple power management chips, the second power pin of the target power management chip in the power management device is connected to the first power pin, and the second power pins of other power management chips in the power management device except the target power management chip are left vacant, so that the electric energy output by the second power pin of the target power management chip can be provided to the configured serial detection chip as the power supply electric energy of the configured serial detection chip.

8. The module according to any one of claims 1 to 7, wherein: Each power management chip includes a status signal pin, and the status signal pin is used to output a first level indicating that each power management chip is normal or a second level indicating that each power management chip is faulty. When the power management device includes multiple power management chips, the status signal pins of the multiple power management chips are connected to a status signal transmission line (L2). When the status signal pins of one or more power management chips output the second level, the level on the status signal transmission line is adjusted to the second level, and the second level on the status signal transmission line indicates a fault in the power management device.

9. The module according to any one of claims 1 to 8, wherein: Each power management chip includes an enable pin, which is used to start or shut down each power management chip, wherein the enable pin of each power management chip is used to receive a control instruction sent by a chip control device, and the control instruction is used to start or shut down each power management chip.

10. The module according to any one of claims 1 to 9, wherein: Each power management chip includes a communication address pin, and the communication address pin is used to indicate the communication address of each power management chip, wherein the communication address pins of the multiple power management chips correspond to different voltages, and the different voltages represent different communication addresses.

11. The module according to claim 2, wherein: A first power supply pin of one of the multiple power management chips is directly connected to a first conductive line (L1), and a first power supply pin of another power management chip of the multiple power management chips is connected to the first conductive line or the first power supply pin of one of the power management chips through a connector (232).

12. The module according to claim 11, wherein: The connecting member comprises: one or more of a resistor with a preset resistance, a connecting line, a switching element and a fuse device.

13. The module according to claim 11, wherein: The connecting member includes a fuse device, and the fuse device is a fuse or an anti-fuse; Wherein, for each other power management chip, when the fuse device corresponding to each other power management chip is in a low resistance state, each other power management chip supplies power to the multiple memory chips; When the fuse device is in a high impedance state, each of the other power management chips does not supply power to the multiple memory chips. electricity.

14. The module according to claim 13, wherein: The resistance state of the fuse device is adjusted by the test machine when the actual number of the power management chips supplied with power is wrong.

15. The module according to claim 14, wherein: The test machine determines whether the actual quantity has an error based on preset power quantity information, wherein the preset power quantity information is stored in a configuration serial detection chip and is used to indicate the quantity of the power management chips in the power management device; Wherein, when the actual number is wrong and the actual number is greater than the number indicated by the preset power quantity information, the test machine adjusts the first target fuse device to a high impedance state to disconnect the power management chip corresponding to the first target fuse device from the power management device; When the actual number is wrong and is less than the number indicated by the preset power quantity information, the test machine adjusts the fuse device to a low resistance state to connect the power management chip corresponding to the second target fuse device to the power management device.

16. The module according to any one of claims 1 to 15, wherein: Each of the power management chips is used to provide power supply energy to some of the memory chips.

17. The module according to claim 16, wherein: The multiple memory chips can be divided into multiple groups, each group of memory chips belongs to one memory channel, each power management chip corresponds to at least one memory channel, and each power management chip is used to provide power supply energy to the memory chips in the corresponding memory channel.

18. An electronic device, wherein: include: A crimped memory module as claimed in any one of claims 1 to 17.

Images