Data reception apparatus

Abstract

Provided in the present disclosure is a data reception apparatus used in wired high-speed data transmission. The data reception apparatus according to the present disclosure comprises: a first conversion unit, configured to convert an input serial signal into a first parallel signal by means of analog equalization; a second conversion unit, configured to convert the input serial signal into a second parallel signal by means of digital equalization; and a selection unit, configured to select one of the first parallel signal and the second parallel signal as an output parallel signal according to a preset condition. The data reception apparatus according to the present disclosure can choose to perform an equalization operation on an input serial signal in an analog mode or a digital mode according to at least one of a Nyquist frequency, a modulation mode, a bit error rate, etc., which are used as preset conditions, so that a balance of performance and power consumption is implemented in a single data reception apparatus.

Description

Data receiving device Technical Field

[0001] The present disclosure relates to the technical field of data processing, and in particular, to a data receiving device used in wired high-speed data transmission. Background Art

[0002] In existing high-speed data receiving devices for wired data transmission, a single equalizer cannot simultaneously meet the requirements of high performance and low power consumption, especially when the Nyquist frequency range of the high-speed input signal is large, or when multiple modulation modes need to be supported, or when the insertion loss of the transmission channel is unknown.

[0003] The above information disclosed in this Background section is only for understanding the background of the present inventive concept and therefore it may contain information that does not constitute prior art. Summary of the Invention

[0004] In order to solve the above problems existing in the prior art, the present disclosure proposes a new high-speed data receiving device.

[0005] According to one aspect of the present disclosure, a data receiving device is provided, which includes: a first conversion unit configured to convert an input serial signal into a first parallel signal through analog equalization; a second conversion unit configured to convert the input serial signal into a second parallel signal through digital equalization; and a selection unit configured to select one of the first parallel signal and the second parallel signal as an output parallel signal according to a preset condition.

[0006] According to the data receiving device of the present disclosure, the data receiving device can choose to perform an equalization operation on the input serial signal in an analog manner or a digital manner according to at least one of the Nyquist frequency, modulation mode, and bit error rate as preset conditions, thereby achieving a balance between performance and power consumption in a single data receiving device.

[0007] However, the effects of the present disclosure are not limited to the above effects, and various extensions can be made without departing from the spirit and scope of the present disclosure. It should be understood that both the foregoing general description and the following detailed description are exemplary and explanatory, and are intended to provide further explanation of the present disclosure as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the disclosure and, together with the description, serve to explain the inventive concept.

[0009] FIG. 1 is a diagram illustrating a configuration of a data receiving device according to an embodiment of the present disclosure.

[0010] FIG. 2 is a diagram illustrating a more detailed configuration of a data receiving device according to an embodiment of the present disclosure.

[0011] FIG3 is a diagram illustrating a configuration of a front-end equalizing unit according to an embodiment of the present disclosure.

[0012] FIG. 4 is a diagram illustrating a configuration of a first equalizing subunit according to an embodiment of the present disclosure.

[0013] FIG. 5 is a diagram illustrating a configuration of an analog-to-digital conversion subunit according to an embodiment of the present disclosure.

[0014] FIG6 is a diagram illustrating a configuration of a second equalizing subunit according to an embodiment of the present disclosure.

[0015] FIG. 7 is a diagram illustrating a configuration of a selection unit according to an embodiment of the present disclosure.

[0016] FIG. 8 is a diagram illustrating a configuration of a selection unit according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0017] In the following description, for the purpose of illustration, many specific details are set forth in order to provide a thorough understanding of each exemplary embodiment of the present disclosure. As used herein, an "embodiment" is a non-limiting example of a device or method using one or more inventive concepts disclosed herein. However, it is apparent that each exemplary embodiment can be implemented without these specific details or with one or more equivalent configurations. In addition, each exemplary embodiment can be different, but does not have to be exclusive. For example, without departing from the present invention, the specific features of other exemplary embodiments can be used or implemented in some exemplary embodiments.

[0018] Unless otherwise specified, the exemplary embodiments described should be understood as providing exemplary features of varying details of some ways in which the present invention can be implemented in practice. Therefore, unless otherwise specified, the features, components, modules, regions, and / or aspects of the various embodiments (hereinafter individually or collectively referred to as "elements") may be combined, separated, interchanged, and / or reconfigured without departing from the present invention.

[0019] For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0020] Although terms such as "first" and "second" may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element.

[0021] The terms used herein are for the purpose of describing specific embodiments and are not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. In addition, when used in this specification, the terms "comprises" and / or "includes" mean the presence of the stated features, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof.

[0022] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0023] The various embodiments of the present disclosure will now be described more fully below with reference to the accompanying drawings. However, the present disclosure can be implemented in many different ways and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be exhaustive and complete and will fully convey the scope of the present disclosure to those skilled in the art. Throughout, the same reference numerals represent the same components.

[0024] In wired high-speed data transmission, the data receiver must accurately receive high-speed input signals. Insertion loss of high-speed input serial signals in the transmission channel is typically compensated for by an equalizer within the high-speed data receiver. The continuous-time linear equalizer (CTLE), a linear equalizer composed of analog circuits, offers a simple structure and low power consumption, but its equalization capabilities are limited. Furthermore, the analog decision feedback equalizer (Analog DFE), a nonlinear equalizer, can effectively reduce inter-symbol interference (ISI) during transmission.

[0025] In many applications, to improve equalization performance, a continuous-time linear equalizer and an analog decision feedback equalizer are connected in series and used simultaneously. As the Nyquist frequency of high-speed input signals increases, the timing requirements of the feedback loop in the analog decision feedback equalizer become increasingly difficult to meet. To reduce the Nyquist frequency, high-speed wired transmission often uses Pulse-Amplitude Modulation N-Level (PAM-N) modulation. For example, the Nyquist frequency of PAM-4 modulation is half that of Non-Return-to-Zero (NRZ) modulation, thus easing the timing requirements of the feedback loop in the analog decision feedback equalizer. However, PAM-4's high-speed input signal consists of four signal levels, compared to the two signal levels of NRZ modulation, which increases the complexity of the analog decision feedback equalizer circuitry.

[0026] With advances in semiconductor technology, digital circuits have grown in size and processing power, enabling high-speed signals to be equalized using digital equalizers. Digital equalizers can be implemented not only as digital decision feedback equalizers (DFEs) but also as digital feed-forward equalizers (FFEs), further enhancing equalization capabilities. Furthermore, as power supply voltages decrease, digital equalizer power consumption also decreases. Consequently, digital equalizers have replaced analog decision feedback equalizers in some applications. It's important to note that digital equalizers require analog-to-digital converters to convert high-speed analog signals into digital signals.

[0027] While both analog decision feedback equalizers and digital equalizers can reduce intersymbol interference (ISI) during transmission, their operating principles differ. First, the analog decision feedback equalizer circuit is relatively simple, especially in NRZ modulation mode, resulting in low power consumption. In contrast, the digital equalizer, combined with the required high-speed analog-to-digital converter, is relatively complex, especially in less advanced semiconductor processes, such as those greater than 14 nm. This results in high power consumption. Second, powerful digital signal processing enables digital equalizers to outperform analog decision feedback equalizers, thus overcoming greater insertion loss in the transmission channel. Furthermore, analog decision feedback equalizers operate at the Nyquist frequency, requiring their feedback loop to meet stringent timing requirements, making them unsuitable for operation at extremely high Nyquist frequencies. In contrast, the digital equalizer's input signal is a digital signal generated by a high-speed analog-to-digital converter. Its operating frequency can be lower than the Nyquist frequency of the high-speed input signal, making the feedback loop's timing requirements more easily met.

[0028] In some applications, high-speed data receivers need to operate within a wide Nyquist frequency range. They also need to support multiple modulation modes. Furthermore, they cannot predict the insertion loss in the transmission channel. When the insertion loss in the transmission channel is high, continuous-time linear equalizers or analog decision feedback equalizers struggle to meet the receiver's performance requirements and overcome all channel attenuation. In these cases, digital equalizers are more capable of meeting performance requirements, but they typically consume more power. When the Nyquist frequency is low, the modulation mode is simple (such as NRZ), or the transmission channel insertion loss is low, continuous-time linear equalizers or analog decision feedback equalizers can meet the performance requirements of high-speed data receivers. Using a digital equalizer in these situations would incur additional power consumption.

[0029] Therefore, a high-speed data receiving device needs to balance the contradiction between performance and power consumption. To this end, the present disclosure proposes a data receiving device that can achieve a balance between performance and power consumption.

[0030] The data receiving device of the present disclosure will be described in more detail below with reference to the accompanying drawings and in combination with specific embodiments.

[0031] Fig. 1 is a diagram showing a configuration of a data receiving device 10 according to an embodiment of the present disclosure. In addition, Fig. 2 is a diagram showing a more detailed configuration of the data receiving device 10 according to an embodiment of the present disclosure.

[0032] 1 , according to an embodiment of the present disclosure, a data receiving device 10 may include: a first conversion unit 700 that converts an input serial signal 11 into a first parallel signal 61 through analog equalization; a second conversion unit 800 that converts the input serial signal 11 into a second parallel signal 62 through digital equalization; and a selection unit 600 that selects one of the first parallel signal 61 and the second parallel signal 62 as an output parallel signal 63 according to a preset condition.

[0033] In addition, as shown in FIG2 , according to an embodiment of the present disclosure, the data receiving device 10 may further include a front-end equalizing unit 100, which performs an analog equalization operation on the input serial signal 11 to generate a front-end equalized serial signal 12, and provides the front-end equalized serial signal 12 to the first conversion unit 700 and the second conversion unit 800, respectively. The front-end equalizing unit 100 will be described in more detail below with reference to FIG3 .

[0034] As shown in FIG2 , according to an embodiment of the present disclosure, the first conversion unit 700 may include: a first equalization subunit 200 that performs an analog equalization operation on the front-end equalized serial signal 12 to generate a first equalized serial signal 31; and a serial-to-parallel conversion subunit 300 that performs a serial-to-parallel conversion operation on the first equalized serial signal 31 to output a first parallel signal 61. The first equalization subunit 200 will be described in more detail below with reference to FIG4 .

[0035] Those skilled in the art will recognize that the first equalization subunit 200 is optional and not necessary. In other words, in certain embodiments of the present disclosure, when the data receiving device 10 includes the front-end equalization unit 100 , the first equalization subunit 200 may be omitted.

[0036] Furthermore, as shown in FIG2 , according to an embodiment of the present disclosure, the second conversion unit 800 may include: an analog-to-digital conversion subunit 400 that converts the front-end equalized serial signal 12 into a digital conversion signal 51; and a digital equalization subunit 500 that performs a digital equalization operation on the digital conversion signal 51 to output a second parallel signal 62. The analog-to-digital conversion subunit 400 and the digital equalization subunit 500 will be described in more detail below with reference to FIG5 and FIG6 , respectively.

[0037] FIG3 is a diagram showing a configuration of the front-end equalizing unit 100 according to an embodiment of the present disclosure.

[0038] As shown in FIG3 , according to an embodiment of the present disclosure, the front-end equalizing unit 100 may be implemented by an analog front-end equalizer, which may include a continuous time linear equalizer (CTLE) 101 and a variable gain amplifier (VGA) 102 .

[0039] According to an embodiment of the present disclosure, the continuous-time linear equalizer 101 can receive a high-speed input serial signal 11, perform a linear equalization operation on the input serial signal 11, and provide an output signal to the variable gain amplifier 102. According to an embodiment of the present disclosure, the variable gain amplifier 102 can perform a gain amplification or gain reduction operation on the output signal of the continuous-time linear equalizer 101 to control the amplitude of the front-end equalized serial signal 12 as its output.

[0040] Alternatively, according to an embodiment of the present disclosure, the front-end equalization unit 100 may include a continuous-time linear equalizer 101 without including the variable gain amplifier 102. In this alternative embodiment, the continuous-time linear equalizer 101 may perform a linear equalization operation on the input serial signal 11, and the front-end equalizes the serial signal 12.

[0041] Alternatively, according to an embodiment of the present disclosure, the variable gain amplifier 102 may receive a high-speed input serial signal 11, i.e., first perform a gain amplification or gain reduction operation on the input serial signal 11 to control the amplitude of its output, and provide its output signal to the continuous time linear equalizer 101. According to this alternative embodiment, the continuous time linear equalizer 101 may then perform a linear equalization operation on the output signal of the variable gain amplifier 102 and output it as the front-end equalized serial signal 12.

[0042] According to an embodiment of the present disclosure, the front-end equalizing unit 100 may include a cascade of multiple continuous-time linear equalizers 101 .

[0043] Furthermore, according to an embodiment of the present disclosure, the front-end equalizing unit 100 may include a cascade of multiple variable gain amplifiers 102 .

[0044] FIG4 is a diagram showing a configuration of the first equalizing subunit 200 according to an embodiment of the present disclosure.

[0045] As shown in FIG. 4 , according to an embodiment of the present disclosure, the first equalization subunit 200 may be implemented by an analog decision feedback equalizer, which may include a first amplifier 201 and a pre-decision analog decision feedback equalizer 202 .

[0046] According to an embodiment of the present disclosure, as shown in FIG4 , the first amplifier 201 may receive the front-end equalized serial signal 12 and perform a gain amplification or gain reduction operation on the front-end equalized serial signal 12 to control the amplitude of the first amplified signal 23 as its output.

[0047] According to an embodiment of the present disclosure, as shown in FIG4 , the first amplifier 201 may further receive a first enable signal 21, and the first enable signal 21 may control the operation enable of the first amplifier 201. Specifically, for example, when the first enable signal 21 is at a high level, the first amplifier 201 may operate normally, and when the first enable signal 21 is at a low level, the first amplifier 201 may not operate.

[0048] According to an embodiment of the present disclosure, as shown in Figure 4, the first amplified signal 23 can be provided to the pre-judgment analog decision feedback equalizer 202, which performs an analog decision feedback equalization operation on the first amplified signal 23 to output a high-speed equalized signal 31.

[0049] According to an embodiment of the present disclosure, as shown in Figure 4, the predictive analog decision feedback equalizer 202 can be a full-speed second-order predictive analog decision feedback equalizer supporting NRZ modulation mode, which includes three summers (i.e., a first summer, a second summer, and a third summer), three triggers (i.e., a first trigger, a second trigger, and a third trigger), a selector, and a multiplier.

[0050] According to an embodiment of the present disclosure, as shown in FIG4 , the first-order coefficient of the pre-judgment analog decision feedback equalizer 202 is h1, and the second-order coefficient is h2, where h2 is the multiplication coefficient of the multiplier.

[0051] According to an embodiment of the present disclosure, as shown in Figure 4, the predictive analog decision feedback equalizer 202 may include three summers, wherein the first summer sums the positive prediction of the coefficient h1, the second summer sums the negative prediction of the coefficient h1, and the third summer sums the feedback of the coefficient h2.

[0052] According to an embodiment of the present disclosure, as shown in Figure 4, the first amplified signal 23 can be input into the third summer, and the high-speed equalized signal 31 is also input into the third summer after feedback of the coefficient h2, and is summed with the first amplified signal 23. The result of the third summer is input into the first summer and the second summer.

[0053] According to an embodiment of the present disclosure, as shown in FIG4 , the first summer sums the result of the third summer and the positive prediction of the coefficient h1 and outputs the result to the first flip-flop.

[0054] According to an embodiment of the present disclosure, as shown in FIG4 , the second summer sums the result of the third summer and the negative prediction of the coefficient h1 , and outputs the result to the second flip-flop.

[0055] According to an embodiment of the present disclosure, as shown in FIG4 , the first flip-flop and the second flip-flop are connected to a selector, which selects one of the results of the first flip-flop or the second flip-flop based on a high-speed equalized signal 31 and outputs it to a third flip-flop. According to an embodiment of the present disclosure, the output of the third flip-flop is the high-speed equalized signal 31.

[0056] According to an embodiment of the present disclosure, as shown in FIG4 , the first, second, and third flip-flops can each be connected to a first clock signal 22. According to an embodiment of the present disclosure, the first clock signal 22 can be generated by a clock data recovery (CDR) unit (not shown). This CDR unit can receive the output parallel signal 63 of the data receiving device 10 according to the present disclosure and recover the first clock signal 22 therefrom. According to an embodiment of the present disclosure, when the first clock signal 22 is at a high level, the first, second, and third flip-flops can sample their inputs. Since clock data recovery units are well known to those skilled in the art, for the sake of brevity, their details will not be described in further detail herein.

[0057] According to an embodiment of the present disclosure, as shown in FIG4 , the first, second, and third summers can each be connected to a first enable signal 21, which controls the operation of the three summers. For example, when the first enable signal 21 is high, the three summers all operate normally, and when the first enable signal 21 is low, the three summers all do not operate.

[0058] According to an embodiment of the present disclosure, the first equalization subunit 200 may include only the pre-determined analog decision feedback equalizer 202 without the first amplifier 201. In this alternative embodiment, the pre-determined analog decision feedback equalizer 202 may directly receive the front-end equalized serial signal 12.

[0059] According to an embodiment of the present disclosure, the first equalizing subunit 200 may include a cascade of multiple first amplifiers 201 .

[0060] Those skilled in the art will appreciate that the first equalization subunit 200 is not limited to being implemented using an analog decision feedback equalizer, that is, not limited to using an analog decision feedback equalizer method. For example, the prejudgment analog decision feedback equalizer 202 can be a first-order or multi-order analog decision feedback equalizer. Furthermore, for example, the prejudgment analog decision feedback equalizer 202 can be a first-order or multi-order analog decision feedback equalizer that supports the PAM-N modulation mode.

[0061] FIG5 is a diagram showing a configuration of the analog-to-digital conversion subunit 400 according to an embodiment of the present disclosure.

[0062] As shown in FIG. 5 , according to an embodiment of the present disclosure, the analog-to-digital conversion subunit 400 may be implemented by the analog-to-digital conversion subunit 400 , which may include a second amplifier 401 , a time-interleaved ADC 402 , and a clock signal generator 403 .

[0063] According to an embodiment of the present disclosure, as shown in FIG5 , the second amplifier 401 may receive the front-end equalized serial signal 12 and perform a gain amplification or gain reduction operation on the front-end equalized serial signal 12 to control the amplitude of the second amplified signal 43 as its output.

[0064] According to an embodiment of the present disclosure, as shown in FIG5 , the second amplifier 401 may further receive a second enable signal 41, and the second enable signal 41 may control the operation enable of the second amplifier 401. Specifically, for example, when the second enable signal 41 is at a high level, the second amplifier 401 may operate normally, and when the second enable signal 41 is at a low level, the second amplifier 401 may not operate.

[0065] According to an embodiment of the present disclosure, as shown in FIG5 , the clock signal generator 403 may generate a clock signal required by the interleaved sampling analog-to-digital converter 402 .

[0066] According to an embodiment of the present disclosure, as shown in FIG5 , a clock signal generator 403 may receive a second enable signal 41 and a second clock signal 42. According to an embodiment of the present disclosure, the second clock signal 42 may also be generated by a clock data recovery (CDR) unit (not shown), which may receive the output parallel signal 63 of the data receiving apparatus 10 according to the present disclosure and recover the second clock signal 42 therefrom. The clock signal generator 403 may generate a first sampling clock signal 44, a second sampling clock signal 45, a third sampling clock signal 46, a fourth sampling clock signal 47, and a synchronization clock signal 48 based on the second enable signal 41 and the second clock signal 42.

[0067] For example, as shown in the timing diagram at the bottom of FIG5 , when the second enable signal 41 is at a low level, the first sampling clock signal 44 , the second sampling clock signal 45 , the third sampling clock signal 46 , the fourth sampling clock signal 47 and the synchronization clock signal 48 are all at a low level.

[0068] In addition, as shown in the timing diagram at the bottom of FIG5 , when the second enable signal 41 is at a high level, the frequencies of the first sampling clock signal 44, the second sampling clock signal 45, the third sampling clock signal 46, the fourth sampling clock signal 47, and the synchronous clock signal 48 generated by the clock signal generator 403 are four times the frequency of the second clock signal 42, wherein the high levels of the first sampling clock signal 44, the second sampling clock signal 45, the third sampling clock signal 46, and the fourth sampling clock signal 47 do not overlap with each other.

[0069] According to an embodiment of the present disclosure, as shown in FIG5 , the second amplified signal 43 may be input to an interleaved sampling analog-to-digital converter 402 .

[0070] According to an embodiment of the present disclosure, as shown in FIG5 , the interleaved sampling analog-to-digital converter 402 may also receive a second enable signal 41. For example, when the second enable signal 41 is at a high level, the interleaved sampling analog-to-digital converter 402 may operate normally, i.e., perform interleaved sampling on the second amplified signal 43 and convert the sampled signal into a digital conversion signal 51. When the second enable signal 41 is at a low level, the interleaved sampling analog-to-digital converter 402 may not operate.

[0071] According to an embodiment of the present disclosure, as shown in FIG5 , the interleaved sampling analog-to-digital converter 402 may include four sample-and-hold units (S / Hs), namely, a first S / H, a second S / H, a third S / H, and a fourth S / H. Furthermore, according to an embodiment of the present disclosure, as shown in FIG5 , the interleaved sampling analog-to-digital converter 402 may also include four sub-analog-to-digital converters (ADCs), namely, a first ADC, a second ADC, a third ADC, and a fourth ADC. Furthermore, according to an embodiment of the present disclosure, as shown in FIG5 , the interleaved sampling analog-to-digital converter 402 may also include a synchronizer.

[0072] According to an embodiment of the present disclosure, the interleaved sampling analog-to-digital converter 402 performs interleaved sampling on the second amplified signal 43 when the first sampling clock signal 44 is at a high level, the second sampling clock signal 45 is at a high level, the third sampling clock signal 46 is at a high level, and the fourth sampling clock signal 47 is at a high level.

[0073] According to an embodiment of the present disclosure, as shown in FIG5 , the first S / H receives the second amplified signal 43, samples the second amplified signal 43 when the first sampling clock signal 44 is at a high level, and holds the sampling result of the first S / H when the first sampling clock signal 44 is at a low level. According to an embodiment of the present disclosure, as shown in FIG5 , the output of the first S / H is provided to the first ADC, which also receives the reference voltage vref and the first sampling clock signal 44. The first ADC performs analog-to-digital conversion on the output of the first S / H and outputs the result to the synchronizer when the first sampling clock signal 44 is at a high level.

[0074] According to an embodiment of the present disclosure, as shown in FIG5 , the second S / H receives the second amplified signal 43, samples the second amplified signal 43 when the second sampling clock signal 45 is at a high level, and holds the sampling result of the second S / H when the second sampling clock signal 45 is at a low level. According to an embodiment of the present disclosure, as shown in FIG5 , the output of the second S / H is provided to the second ADC, which also receives the reference voltage vref and the second sampling clock signal 45. The second ADC performs analog-to-digital conversion on the output of the second S / H and outputs the result to the synchronizer when the second sampling clock signal 45 is at a high level.

[0075] According to an embodiment of the present disclosure, as shown in FIG5 , the third S / H receives the second amplified signal 43, samples the second amplified signal 43 when the third sampling clock signal 46 is at a high level, and holds the sampling result of the third S / H when the third sampling clock signal 46 is at a low level. According to an embodiment of the present disclosure, as shown in FIG5 , the output of the third S / H is provided to the third ADC. The third ADC also receives the reference voltage vref and the third sampling clock signal 46. The third ADC performs analog-to-digital conversion on the output of the third S / H and outputs the result to the synchronizer when the third sampling clock signal 46 is at a high level.

[0076] According to an embodiment of the present disclosure, as shown in FIG5 , the fourth S / H receives the second amplified signal 43, samples the second amplified signal 43 when the fourth sampling clock signal 47 is at a high level, and holds the sampling result of the fourth S / H when the fourth sampling clock signal 47 is at a low level. According to an embodiment of the present disclosure, as shown in FIG5 , the output of the fourth S / H is provided to the fourth ADC, which also receives the reference voltage vref and the fourth sampling clock signal 47. The fourth ADC performs analog-to-digital conversion on the output of the fourth S / H and outputs the result to the synchronizer when the fourth sampling clock signal 47 is at a high level.

[0077] According to an embodiment of the present disclosure, as shown in FIG5 , a synchronizer is connected to the first ADC, the second ADC, the third ADC, the fourth ADC, and the synchronization clock signal 48, performs synchronization operations on the outputs of the first ADC, the second ADC, the third ADC, and the fourth ADC, and generates a digital conversion signal 51 when the synchronization clock signal 48 is at a rising edge. According to an embodiment of the present disclosure, the digital conversion signal 51 can be a four-frequency digital signal equivalent to the front-end equalized serial signal 12.

[0078] According to an embodiment of the present disclosure, the analog-to-digital conversion subunit 400 may not include the second amplifier 401. In this alternative embodiment, the sampling interleaved analog-to-digital converter 402 may directly receive the front-end equalized serial signal 12.

[0079] According to an embodiment of the present disclosure, the analog-to-digital conversion subunit 400 may include a cascade of multiple second amplifiers 401 .

[0080] Those skilled in the art should realize that the analog-to-digital conversion subunit 400 is not limited to using the high-speed analog-to-digital conversion method described above based on a high-speed analog-to-digital converter.

[0081] According to an embodiment of the present disclosure, the interleaved sampling analog-to-digital converter 402 may include a plurality of interleaved sampling analog-to-digital converters connected in series to further reduce the frequency of the digital conversion signal 51 .

[0082] According to an embodiment of the present disclosure, the interleaved sampling analog-to-digital converter 402 may be a direct comparison ADC (Flash ADC) or an interleaved sampling direct comparison ADC.

[0083] According to an embodiment of the present disclosure, the interleaved sampling analog-to-digital converter 402 may be a pipelined ADC (Pipelined-ADC) or an interleaved sampling pipelined ADC.

[0084] According to an embodiment of the present disclosure, the interleaved sampling analog-to-digital converter 402 may be a successive approximation register ADC (SAR ADC) or an interleaved sampling successive approximation register ADC.

[0085] FIG. 6 is a diagram illustrating a configuration of a second equalizing subunit 500 according to an embodiment of the present disclosure.

[0086] According to an embodiment of the present disclosure, the second equalizing subunit 500 may be implemented by a digital equalizer, which may include a digital feed-forward equalizer (Digital FFE) 501 and a digital decision feedback equalizer (Digital DFE) 502 .

[0087] According to an embodiment of the present disclosure, as shown in FIG6 , a digital feedforward equalizer 501 may receive a digital conversion signal 51 and perform a digital feedforward equalization operation on the digital conversion signal 51. Subsequently, the output signal of the digital feedforward equalizer 501 may be provided to a digital decision feedback equalizer 502, which performs a digital decision feedback equalization operation on the output signal of the digital feedforward equalizer 501 and outputs a second parallel signal 62.

[0088] Alternatively, according to an embodiment of the present disclosure, the digital equalizer for implementing the second equalization subunit 500 may include only the digital feedforward equalizer 501 without the digital decision feedback equalizer 502. In this alternative embodiment, the digital feedforward equalizer 501 directly outputs the second parallel signal 62.

[0089] Alternatively, according to an embodiment of the present disclosure, the digital equalizer for implementing the second equalization subunit 500 may include only the digital decision feedback equalizer 502 without including the digital feedforward equalizer 501. In this alternative embodiment, the digital decision feedback equalizer 502 may perform a digital equalization operation on the digital conversion signal 51 and output a second parallel signal 62.

[0090] Alternatively, according to an embodiment of the present disclosure, the digital decision feedback equalizer 502 may receive the digital conversion signal 51 and perform a digital decision feedback equalization operation on the digital conversion signal 51. Subsequently, the output signal of the digital decision feedback equalizer 502 may be provided to the digital feedforward equalizer 501, which performs a digital feedforward equalization operation on the output signal of the digital decision feedback equalizer 502 and outputs a second parallel signal 62.

[0091] According to an embodiment of the present disclosure, the digital equalizer for implementing the second equalizing subunit 500 may include a cascade of multiple digital feedforward equalizers 501 .

[0092] According to an embodiment of the present disclosure, the digital equalizer for implementing the second equalization subunit 500 includes a cascade of multiple digital decision feedback equalizers 502 .

[0093] FIG7 is a diagram illustrating a configuration of the selection unit 600 according to an embodiment of the present disclosure.

[0094] According to an embodiment of the present disclosure, as shown in FIG. 7 , the selection unit 600 may include a data selector 601 .

[0095] According to an embodiment of the present disclosure, as shown in FIG. 7 , a data selector 601 may receive a first parallel signal 61 , a second parallel signal 62 , and a selection signal 64 .

[0096] According to an embodiment of the present disclosure, the data selector 601 may select one of the first parallel signal 61 or the second parallel signal 62 according to the selection signal 64 and output it as the output parallel signal 63 .

[0097] According to an embodiment of the present disclosure, the selection signal 64 may be provided from outside the data receiving device 10 .

[0098] According to an embodiment of the present disclosure, the selection signal 64 may be provided from a built-in memory of the data receiving device 10 .

[0099] According to an embodiment of the present disclosure, the selection signal 64 may be set according to a preset condition, wherein the preset condition may be selected from at least one of the following: Nyquist frequency, modulation mode, and bit error rate.

[0100] Specifically, according to an embodiment of the present disclosure, the selection signal 64 may be set according to the Nyquist frequency of the input serial signal 11 .

[0101] According to an embodiment of the present disclosure, when the Nyquist frequency of the input serial signal 11 is lower than a preset Nyquist frequency threshold, the data selector 601 may select the first parallel signal 61 according to the selection signal 64 .

[0102] In addition, according to an embodiment of the present disclosure, when the Nyquist frequency of the input serial signal 11 is higher than a preset Nyquist frequency threshold, the data selector 601 may select the second parallel signal 62 according to the selection signal 64 .

[0103] According to an embodiment of the present disclosure, the selection signal 64 may be set according to a modulation mode.

[0104] According to an embodiment of the present disclosure, when the modulation mode is the NRZ mode, the data selector 601 may select the first parallel signal 61 according to the selection signal 64 .

[0105] In addition, according to an embodiment of the present disclosure, when the preset modulation mode is the PAM-N (N>2) mode, the data selector 601 may select the second parallel signal 62 according to the selection signal 64 .

[0106] According to an embodiment of the present disclosure, the selection signal 64 may be set according to a combination of the Nyquist frequency and the modulation mode of the input serial signal 11 .

[0107] According to an embodiment of the present disclosure, when the Nyquist frequency of the input serial signal 11 is lower than a preset Nyquist frequency threshold and the preset modulation mode is the NRZ mode, the data selector 601 may select the first parallel signal 61 according to the selection signal 64 .

[0108] Furthermore, according to an embodiment of the present disclosure, when the Nyquist frequency of the input serial signal 11 is higher than a preset Nyquist frequency threshold and the modulation mode is PAM-N (N>2) mode, the data selector 601 may select the second parallel signal according to the selection signal 64 .

[0109] FIG. 8 is a diagram illustrating a configuration of a selection unit 600 according to another embodiment of the present disclosure.

[0110] According to an embodiment of the present disclosure, as shown in FIG8 , in addition to the data selector 601 , the selection unit 600 may further include a bit error rate detector 602 .

[0111] According to an embodiment of the present disclosure, as shown in FIG8 , the bit error rate detector 602 can detect the bit error rates of the first parallel signal 61 and the second parallel signal 62 and output a selection signal 64 based on the detection result. As described above, the data selector 601 can select one of the first parallel signal 61 or the second parallel signal 62 based on the selection signal 64 and output it as the output parallel signal 63.

[0112] According to an embodiment of the present disclosure, the bit error rate detector 602 can perform error correction code or error detection code calculation on the input serial signal 11 based on the error correction code or error detection code included in the input serial signal 11 to obtain error data, and calculate the bit error rate accordingly. Common error correction codes or error detection codes include ECC, CRC, etc., and the present disclosure does not particularly limit the type of error correction code or error detection code.

[0113] According to an embodiment of the present disclosure, when the bit error rate of the first parallel signal 61 is less than or equal to the bit error rate of the second parallel signal 62 , the data selector 601 may select the first parallel signal 61 according to the selection signal 64 .

[0114] According to an embodiment of the present disclosure, when the bit error rate of the first parallel signal 61 is greater than or equal to the bit error rate of the second parallel signal 62 , the data selector 601 may select the second parallel signal 62 according to the selection signal 64 .

[0115] Alternatively, according to an embodiment of the present disclosure, the bit error rate detector 602 may only detect the bit error rate of the first parallel signal 61. In this alternative embodiment, when the bit error rate of the first parallel signal 61 is less than or equal to the first preset threshold, the data selector 601 may select the first parallel signal 61 according to the selection signal 64. In addition, when the bit error rate of the first parallel signal 61 is greater than the first preset threshold, the data selector 601 may select the second parallel signal 62 according to the selection signal 64.

[0116] Alternatively, according to an embodiment of the present disclosure, the bit error rate detector 602 may only detect the bit error rate of the second parallel signal 62. In this alternative embodiment, when the bit error rate of the second parallel signal 62 is less than or equal to the second preset threshold, the data selector 601 may select the second parallel signal 62 according to the selection signal 64. In addition, when the bit error rate of the second parallel signal 62 is greater than the second preset threshold, the data selector 601 may select the first parallel signal 61 according to the selection signal 64.

[0117] Although not shown in the drawings, according to an embodiment of the present disclosure, the selection unit 600 may be configured to disable the second conversion unit 800 when the first parallel signal 61 is selected, and disable the first conversion unit 700 when the second parallel signal 62 is selected.

[0118] For example, according to an embodiment of the present disclosure, when the selection unit 600 selects the first parallel signal 61 , the selection unit 600 may generate a low-level second enable signal 41 so that circuit units such as the second amplifier 401 do not operate, thereby disabling the second conversion unit 800 .

[0119] In addition, for example, according to an embodiment of the present disclosure, when the selection unit 600 selects the second parallel signal 62 , the selection unit 600 may generate a low-level first enable signal 21 so that the first amplifier 401 and other circuit units do not operate, thereby disabling the first conversion unit 700 .

[0120] According to the data receiving device of the present disclosure, the data receiving device can choose to perform an equalization operation on the input serial signal in an analog manner or a digital manner according to at least one of the Nyquist frequency, modulation mode, and bit error rate as preset conditions, thereby achieving a balance between performance and power consumption in a single data receiving device.

[0121] For illustrative purposes, a limited number of possible embodiments of the present disclosure have been given above. Although the present disclosure has been described with reference to the embodiments thereof, it will be understood by those skilled in the art that various modifications and changes may be made to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure as disclosed in the appended claims.

[0122] Although this document contains many details, these details should not be construed as limitations on the scope of the present disclosure or what may be claimed, but rather as descriptions of features that may be specific to particular embodiments. Certain features described herein in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented in multiple embodiments separately or in any suitable subcombination. Furthermore, although features may be described above as functioning in certain combinations, and even initially stated as such, in some cases one or more features in a combination may be deleted from the claimed combination, and the claimed combination may involve subcombinations or variations of subcombinations.

Claims

1. A data receiving device, comprising: A first conversion unit, configured to convert an input serial signal into a first parallel signal by analog equalization; A second conversion unit is configured to convert the input serial signal into a second parallel signal by digital equalization; as well as The selection unit is configured to select one of the first parallel signal and the second parallel signal as an output parallel signal according to a preset condition.

2. The data receiving device according to claim 1, further comprising: The front-end equalizing unit is configured to perform an analog equalizing operation on the input serial signal to generate a front-end equalized serial signal, and provide the front-end equalized serial signal to the first converting unit and the second converting unit respectively.

3. The data receiving device according to claim 2, wherein: The front-end equalization unit includes a continuous time linear equalizer and a variable gain amplifier.

4. The data receiving device according to claim 1, wherein: The first conversion unit comprises: A first equalization subunit configured to perform an analog equalization operation on the input serial signal to generate a first equalized serial signal; and The serial-to-parallel conversion subunit is configured to perform a serial-to-parallel conversion operation on the first balanced serial signal to output the first parallel signal.

5. The data receiving device according to claim 4, wherein: The first equalizing subunit is implemented by an analog decision feedback equalizer.

6. The data receiving device according to claim 1, wherein: The second conversion unit comprises: an analog-to-digital conversion subunit configured to convert the input serial signal into a digital conversion signal; and The digital equalization subunit is configured to perform a digital equalization operation on the digital conversion signal to output the second parallel signal.

7. The data receiving device according to claim 6, wherein: The digital equalization subunit includes a digital feedforward equalizer and / or a digital decision feedback equalizer.

8. The data receiving device according to claim 1, wherein: The selection unit is configured to: When the first parallel signal is selected, the second conversion unit is disabled, and When the second parallel signal is selected, the first conversion unit is disabled.

9. The data receiving device according to claim 1, wherein: The preset condition is selected from at least one of the following: Nyquist frequency, modulation mode and bit error rate.

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