Method for manufacturing semiconductor device, and semiconductor process apparatus

Abstract

Disclosed in the present application are a method for manufacturing a semiconductor device, and a semiconductor process apparatus. The method comprises: modifying a roughened layer by using a first process gas, so as to reduce the surface roughness of the roughened layer, wherein the first process gas comprises a chemical etching gas capable of reacting with the roughened layer, and a physical-bombardment gas capable of physically bombarding the roughened layer, the proportion of the physical-bombardment gas in the first process gas being greater than the proportion of the chemical etching gas in the first process gas; and etching the modified roughened layer, a second-conductive-type semiconductor layer, an active layer and a first-conductive-type semiconductor layer to a target depth by using a second process gas. The present application can reduce the loading effect of etching byproducts on a roughened surface on an etching process, thus improving the luminance and electrical stability of chips.

Description

Semiconductor device manufacturing method and semiconductor process equipment Technical Field

[0001] The present application belongs to the field of semiconductor technology, and more specifically, relates to a method for manufacturing a semiconductor device and a semiconductor process equipment. Background Art

[0002] Currently, to produce high-brightness LED chips, the industry often uses a solution that directly increases the current to improve brightness. However, as the loading current increases, the LED chip will overheat and age, affecting its service life. With the development and improvement of technology, it is necessary to optimize the process flow of high-brightness LED improvement solutions. Among them, the mainstream process technology uses a roughening process to treat the chip. On the one hand, the roughened surface can increase the chance of photons being emitted. On the other hand, it can increase the number of light outside the critical incident angle to enter the critical angle through multiple refractions, thereby improving the brightness performance of the device. For the red-yellow light AlGaInP (aluminum gallium indium phosphide) roughening process, the roughening process is first performed and then the etching process is performed. This not only reduces the process steps, but also ensures the sidewall morphology while improving the brightness, reduces sidewall damage, and improves the electrical stability of the device. However, with this roughening process, the area of ​​the top roughened surface increases during etching due to post-roughening, and the top surface is loose and porous, resulting in rough sidewalls after etching, which seriously affects the electrical performance and luminescence effect of the device. Secondly, for red-yellow light etching processes, the byproducts corresponding to the In and Al elements have high evaporation temperatures and are difficult to volatilize. In particular, as this loading increases, it becomes more difficult for the byproducts to desorb from the sample surface, thereby producing mask-like substances and gradually generating "black spots" (bumps) on the etched sidewalls and bottom as the etching progresses. This leads to the risk of leakage when packaging the device. Therefore, finding a roughened surface red-yellow light AlGaInP etching process is key to improving the performance of LED chips.

[0003] Summary of the Invention

[0004] The purpose of this application is to propose a method for manufacturing a semiconductor device and a semiconductor process equipment to reduce the impact of roughened surface etching byproducts on the etching load and improve the chip brightness and electrical stability.

[0005] To achieve the above objectives, in a first aspect, the present application provides a method for manufacturing a semiconductor device, wherein the semiconductor device includes a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer stacked from bottom to top, wherein the second conductivity type semiconductor layer has a roughened layer on its surface, the method comprising:

[0006] Modifying the roughening layer using a first process gas to reduce the surface roughness of the roughening layer, the first process gas comprising a chemical etching gas capable of reacting with the roughening layer and a physical bombardment gas capable of physically bombarding the roughening layer, wherein a proportion of the physical bombardment gas in the first process gas is greater than a proportion of the chemical etching gas in the first process gas;

[0007] The modified roughening layer, the second conductive type semiconductor layer, the active layer and the first conductive type semiconductor layer are etched to a target depth using a second process gas.

[0008] In some embodiments, the roughened layer includes In element and / or Al element.

[0009] In some embodiments, the material of the roughening layer includes AlGaInP.

[0010] In some embodiments, in the first process gas, the gas flow ratio of the physical bombardment gas to the chemical etching gas is in a range of 5:1 to 20:1; or

[0011] The flow rate of the physical bombardment gas is in the range of 25 sccm to 200 sccm, and the flow rate of the chemical etching gas is in the range of 5 sccm to 40 sccm; or

[0012] In the first process gas, the total gas flow rate of the physical bombardment gas and the chemical etching gas is in the range of 30 sccm to 240 sccm; or

[0013] In the step of etching the roughened layer using the first process gas, the pressure of the process chamber is in a range of 2 mT to 8 mT.

[0014] In some embodiments, in the step of etching the roughened layer using the first process gas, the process parameters used further include:

[0015] The upper electrode radio frequency power range is: 300W ~ 800W;

[0016] The radio frequency power range of the lower electrode is: 50W~300W;

[0017] Process temperature range: 120℃~150℃;

[0018] The process time range is: 10s to 60s.

[0019] In some embodiments, the chemical etching gas includes Cl 2 , and the physical bombardment gas includes Ar.

[0020] In some embodiments, the roughened layer, the first conductive type semiconductor layer, and the second conductive type semiconductor layer are made of the same material.

[0021] In some embodiments, the second process gas includes Cl 2 , BCl 3 , and HBr.

[0022] In some embodiments, the gas flow ratio of Cl2, BCl3 and HBr in the second process gas is in the range of 1:2:5 to 1:2:20; or

[0023] In the second process gas, the flow rate range of Cl2 is 5 sccm to 20 sccm, the flow rate range of BCl3 is 20 sccm to 40 sccm, and the flow rate range of HBr is 25 sccm to 100 sccm; or

[0024] The chamber pressure range is 2mT to 6mT; or

[0025] In the step of continuing to etch the roughening layer, the second conductive type semiconductor layer, the active layer and the first conductive type semiconductor layer to a target depth using a second process gas, the RF power range of the upper electrode is 400W to 900W, and the RF power range of the lower electrode is 200W to 450W.

[0026] In the second aspect, the present application proposes a semiconductor process equipment, including a process chamber, an air inlet assembly, an upper electrode assembly, a lower electrode assembly and a controller, the controller including at least one processor and at least one memory, the memory storing a computer program, and when the computer program is executed by the processor, the manufacturing method of the semiconductor device described in the first aspect is implemented.

[0027] The beneficial effects of this application are:

[0028] The etching method of the present application first uses a first process gas containing a chemical etching gas and a physical bombardment gas to modify the roughened layer, that is, the surface roughness of the roughened layer is reduced by the chemical etching effect of the chemical etching gas and the physical bombardment effect of the physical bombardment gas, and by making the proportion of the physical bombardment gas in the first process gas greater than the proportion of the chemical etching gas in the first process gas, on the one hand, the physical bombardment characteristics of the ions in the physical bombardment gas are utilized to perform ion bombardment on the roughened surface of the roughened layer to reduce the surface roughness; on the other hand, the use of a relatively small amount of chemical etching gas at the same time can not only adjust the bombardment effect, but also increase the chemical etching of the roughened surface, further reduce the surface roughness of the roughened layer, and at the same time, can also etch the debris produced by the ion bombardment, reducing the generation of protrusions on the subsequent etched surface. Therefore, the present application can reduce the load impact caused by the roughened surface etching by-products and reduce the generation of protrusions on the surface of the subsequent etching morphology. In the subsequent process of continuing to etch to the target depth using the second process gas, the modification treatment reduces the etching load on the surface of the roughened layer, so a smoother etching morphology can be obtained, thereby improving the chip brightness and electrical stability.

[0029] The system of the present application has other features and advantages, which will be apparent from the drawings and subsequent detailed descriptions incorporated herein, or will be described in detail in the drawings and subsequent detailed descriptions incorporated herein, which together serve to explain the specific principles of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other objects, features and advantages of the present application will become more apparent through a more detailed description of exemplary embodiments of the present application in conjunction with the accompanying drawings, in which the same reference numerals generally represent the same components.

[0031] FIG1 shows a schematic diagram of a semiconductor device corresponding to each step of a conventional red-yellow light AlGaInP roughened surface etching process.

[0032] FIG. 2 shows an electron microscope image of etching results of a related art AlGaInP roughened surface etching method.

[0033] FIG3 shows an electron microscope image of etching results of a second AlGaInP roughened surface etching method according to related art.

[0034] FIG4 shows a step diagram of a method for manufacturing a semiconductor device according to an embodiment of the present application.

[0035] 5a-5c respectively show schematic diagrams of a semiconductor device corresponding to each step of a method for manufacturing a semiconductor device according to an embodiment of the present application.

[0036] FIG6 shows an electron microscope image of an etching result of a method for manufacturing a semiconductor device according to an embodiment of the present application.

[0037] FIG7 shows a schematic diagram of a semiconductor process equipment according to an embodiment of the present application. DETAILED DESCRIPTION

[0038] The conventional red-yellow light AlGaInP roughening etching process is shown in FIG1 . First, an AlGaInP epitaxial wafer is provided, which includes a stacked GaAs layer, a first AlGaInP layer (AlGaInP1), a multi-quantum well layer (MQW), a second AlGaInP layer (AlGaInP2), and a GaP layer. A new substrate is then bonded. Specifically, a sapphire substrate (Al2O3) or a silicon substrate (Si substrate) is bonded to the GaP layer via a bonding layer. The original substrate is then peeled off and the GaAs layer removed. The surface of the first AlGaInP layer on the epitaxial wafer is then roughened. A photoresist layer (PR) is then formed on the roughened surface and patterned (photolithographically). The film layer in the cut-strip area exposed by the photoresist is then directly etched to the target depth using a one-step etching process.

[0039] Related technology 1 uses a BCl3+Cl2 etching gas system for AlGaInP etching. For red and yellow light AlGaInP material etching, a one-step process is typically used. If the process is paused, the resulting byproducts are difficult to volatilize, significantly affecting the surface morphology. A typical AlGaInP etching recipe is: 1.5-5mT / SRF400-1500 / BRF50-500 / 10-150Cl2+5-50BCl3 / 4-8T back He / 20-80°C chiller. Specifically, the chamber pressure range is 1.5mT to 5mT; the upper electrode RF power range is 400W to 1500W; the lower electrode RF power range is 50W to 500W; the Cl2 gas flow rate range is 10sccm to 150sccm; the BCl3 gas flow rate range is 5sccm to 50sccm; the back-purge gas (He) pressure is 4Torr to 8Torr; and the chiller temperature range is 20°C to 80°C. Using this recipe, the sidewalls and bottom of the etched surface are roughened, as shown in Figure 2.

[0040] Related technology 2 typically uses a Cl2+BCl3+HBr gas system for one-step AlGaInP etching. For red and yellow light AlGaInP material etching, this one-step process is also used. If the etching is paused, the byproducts produced are difficult to volatilize, significantly affecting the surface morphology. A typical AlGaInP etching recipe is: 1.5-5mT / SRF300-1000 / BRF150-500 / 5-50Cl2+5-50BCl3+5-100HBr / 4-8T back He / 0-80°C chiller. Specifically, the chamber pressure range is 1.5mT to 5mT; the upper electrode RF power range is 300W to 1000W; the lower electrode RF power range is 150W to 500W; the Cl2 gas flow rate range is 5sccm to 50sccm; the BCl3 gas flow rate range is 5sccm to 50sccm; the HBr gas flow rate range is 5sccm to 100sccm; the back-purge gas (He) pressure range is 4Torr to 8Torr; and the chiller temperature range is 0°C to 80°C. After etching using this recipe, the bottom morphology is abnormally convex and high in density, while some areas on the top are damaged, and the etched morphology cannot be guaranteed. The etching results are shown in Figure 3.

[0041] The present application provides a method for manufacturing a semiconductor device and a semiconductor process equipment, which can reduce the load effect of the surface roughness of the roughened layer and improve the brightness and electrical stability of the chip.

[0042] The present application will be described in more detail below with reference to the accompanying drawings. Although preferred embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided to make the present application more thorough and complete, and to fully convey the scope of the present application to those skilled in the art.

[0043] Example 1

[0044] As shown in Figures 4 and 5a, this embodiment provides a method for manufacturing a semiconductor device, which includes a first conductive type semiconductor layer 4, an active layer 5, and a second conductive type semiconductor layer 6 stacked from bottom to top, and the surface of the second conductive type semiconductor layer 6 has a roughened layer 7. It should be noted that from bottom to top refers to the direction away from the substrate layer 1.

[0045] The method comprises the following steps:

[0046] S1: modifying the roughened layer 7 using a first process gas to reduce the surface roughness of the roughened layer 7, wherein the first process gas includes a chemical etching gas capable of reacting with the roughened layer 7 and a physical bombardment gas capable of physically bombarding the roughened layer 7, wherein the proportion of the physical bombardment gas in the first process gas is greater than the proportion of the chemical etching gas in the first process gas;

[0047] In some embodiments, the roughening layer 7 includes In and / or Al. In this embodiment, the material of the roughening layer 7 includes AlGaInP. The roughening layer 7, the first conductive type semiconductor layer 4, and the second conductive type semiconductor layer 6 are made of the same material. The active layer 5 is a multi-quantum well layer.

[0048] Specifically, as shown in FIG5a, the semiconductor device of this embodiment includes, stacked from bottom to top, a substrate layer 1, a bonding layer 2, a GaP layer 3, a first conductivity type semiconductor layer 4 of AlGaInP material, an active layer 5 (multi-quantum well layer), a second conductivity type semiconductor layer 6 of AlGaInP material, and a patterned photoresist layer 8, wherein the substrate layer 1 is a sapphire substrate or a silicon substrate. The surface of the second conductivity type semiconductor layer 6 has a roughening layer 7, and the pattern of the patterned photoresist layer 8 exposes a portion of the second conductivity type semiconductor layer 6. The roughening layer 7 is formed by roughening the surface of the second conductivity type semiconductor layer 6.

[0049] In a specific embodiment, the method for preparing the semiconductor device includes:

[0050] A red-yellow light AlGaInP epitaxial wafer is provided. The epitaxial wafer includes a stacked GaP layer 3, a first conductivity type semiconductor layer 4, an active layer 5, a second conductivity type semiconductor layer 6, and a GaAs substrate (not shown). The red-yellow light AlGaInP epitaxial wafer is bonded to a new substrate using a bonding technique. The new substrate is the substrate layer 1 shown in FIG. 5 a. The substrate layer 1 is, for example, a sapphire (Al2O3) substrate or a Si substrate, and a Si substrate is typically used.

[0051] The original GaAs substrate on the epitaxial wafer after the substrate is transferred is subjected to laser lift-off to separate the original GaAs substrate from the second conductive type semiconductor layer 6;

[0052] Then, a wet etching process is used to roughen the surface of the second conductive type semiconductor layer 6 to form a roughened layer 7. Depending on the roughening process, the surface roughness of the roughened layer 7 typically ranges from 300 nm to 1200 nm (the surface roughness is characterized, for example, by the roughening depth. If the roughening depth is too shallow or too deep, the light extraction effect will be affected).

[0053] A photoresist mask layer 8 is formed on the semiconductor device after the surface roughening, and photolithography patterning and etching preparation are performed.

[0054] Then, the above-mentioned step S1 is performed, that is, before performing step S1, the surface of the second conductive type semiconductor layer 6 has been roughened to obtain a roughened layer 7 with a certain surface roughness range, and the above-mentioned step S1 is to modify the roughened layer 7 with a certain surface roughness range, and the surface roughness of the roughened layer 7 has been reduced.

[0055] In step S1, the roughening layer 7 is modified by using a first process gas to reduce the surface roughness of the roughening layer 7. The chemical etching gas used in the first process gas includes Cl2, and the physical bombardment gas includes Ar, that is, the first process gas uses a combination of Cl2 and Ar.

[0056] In some embodiments, the proportion of the physical bombardment gas in the first process gas is greater than the proportion of the chemical etching gas in the first process gas.

[0057] The etching method of the present application first uses a first process gas containing a chemical etching gas and a physical bombardment gas to modify the roughened layer, that is, the surface roughness of the roughened layer is reduced by the chemical etching effect of the chemical etching gas and the physical bombardment effect of the physical bombardment gas, and by making the proportion of the physical bombardment gas in the first process gas greater than the proportion of the chemical etching gas in the first process gas, on the one hand, the physical bombardment characteristics of the ions in the physical bombardment gas are utilized to perform ion bombardment on the roughened surface of the roughened layer to reduce the surface roughness; on the other hand, the use of a relatively small amount of chemical etching gas at the same time can not only adjust the bombardment effect, but also increase the chemical etching of the roughened surface, further reduce the surface roughness of the roughened layer, and at the same time, can also etch the debris produced by the ion bombardment, reducing the generation of protrusions on the subsequent etched surface. Therefore, the present application can reduce the load impact caused by the roughened surface etching by-products and reduce the generation of protrusions on the surface of the subsequent etching morphology. In the subsequent process of continuing to etch to the target depth using the second process gas, the modification treatment reduces the etching load on the surface of the roughened layer, so a smoother etching morphology can be obtained, thereby improving the chip brightness and electrical stability.

[0058] On this basis, in some embodiments, the gas flow ratio of the physical bombardment gas (such as Ar) to the chemical etching gas (such as Cl2) in the first process gas ranges from 5:1 to 20:1. This gas flow ratio range is used to adjust the bombardment effect.

[0059] In some embodiments, the flow rate of the physical bombardment gas (eg, Ar) ranges from 25 sccm to 200 sccm, and the flow rate of the chemical etching gas (eg, Cl 2 ) ranges from 5 sccm to 40 sccm.

[0060] In some embodiments, the total flow rate of the physical bombardment gas (eg, Ar) and the chemical etching gas (eg, Cl 2 ) ranges from 30 sccm to 240 sccm.

[0061] In some embodiments, in step S1 of etching the roughened layer 7 using the first process gas, the pressure of the process chamber ranges from 2 mT to 8 mT.

[0062] In some embodiments, the process parameters used in this step S1 also include: the upper electrode RF power range is: 300W~800W; the lower electrode RF power range is: 50W~300W; the process temperature range is: 120℃~150℃; the process time range is: 10s~60s.

[0063] Step S1 is a pre-processing step for the main etching step. Specifically, a physical bombardment gas (e.g., Ar) and a chemical etching gas (e.g., Cl₂) are introduced into the process chamber of an inductively coupled plasma (ICP) device. The ratio of the physical bombardment gas (e.g., Ar) to the chemical etching gas (e.g., Cl₂) is 5:1 to 20:1, primarily to adjust the bombardment effect. A constant chamber pressure is maintained, preferably within a fixed range of 2 mT to 8 mT. A certain upper electrode RF power is applied to ionize the gas in the process chamber to generate plasma, and the upper electrode RF power range is selected to be 300W to 800W; then a certain lower electrode RF power is applied to accelerate the plasma downward to bombard the surface of the roughened layer 7 for etching, and the lower RF power range is selected to be 50W to 300W; the wafer (i.e., semiconductor device) is placed on a quartz or SiC carrier, and a back-blowing gas (He) at a certain pressure is introduced under the carrier to cool the carrier and improve the temperature uniformity of the carrier, and to conduct heat dissipation so that the surface temperature of the wafer above the carrier (i.e., process temperature) is controlled to be above 120°C without causing adhesive sticking, for example, 120°C to 150°C. The wafer surface temperature is determined by the RF power in the process recipe (including the upper electrode RF power and the lower electrode RF power) and the temperature control system (chiller). Generally, after the RF power in the process recipe is selected, the wafer surface temperature is basically determined to be within a certain range; the process time range is, for example, 10s to 60s, which is determined by the surface roughening thickness of the roughened layer 7 and the etching rate.

[0064] The chemical reaction formula involved in the etching process of step S1 is as follows:

[0065] Ar→Ar + +e;

[0066] Cl2→Cl - +Cl*+e;

[0067] AlGaInP (bulk material) + Ar + +e→AlGaInP↑(molecule)+Ar(physical bombardment);

[0068] AlGaInP+Cl - →GaCl3↑+AlCl3↑+InCl3↑+PCly↑(y=3,5)(chemical etching);

[0069] In this step S1, Cl2+Ar gas system is used to etch the area of ​​the roughened layer 7 of the AlGaInP material that is not covered by the photoresist mask. The roughened surface of the roughened layer 7 in other areas is not damaged because it is protected by the photoresist mask. In this step S1, suitable power conditions and the physical bombardment characteristics of Ar ions are mainly used to Ar-etch the roughened surface of the roughened layer 7 in the area not covered by the mask. + Ion bombardment reduces the surface roughness; it is easy to understand that this step S1 is to modify the roughened layer 7 with a certain surface roughness range. Under the premise that the roughened layer 7 itself has a certain surface roughness, the surface roughness is reduced by Ar + Ion bombardment of the roughened surface of the roughened layer 7 can reduce the surface roughness of the roughened layer 7. + When ions bombard a smooth surface, they actually increase the surface roughness.

[0070] Secondly, in this process, a small amount of Cl2 is used. On the one hand, the bombardment effect can be adjusted. On the other hand, a small amount of Cl radicals can also increase the chemical etching of the roughened surface, further reducing the surface roughness of the roughened layer 7; in particular, Cl radicals can also etch some of the debris bombarded by Ar+ ions, reducing the generation of protrusions on the subsequent etched surface.

[0071] It should be noted that, through Ar + The physical bombardment of ions is the main etching part. Most of the AlGaInP on the roughened surface of the roughened layer 7 will be etched by Ar. + However, due to the honeycomb shape on the roughened surface of the roughened layer 7 (as shown in the roughened surface morphology in FIG6 ), there are many holes, so some of the small particles bombarded will be stuck on the bottom or side wall of the roughened surface. + The bombardment of ions cannot act directly, and can only chemically etch through Cl radicals. As the etching proceeds, the etching temperature gradually increases, and a small amount of by-products such as AlClx and InClx produced by chemical etching gradually evaporate, thereby reducing the generation of micromasks in the subsequent etching process and reducing the generation of protrusions on the subsequent etching surface.

[0072] The process recipe for step S1 is, for example, as follows: chamber pressure: 2mT-8mT, SRF (top electrode RF power): 300W-800W, BRF (bottom electrode RF power): 50W-300W, 25sccm-200sccm Ar + 5sccm-40sccm Cl₂, 4Torr-8Torr back He, chiller temperature: 0°C-70°C, process time: 10s-60s (the time can be adjusted based on the roughening depth). The film structure after step S1 is shown in FIG5b .

[0073] S2: using a second process gas to etch the modified roughened layer 7, the second conductive type semiconductor layer 6, the active layer 5 and the first conductive type semiconductor layer 4 to a target depth;

[0074] In step S2 , the second process gas includes Cl 2 , BCl 3 and HBr. In some embodiments, the gas flow ratio of Cl 2 , BCl 3 and HBr in the second process gas ranges from 1:2:5 to 1:2:20.

[0075] In some embodiments, the flow rate of Cl2 is in the range of 5 sccm to 20 sccm, the flow rate of BCl3 is in the range of 20 sccm to 40 sccm, and the flow rate of HBr is in the range of 25 sccm to 100 sccm.

[0076] In some embodiments, the radio frequency power of the upper electrode ranges from 400W to 900W, and the radio frequency power of the lower electrode ranges from 200W to 450W.

[0077] In some embodiments, the chamber pressure ranges from 2 mT to 6 mT.

[0078] In some embodiments, the process parameters used in this step S2 also include: the upper electrode RF power range is selected between 400W and 900W; the lower electrode RF power range is selected between 200W and 450W; the process temperature range is: 120℃~150℃; the process time range is: 300s~700s.

[0079] This step S2 is the main etching step. During the specific implementation, when the above-mentioned first etching step (i.e., the pre-treatment step) is completed, the main etching step is switched and the second etching step is directly performed. During the etching process of this step S2, since the surface roughness of the roughened layer 7 is optimized, according to the requirement of smooth sidewall morphology, the Cl2+BCl3+HBr system is used for etching. However, since the by-products of the AlGaInP material are difficult to volatilize, the etching gas and RF power in the process formula need to be controlled within a certain range to avoid affecting the electrical results. Therefore, after the completion of step S1, Cl2, BCl3 and HBr gases are introduced into the process chamber, wherein the gas flow ratio of Cl2:BCl3:HBr is in the range of 1:2:5 to 1:2:20; a certain chamber pressure is maintained, and the chamber pressure range is selected to be a fixed value between 2mT and 6mT. By applying a certain upper electrode RF power, the gas in the process chamber is ionized to generate plasma, and the upper electrode RF power range is selected to be 400W~900W; then a certain lower electrode RF power is applied to accelerate the plasma downward to bombard the material surface for etching, and the lower electrode RF power range is selected to be 200W~450W; the wafer (i.e., semiconductor device) is placed on a quartz or SiC carrier, and a certain pressure of back-blowing gas (He) is introduced under the carrier to cool the carrier and improve the temperature uniformity of the carrier, and to conduct heat dissipation so that the surface temperature of the wafer above the carrier (i.e., process temperature) is controlled above 120°C and does not cause glue sticking; the process time range is, for example, 300s~700s.

[0080] The process recipe for step S2 is, for example, as follows: chamber pressure 2mT-6mT, SRF (upper electrode RF power) 400W-900W, BRF (lower electrode RF power) 200W-450W, 5sccm-20sccmCl2 + 20sccm-40sccmBCl3 + 25sccm-100sccmHBr / 4Torr back He, chiller temperature 0°C-70°C, process time 300s-700s (adjustable based on different etching depths or etching recipes). The film structure after step S2 is shown in FIG5c.

[0081] Etching is performed in combination with the process recipes of steps S1 and S2 above, and the obtained etching results are shown in FIG6 . It can be seen that the etching morphology obtained by the manufacturing method of the semiconductor device of this embodiment has a smooth bottom and sidewall etching, thereby effectively improving the brightness and electrical stability of the chip.

[0082] It should be noted that this embodiment is only illustrative of the roughening layer 7 of AlGaInP material. The method of the present application is also applicable to the etching of a roughening layer containing In elements or Al elements. Accordingly, for roughening layers 7 of other different materials or first conductive type semiconductor layers 4, active layers 5 and second conductive type semiconductor layers 6 of other different materials, other corresponding first process gases and second process gases can be selected according to the requirements of the above-mentioned etching effect of the present application.

[0083] Example 2

[0084] FIG7 is a schematic structural diagram of a semiconductor process equipment according to an embodiment of the present application.

[0085] As shown in FIG7 , the semiconductor process equipment 200 includes a process chamber 20, an inlet assembly 20A, an upper electrode assembly 20B, a lower electrode assembly 20C, and a controller (not shown in FIG7 ). The controller includes at least one processor and at least one memory, wherein the memory stores a computer program. When the computer program is executed by the processor, the method for manufacturing a semiconductor device according to any of the above-described embodiments is implemented.

[0086] For example, the controller can be a host computer or a slave computer. Specifically, the controller can control the opening of the valve of the gas inlet assembly 20A to introduce the corresponding process gas into the process chamber 20. The controller can also control the opening and closing of the valve of the gas inlet assembly 20A to control the flow rate of the process gas. The controller can also control the exhaust assembly to exhaust the interior of the process chamber 20 to control the pressure (i.e., chamber pressure) inside the process chamber 20 and discharge reaction byproducts.

[0087] The upper electrode assembly 20B includes an RF coil 21, an upper RF power supply 23, and an upper matcher 25. The controller is further configured to control the upper RF power supply 23 to provide upper electrode RF power to the RF coil 21 via the upper matcher 25, so that the RF coil 21 excites the process gas inside the process chamber 20 to generate plasma 100.

[0088] The lower electrode assembly 20C includes a wafer carrier 22, a lower RF power supply 24, and a lower matcher 26. The controller is further configured to control the lower RF power supply 24 to provide lower electrode RF power to the lower electrode of the wafer carrier 22 via the lower matcher 26, thereby providing an RF bias to the lower electrode of the wafer carrier 22 to attract plasma above the object to be etched (e.g., a wafer) to bombard the object to be etched.

[0089] The semiconductor process equipment 200 of the embodiment of the present application can be an inductively coupled plasma (ICP) etching equipment or a capacitively coupled plasma (CCP) etching equipment. The embodiment of the present application does not limit the type of the semiconductor process equipment 200.

[0090] While various embodiments of the present application have been described above, the above description is intended to be illustrative, not exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments.

Claims

1. A method for manufacturing a semiconductor device, wherein the semiconductor device comprises a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer stacked from bottom to top, wherein the second conductive type semiconductor layer has a roughened layer on its surface, characterized in that: The method comprises: The roughening layer is modified by using a first process gas to reduce the surface roughness of the roughening layer, wherein the first process gas includes a chemical etching gas capable of reacting with the roughening layer and a physical bombardment gas capable of physically bombarding the roughening layer, and the proportion of the physical bombardment gas in the first process gas is greater than the proportion of the chemical etching gas in the first process gas; The modified roughened layer, the second conductive type semiconductor layer, the active layer and the first conductive type semiconductor layer are etched to a target depth using a second process gas.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The roughened layer includes In element and / or Al element.

3. The method for manufacturing a semiconductor device according to claim 2, wherein: The material of the roughened layer includes AlGaInP.

4. The method for manufacturing a semiconductor device according to claim 1, wherein: In the first process gas, the gas flow ratio of the physical bombardment gas to the chemical etching gas is in a range of 5:1 to 20:1; or The flow rate of the physical bombardment gas is in the range of 25 sccm to 200 sccm, and the flow rate of the chemical etching gas is in the range of 5 sccm to 40 sccm; or In the first process gas, the total gas flow rate of the physical bombardment gas and the chemical etching gas is in the range of 30 sccm to 240 sccm; or In the step of etching the roughened layer by using the first process gas, the pressure range of the process chamber is 2 mT to 8 mT.

5. The method for manufacturing a semiconductor device according to claim 4, wherein: In the step of etching the roughening layer using the first process gas, the process parameters used also include: The upper electrode RF power range is: 300W~800W; The lower electrode RF power range is: 50W~300W; Process temperature range: 120℃~150℃; The process time range is: 10s~60s.

6. The method for manufacturing a semiconductor device according to any one of claims 1 to 5, characterized in that: The chemical etching gas includes Cl2, and the physical bombardment gas includes Ar.

7. The method for manufacturing a semiconductor device according to claim 3, wherein: The roughened layer, the first conductive type semiconductor layer and the second conductive type semiconductor layer are made of the same material.

8. The method for manufacturing a semiconductor device according to claim 7, wherein: The second process gas includes Cl2, BCl3 and HBr.

9. The method for manufacturing a semiconductor device according to claim 8, wherein: In the second process gas, the gas flow ratio of Cl2, BCl3 and HBr is in the range of 1:2:5 to 1:2:20; or In the second process gas, the flow rate of Cl2 is in the range of 5 sccm to 20 sccm, the flow rate of BCl3 is in the range of 20 sccm to 40 sccm, and the flow rate of HBr is in the range of 25 sccm to 100 sccm; or The chamber pressure range is 2mT to 6mT; or In the step of continuing to etch the roughening layer, the second conductive type semiconductor layer, the active layer and the first conductive type semiconductor layer to a target depth using a second process gas, the RF power range of the upper electrode is 400W to 900W, and the RF power range of the lower electrode is 200W to 450W.

10. A semiconductor process equipment, comprising a process chamber, an air inlet assembly, an upper electrode assembly, a lower electrode assembly and a controller, characterized in that: The controller includes at least one processor and at least one memory, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, the method for manufacturing a semiconductor device according to any one of claims 1 to 9 is implemented.

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