Forming method for memory device, and memory device

Abstract

The present disclosure provides a forming method for a memory device, and a memory device. The forming method comprises: providing a semiconductor substrate; successively forming a spin-orbit torque layer and a magnetic tunnel junction on one side of the semiconductor substrate, such that the spin-orbit torque layer is located between the magnetic tunnel junction and the semiconductor substrate, and the side of the spin-orbit torque layer away from the semiconductor substrate is provided with an exposed region not covered by the magnetic tunnel junction; forming a first insulating dielectric layer on the side of the spin-orbit torque layer away from the semiconductor substrate, such that the first insulating dielectric layer covers the exposed region and the magnetic tunnel junction; removing the portion of the first insulating dielectric layer covering the side wall of the magnetic tunnel junction; and thinning the portion of the first insulating dielectric layer covering the exposed region, so as to form a target insulating dielectric layer, the target insulating dielectric layer covering the exposed region, and allowing the side wall of a tunneling barrier layer of the magnetic tunnel junction to be completely exposed. The present disclosure solves the problem of poor reliability of memory devices caused by metal back-sputtering.

Description

Method for forming memory device and memory device Technical Field

[0001] The present disclosure relates to the field of memory technology, and in particular to a method for forming a memory device and the memory device. Background Art

[0002] With the rapid development of electronic technology, non-volatile memory (NVM) has become a key research topic. Its high density, fast read / write speeds, and ultra-long operating life make it a promising candidate for broad market applications. Among these, spin-orbit-torque (SOT-MRAM) is a three-terminal device that utilizes a bottom heavy metal orbital layer (SOT layer) to provide a spin-polarized current, assisted by the STT spin current. This allows for device flipping speeds of up to sub-nanometers, further reducing MRAM device energy consumption and making it suitable for fast SRAM cache replacement. During the manufacturing process of SOT-MRAM, the magnetic tunnel junction (MTJ) etching process is crucial for the mass production of SOT-MRAM. This etching process presents numerous issues, such as damage and short circuits. These issues can impact morphological uniformity at best, and can even lead to performance degradation and yield degradation at worst. These challenges represent a pressing challenge that must be overcome and addressed.

[0003] For example, in the SOT-MRAM etching process based on the TP architecture, the etching process is greatly challenged by the limitation of the bottom heavy metal track layer (spin-orbit torque layer). First, the heavy metal track electrode is too close to the tunneling barrier layer (dielectric layer, MgO), which causes the metal splashed back in the MTJ etching process to produce secondary deposition (re-dep) and easily adhere to the tunneling barrier layer (dielectric layer, MgO) in the magnetic tunnel junction, resulting in short. Secondly, since the heavy metal track layer cannot be disconnected, the over-etching amount (OE) is greatly limited, which in turn reduces the ability and space to eliminate the secondary deposition (re-dep) metal.

[0004] Summary of the Invention

[0005] The main purpose of the present disclosure is to provide a method for forming a memory device and a memory device, so as to solve the problem of poor reliability of the memory device caused by metal backsplash in the prior art.

[0006] To achieve the above-mentioned purpose, according to one aspect of the present disclosure, a method for forming a memory device is provided, the method comprising: providing a semiconductor substrate; sequentially forming a spin-orbit torque layer and a magnetic tunnel junction on one side of the semiconductor substrate, so that the spin-orbit torque layer is located between the magnetic tunnel junction and the semiconductor substrate, and a side of the spin-orbit torque layer away from the semiconductor substrate has an exposed area not covered by the magnetic tunnel junction; forming a first insulating dielectric layer on a side of the spin-orbit torque layer away from the semiconductor substrate, so that the first insulating dielectric layer covers the exposed area and the magnetic tunnel junction; removing a portion of the first insulating dielectric layer covering the sidewall of the magnetic tunnel junction; thinning a portion of the first insulating dielectric layer covering the exposed area to form a target insulating dielectric layer, the target insulating dielectric layer covering the exposed area and completely exposing the sidewall of the tunnel barrier layer of the magnetic tunnel junction.

[0007] Furthermore, the steps of forming a magnetic tunnel junction include: covering a magnetic thin film functional layer and a hard mask layer on the side of the spin-orbit torque layer away from the semiconductor substrate, the hard mask layer being located on the side of the magnetic thin film functional layer away from the spin-orbit torque layer; and etching the magnetic thin film functional layer using the emission spectra of the hard mask layer and the magnetic thin film functional layer to form a magnetic tunnel junction.

[0008] Furthermore, the thickness of the first insulating dielectric layer in a direction perpendicular to the spin-orbit torque layer is greater than the thickness of the magnetic tunnel junction.

[0009] Furthermore, the step of forming the first insulating dielectric layer includes: forming the first insulating dielectric layer using a chemical vapor deposition process, the first insulating dielectric layer having a step structure, the step structure including a first part and a second part with an angle, the first part covering the exposed area, and the second part covering the side wall of the magnetic tunnel junction.

[0010] Furthermore, the first part has a first thickness in the first direction, the second part has a second thickness in the second direction, and the ratio of the second thickness to the first thickness is greater than 0 and less than 0.7, wherein the first direction is the direction perpendicular to the spin-orbit torque layer, and the second direction is the direction perpendicular to the first direction.

[0011] Furthermore, the portion of the side wall of the magnetic tunnel junction in the first insulating dielectric layer is removed, including: using a dry etching process to etch the first insulating dielectric layer to remove the portion of the side wall of the magnetic tunnel junction in the first insulating dielectric layer, wherein the angle between the ion beam incident direction in the dry etching process and the first direction is controlled to be 70° to 90°, and the first direction is the direction perpendicular to the spin-orbit torque layer.

[0012] Furthermore, the step of forming a target insulating dielectric layer includes: using a dry etching process to etch the first insulating dielectric layer to form a target insulating dielectric layer, wherein the angle between the ion beam incident direction in the dry etching process and the first direction is controlled to be 20° to 60°, and the first direction is the direction perpendicular to the spin-orbit torque layer.

[0013] Furthermore, the process of etching the magnetic thin film functional layer is selected from any one of ion beam etching, reactive ion etching, cyclotron resonance plasma etching and inductively coupled plasma etching.

[0014] Furthermore, the thickness of the first insulating dielectric layer is 10-30 nm.

[0015] According to another aspect of the present disclosure, a memory device is provided. The memory device is prepared by the above-mentioned memory device formation method, and the memory device includes: a semiconductor substrate having a first surface; a spin-orbit torque layer located on the first surface; a magnetic tunnel junction located on a side of the spin-orbit torque layer away from the semiconductor substrate, such that the spin-orbit torque layer is located between the magnetic tunnel junction and the semiconductor substrate, and the side of the spin-orbit torque layer away from the semiconductor substrate has an exposed area not covered by the magnetic tunnel junction; and a target insulating dielectric layer covering the exposed area.

[0016] The technical solution disclosed in the present invention is applied to provide a method for forming a memory device, wherein, in the process of removing the first insulating dielectric layer covering the exposed area of ​​the spin-orbit torque layer and the sidewall of the magnetic tunnel junction, two removal steps are adopted, and the main removal objects are divided in the two removal steps, that is, in the first removal step of the first insulating dielectric layer, the portion covering the sidewall of the magnetic tunnel junction is selected to be removed, so that in this step, a portion of the metal secondarily deposited on the sidewall of the magnetic tunnel junction is first removed, and then in the second removal step of the first insulating dielectric layer, the portion covering the exposed area of ​​the spin-orbit torque layer is selected to be removed, and since the portion covering the exposed area of ​​the spin-orbit torque layer also covers the exposed area of ​​the magnetic tunnel junction, the exposed area of ​​the magnetic tunnel junction is removed. The part of the side wall of the magnetic tunnel junction is covered, so that in the process of removing the part of the exposed area covering the spin-orbit torque layer, the metal deposited on the side wall of the tunnel barrier layer in the magnetic tunnel junction can be further eliminated. At the same time, since in the process of secondary removal of the secondary deposited backsplashed metal (metal sputtered on the side wall of the tunnel barrier layer during the etching process to form the magnetic tunnel junction), the part of the exposed area covering the spin-orbit torque layer is only thinned but not completely removed, when the secondary deposited backsplashed metal is secondary removed, the metal of the spin-orbit torque layer is avoided from being splashed back onto the side wall of the tunnel barrier layer of the magnetic tunnel junction. Therefore, the present disclosure solves the technical problem of poor reliability of the storage device caused by metal backsplash. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings, which constitute part of the present disclosure, are intended to provide a further understanding of the present disclosure. The exemplary embodiments of the present disclosure and their descriptions are intended to explain the present disclosure and do not constitute an improper limitation of the present disclosure. In the accompanying drawings:

[0018] FIG1 shows a schematic cross-sectional structure diagram of a substrate after forming a first insulating dielectric layer in a method for forming a memory device according to an embodiment of the present disclosure;

[0019] FIG2 is a schematic diagram showing a cross-sectional structure of the substrate after a portion of the first insulating dielectric layer covering the sidewalls of the magnetic tunnel junction in the structure shown in FIG1 is removed;

[0020] FIG3 is a schematic diagram showing a cross-sectional structure of the substrate after thinning a portion of the first insulating dielectric layer covering the exposed area in the structure shown in FIG2 ;

[0021] 4 shows a schematic cross-sectional structure diagram of a substrate after forming a first insulating dielectric layer in a method for forming a memory device according to another embodiment of the present disclosure;

[0022] FIG5 is a schematic diagram showing a cross-sectional structure of a substrate after forming a first insulating dielectric layer in a method for forming a memory device according to yet another embodiment of the present disclosure.

[0023] The above drawings include the following reference numerals:

[0024] 100, bottom metal interconnect structure; 10, spin-orbit torque layer; 201, free layer; 202, tunneling barrier layer; 203, reference layer; 20, magnetic tunnel junction; 30, hard mask layer; 40, first insulating dielectric layer; 50, target insulating dielectric layer. DETAILED DESCRIPTION

[0025] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in the present disclosure may be combined with each other. The present disclosure will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0026] In order to enable those skilled in the art to better understand the solutions of the present disclosure, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present disclosure.

[0027] It should be noted that the terms "first," "second," and the like in the specification and claims of the present disclosure and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate for the embodiments of the present disclosure described herein. In addition, the terms "including" and "having," and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or inherent to these processes, methods, products, or apparatus.

[0028] As mentioned in the background technology, during the SOT-MRAM etching process under TP architecture conditions, the etching process is greatly challenged by the limitation of the bottom heavy metal track layer (spin-orbit torque layer). First, the heavy metal track electrode is too close to the tunneling barrier layer (dielectric layer, MgO). Since the metal backsplashed in the MTJ etching process will produce secondary deposition (re-dep) and easily adhere to the tunneling barrier layer (dielectric layer, MgO) in the magnetic tunnel junction, the device will be short. Secondly, since the heavy metal track layer cannot be disconnected, the over-etching amount (OE) is greatly limited, which in turn reduces the ability and space to eliminate the secondary deposition (re-dep) metal, resulting in poor reliability of the storage device. Therefore, in order to solve the technical problem of poor reliability of the storage device caused by metal backsplash, the present disclosure proposes a method for forming a storage device and a storage device.

[0029] In some optional embodiments, a method for forming a memory device is provided, the method comprising: providing a semiconductor substrate; sequentially forming a spin-orbit torque layer 10 and a magnetic tunnel junction 20 on one side of the semiconductor substrate, such that the spin-orbit torque layer 10 is located between the magnetic tunnel junction 20 and the semiconductor substrate, and a side of the spin-orbit torque layer 10 away from the semiconductor substrate has an exposed area not covered by the magnetic tunnel junction 20; forming a first insulating dielectric layer 40 on a side of the spin-orbit torque layer 10 away from the semiconductor substrate, such that the first insulating dielectric layer 40 covers the exposed area and the magnetic tunnel junction 20, as shown in FIG1 ; removing a portion of the first insulating dielectric layer 40 covering the sidewall of the magnetic tunnel junction 20, as shown in FIG2 ; and thinning a portion of the first insulating dielectric layer 40 covering the exposed area to form a target insulating dielectric layer 50, wherein the target insulating dielectric layer 50 covers the exposed area and completely exposes the sidewall of the tunnel barrier layer 202 of the magnetic tunnel junction 20, as shown in FIG3 .

[0030] Specifically, as shown in FIG1 , the semiconductor substrate may include a plurality of spaced-apart bottom metal interconnect structures 100, each of which has an exposed surface. The spin-orbit torque layer 10 covers the exposed surface of each bottom metal interconnect structure 100, so that the plurality of bottom metal interconnect structures 100 are electrically connected to the spin-orbit torque layer 10. An insulating dielectric layer may be included between any two adjacent bottom metal interconnect structures 100. Optionally, the height of the insulating dielectric layer in the vertical direction is flush with the height of the bottom metal interconnect structure 100 in the vertically opposite direction, and the vertical direction is perpendicular to the direction in which any two bottom metal interconnect structures 100 are spaced-apart.

[0031] Optionally, the surface of the semiconductor substrate covered by the spin-orbit torque layer 10 may include multiple exposed areas of multiple bottom metal interconnect structures 100. Optionally, the horizontal dimension of each bottom metal interconnect structure 100 may be 150-250 nm.

[0032] Optionally, the surface of the semiconductor substrate covered by the spin-orbit torque layer 10 may also include an exposed area of ​​the insulating dielectric layer between any two adjacent bottom metal interconnect structures 100. After forming the bottom metal interconnect structures 100, an insulating material layer (not shown) may be deposited on one side of the bottom metal interconnect structures 100 so that the insulating material layer completely covers the multiple bottom metal interconnect structures 100. The insulating material may then be planarized to expose the surface of the bottom metal interconnect structures 100.

[0033] Specifically, as shown in Figures 1 to 3, the magnetic tunnel junction 20 may include a stacked free layer 201, a tunneling barrier layer 202, and a reference layer 203, wherein the free layer 201 is in contact with the spin-orbit torque layer 10. Optionally, a hard mask layer 30 may be included on the side of the reference layer 203 away from the tunneling barrier layer 202. Optionally, the thickness of the hard mask layer 30 may be 80 to 200 nm. Optionally, the material of the hard mask layer 30 may include, but is not limited to, tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), and tungsten (W). Optionally, the hard mask layer 30 may also be a composite layer structure of metal and oxide.

[0034] Optionally, the magnetic tunnel junction 20 may include, but is not limited to, a single-layer barrier structure or a double-layer barrier structure. For example, the single-layer barrier structure may include a stacked free layer 201, a tunneling barrier layer 202, and a reference layer 203, while the double-layer barrier structure may include a stacked free layer 201, a tunneling barrier layer 202, a reference layer 203, and an oxide layer.

[0035] Specifically, as shown in Figures 1 to 3, the spin-orbit torque layer 10 is located between the semiconductor substrate and the magnetic tunnel junction 20, that is, the spin-orbit torque layer 10 can have a first vertical projection on the semiconductor substrate, and the magnetic tunnel junction 20 can have a second vertical projection on the semiconductor substrate. The above-mentioned second vertical projection is located in the above-mentioned first vertical projection, and the area of ​​the above-mentioned first vertical projection is larger than the area of ​​the second vertical projection. Therefore, it can be understood that the spin-orbit torque layer 10 also includes an exposed area on the side surface away from the semiconductor substrate, and the exposed area is the portion of the surface of the spin-orbit torque layer 10 on the side surface away from the semiconductor substrate that is not covered by the magnetic tunnel junction 20.

[0036] Specifically, as shown in FIG1 , an insulating dielectric material can be deposited on the side of the spin-orbit torque layer 10 away from the semiconductor substrate to form a first insulating dielectric layer 40. The first insulating dielectric layer 40 can cover the exposed area of ​​the surface of the spin-orbit torque layer 10 away from the semiconductor substrate, all sidewalls of the magnetic tunnel junction 20, and the surface of the magnetic tunnel junction 20 away from the spin-orbit torque layer 10. Therefore, the first insulating dielectric layer 40 covers the exposed area and all sidewalls of the tunneling barrier layer 202 in the magnetic tunnel junction 20. Optionally, the material of the first insulating dielectric layer 40 can include, but is not limited to, silicon oxide (SiO2), silicon oxynitride (SiON), silicon nitride (SiN), and silicon carbonitride (SiCN). Optionally, the insulating dielectric material can be deposited using a PECVD process, and the deposition temperature of the deposition process can be 200-300°C.

[0037] Specifically, the first insulating dielectric layer 40 may include a portion covering the above-mentioned exposed area of ​​the spin-orbit torque layer 10 and a portion covering the sidewall of the magnetic tunnel junction 20. It can be understood that the portion of the first insulating dielectric layer 40 covering the sidewall of the magnetic tunnel junction 20 can be located on the side of the portion of the first insulating dielectric layer 40 covering the above-mentioned exposed area of ​​the spin-orbit torque layer 10 away from the spin-orbit torque layer 10, so that in the direction perpendicular to the spin-orbit torque layer 10, the height of the portion of the first insulating dielectric layer 40 covering the sidewall of the magnetic tunnel junction 20 above the portion of the first insulating dielectric layer 40 covering the above-mentioned exposed area of ​​the spin-orbit torque layer 10 will change with the change of the thickness of the portion of the first insulating dielectric layer 40 covering the above-mentioned exposed area of ​​the spin-orbit torque layer 10.

[0038] For example, the portion of the exposed area in the first insulating dielectric layer 40 covering the spin-orbit torque layer 10 may have a first extension height in a direction perpendicular to the spin-orbit torque layer 10. The first extension height may be higher than the maximum height of the tunneling barrier layer 202 of the magnetic tunnel junction 20 from the spin-orbit torque layer 10. The first extension height may also be lower than the maximum height of the tunneling barrier layer 202 of the magnetic tunnel junction 20 from the spin-orbit torque layer 10 and higher than the minimum height of the tunneling barrier layer 202 of the magnetic tunnel junction 20 from the spin-orbit torque layer 10.

[0039] Specifically, in a specific exemplary embodiment, when the above-mentioned first extension height is higher than the maximum height of the tunneling barrier layer 202 of the magnetic tunnel junction 20 from the spin-orbit torque layer 10, it can be considered that the portion of the first insulating dielectric layer 40 covering the side wall of the magnetic tunnel junction 20 and the portion of the first insulating dielectric layer 40 covering the above-mentioned exposed area of ​​the spin-orbit torque layer 10 are the same portion, so that the removal of the portion of the first insulating dielectric layer 40 covering the side wall of the magnetic tunnel junction 20 can be considered as the first thinning of the portion of the first insulating dielectric layer 40 covering the above-mentioned exposed area of ​​the spin-orbit torque layer 10, as shown in Figure 2.

[0040] Furthermore, in the above example, after removing the portion of the first insulating dielectric layer 40 covering the sidewalls of the magnetic tunnel junction 20 (i.e., the first thinning), the remaining portion covering the exposed area of ​​the spin-orbit torque layer 10 can have a second extension height. This second extension height can be higher than the minimum height of the tunneling barrier layer 202 of the magnetic tunnel junction 20 from the spin-orbit torque layer 10 and lower than the maximum height of the tunneling barrier layer 202 of the magnetic tunnel junction 20 from the spin-orbit torque layer 10; or this second extension height can still be higher than the maximum height of the tunneling barrier layer 202 of the magnetic tunnel junction 20 from the spin-orbit torque layer 10 but lower than the first extension height, as shown in FIG2 . The first insulating dielectric layer 40 remaining after the first thinning can then be thinned a second time, so that after forming the target insulating dielectric layer 50, the sidewalls of the tunneling barrier layer 202 in the magnetic tunnel junction 20 are completely exposed, and the target insulating dielectric layer 50 covers the exposed area, as shown in FIG3 .

[0041] Specifically, in another specific exemplary embodiment, the first extension height is lower than the maximum height of the tunneling barrier layer 202 of the magnetic tunnel junction 20 from the spin-orbit torque layer 10 and higher than the minimum height of the tunneling barrier layer 202 of the magnetic tunnel junction 20 from the spin-orbit torque layer 10, so that part of the sidewall of the tunneling barrier layer 202 of the magnetic tunnel junction 20 can be covered by the part of the first insulating dielectric layer 40 covering the sidewall of the magnetic tunnel junction 20, and another part of the sidewall of the tunneling barrier layer 202 of the magnetic tunnel junction 20 can be covered by the part of the first insulating dielectric layer 40 covering the above-mentioned exposed area of ​​the spin-orbit torque layer 10. Therefore, after removing the part of the first insulating dielectric layer 40 covering the above-mentioned magnetic tunnel junction 20, part of the sidewall of the tunneling barrier layer 202 can still be covered by the part of the first insulating dielectric layer 40 covering the above-mentioned exposed area of ​​the spin-orbit torque layer 10. Furthermore, the portion of the first insulating dielectric layer 40 covering the exposed area of ​​the spin-orbit torque layer 10 can be thinned, so that after the target insulating dielectric layer 50 is formed, the sidewalls of the tunneling barrier layer 202 in the magnetic tunnel junction 20 are completely exposed and the target insulating dielectric layer 50 covers the exposed area.

[0042] That is, the formation method of the above-mentioned memory device adopted by the present disclosure adopts two removal steps in the process of removing the first insulating dielectric layer 40 covering the exposed area of ​​the spin-orbit torque layer 10 and the sidewall of the magnetic tunnel junction 20, and the main removal objects are divided in the two removal steps, that is, in the first removal step of the first insulating dielectric layer 40, the part covering the sidewall of the magnetic tunnel junction 20 is selected to be removed, so that in this step, part of the metal deposited on the sidewall of the magnetic tunnel junction 20 is first removed, and then in the second removal step of the first insulating dielectric layer 40, the part covering the exposed area of ​​the spin-orbit torque layer 10 is selected to be removed. Since the part covering the exposed area of ​​the spin-orbit torque layer 10 is also covered by the magnetic tunnel junction, the exposed area of ​​the magnetic tunnel junction 20 is removed. The exposed area of ​​the spin-orbit torque layer 20 is partially removed, thereby further eliminating the metal secondarily deposited on the side wall of the tunnel barrier layer 202 in the magnetic tunnel junction 20 during the process of removing the portion of the exposed area covering the spin-orbit torque layer 10. At the same time, since the portion of the exposed area covering the spin-orbit torque layer 10 is only thinned but not completely removed during the secondary removal of the secondary deposited backsplashed metal (the metal sputtered on the side wall of the tunnel barrier layer 202 during the etching process to form the magnetic tunnel junction 20), the metal of the spin-orbit torque layer 10 is avoided from being splashed back onto the side wall of the tunnel barrier layer 202 of the magnetic tunnel junction 20 during the secondary removal of the secondary deposited backsplashed metal. Therefore, the present disclosure solves the technical problem of poor reliability of the storage device caused by metal backsplashing.

[0043] The following will describe in more detail exemplary embodiments of the method for forming a memory device according to the present disclosure. However, these exemplary embodiments can be implemented in a variety of different forms and should not be construed as being limited to the embodiments described herein. It should be understood that these embodiments are provided to make the disclosure of this disclosure thorough and complete, and to fully convey the concepts of these exemplary embodiments to those of ordinary skill in the art.

[0044] In some optional embodiments, in order to protect the above-mentioned storage device, the above-mentioned formation method may further include forming a dielectric protection layer on the side of the target insulating dielectric layer away from the semiconductor substrate, and the dielectric protection layer may cover the sidewalls and upper surface of the above-mentioned target insulating dielectric layer and the magnetic tunnel junction, and the upper surface is the surface of the side of the magnetic tunnel junction away from the spin-orbit torque layer. Optionally, the material of the dielectric protection layer may include but is not limited to silicon nitride (SiN), silicon carbonitride (SiCN) and silicon oxycarbide (SiOC). Optionally, the precursor or reactant of the above-mentioned dielectric protection layer may include but is not limited to methane silicon (SiH4), hexamethylcyclotrisilazane (C6H 21 N3Si3) or trimethylsilane (C3H 10 Alternatively, the dielectric protection layer may be formed by using a PECVD process or an atomic layer deposition process (ALD).

[0045] In some optional embodiments, in order to form a magnetic tunnel junction on the side of the spin-orbit torque layer away from the semiconductor substrate and prevent over-etching damage to the spin-orbit torque layer during the formation of the magnetic tunnel junction, the steps of forming the above-mentioned magnetic tunnel junction include: covering the side of the above-mentioned spin-orbit torque layer away from the above-mentioned semiconductor substrate with a magnetic thin film functional layer and a hard mask layer, and the above-mentioned hard mask layer is located on the side of the above-mentioned magnetic thin film functional layer away from the above-mentioned spin-orbit torque layer; utilizing the emission spectra of the above-mentioned hard mask layer and the above-mentioned magnetic thin film functional layer, etching the above-mentioned magnetic thin film functional layer to form the above-mentioned magnetic tunnel junction.

[0046] The magnetic thin film functional layer may include a first ferromagnetic layer, an oxide layer, and a second ferromagnetic layer. The first ferromagnetic layer forms a free layer of a magnetic tunnel junction, the oxide layer forms a tunneling barrier layer of the magnetic tunnel junction, and the second ferromagnetic layer forms a reference layer of the magnetic tunnel junction. Optionally, after forming the magnetic thin film functional layer, an initial emission spectrum of the material corresponding to the magnetic thin film functional layer may be recorded using a spectrometer or other spectral analysis equipment.

[0047] Specifically, the hard mask layer has a preset pattern, which is used to prevent part of the magnetic thin film functional layer from being removed, so that the part of the magnetic thin film functional layer that is not removed forms a magnetic tunnel junction. In the process of using the hard mask layer to remove part of the magnetic thin film functional layer, the emission spectrum of the magnetic thin film functional layer can be recorded periodically or continuously, so that the initial light emission spectrum and the spectrum during the etching process can be compared to calculate the intensity change of the spectral line, and then the etching depth of the magnetic thin film functional layer can be determined according to the intensity change of the spectral line, thereby avoiding over-etching of the magnetic thin film functional layer to damage the spin-orbit torque layer, and achieving the purpose of accurately controlling the etching stop position.

[0048] Optionally, the etching process for etching the magnetic thin film functional layer to form the magnetic tunnel junction may be selected from any one of ion beam etching, reactive ion etching, cyclotron resonance plasma etching and inductively coupled plasma etching.

[0049] Optionally, as shown in Figure 1, the above-mentioned first insulating dielectric layer 40 can be formed by a chemical vapor deposition process. In some optional embodiments, in order to make the first insulating dielectric layer 40 cover the exposed area of ​​the spin-orbit torque layer 10 and the side wall of the above-mentioned magnetic tunnel junction 20, the thickness of the above-mentioned first insulating dielectric layer 40 in the direction perpendicular to the above-mentioned spin-orbit torque layer 10 is greater than the thickness of the above-mentioned magnetic tunnel junction 20.

[0050] Specifically, as shown in Figure 1, the semiconductor substrate includes a bottom metal interconnect structure 100, the spin-orbit torque track layer covers the bottom metal interconnect structure 100, the magnetic tunnel junction 20 is located on the above-mentioned spin-orbit torque track layer, and the magnetic tunnel junction 20 may include a stacked free layer 201, a tunneling barrier layer 202, a reference layer 203 and a hard mask layer 30, and then a thicker insulating material layer can be deposited on the side of the spin-orbit torque track layer away from the bottom metal interconnect structure 100, and the insulating material layer completely covers the magnetic tunnel junction 20 and the spin-orbit torque layer 10, and then the insulating material layer can be flattened by chemical flattening to form a first insulating dielectric layer 40.

[0051] The first insulating dielectric layer 40 can then be etched at an angle perpendicular to the spin-orbit torque layer 10, so that the portion of the first insulating dielectric layer 40 covering the sidewall of the magnetic tunnel junction 20 is removed, while the portion of the first insulating dielectric layer 40 covering the exposed area of ​​the spin-orbit torque layer 10 is retained, as shown in FIG2 .

[0052] Then, the etching angle and etching energy can be changed to thin the portion of the first insulating dielectric layer 40 covering the exposed area of ​​the spin-orbit torque layer 10, so that the entire side wall of the tunneling barrier layer 202 is completely exposed, thereby achieving the purpose of secondary cleaning of the backsplash metal on the side wall of the tunneling barrier layer 202. It should be noted that at this time, the exposed area of ​​the spin-orbit torque layer 10 is still covered by a portion of the first insulating dielectric layer 40, as shown in Figure 3.

[0053] Optionally, in other optional embodiments, in order to make the first insulating dielectric layer 40 cover the exposed area of ​​the spin-orbit torque layer 10 and the side wall of the magnetic tunnel junction 20, the step of forming the first insulating dielectric layer 40 includes: forming the first insulating dielectric layer 40 by a chemical vapor deposition process, the first insulating dielectric layer 40 has a step structure, the step structure includes a first part and a second part with an angle, the first part covers the exposed area, and the second part covers the side wall of the magnetic tunnel junction 20, as shown in Figures 4 and 5.

[0054] Specifically, during the deposition and growth of the first insulating dielectric layer 40, the step coverage of the film growth (the ratio of the thickness of the first insulating dielectric layer 40 in a direction perpendicular to the sidewalls to the thickness of the first insulating dielectric layer 40 in a direction perpendicular to the spin-orbit torque layer 10) can be adjusted, so that the thickness of the portion of the first insulating dielectric layer 40 covering the sidewalls of the magnetic tunnel junction 20 is relatively thin, while the thickness of the portion of the first insulating dielectric layer 40 covering the exposed area of ​​the spin-orbit torque layer 10 is relatively thick. Optionally, the ratio of the thickness of the first insulating dielectric layer 40 in a direction perpendicular to the sidewalls to the thickness of the first insulating dielectric layer 40 in a direction perpendicular to the spin-orbit torque layer 10 can be less than 0.4, as shown in FIG. 4 . This allows the first insulating dielectric layer 40 to be etched on the sidewalls during subsequent sidewall etching, eliminating the need to etch the sidewalls. Instead, the first insulating dielectric layer 40 covering the exposed area of ​​the spin-orbit torque layer 10 can be directly thinned until the entire sidewall of the tunneling barrier layer 202 is exposed.

[0055] Optionally, in some embodiments, in order to ensure that the exposed area of ​​the spin-orbit torque layer 10 is still covered by the first insulating dielectric layer 40 after removing the portion of the first insulating dielectric layer 40 covering the sidewall of the magnetic tunnel junction 20, the first portion has a first thickness in the first direction, the second portion has a second thickness in the second direction, and the ratio of the second thickness to the first thickness is greater than 0 and less than 0.7, as shown in Figure 5, wherein the first direction A is a direction perpendicular to the spin-orbit torque layer 10, and the second direction B is a direction perpendicular to the first direction.

[0056] In some optional embodiments, the above-mentioned removal of the portion of the first insulating dielectric layer 40 covering the side wall of the magnetic tunnel junction 20 includes: using a dry etching process to etch the first insulating dielectric layer 40 to remove the portion of the first insulating dielectric layer 40 covering the side wall of the magnetic tunnel junction 20, as shown in Figure 2, wherein the angle between the ion beam incident direction in the above-mentioned dry etching process and the first direction is controlled to be 70° to 90°, and the above-mentioned first direction is a direction perpendicular to the above-mentioned spin-orbit torque layer 10.

[0057] In the above embodiment, the above-mentioned dry etching may include but is not limited to ion beam etching, reactive ion etching, cyclotron resonance plasma etching or inductively coupled plasma etching, that is, ion beam etching, reactive ion etching, cyclotron resonance plasma etching or inductively coupled plasma etching can be used to etch the portion of the first insulating dielectric layer 40 covering the entire side wall of the tunnel barrier layer 202 in the magnetic tunnel junction 20.

[0058] Specifically, the above-mentioned first direction is the direction perpendicular to the spin-orbit torque layer 10. When etching the portion of the first insulating dielectric layer 40 covering the side wall of the magnetic tunnel junction 20, the stage in the ion etching reaction chamber can be controlled to rotate to a first preset angle, so that the incident angle between the incident direction of the ion beam and the first direction is the above-mentioned 70°~90°, so that the characteristic of faster lateral etching can be utilized to first remove the portion of the first insulating dielectric layer 40 covering the side wall of the magnetic tunnel junction 20, while the exposed area of ​​the spin-orbit torque layer 10 is still covered with the portion of the first insulating dielectric layer 40 that is not etched by the ion beam.

[0059] In some optional embodiments, the step of forming the above-mentioned target insulating dielectric layer 50 includes: using a dry etching process to etch the above-mentioned first insulating dielectric layer 40 to form the above-mentioned target insulating dielectric layer 50, as shown in Figure 3, wherein the angle between the ion beam incident direction in the above-mentioned dry etching process and the first direction is controlled to be 20°~60°, and the above-mentioned first direction is a direction perpendicular to the above-mentioned spin-orbit torque layer 10.

[0060] Similarly, the dry etching in the above embodiment may also include but is not limited to ion beam etching, reactive ion etching, cyclotron resonance plasma etching or inductively coupled plasma etching, that is, ion beam etching, reactive ion etching, cyclotron resonance plasma etching or inductively coupled plasma etching may be used to etch the portion of the exposed area covering the spin-orbit torque layer 10 in the above-mentioned first insulating dielectric layer 40.

[0061] Specifically, when etching the portion of the first insulating dielectric layer 40 covering the exposed region of the spin-orbit torque layer 10, the stage within the ion etching reaction chamber can be controlled to rotate by a second predetermined angle, such that the incident angle between the incident direction of the ion beam and the first direction is within the aforementioned range of 20° to 60°, thereby further removing the portion of the first insulating dielectric layer 40 covering the exposed region of the spin-orbit torque layer 10. It should be noted that, as shown in FIG3 , in this step, to prevent metal from the spin-orbit torque layer 10 from splashing back onto the sidewalls of the tunneling barrier layer 202 of the magnetic tunnel junction 20, the portion covering the exposed region of the spin-orbit torque layer 10 can be thinned. This allows the exposed region of the spin-orbit torque layer 10 to remain covered by a portion of the first insulating dielectric layer 40 after the sidewalls of the tunneling barrier layer 202 are completely exposed. This portion of the first insulating dielectric layer 40 serves as the target insulating dielectric layer 50. Optionally, the energy of the ion beam in this etching step may be less than the ion beam energy required to remove the portion of the first insulating dielectric layer 40 covering the sidewalls of the tunneling barrier layer 202. Optionally, in order to increase the cleaning time of the tunneling barrier layer 202 while thinning the portion of the first insulating dielectric layer 40 covering the exposed area, the selectivity may be adjusted by ion beam etching or reactive ion etching, thereby further increasing the cleaning process window for cleaning the tunneling barrier layer 202.

[0062] Optionally, in order to ensure that after a portion of the first insulating dielectric layer is removed, the remaining target insulating dielectric layer still covers the exposed area of ​​the spin-orbit torque layer, the thickness of the first insulating dielectric layer may be 10-30 nm.

[0063] According to another aspect of the present disclosure, a memory device is provided, which is prepared by the above-mentioned memory device formation method, and the memory device includes: a semiconductor substrate having a first surface; a spin-orbit torque layer located on the above-mentioned first surface; a magnetic tunnel junction located on a side of the above-mentioned spin-orbit torque layer away from the above-mentioned semiconductor substrate, so that the above-mentioned spin-orbit torque layer is located between the above-mentioned magnetic tunnel junction and the above-mentioned semiconductor substrate, and the side of the above-mentioned spin-orbit torque layer away from the above-mentioned semiconductor substrate has an exposed area not covered by the above-mentioned magnetic tunnel junction; and a target insulating dielectric layer covering the above-mentioned exposed area.

[0064] In the above embodiment, since the memory device is manufactured using the above memory device formation method, no secondary deposited metal exists on the sidewalls of the tunneling barrier layer of the magnetic tunnel junction, thereby preventing the memory device from short-circuiting and improving the reliability of the memory device.

[0065] From the above description, it can be seen that the above embodiments of the present disclosure achieve the following technical effects:

[0066] 1) Since two removal steps are adopted in the process of removing the first insulating dielectric layer covering the exposed area of ​​the spin-orbit torque layer and the sidewall of the magnetic tunnel junction, and the main removal objects are divided in the two removal steps, that is, in the first removal step of the first insulating dielectric layer, the portion covering the sidewall of the magnetic tunnel junction is selected to be removed, so that in this step, part of the metal secondarily deposited on the sidewall of the magnetic tunnel junction is first removed, and then in the second removal step of the first insulating dielectric layer, the portion covering the exposed area of ​​the spin-orbit torque layer is selected to be removed. Since the portion covering the exposed area of ​​the spin-orbit torque layer also covers part of the sidewall of the magnetic tunnel junction, the metal secondarily deposited on the sidewall of the tunnel barrier layer in the magnetic tunnel junction can be further removed in the process of removing the portion covering the exposed area of ​​the spin-orbit torque layer.

[0067] 2) Since, during the secondary removal of the secondary deposited backsplash metal (the metal sputtered on the side walls of the tunneling barrier layer during the etching process to form the magnetic tunnel junction), the portion of the exposed area covering the spin-orbit torque layer is only thinned but not completely removed, when the secondary deposited backsplash metal is secondary removed, the metal of the spin-orbit torque layer is prevented from splashing back onto the side walls of the tunneling barrier layer of the magnetic tunnel junction. Therefore, the present disclosure solves the technical problem of poor reliability of the storage device caused by metal backsplash.

[0068] The foregoing description is merely a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. Those skilled in the art will readily appreciate that various modifications and variations are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present disclosure shall be included within the scope of protection of the present disclosure.

Claims

1. A method for forming a memory device, the method comprising: providing a semiconductor substrate; A spin-orbit torque layer and a magnetic tunnel junction are sequentially formed on one side of the semiconductor substrate, so that the spin-orbit torque layer is located between the magnetic tunnel junction and the semiconductor substrate, and a side of the spin-orbit torque layer away from the semiconductor substrate has an exposed area not covered by the magnetic tunnel junction; forming a first insulating dielectric layer on a side of the spin-orbit torque layer away from the semiconductor substrate, so that the first insulating dielectric layer covers the exposed area and the magnetic tunnel junction; removing a portion of the first insulating dielectric layer that covers a side wall of the magnetic tunnel junction; The portion of the first insulating dielectric layer covering the exposed area is thinned to form a target insulating dielectric layer, wherein the target insulating dielectric layer covers the exposed area and completely exposes the sidewall of the tunnel barrier layer of the magnetic tunnel junction.

2. The forming method according to claim 1, wherein: The steps of forming the magnetic tunnel junction include: A magnetic film functional layer and a hard mask layer are covered on a side of the spin-orbit torque layer away from the semiconductor substrate, wherein the hard mask layer is located on a side of the magnetic film functional layer away from the spin-orbit torque layer; The magnetic thin film functional layer is etched using the emission spectra of the hard mask layer and the magnetic thin film functional layer to form the magnetic tunnel junction.

3. The forming method according to claim 1, wherein: The thickness of the first insulating dielectric layer in a direction perpendicular to the spin-orbit torque layer is greater than the thickness of the magnetic tunnel junction.

4. The forming method according to claim 1, wherein: The step of forming the first insulating dielectric layer comprises: The first insulating dielectric layer is formed by chemical vapor deposition process. The first insulating dielectric layer has a step structure. The step structure includes a first part and a second part with an angle. The first part covers the exposed area, and the second part covers the sidewall of the magnetic tunnel junction.

5. The forming method according to claim 4, wherein: The first part has a first thickness in a first direction, the second part has a second thickness in a second direction, and a ratio of the second thickness to the first thickness is greater than 0 and less than 0.7, wherein the first direction is a direction perpendicular to the spin-orbit torque layer, and the second direction is a direction perpendicular to the first direction.

6. The forming method according to any one of claims 1 to 5, wherein: The removing of the portion of the first insulating dielectric layer covering the sidewall of the magnetic tunnel junction comprises: The first insulating dielectric layer is etched by dry etching to remove a portion of the first insulating dielectric layer covering the side wall of the magnetic tunnel junction. The angle between the incident direction of the ion beam in the dry etching process and the first direction is controlled to be 70° to 90°, and the first direction is a direction perpendicular to the spin-orbit moment layer.

7. The forming method according to any one of claims 1 to 5, wherein: The step of forming the target insulating dielectric layer comprises: The first insulating dielectric layer is etched by dry etching to form the target insulating dielectric layer. The angle between the incident direction of the ion beam in the dry etching process and the first direction is controlled to be 20° to 60°, and the first direction is a direction perpendicular to the spin-orbit moment layer.

8. The forming method according to claim 2, wherein: The process for etching the magnetic thin film functional layer is selected from any one of ion beam etching, reactive ion etching, cyclotron resonance plasma etching and inductively coupled plasma etching.

9. The forming method according to any one of claims 1 to 5, wherein: The thickness of the first insulating dielectric layer is 10-30 nm.

10. A memory device, the memory device being prepared by the method for forming a memory device according to any one of claims 1 to 9, the memory device comprising: A semiconductor substrate having a first surface; A spin-orbit torque layer located on the first surface; A magnetic tunnel junction is located on a side of the spin-orbit torque layer away from the semiconductor substrate, so that the spin-orbit torque layer is located between the magnetic tunnel junction and the semiconductor substrate, and the side of the spin-orbit torque layer away from the semiconductor substrate has an exposed area not covered by the magnetic tunnel junction; The target insulating dielectric layer covers the exposed area.

Images