Solid-state imaging device

Abstract

[Problem] To appropriately control current generated at signal reset timing. [Solution] A solid-state imaging device according to the present invention comprises a photoelectric conversion element, an amplification transistor, capacitors, and transistors. The photoelectric conversion element outputs a signal that corresponds to received light. The signal outputted from the photoelectric conversion element is applied to a gate of the amplification transistor, one end of which is connected to a first power supply voltage line. One end of a first capacitor is connected to the other end of the amplification transistor. One end of a first transistor is connected to the other end of the first capacitor. One end of a second capacitor is connected to the other end of the amplification transistor. One end of a second transistor is connected to the other end of the second capacitor, and the other end is connected to the other end of the first transistor. One end of a third transistor is connected to a second power supply voltage line, and the other end is connected to the other end of the first transistor and the other end of the second transistor. One end of a fourth transistor is connected to the second power supply voltage line, and the other end is connected to the one end of the first capacitor and the one end of the second capacitor.

Description

solid-state imaging device

[0001] The present disclosure relates to a solid-state imaging device.

[0002] Voltage domain circuits can be realized as a global shutter technology for solid-state imaging devices. When using this circuit, for example, to support a pixel count of 1,600 x 2,100 pixels, a large current of 400 mA continues to flow at the capacitor reset timing. This results in high power consumption, and a reduction in this current is required.

[0003] Furthermore, since this large current flows from the negative power supply potential through the pad and wiring to the ground potential of the interposer, in order to suppress the bounce of the negative power supply potential, it becomes necessary to design the negative power supply voltage to have a low impedance and increase the number of wiring, which results in an increase in the layout area.

[0004] International Publication No. 2021 / 215093

[0005] Therefore, one non-limiting problem that the embodiments of the present disclosure aim to solve is to configure a circuit that appropriately controls the current generated at the signal reset timing. The problem that the embodiments of the present disclosure aim to solve can also be, as some non-limiting examples, a problem corresponding to the effects described in the embodiments. In other words, a problem that corresponds to at least one of the effects described in the description of the embodiments of the present disclosure can be a problem that the present disclosure aims to solve.

[0006] According to one embodiment, a solid-state imaging device includes a first pixel circuit and a second pixel circuit. The first pixel circuit includes at least a photoelectric conversion element that outputs a signal corresponding to received light, and an amplifying transistor having a gate to which a signal output from the photoelectric conversion element is applied and one end connected to a first power supply voltage line. The second pixel circuit includes at least a first capacitor having one end connected to the other end of the amplifying transistor, a first transistor having one end connected to the other end of the first capacitor, a second capacitor having one end connected to the other end of the amplifying transistor, a second transistor having one end connected to the other end of the second capacitor and the other end connected to the other end of the first transistor, a third transistor having one end connected to a second power supply voltage line and the other end connected to the other end of the first transistor and the other end of the second transistor, and a fourth transistor having one end connected to the second power supply voltage line and the other end connected to one end of the first capacitor and one end of the second capacitor.

[0007] The current source may not be provided on the other end side of the amplifying transistor.

[0008] In the precharge of the reset period, the first transistor, the third transistor, and the fourth transistor may be turned on, and the second transistor may be turned off.

[0009] According to the above configuration, in the precharge during the reset period, the first capacitor can hold a charge based on the performance of the first transistor, the third transistor, and the fourth transistor.

[0010] In the reset level transfer during the reset period, the first transistor and the third transistor may be turned on, and the second transistor and the fourth transistor may be turned off.

[0011] According to the above configuration, in the reset level transfer during the reset period, the first capacitor can hold charge based on the reset level of the pixel output from the amplifying transistor.

[0012] At a reset level output timing in the reset period, the first transistor and the fourth transistor may be turned on, and the second transistor and the third transistor may be turned off.

[0013] In the precharge of the data transfer period, the second transistor, the third transistor, and the fourth transistor may be turned on, and the first transistor may be turned off.

[0014] According to the above configuration, in the precharge during the data transfer period, the second capacitor can hold a charge based on the performance of the second transistor, the third transistor, and the fourth transistor.

[0015] During data transfer during a data transfer period, the second transistor and the third transistor may be turned on, and the first transistor and the fourth transistor may be turned off.

[0016] According to the above configuration, during data transfer during the data transfer period, the second capacitor can hold charge based on the signal level of the pixel output from the amplifying transistor.

[0017] A switch may be provided between the other end of the amplification transistor and one end of the first capacitor, one end of the second capacitor, and the other end of the fourth transistor.

[0018] The subsequent circuit may further include a fifth transistor having a gate connected to the other end of the third transistor and one end connected to a third power supply voltage line, and a sixth transistor having one end connected to the other end of the fifth transistor and the other end connected to an output signal line.

[0019] The image display device may further include a signal processing circuit that generates image data based on the output from the output signal line.

[0020] According to one embodiment, an electronic device includes a plurality of first pixel circuits described above, a plurality of second pixel circuits described above corresponding to the plurality of first pixel circuits, a plurality of subsequent circuits described above corresponding to the plurality of second pixel circuits, and a signal processing circuit that generates image data based on output from the output signal line.

[0021] According to one embodiment, a solid-state imaging device includes a first pixel circuit and a second pixel circuit. The first pixel circuit includes at least a photoelectric conversion element that outputs a signal corresponding to received light, and an amplifying transistor having a gate to which a signal output from the photoelectric conversion element is applied and one end connected to a first power supply voltage line. The second pixel circuit includes at least a first capacitor having one end connected to the other end of the amplifying transistor, a first transistor having one end connected to the other end of the first capacitor, a second capacitor having one end connected to the other end of the amplifying transistor, a second transistor having one end connected to the other end of the second capacitor and the other end connected to the other end of the first transistor, a third transistor having one end connected to a second power supply voltage line and the other end connected to the other end of the first transistor and the other end of the second transistor, and a fourth transistor connected to release the capacitances of the first capacitor and the second capacitor.

[0022] The fourth transistor may have one end connected to one end of the first capacitor and one end of the second capacitor, and the other end connected to the other end of the first transistor and the other end of the second transistor.

[0023] The circuit may include two fourth transistors, one of which has one end connected to one end of the first capacitor and the other end connected to the other end of the first capacitor, and the other of which has one end connected to one end of the second capacitor and the other end connected to the other end of the second capacitor.

[0024] 1 is a block diagram schematically showing a solid-state imaging device according to an embodiment. FIG. 1 is a block diagram schematically showing a solid-state imaging element according to an embodiment. FIG. 2 is a diagram showing an example of a portion of a pixel circuit according to an embodiment. FIG. 3 is a diagram showing an example of a portion of a pixel circuit according to an embodiment. FIG. 4 is a diagram showing an example of an operation of a portion of a pixel circuit according to an embodiment. FIG. 5 is a diagram showing an example of an operation of a portion of a pixel circuit according to an embodiment. FIG. 6 is a diagram showing an example of an operation of a portion of a pixel circuit according to an embodiment. FIG. 7 is a diagram showing an example of an operation of a portion of a pixel circuit according to an embodiment. FIG. 8 is a diagram showing an example of an operation of a portion of a pixel circuit according to an embodiment. FIG. 9 is a block diagram showing an example of a schematic configuration of a vehicle control system. FIG. 10 is an explanatory diagram showing an example of the installation positions of an outside information detection unit and an imaging unit.

[0025] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. The drawings are used for explanation purposes, and the shape, size, and size ratio of each component in an actual device do not necessarily have to be the same as those shown in the drawings. Furthermore, since the drawings are simplified, components necessary for implementation other than those shown in the drawings are also assumed to be appropriately provided.

[0026] 1 is a block diagram schematically illustrating an example configuration of a solid-state imaging device 1 according to an embodiment of the present disclosure. The solid-state imaging device 1 is a device that captures image data. The solid-state imaging device 1 includes an optical system 10, a solid-state imaging element 12, a storage unit 14, a control unit 16, and an I / F 18. The solid-state imaging device 1 may be, for example and without limitation, included in an electronic device such as a digital still camera, a digital video camera, a smartphone with an imaging function, a tablet terminal, or a personal computer, or may be the electronic device itself.

[0027] The optical system 10 is an optical system for appropriately focusing light onto the solid-state image sensor 12 .

[0028] The solid-state imaging element 12 captures image data under the control of the control unit 16. The solid-state imaging element 12 can transmit the image data to the storage unit 14 via a signal line and can also output the image data to the outside via the I / F 18.

[0029] The memory unit 14 stores image data. In addition, the memory unit 14 can store, as needed, data required for the operation of the solid-state imaging device 1. When the control unit 16 specifically realizes information processing by software using hardware resources, the memory unit 14 can store programs, executable files, etc. related to this software.

[0030] The control unit 16 controls the solid-state imaging device 1 to capture image data. The control unit 16 controls the solid-state imaging element 12 by supplying an imaging control signal including, for example, a vertical synchronization signal to the solid-state imaging device 1 via a signal line.

[0031] The I / F 18 is an interface that connects the inside and outside of the solid-state imaging device 1. The solid-state imaging device 1 can input and output user requests, data, etc. between the inside and outside via the I / F 18.

[0032] The solid-state imaging device 1 is further provided with a power supply and the like necessary for operation, although not shown.

[0033] 2 is a diagram schematically illustrating an example of a solid-state imaging device 12 according to an embodiment. The solid-state imaging device 12 includes, for example, a pixel array 100, a control circuit 102, a control circuit 104 (line control circuit), a vertical control circuit 106 (column control circuit), and a signal processing circuit 108.

[0034] The pixel array 100 is an area in which pixels 120 are arranged in a two-dimensional array. The optical system 10 in FIG.

[0035] The control circuit 102 is a circuit that controls the solid-state imaging device 12, and outputs control signals to, for example, a horizontal control circuit 104, a vertical control circuit 106, and a signal processing circuit 108. The control circuit 102 receives control signals from, for example, the control unit 16 in Fig. 1, and appropriately outputs signals for controlling the respective components.

[0036] The horizontal control circuit 104 is a circuit that drives the pixels 120 arranged in the horizontal direction (line direction) in the pixel array 100 by selecting a line.

[0037] The vertical control circuit 106 is a circuit that drives the output transistors of the pixels 120 arranged in the vertical direction (column direction) in the pixel array 100 and outputs signals via output signal lines extending in the vertical direction. Signals from the pixels selected by the horizontal control circuit 104 and the vertical control circuit 106 are output to the signal processing circuit 108.

[0038] The signal processing circuit 108 is a circuit that receives signals from the pixels 120 belonging to the pixel array 100 and outputs image data by appropriately processing the signals. The signal processing circuit 108 may have the function of, for example, an ADC (Analog to Digital Converter) that converts analog signals output from the pixels 120 into digital signals and outputs the digital signals. Furthermore, the signal processing may be processing that includes image processing.

[0039] When operating as an ADC, the signal processing circuit 108 converts analog signals supplied from the pixels 120 into digital signals based on a ramp signal generated by a DAC (Digital to Analog Converter) not shown.

[0040] 2, the signal processing circuit 108 is provided as part of the solid-state imaging element 12, but this is not limiting. At least one operation of the signal processing circuit 108 described below may be realized outside the solid-state imaging element 12 or outside the solid-state imaging device 1. For example, if the solid-state imaging device 1 can operate independently, some signal processing may be performed in an electronic device including the solid-state imaging device 1.

[0041] In the present disclosure, the signal processing circuit 108 converts the analog signals output by each pixel 120 into digital signals, for example, by CDS (Correlated Double Sampling). The following description of the present disclosure will discuss non-limiting exemplary embodiments of a circuit for transmitting signals used in CDS. However, all of the embodiments are not limited to CDS and can be applied to signal transfer in an imaging device in which circuit reset and data transfer are achieved on the same circuit.

[0042] The solid-state imaging device 1 includes a first pixel circuit, part of which is shared by each pixel 120 or a plurality of pixels 120, and a second pixel circuit that stores, outputs, and discharges the output from the first pixel circuit at appropriate timing. The pixel circuit that constitutes the pixel 120 includes the first pixel circuit and the second pixel circuit.

[0043] Fig. 3 is a diagram showing an example of a pixel circuit according to an embodiment. Fig. 3 shows a simple circuit as an example of a first pixel circuit, and the configuration of the first pixel circuit is not limited to the configuration shown in Fig. 3. The first pixel circuit may have any circuit configuration that allows exposure by a global shutter method, for example.

[0044] The first pixel circuit 20 includes a light receiving element 200, a transfer transistor 202, a reset transistor 204, an amplification transistor 206, and a switch 208 (first selection transistor). The first pixel circuit 20 is a circuit that constitutes a part that outputs an analog signal of the pixel 120, and is a circuit that photoelectrically converts received light and outputs an analog signal according to the intensity of the received light.

[0045] The light receiving element 200 is, for example, a light receiving element such as a photodiode, and outputs a signal according to the intensity of the received light by photoelectrically converting the received light. The anode of the light receiving element 200 may be grounded or set to an appropriate negative potential, for example.

[0046] The transfer transistor 202 is a transistor that transfers a signal generated by the light receiving element 200 to the floating diffusion region FD at an appropriate timing. A voltage that drives the transfer transistor 202 is applied to the gate of the transfer transistor 202 at the signal transfer timing, one end is connected to the light receiving element 200, and the other end is connected to the floating diffusion region FD. The transfer transistor 202 may be, for example, an n-type MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor).

[0047] The reset transistor 204 is a transistor that resets the potential of the floating diffusion region FD at an appropriate timing. A voltage that drives the reset transistor 204 is applied to the gate of the reset transistor 204 at the reset timing of the floating diffusion region FD, one end is connected to the first power supply voltage line VDD, and the other end is connected to the floating diffusion region FD. The reset transistor 204 may be, for example, an n-type MOSFET.

[0048] The first power supply voltage line VDD supplies the first power supply voltage Vdd to the circuit.

[0049] The floating diffusion region FD is a region that temporarily stores the charge generated by photoelectric conversion in the light receiving element 200. In this figure, one floating diffusion region FD is provided for one light receiving element 200, but a configuration in which multiple light receiving elements 200 share the floating diffusion region FD is also possible.

[0050] The amplifying transistor 206 is a transistor that receives a signal output from the light receiving element 200 at its gate, multiplies the signal applied to the gate by a gain, and outputs the result. The amplifying transistor 206 has a gate connected to the floating diffusion region FD, one end connected to the first power supply voltage line VDD, and the other end outputting a signal corresponding to the intensity of light received by the light receiving element 200 or a signal corresponding to the reset potential of the floating diffusion region FD. The amplifying transistor 206 may be, for example, an n-type MOSFET.

[0051] The switch 208 supplies the signal output from the amplifying transistor 206 to the outside. The switch 208 may be, for example, an n-type MOSFET. If the switch 208 is a MOSFET, one end of the switch 208 is connected to the other end of the amplifying transistor 206, and the other end of the switch 208 outputs a current based on the signal generated by the light receiving element 200. A drive voltage is applied to the gate of the switch 208 at an appropriate timing, and the switch 208 supplies a signal based on the signal generated by the light receiving element 200 to the outside.

[0052] Note that the switch 208 is not an essential component depending on the circuit design, and may be omitted.

[0053] The second pixel circuit is a circuit connected to the other end of the amplification transistor 206 via the switch 208, and is a circuit that appropriately controls the signal supplied from the amplification transistor 206 and outputs a signal suitable for AD conversion.

[0054] 4 is a diagram showing an example of a portion of a pixel circuit according to an embodiment. This FIG. 4 mainly shows an example of the second pixel circuit. The left side of the dashed line shows the first pixel circuit 20, and the right side of the dashed line shows the second pixel circuit 30. The illustrated amplifier transistor 206 and switch 208 are the amplifier transistor 206 and switch 208 in FIG. 3, respectively.

[0055] The first pixel circuit 20 and the second pixel circuit 30 may each be produced on separate substrates and stacked in an appropriate manner to form an electrically connected semiconductor chip.

[0056] The second pixel circuit 30 includes a first capacitor C1, a second capacitor C2, a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, and a sixth transistor M6. The second pixel circuit 30 is a circuit that suppresses transistor-related noise that may be superimposed on the output from the first pixel circuit 20.

[0057] Although the second pixel circuit 30 includes the fifth transistor M5 and the sixth transistor M6, this is not limiting. For example, the second pixel circuit 30 may include a first capacitor C1, a second capacitor C2, a first transistor M1, a second transistor M2, a third transistor M3, and a fourth transistor M4, with a fifth transistor M5 and a sixth transistor M6 provided as a subsequent circuit.

[0058] The first capacitor C1 is a capacitor having one end connected to the other end of the amplification transistor 206 via the switch 208 and the other end connected to one end of the first transistor M1. The first capacitor C1 is, for example, a capacitor having an MIM (Metal-Insulator-Metal) structure.

[0059] The first transistor M1 is a transistor having one end connected to the other end of the first capacitor C1. The first transistor M1 is, for example, an n-type MOSFET. When the first transistor M1 is turned on, the first capacitor C1 performs a charge or discharge operation.

[0060] The second capacitor C2 has one end connected to the other end of the amplifier transistor 206 and one end of the first capacitor C1 via the switch 208, and the other end connected to one end of the second transistor M2. The second capacitor C2 is, for example, a capacitor having an MIM structure.

[0061] The second transistor M2 has one end connected to the other end of the second capacitor C2 and the other end connected to the other end of the first transistor M1. The second transistor M2 is, for example, an n-type MOSFET. When the second transistor M2 is turned on, the second capacitor C2 performs a charge or discharge operation.

[0062] As shown in the figure, a first capacitor C1 and a first transistor M1, and a second capacitor C2 and a second transistor M2 are provided in parallel between the output of the first pixel circuit 20 and the output of the second pixel circuit 30.

[0063] The third transistor M3 has one end connected to the second power supply voltage line VREG and the other end connected to the other end of the first transistor M1 and the other end of the second transistor M2.

[0064] The second power supply voltage line VREG supplies the circuit with a second power supply voltage Vreg, which is a different potential from the first power supply voltage Vdd (for example, a lower potential than the first power supply voltage Vdd).

[0065] The fourth transistor M4 has one end connected to the other end of the amplifying transistor 206, one end of the first capacitor C1, and one end of the second capacitor C2 via the switch 208, and the other end connected to the second power supply voltage line VREG and one end of the third transistor M3.

[0066] The fifth transistor M5 has a gate connected to the other end of the third transistor M3, the other end of the first transistor M1, and the other end of the second transistor M2, and one end connected to the first power supply voltage line VDD. The fifth transistor M5 operates as a transistor that amplifies a signal based on the voltage stored in the first capacitor C1 or the second capacitor C2. The fifth transistor M5 is connected to, for example, the third power supply voltage line, and this power supply voltage may be the same voltage as the first power supply voltage Vdd applied to the first power supply voltage line VDD.

[0067] The sixth transistor M6 has one end connected to the other end of the fifth transistor M5 and the other end connected to the output signal line VSL. The gate of the sixth transistor M6 is turned on and off by, for example, the horizontal control circuit 104, and outputs a pixel signal from the output signal line VSL at an appropriate timing.

[0068] Signals that switch on and off at appropriate times are applied to the gates of the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4 and the sixth transistor M6, causing a drain current to flow.

[0069] The output signal line VSL is connected to, for example, a signal processing circuit 108, and the signal processing circuit 108 converts the signal from the pixel 120 output via the output signal line VSL from an analog signal into a digital signal, thereby generating image data.

[0070] In this circuit, as shown in the figure, it is possible to configure the switch 208 without providing a current source on the other end side thereof.

[0071] The operation of the second pixel circuit 30 will be described.

[0072] 5 is a diagram showing an example of the operation of the second pixel circuit 30 according to one embodiment. The region indicated by the dashed line in the circuit indicates a region where the transistor is turned off and no change occurs in current or voltage (the same applies to FIG. 6 and subsequent figures).

[0073] First, the floating diffusion region FD in the first pixel circuit 20 is reset by turning on the transfer transistor 202 and the reset transistor 204. After this, the transfer transistor 202 is turned off. The reset transistor 204 may be turned on until the transfer of the reset level in the second pixel circuit 30 is completed, but it may also be turned off at any time after the transfer transistor 202 is turned off.

[0074] In parallel with this timing or after this timing, the following driving is performed to precharge the floating diffusion region FD for reading the reset level (setting the initial value of the node 300).

[0075] The reset period is the timing after the floating diffusion region FD is reset in the first pixel circuit 20, when the level of the node 300 in the second pixel circuit 30 is set to a potential corresponding to the reset level of the floating diffusion region FD of the first pixel circuit 20. At the precharge timing for reading the reset level in this reset period, the switch 208 and the second transistor M2 are turned off, and the first transistor M1, the third transistor M3, and the fourth transistor M4 are turned on.

[0076] For example, the control circuit 102 applies, via an appropriate circuit, a signal to the gate of each transistor that turns on these transistors at the timing of precharge during the reset period.

[0077] By controlling this transistor, both ends of the first capacitor C1 are shorted, and current flows from the electrode of the first capacitor C1 with the higher potential to the electrode with the lower potential. As a result, at the timing of pre-charge in the reset period, the first capacitor C1 holds and maintains a charge based on the second power supply voltage Vreg, which is due to the performance of the first transistor M1, the third transistor M3, and the fourth transistor M4.

[0078] During the precharge period of this reset period, no current source for drawing out excess current is connected to either end of the first capacitor C1, so no current flows to the outside during or after the potential control is completed. In other words, the current for resetting the first capacitor C1 flows within the first pixel circuit 20 and the second pixel circuit 30, and no excess current flows to the outside.

[0079] That is, when the second pixel circuit 30 is formed on one chip (which may be a chip including the first pixel circuit 20), there is no need to form a path for current to flow to the outside.

[0080] 6 is a diagram illustrating an example of the operation of the second pixel circuit 30 according to an embodiment. After FIG. 5, the fourth transistor M4 is turned off and the switch 208 is turned on. That is, the switch 208, the first transistor M1, and the third transistor M3 are turned on, and the second transistor M2 and the fourth transistor M4 are turned off. By controlling in this manner, the short-circuit state of the first capacitor C1 is released and one end of the first capacitor C1 and the other end of the amplification transistor 206 are electrically connected at the timing of transferring the reset level during the reset period.

[0081] By controlling this transistor, the short circuit state across both ends of the first capacitor C1 is released, and at the timing of the reset level transfer in the reset period, the first capacitor C1 is maintained at a voltage based on the reset potential of the region including the light receiving element 200 (particularly, the floating diffusion region FD) output by the amplifying transistor 206 and the second power supply voltage Vreg.

[0082] First, a signal generated by the light-receiving element 200 is transferred to the floating diffusion region FD in the first pixel circuit 20. After photoelectric conversion by the light-receiving element 200 is completed, the reset transistor 204 and switch 208 are turned off, and the transfer transistor 202 is turned on. If the switch 208 was off before the control, it remains off.

[0083] The light-receiving element 200 may include a memory transistor for storing data. In this case, a signal according to the intensity of the received light is transferred from the memory to the floating diffusion region FD via the reset transistor 204. After the transfer is complete, the transfer transistor 202 may be turned off.

[0084] FIG. 7 is a diagram showing the connection state of the second pixel circuit 30 at the timing of precharge during the data transfer period.

[0085] At the precharge timing during the data transfer period, the switch 208 turns off the first transistor M1 and turns on the second transistor M2, the third transistor M3, and the fourth transistor M4.

[0086] For example, the control circuit 102 applies, via an appropriate circuit, signals to the gates of the respective transistors to turn on these transistors at the precharge timing during the data transfer period.

[0087] By controlling this transistor, both ends of the second capacitor C2 are shorted, and current flows from the electrode of the second capacitor C2 with the higher potential to the electrode with the lower potential. As a result, at the timing of precharging in the data transfer period, the second capacitor C2 holds and maintains a charge based on the second power supply voltage Vreg, which is due to the performance of the second transistor M2, the third transistor M3, and the fourth transistor M4.

[0088] By using the initial value of this second capacitor C2 as a reference, the influence of each transistor in the first pixel circuit 20, and the third transistor M3, fourth transistor M4, fifth transistor M5, and sixth transistor M6 in the second pixel circuit 30 can be reduced at the timing of conversion to a digital signal in the signal processing circuit 108, along with reading the reset level.

[0089] 8, after the precharge is completed, the fourth transistor M4 is turned off and the switch 208 is turned on, thereby storing electricity in the second capacitor C2 based on the signal level of the floating diffusion region FD. At this timing, the signal level of the floating diffusion region FD is at a potential based on the signal level generated by the light receiving element 200, i.e., the signal level output by the pixel 120, so the second capacitor C2 holds a charge based on the signal level output by the pixel 120.

[0090] In this way, after the precharge and signal transfer (sampling and holding of the signal level of the floating diffusion region FD based on the signal of the received light) during the data transfer period are completed, the second pixel circuit 30 outputs the reset level and signal level for AD conversion.

[0091] As shown in FIG. 9, at the timing of outputting the reset level, the second transistor M2 and the fourth transistor M4 are turned off, and the switch 208, the first transistor M1, the third transistor M3, the fifth transistor M5, and the sixth transistor M6 are turned on, thereby outputting the reset level of the floating diffusion region FD to the signal processing circuit 108 via the output signal line VSL.

[0092] 10 is a diagram showing another example of the timing of outputting the reset level. Unlike in FIG. 9, the switch 208 may output the reset level by turning off the second transistor M2 and the third transistor M3 and turning on the first transistor M1, the fourth transistor M4 and the sixth transistor M6.

[0093] In this case, the switch 208 disconnects the first pixel circuit 20 and the second pixel circuit 30, which increases the degree of freedom in timing control of the potential of the floating diffusion region FD. Also, in the case of Figure 9, the on-resistance of the amplifier transistor 206 increases, which may reduce the stability of the output signal from the fifth transistor M5. Furthermore, because the maximum value of the voltage applied to the gate of the switch 208 is the power supply voltage on the same substrate as the light-receiving element 200, it cannot be made very high.

[0094] 10, it is possible to sufficiently increase the gate potential of the fourth transistor M4 by using a charge pump on a substrate separate from the light receiving element 200, and by sufficiently increasing the second power supply voltage Vreg, it is possible to supply a stable signal to the fifth transistor M5. As a result, it is possible to use a low-voltage power device such as an LVMOS on the side receiving the output of the output signal line VSL.

[0095] 11, when the data transfer to the second capacitor C2 is completed, data is output via the output signal line VSL. At this timing, the switch 208 turns off the first transistor M1 and the third transistor M3 and turns on the second transistor M2, the fourth transistor M4, and the sixth transistor M6, thereby supplying the signal output from the fifth transistor M5 to the signal processing circuit 108 via the output signal line VSL.

[0096] By transferring the signal level with the switch 208 turned off, it is possible to reset the first pixel circuit 20 in parallel with the transfer of the signal level.

[0097] 12 is a diagram showing another example of data output timing. Data can be output by turning on the switch 208, the second transistor M2, and the sixth transistor M6, and turning off the first transistor M1, the third transistor M3, and the fourth transistor M4.

[0098] As described above, according to this embodiment, it is possible to read out an appropriate reset level and a data level, and to output a digital pixel signal based on a method such as CDS. As described above, because the current at the precharge timing is generated in a closed loop inside the second pixel circuit 30, there is no need to consider the current path to the outside, and metal wiring for reducing impedance in the current path and an output terminal (pad) for the current to the outside are not required.

[0099] Furthermore, as mentioned above, no unnecessary current flows after precharging is completed, which reduces power consumption. By not using a current source, the precharge time is defined by an RC time constant, allowing for node initialization in a short time. Furthermore, since no current source is required, there is no need to secure an area for a current mirror that forms a current source, which allows for greater freedom in layout.

[0100] Furthermore, since the switch 208 only needs to be driven in a saturated state, an intermediate voltage is not required, which results in a reduction in the layout area. Also, since there is no need to estimate the bounce of the ground voltage Vss, this leads to an improvement in the degree of freedom in design.

[0101] 13 is a diagram showing a non-limiting modification of the second pixel circuit 30. As shown in this Fig. 13, the fourth transistor M4 may have one end connected to one end of the first capacitor C1 and one end of the second capacitor C2, and the other end connected to the other end of the first transistor M1 and the other end of the second transistor M2. Even with this type of connection, by shorting both ends of each capacitor at the pre-charge timing, resetting is possible and current leakage to the outside can be suppressed.

[0102] At the timing of precharging to the reset level, the switch 208 turns off the second transistor M2 and the sixth transistor M6 and turns on the first transistor M1, the third transistor M3 and the fourth transistor M4. This switching shorts both ends of the first capacitor C1, resetting it.

[0103] At the timing for transferring the reset level, the second transistor M2, the fourth transistor M4, and the sixth transistor M6 are turned off, and the switch 208, the first transistor M1, and the third transistor M3 are turned on. By this switching, the reset level based on the potential of the floating diffusion region FD is transferred to the first capacitor C1.

[0104] During data precharge, the switch 208 turns off the first transistor M1 and the sixth transistor M6 and turns on the second transistor M2, the third transistor M3, and the fourth transistor M4. This switching shorts both ends of the second capacitor C2, resetting it.

[0105] At the timing of data transfer, the first transistor M1, the fourth transistor M4, and the sixth transistor M6 are turned off, and the switch 208, the second transistor M2, and the third transistor M3 are turned on. This switching transfers data based on the potential of the floating diffusion region FD to the second capacitor C2.

[0106] At the timing to output the reset level, the second transistor M2, the third transistor M3, and the fourth transistor M4 are turned off, and the switch 208, the first transistor M1, and the sixth transistor M6 are turned on. By this switching, a signal based on the reset level maintained in the first capacitor C1 is output to the signal line VSL via the fifth transistor M5 and the sixth transistor M6.

[0107] At the timing of data output, the first transistor M1, the third transistor M3, and the fourth transistor M4 are turned off, and the switch 208, the second transistor M2, and the sixth transistor M6 are turned on. By this switching, a signal based on the data stored in the second capacitor C2 is output to the signal line VSL via the fifth transistor M5 and the sixth transistor M6.

[0108] 14 is a diagram showing a non-limiting modification of the second pixel circuit 30. A fourth transistor M4 may be provided for each capacitor and connected to directly short-circuit both ends of each capacitor. For example, as shown in the figure, the fourth transistor M41 may have one end connected to one end of the first capacitor C1 and the other end connected to the other end of the first capacitor C1, and the fourth transistor M42 may have one end connected to one end of the second capacitor C2 and the other end connected to the other end of the second capacitor C2.

[0109] At the timing of precharging to the reset level, the switch 208 turns off the second transistor M2, the fourth transistor M42 corresponding to the second capacitor C2, and the sixth transistor M6, and turns on the first transistor M1, the fourth transistor M41 corresponding to the first capacitor C1, and the third transistor M3. This switching shorts both ends of the first capacitor C1, resetting it.

[0110] At the timing for transferring the reset level, the second transistor M2, the fourth transistor M41 corresponding to the first capacitor C1, the fourth transistor M42 corresponding to the second capacitor C2, and the sixth transistor M6 are turned off, and the switch 208, the first transistor M1, and the third transistor M3 are turned on. By this switching, the reset level based on the floating diffusion region FD is transferred to the first capacitor C1.

[0111] During data precharge, the switch 208 turns off the first transistor M1, the fourth transistor M41 corresponding to the first capacitor C1, and the sixth transistor M6, and turns on the second transistor M2, the fourth transistor M42 corresponding to the second capacitor C2, and the third transistor M3. This switching shorts both ends of the second capacitor C2, resetting it.

[0112] At the timing of data transfer, the first transistor M1, the fourth transistor M41 corresponding to the first capacitor C1, the fourth transistor M42 corresponding to the second capacitor C2, and the sixth transistor M6 are turned off, and the switch 208, the second transistor M2, and the third transistor M3 are turned on. By this switching, data based on the floating diffusion region FD is transferred to the second capacitor C2.

[0113] At the timing to output the reset level, the second transistor M2, the third transistor M3, and the fourth transistors M41 and M42 are turned off, and the switch 208, the first transistor M1, and the sixth transistor M6 are turned on. By this switching, a signal based on the reset level maintained in the first capacitor C1 is output to the signal line VSL via the fifth transistor M5 and the sixth transistor M6.

[0114] At the timing of data output, the first transistor M1, the third transistor M3, and the fourth transistors M41 and M42 are turned off, and the switch 208, the second transistor M2, and the sixth transistor M6 are turned on. By this switching, a signal based on the data stored in the second capacitor C2 is output to the signal line VSL via the fifth transistor M5 and the sixth transistor M6.

[0115] 13 and 14, similar to the above-described embodiment, circuit initialization can be achieved without using a current source, and as a result, the same effects as those of the above-described embodiment can be achieved.

[0116] In this way, the second pixel circuit 30 according to the present disclosure includes at least a first capacitor C1, a second capacitor C2, a first transistor M1, a second transistor M2, a third transistor M3, and a fourth transistor M4, each of which can be configured to be connected as follows:

[0117] The first capacitor C1 has one end connected to the other end of the switch 208.

[0118] The first transistor M1 has one end connected to the other end of the first capacitor C1.

[0119] A second capacitor C2 has one end connected to the other end of the switch 208.

[0120] The second transistor M2 has one end connected to the other end of the second capacitor C2 and the other end connected to the other end of the first transistor M1.

[0121] The third transistor M3 has one end connected to the second power supply voltage line VREG and the other end connected to the other end of the first transistor M1.

[0122] The fourth transistor M4 is electrically connected directly or indirectly to both ends of the first capacitor C1 and the second capacitor C2 so as to release the capacitance of the first capacitor C1 and the second capacitor C2.

[0123] The electronic device according to the present disclosure (a concept including the solid-state imaging device 1 itself) includes a plurality of first pixel circuits 20 described above and a plurality of second pixel circuits 30 described above. One or more first pixel circuits 20 are provided for one or more of the pixels 120 belonging to the pixel array 100, and one or more second pixel circuits 30 corresponding to the one or more first pixel circuits 20 may be provided.

[0124] The technology according to the present disclosure can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of moving body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, a robot, construction machinery, or agricultural machinery (tractor).

[0125] 15 is a block diagram showing a schematic configuration example of a vehicle control system 7000, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied. The vehicle control system 7000 includes a plurality of electronic control units connected via a communication network 7010. In the example shown in FIG. 15, the vehicle control system 7000 includes a drive system control unit 7100, a body system control unit 7200, a battery control unit 7300, an outside-vehicle information detection unit 7400, an inside-vehicle information detection unit 7500, and an integrated control unit 7600. The communication network 7010 connecting these multiple control units may be an in-vehicle communication network conforming to any standard, such as a Controller Area Network (CAN), a Local Interconnect Network (LIN), a Local Area Network (LAN), or FlexRay (registered trademark).

[0126] Each control unit includes a microcomputer that performs arithmetic processing according to various programs, a memory unit that stores the programs executed by the microcomputer or parameters used in various calculations, and a drive circuit that drives various controlled devices. Each control unit includes a network I / F for communicating with other control units via a communication network 7010, and a communication I / F for communicating with devices or sensors inside and outside the vehicle via wired or wireless communication. Figure 15 illustrates the functional configuration of the integrated control unit 7600, including a microcomputer 7610, a general-purpose communication I / F 7620, a dedicated communication I / F 7630, a positioning unit 7640, a beacon receiving unit 7650, an in-vehicle device I / F 7660, an audio / video output unit 7670, an in-vehicle network I / F 7680, and a memory unit 7690. Other control units also include a microcomputer, a communication I / F, a memory unit, and the like.

[0127] The drivetrain control unit 7100 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 7100 functions as a control device for a drive force generating device for generating drive force for the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating braking force for the vehicle. The drivetrain control unit 7100 may also function as a control device for an ABS (Antilock Brake System) or an ESC (Electronic Stability Control), etc.

[0128] A vehicle state detection unit 7110 is connected to the drivetrain control unit 7100. The vehicle state detection unit 7110 includes at least one of a gyro sensor that detects the angular velocity of the axial rotational motion of the vehicle body, an acceleration sensor that detects the acceleration of the vehicle, or a sensor that detects the amount of operation of the accelerator pedal, the amount of operation of the brake pedal, the steering angle of the steering wheel, the engine rotation speed, the rotation speed of the wheels, etc. The drivetrain control unit 7100 performs arithmetic processing using signals input from the vehicle state detection unit 7110, and controls the internal combustion engine, the drive motor, the electric power steering device, the brake device, etc.

[0129] The body system control unit 7200 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 7200 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 7200. The body system control unit 7200 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0130] The battery control unit 7300 controls the secondary battery 7310, which is the power supply source for the drive motor, in accordance with various programs. For example, information such as battery temperature, battery output voltage, or remaining battery capacity is input to the battery control unit 7300 from a battery device equipped with the secondary battery 7310. The battery control unit 7300 performs arithmetic processing using these signals, and controls the temperature regulation of the secondary battery 7310 or a cooling device or the like equipped in the battery device.

[0131] The outside vehicle information detection unit 7400 detects information outside the vehicle equipped with the vehicle control system 7000. For example, at least one of an imaging unit 7410 and an outside vehicle information detection unit 7420 is connected to the outside vehicle information detection unit 7400. The imaging unit 7410 includes at least one of a time-of-flight (ToF) camera, a stereo camera, a monocular camera, an infrared camera, and other cameras. The outside vehicle information detection unit 7420 includes at least one of an environmental sensor for detecting the current weather or climate, or a surrounding information detection sensor for detecting other vehicles, obstacles, pedestrians, etc. around the vehicle equipped with the vehicle control system 7000.

[0132] The environmental sensor may be, for example, at least one of a raindrop sensor that detects rain, a fog sensor that detects fog, a sunshine sensor that detects the degree of sunshine, and a snow sensor that detects snowfall. The surrounding information detection sensor may be at least one of an ultrasonic sensor, a radar device, and a LIDAR (Light Detection and Ranging, Laser Imaging Detection and Ranging) device. The imaging unit 7410 and the outside vehicle information detection unit 7420 may each be provided as an independent sensor or device, or may be provided as a device in which multiple sensors or devices are integrated.

[0133] 16 shows an example of the installation positions of the imaging unit 7410 and the vehicle exterior information detection unit 7420. The imaging units 7910, 7912, 7914, 7916, and 7918 are installed, for example, at least one of the front nose, side mirrors, rear bumper, back door, and upper part of the windshield inside the vehicle cabin of the vehicle 7900. The imaging unit 7910 installed on the front nose and the imaging unit 7918 installed on the upper part of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 7900. The imaging units 7912 and 7914 installed on the side mirrors mainly acquire images of the sides of the vehicle 7900. The imaging unit 7916 installed on the rear bumper or back door mainly acquires images of the rear of the vehicle 7900. The imaging unit 7918 installed on the upper part of the windshield inside the vehicle cabin is mainly used to detect leading vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0134] 16 shows an example of the imaging ranges of the imaging units 7910, 7912, 7914, and 7916. Imaging range a indicates the imaging range of the imaging unit 7910 provided on the front nose, imaging ranges b and c indicate the imaging ranges of the imaging units 7912 and 7914 provided on the side mirrors, respectively, and imaging range d indicates the imaging range of the imaging unit 7916 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 7910, 7912, 7914, and 7916, a bird's-eye view image of the vehicle 7900 viewed from above can be obtained.

[0135] The outside vehicle information detection units 7920, 7922, 7924, 7926, 7928, and 7930 provided on the front, rear, sides, corners, and above the windshield inside the vehicle cabin of the vehicle 7900 may be, for example, ultrasonic sensors or radar devices. The outside vehicle information detection units 7920, 7926, and 7930 provided on the front nose, rear bumper, back door, and above the windshield inside the vehicle cabin of the vehicle 7900 may be, for example, LIDAR devices. These outside vehicle information detection units 7920 to 7930 are mainly used to detect preceding vehicles, pedestrians, obstacles, etc.

[0136] Returning to FIG. 15 , the explanation continues. The outside-vehicle information detection unit 7400 causes the imaging unit 7410 to capture an image outside the vehicle and receives the captured image data. The outside-vehicle information detection unit 7400 also receives detection information from the connected outside-vehicle information detection unit 7420. If the outside-vehicle information detection unit 7420 is an ultrasonic sensor, a radar device, or a LIDAR device, the outside-vehicle information detection unit 7400 emits ultrasonic waves or electromagnetic waves and receives information on the received reflected waves. Based on the received information, the outside-vehicle information detection unit 7400 may perform object detection processing or distance detection processing for people, vehicles, obstacles, signs, or text on the road surface. Based on the received information, the outside-vehicle information detection unit 7400 may also perform environment recognition processing for recognizing rainfall, fog, road conditions, etc. Based on the received information, the outside-vehicle information detection unit 7400 may also calculate the distance to an object outside the vehicle.

[0137] The outside vehicle information detection unit 7400 may also perform image recognition processing or distance detection processing to recognize people, vehicles, obstacles, signs, or characters on the road surface based on the received image data. The outside vehicle information detection unit 7400 may perform processing such as distortion correction or alignment on the received image data, and may also generate an overhead image or a panoramic image by combining image data captured by different image capturing units 7410. The outside vehicle information detection unit 7400 may also perform viewpoint conversion processing using image data captured by different image capturing units 7410.

[0138] The interior information detection unit 7500 detects information inside the vehicle. A driver state detection unit 7510 that detects the driver's state is connected to the interior information detection unit 7500, for example. The driver state detection unit 7510 may include a camera that captures an image of the driver, a biosensor that detects the driver's biometric information, or a microphone that collects sound from within the vehicle cabin. The biosensor is provided, for example, on the seat or steering wheel, and detects the biometric information of a passenger sitting in the seat or the driver gripping the steering wheel. The interior information detection unit 7500 may calculate the driver's level of fatigue or concentration based on the detection information input from the driver state detection unit 7510, or may determine whether the driver is dozing off. The interior information detection unit 7500 may perform processing such as noise canceling on the collected audio signal.

[0139] The integrated control unit 7600 controls the overall operation of the vehicle control system 7000 according to various programs. An input unit 7800 is connected to the integrated control unit 7600. The input unit 7800 may be implemented by a device that can be operated by a passenger, such as a touch panel, a button, a microphone, a switch, or a lever. Data obtained by voice recognition of a voice input through a microphone may be input to the integrated control unit 7600. The input unit 7800 may be, for example, a remote control device using infrared or other radio waves, or an externally connected device such as a mobile phone or a personal digital assistant (PDA) that can operate the vehicle control system 7000. The input unit 7800 may be, for example, a camera, in which case the passenger can input information using gestures. Alternatively, data obtained by detecting the movement of a wearable device worn by the passenger may be input. Furthermore, the input unit 7800 may include, for example, an input control circuit that generates an input signal based on information input by the passenger using the input unit 7800 and outputs the input signal to the integrated control unit 7600. Passengers and the like operate this input unit 7800 to input various data to the vehicle control system 7000 and to instruct processing operations.

[0140] The storage unit 7690 may include a ROM (Read Only Memory) that stores various programs executed by the microcomputer, and a RAM (Random Access Memory) that stores various parameters, calculation results, sensor values, etc. The storage unit 7690 may also be realized by a magnetic storage device such as an HDD (Hard Disc Drive), a semiconductor storage device, an optical storage device, a magneto-optical storage device, or the like.

[0141] The general-purpose communication I / F 7620 is a general-purpose communication I / F that mediates communication with various devices present in the external environment 7750. The general-purpose communication I / F 7620 may implement a cellular communication protocol such as GSM (Global System of Mobile communications), WiMAX (registered trademark), LTE (Long Term Evolution), or LTE-Advanced (LTE-A), or other wireless communication protocols such as a wireless LAN (also referred to as Wi-Fi (registered trademark)) or Bluetooth (registered trademark). The general-purpose communication I / F 7620 may connect to a device (e.g., an application server or a control server) present on an external network (e.g., the Internet, a cloud network, or an operator-specific network) via, for example, a base station or an access point. In addition, the general-purpose communication I / F 7620 may connect to a terminal located near the vehicle (e.g., a terminal of a driver, pedestrian, or store, or an MTC (Machine Type Communication) terminal) using, for example, P2P (Peer To Peer) technology.

[0142] The dedicated communication I / F 7630 is a communication I / F that supports a communication protocol designed for use in vehicles. The dedicated communication I / F 7630 may implement a standard protocol such as WAVE (Wireless Access in Vehicle Environment), which is a combination of a lower layer IEEE 802.11p and an upper layer IEEE 1609, DSRC (Dedicated Short Range Communications), or a cellular communication protocol. The dedicated communication I / F 7630 typically performs V2X communication, which is a concept including one or more of vehicle-to-vehicle communication, vehicle-to-infrastructure communication, vehicle-to-home communication, and vehicle-to-pedestrian communication.

[0143] The positioning unit 7640 performs positioning by receiving, for example, GNSS signals from GNSS (Global Navigation Satellite System) satellites (for example, GPS signals from GPS (Global Positioning System) satellites), and generates position information including the latitude, longitude, and altitude of the vehicle. Note that the positioning unit 7640 may identify the current position by exchanging signals with a wireless access point, or may obtain position information from a terminal such as a mobile phone, PHS, or smartphone that has a positioning function.

[0144] The beacon receiving unit 7650 receives, for example, radio waves or electromagnetic waves transmitted from radio stations or the like installed on the road, and acquires information such as the current location, congestion, road closures, required travel time, etc. The function of the beacon receiving unit 7650 may be included in the dedicated communication I / F 7630 described above.

[0145] The in-vehicle device I / F 7660 is a communication interface that mediates connections between the microcomputer 7610 and various in-vehicle devices 7760 present in the vehicle. The in-vehicle device I / F 7660 may establish wireless connections using wireless communication protocols such as wireless LAN, Bluetooth (registered trademark), NFC (Near Field Communication), or WUSB (Wireless USB). Furthermore, the in-vehicle device I / F 7660 may establish a wired connection such as USB (Universal Serial Bus), HDMI (High-Definition Multimedia Interface), or MHL (Mobile High-Definition Link) via a connection terminal (and a cable, if necessary) not shown. The in-vehicle device 7760 may include, for example, at least one of a mobile device or a wearable device owned by a passenger, or an information device carried into or attached to the vehicle. The in-vehicle device 7760 may also include a navigation device that searches for a route to an arbitrary destination. The in-vehicle device I / F 7660 exchanges control signals or data signals with these in-vehicle devices 7760.

[0146] The in-vehicle network I / F 7680 is an interface that mediates communication between the microcomputer 7610 and the communication network 7010. The in-vehicle network I / F 7680 transmits and receives signals in accordance with a predetermined protocol supported by the communication network 7010.

[0147] The microcomputer 7610 of the integrated control unit 7600 controls the vehicle control system 7000 in accordance with various programs based on information acquired via at least one of the general-purpose communication I / F 7620, the dedicated communication I / F 7630, the positioning unit 7640, the beacon receiving unit 7650, the in-vehicle device I / F 7660, and the in-vehicle network I / F 7680. For example, the microcomputer 7610 may calculate control target values ​​for the driving force generating device, the steering mechanism, or the braking device based on the acquired information inside and outside the vehicle, and output control commands to the drivetrain control unit 7100. For example, the microcomputer 7610 may perform cooperative control aimed at realizing functions of an Advanced Driver Assistance System (ADAS), including vehicle collision avoidance or impact mitigation, following driving based on the following distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane departure warning, etc. In addition, the microcomputer 7610 may perform cooperative control for the purpose of autonomous driving, in which the vehicle travels autonomously without relying on driver operation, by controlling a driving force generating device, a steering mechanism, a braking device, etc. based on information acquired about the vehicle's surroundings.

[0148] The microcomputer 7610 may generate three-dimensional distance information between the vehicle and objects such as surrounding structures and people, and create local map information including information about the vicinity of the vehicle's current location, based on information acquired via at least one of the general-purpose communication I / F 7620, the dedicated communication I / F 7630, the positioning unit 7640, the beacon receiving unit 7650, the in-vehicle device I / F 7660, and the in-vehicle network I / F 7680. Furthermore, the microcomputer 7610 may predict dangers, such as a vehicle collision, the approach of a pedestrian, or entry into a closed road, based on the acquired information, and generate a warning signal. The warning signal may be, for example, a signal for generating a warning sound or turning on a warning lamp.

[0149] The audio / image output unit 7670 transmits at least one audio and / or image output signal to an output device capable of visually or audibly notifying vehicle occupants or the outside of the vehicle of information. In the example of FIG. 15 , an audio speaker 7710, a display unit 7720, and an instrument panel 7730 are illustrated as output devices. The display unit 7720 may include, for example, at least one of an on-board display and a head-up display. The display unit 7720 may have an AR (Augmented Reality) display function. The output device may also be other devices, such as headphones, a wearable device such as a glasses-type display worn by the occupant, a projector, or a lamp. When the output device is a display device, the display device visually displays results obtained by various processes performed by the microcomputer 7610 or information received from other control units in various formats, such as text, images, tables, and graphs. When the output device is an audio output device, the audio output device converts audio signals, such as reproduced audio data or acoustic data, into analog signals and audibly outputs the analog signals.

[0150] In the example shown in FIG. 15 , at least two control units connected via the communication network 7010 may be integrated into a single control unit. Alternatively, each control unit may be composed of multiple control units. Furthermore, the vehicle control system 7000 may include another control unit not shown. In the above description, some or all of the functions performed by one control unit may be performed by another control unit. In other words, as long as information is transmitted and received via the communication network 7010, predetermined arithmetic processing may be performed by one of the control units. Similarly, a sensor or device connected to one control unit may be connected to another control unit, and multiple control units may transmit and receive detection information to and from each other via the communication network 7010.

[0151] A computer program for realizing each function of the solid-state imaging device 1 according to this embodiment described with reference to FIGS. 1 to 14 can be implemented in any control unit or the like. A computer-readable recording medium storing such a computer program can also be provided. The recording medium can be, for example, a magnetic disk, an optical disk, a magneto-optical disk, or a flash memory. The computer program may also be distributed, for example, via a network, without using a recording medium.

[0152] In the vehicle control system 7000 described above, the solid-state imaging device 1 according to the present embodiment described with reference to Figures 1 to 14 can be applied to the integrated control unit 7600 of the application example shown in Figure 15. For example, at least some of the components of the solid-state imaging device 1 may be implemented in a module (e.g., an integrated circuit module configured on a single die) for the integrated control unit 7600 shown in Figure 15. Alternatively, the solid-state imaging device 1 described with reference to Figures 1 to 14 may be implemented by multiple control units of the vehicle control system 7000 shown in Figure 15.

[0153] The above-described embodiment may be modified as follows.

[0154] (1) A solid-state imaging device comprising a first pixel circuit and a second pixel circuit, wherein the first pixel circuit has at least: a photoelectric conversion element that outputs a signal according to received light; and an amplifying transistor to whose gate a signal output from the photoelectric conversion element is applied and whose one end is connected to a first power supply voltage line; and the second pixel circuit has at least: a first capacitor having one end connected to the other end of the amplifying transistor; a first transistor having one end connected to the other end of the first capacitor; a second capacitor having one end connected to the other end of the amplifying transistor; a second transistor having one end connected to the other end of the second capacitor and the other end connected to the other end of the first transistor; a third transistor having one end connected to a second power supply voltage line and the other end connected to the other end of the first transistor and the other end of the second transistor; and a fourth transistor having one end connected to the second power supply voltage line and the other end connected to one end of the first capacitor and one end of the second capacitor.

[0155] (2) The solid-state imaging device according to (1), wherein a current source is not provided on the other end side of the amplifying transistor.

[0156] (3) The solid-state imaging device according to (1) or (2), wherein, in precharging during a reset period, the first transistor, the third transistor, and the fourth transistor are turned on, and the second transistor is turned off.

[0157] (4) The solid-state imaging device according to (3), wherein, in the precharge during the reset period, the first capacitor holds a charge based on the performance of the first transistor, the third transistor, and the fourth transistor.

[0158] (5) The solid-state imaging device according to (3) or (4), wherein, in a reset level transfer during a reset period, the first transistor and the third transistor are turned on, and the second transistor and the fourth transistor are turned off.

[0159] (6) The solid-state imaging device according to (5), wherein, in the reset level transfer during the reset period, the first capacitor holds a charge based on the reset level of the pixel output from the amplifying transistor.

[0160] (7) The solid-state imaging device according to (5) or (6), wherein, at a reset level output timing in a reset period, the first transistor and the fourth transistor are turned on, and the second transistor and the third transistor are turned off.

[0161] (8) The solid-state imaging device according to any one of (3) to (7), wherein, in precharging during a data transfer period, the second transistor, the third transistor, and the fourth transistor are turned on, and the first transistor is turned off.

[0162] (9) The solid-state imaging device according to (8), wherein in the precharge during the data transfer period, the second capacitor holds a charge based on the performance of the second transistor, the third transistor, and the fourth transistor.

[0163] (10) The solid-state imaging device according to (8) or (9), wherein, during data transfer during a data transfer period, the second transistor and the third transistor are turned on, and the first transistor and the fourth transistor are turned off.

[0164] (11) The solid-state imaging device according to (10), wherein during data transfer during a data transfer period, the second capacitor holds a charge based on a signal level of a pixel output from the amplifying transistor.

[0165] (12) The solid-state imaging device according to any one of (1) to (11), further comprising a switch between the other end of the amplifying transistor and one end of the first capacitor, one end of the second capacitor, and the other end of the fourth transistor.

[0166] (13) A solid-state imaging device according to any one of (1) to (12), further comprising a subsequent circuit, the subsequent circuit having: a fifth transistor having a gate connected to the other end of the third transistor and one end connected to a third power supply voltage line; and a sixth transistor having one end connected to the other end of the fifth transistor and the other end connected to an output signal line.

[0167] (14) The solid-state imaging device according to (13), further comprising: a signal processing circuit that generates image data based on an output from the output signal line.

[0168] (15) An electronic device comprising: a plurality of first pixel circuits according to (13); a plurality of second pixel circuits according to (13) corresponding to the plurality of first pixel circuits; a plurality of subsequent circuits according to (13) corresponding to the plurality of second pixel circuits; and a signal processing circuit that generates image data based on an output from the output signal line.

[0169] (16) A solid-state imaging device comprising a first pixel circuit and a second pixel circuit, wherein the first pixel circuit has at least: a photoelectric conversion element that outputs a signal according to received light; and an amplifying transistor to whose gate a signal output from the photoelectric conversion element is applied and one end connected to a first power supply voltage line; and the second pixel circuit has at least: a first capacitor having one end connected to the other end of the amplifying transistor; a first transistor having one end connected to the other end of the first capacitor; a second capacitor having one end connected to the other end of the amplifying transistor; a second transistor having one end connected to the other end of the second capacitor and the other end connected to the other end of the first transistor; a third transistor having one end connected to a second power supply voltage line and the other end connected to the other end of the first transistor and the other end of the second transistor; and a fourth transistor connected to release the capacitance of the first capacitor and the second capacitor.

[0170] (17) The solid-state imaging device described in (16), wherein one end of the fourth transistor is connected to one end of the first capacitor and one end of the second capacitor, and the other end is connected to the other end of the first transistor and the other end of the second transistor.

[0171] (18) A solid-state imaging device as described in (16), comprising two fourth transistors, one of which has one end connected to one end of the first capacitor and the other end connected to the other end of the first capacitor, and the other of which has one end connected to one end of the second capacitor and the other end connected to the other end of the second capacitor.

[0172] The aspects of the present disclosure are not limited to the above-described embodiments and include various conceivable modifications, and the effects of the present disclosure are not limited to the above-described contents. The components in each embodiment may be appropriately combined and applied. In other words, various additions, modifications, and partial deletions are possible within the scope of the conceptual idea and intent of the present disclosure, which is derived from the content defined in the claims and their equivalents.

[0173] 1: solid-state imaging device, 10: optical system, 12: solid-state imaging element, 100: pixel array, 120: pixel, 102: control circuit, 104: horizontal control circuit, 106: vertical control circuit, 108: signal processing circuit, 20: first pixel circuit, 200: light receiving element, 202: transfer transistor, 204: reset transistor, 206: amplification transistor, 208: switch, FD: floating diffusion region, VDD: first power supply voltage line, 30: second pixel circuit, 300: node, C1: first capacitor, C2: second capacitor, M1: first transistor, M2: second transistor, M3: third transistor, M4, M41, M42: fourth transistor, M5: fifth transistor, M6: sixth transistor, VREG: second power supply voltage line, VSL: Output signal line, 14: memory unit, 16: control unit, 18: I / F

Claims

1. A solid-state imaging device comprising a first pixel circuit and a second pixel circuit, wherein the first pixel circuit has at least a photoelectric conversion element which outputs a signal according to received light, and an amplifying transistor to whose gate a signal output from the photoelectric conversion element is applied and one end is connected to a first power supply voltage line, and the second pixel circuit has at least a first capacitor having one end connected to the other end of the amplifying transistor, a first transistor having one end connected to the other end of the first capacitor, a second capacitor having one end connected to the other end of the amplifying transistor, a second transistor having one end connected to the other end of the second capacitor and the other end connected to the other end of the first transistor, a third transistor having one end connected to a second power supply voltage line and the other end connected to the other end of the first transistor and the other end of the second transistor, and a fourth transistor having one end connected to the second power supply voltage line and the other end connected to one end of the first capacitor and one end of the second capacitor.

2. The solid-state imaging device according to claim 1, wherein no current source is provided on the other end side of the amplifying transistor.

3. The solid-state imaging device according to claim 1, wherein, during precharging in a reset period, the first transistor, the third transistor and the fourth transistor are turned on, and the second transistor is turned off.

4. The solid-state imaging device according to claim 3, wherein, in a precharge during a reset period, the first capacitor holds a charge based on the performance of the first transistor, the third transistor, and the fourth transistor.

5. The solid-state imaging device according to claim 3, wherein, in a reset level transfer during a reset period, the first transistor and the third transistor are turned on, and the second transistor and the fourth transistor are turned off.

6. The solid-state imaging device according to claim 5, wherein, during reset level transfer in the reset period, the first capacitor holds charge based on the reset level of the pixel output from the amplifying transistor.

7. The solid-state imaging device according to claim 5, wherein, at a reset level output timing in a reset period, the first transistor and the fourth transistor are turned on, and the second transistor and the third transistor are turned off.

8. The solid-state imaging device according to claim 3, wherein, during precharging in a data transfer period, the second transistor, the third transistor and the fourth transistor are turned on, and the first transistor is turned off.

9. The solid-state imaging device according to claim 8, wherein, in a precharge during a data transfer period, the second capacitor holds a charge based on the performance of the second transistor, the third transistor, and the fourth transistor.

10. The solid-state imaging device according to claim 8, wherein, during data transfer in a data transfer period, the second transistor and the third transistor are turned on, and the first transistor and the fourth transistor are turned off.

11. The solid-state imaging device according to claim 10, wherein, during data transfer during a data transfer period, the second capacitor holds a charge based on a pixel signal level output from the amplifying transistor.

12. The solid-state imaging device according to claim 1, further comprising a switch between the other end of the amplifying transistor and one end of the first capacitor, one end of the second capacitor, and the other end of the fourth transistor.

13. The solid-state imaging device of claim 1, further comprising a subsequent circuit, the subsequent circuit having: a fifth transistor having a gate connected to the other end of the third transistor and one end connected to a third power supply voltage line; and a sixth transistor having one end connected to the other end of the fifth transistor and the other end connected to an output signal line.

14. The solid-state imaging device according to claim 13, further comprising a signal processing circuit that generates image data based on an output from the output signal line.

15. An electronic device comprising: a plurality of first pixel circuits as recited in claim 13; a plurality of second pixel circuits as recited in claim 13 corresponding to the plurality of first pixel circuits; a plurality of subsequent circuits as recited in claim 13 corresponding to the plurality of second pixel circuits; and a signal processing circuit that generates image data based on output from the output signal line.

16. A solid-state imaging device comprising a first pixel circuit and a second pixel circuit, wherein the first pixel circuit has at least a photoelectric conversion element which outputs a signal according to received light, and an amplifying transistor to whose gate a signal output from the photoelectric conversion element is applied and one end is connected to a first power supply voltage line, and the second pixel circuit has at least a first capacitor having one end connected to the other end of the amplifying transistor, a first transistor having one end connected to the other end of the first capacitor, a second capacitor having one end connected to the other end of the amplifying transistor, a second transistor having one end connected to the other end of the second capacitor and the other end connected to the other end of the first transistor, a third transistor having one end connected to a second power supply voltage line and the other end connected to the other end of the first transistor and the other end of the second transistor, and a fourth transistor connected to release the capacitance of the first capacitor and the second capacitor.

17. The solid-state imaging device according to claim 16, wherein one end of the fourth transistor is connected to one end of the first capacitor and one end of the second capacitor, and the other end is connected to the other end of the first transistor and the other end of the second transistor.

18. The solid-state imaging device of claim 16, comprising two fourth transistors, one of the fourth transistors having one end connected to one end of the first capacitor and the other end connected to the other end of the first capacitor, and the other of the fourth transistor having one end connected to one end of the second capacitor and the other end connected to the other end of the second capacitor.

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