Multilayer ceramic electronic component and method for manufacturing same

Abstract

This multilayer ceramic electronic component has: a lamination body in which inner electrode layers and dielectric layers are alternately laminated and which has a substantially rectangular parallelepiped shape; and a pair of outer electrodes which are connected to the inner electrode layers alternately drawn out, at two end faces directed in a substantially orthogonal direction with respect to the lamination direction of the lamination body. The lamination body has: a capacitance formation part in which the inner electrode layers connected to the mutually different outer electrodes face each other with the dielectric layers therebetween so as to form capacitances; and an end margin part which is located, in the substantially orthogonal direction, on an end face side viewed from the capacitance formation part. In a cross section of the lamination body along the lamination direction and the substantially orthogonal direction, the ratio of the number of flat ceramic particles with respect to the number of all ceramic particles per unit area within the end margin part is greater than the ratio of the number of the flat ceramic particles with respect to the number of all ceramic particles per unit area within the capacitance formation part.　

Description

Multilayer ceramic electronic component and its manufacturing method

[0001] The present invention relates to a multilayer ceramic electronic component and a method for manufacturing the same.

[0002] When a voltage is applied to a multilayer ceramic electronic component such as a multilayer ceramic capacitor from an external electrode, in a laminate in which dielectric layers and internal electrode layers are stacked, an electric field may concentrate at the tips of the internal electrode layers, causing dielectric breakdown and reducing reliability. For example, Patent Document 1 describes that in a multilayer ceramic capacitor, to prevent local dielectric breakdown between the internal electrode layers due to electric field concentration at the tips of the internal electrode layers, the dielectric layer in the relevant portion is made thicker than the other dielectric layers.

[0003] Japanese Patent Application Laid-Open No. 2016-197645

[0004] However, increasing the thickness of the dielectric layers not only increases the size of the multilayer ceramic capacitor, but also makes it difficult to effectively suppress dielectric breakdown, since dielectric breakdown can occur between the internal electrode layers and the external electrodes.

[0005] SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a multilayer ceramic electronic component that can improve reliability, and a method for manufacturing the same.

[0006] The present invention provides a multilayer ceramic electronic component comprising: a laminate having a substantially rectangular parallelepiped shape in which internal electrode layers and dielectric layers are alternately stacked; and a pair of external electrodes connected to the internal electrode layers, which are alternately drawn out to two end faces of the laminate facing a direction substantially perpendicular to the stacking direction, among the six faces of the laminate; the laminate has a capacitance-forming portion in which the internal electrode layers connected to different external electrodes face each other via the dielectric layer so as to form a capacitance; and an end margin portion located on the end face side as viewed from the capacitance-forming portion in the substantially perpendicular direction; and in a cross section of the laminate taken along the stacking direction and the substantially perpendicular direction, the ratio of the number of flat ceramic particles per unit area in the end margin portion to the number of all ceramic particles per unit area is greater than the ratio of the number of the flat ceramic particles to the number of all ceramic particles per unit area in the capacitance-forming portion.

[0007] In the above-described multilayer ceramic electronic component, the flat ceramic particles may be arranged so that their longitudinal direction is aligned with the substantially perpendicular direction.

[0008] In the above-described monolithic ceramic electronic component, the ratio of the major axis to the minor axis of the flat ceramic particles may be 1.3 or more.

[0009] The method for manufacturing a multilayer ceramic electronic component of the present invention includes the steps of: forming a laminate having a substantially rectangular parallelepiped shape in which unsintered internal electrode layers and dielectric layers are alternately stacked; forming unsintered external electrodes by applying a conductive paste containing a ceramic-based co-material to two end faces of the six faces of the laminate, which are oriented in a direction substantially perpendicular to the stacking direction of the laminate and from which first ends of the internal electrode layers are alternately drawn, and to two main faces of the laminate facing the stacking direction; and firing the laminate on which the external electrodes have been formed. In the step of forming the external electrodes, the internal electrode layers connected to different external electrodes face each other via the dielectric layer so as to form a capacitance in the laminate. In the process of applying the conductive paste to regions adjacent to the end faces on the two main surfaces so as to sandwich the end margins located on the end face sides in the approximately orthogonal direction from above and below in the stacking direction, and firing the laminate, pressure is applied from the fired external electrode on the adjacent region to the unsintered end margins for a time corresponding to the amount of added co-material, so that in a cross section of the laminate taken along the stacking direction and the approximately orthogonal direction, the ratio of the number of flat ceramic particles per unit area in the end margins to the number of all ceramic particles per unit area in the end margins is greater than the ratio of the number of flat ceramic particles to the number of all ceramic particles per unit area in the capacitance forming portion.

[0010] According to the present invention, the reliability of multilayer ceramic electronic components can be improved.

[0011] FIG. 1 is a perspective view showing an example of a multilayer ceramic capacitor. FIG. 2 is a cross-sectional view of the multilayer ceramic capacitor taken along line A-A in FIG. 1. FIG. 3 is a cross-sectional view of the multilayer ceramic capacitor taken along line B-B in FIG. 2. FIG. 4 is a cross-sectional view of the multilayer ceramic capacitor taken along line C-C in FIG. 2. FIG. 5 is a cross-sectional view showing an example of an electric field generated within a laminate when a voltage is applied to the multilayer ceramic capacitor from external electrodes. FIG. 6 is a cross-sectional view showing an example of the microstructure of a central region of a dielectric layer in the longitudinal direction of the laminate. FIG. 7 is a cross-sectional view showing an example of the microstructure of an end region of a dielectric layer on an end margin side in the longitudinal direction of the laminate. FIG. 8 is a flowchart showing an example of a manufacturing process for a multilayer ceramic capacitor. FIG. 9 is a cross-sectional view showing the green sheet forming process, the internal electrode pattern forming process, the end margin forming process, and the lamination and pressure-bonding process.

[0012] (Configuration of Multilayer Ceramic Capacitor) Fig. 1 is a perspective view showing an example of a multilayer ceramic capacitor 1. Fig. 2 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line A-A in Fig. 1. Fig. 3 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line B-B in Fig. 2. Fig. 4 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line CC in Fig. 2.

[0013] The multilayer ceramic capacitor 1 has a laminate 2 having a substantially rectangular parallelepiped shape and external electrodes 3 a, 3 b provided on a pair of opposing end faces 2A, 2B of the laminate 2. The multilayer ceramic capacitor 1 is an example of a multilayer ceramic electronic component. Other examples of multilayer ceramic electronic components include a multilayer ceramic varistor and a multilayer ceramic thermistor, and in this embodiment, the multilayer ceramic capacitor 1 is used as a representative example of these.

[0014] 1 to 4 show mutually orthogonal X, Y, and Z directions. The X direction is the length (L) direction of the multilayer ceramic capacitor 1 and coincides with the direction in which a pair of end faces 2A, 2B of the laminate 2 face each other. The Y direction is the width (W) direction of the multilayer ceramic capacitor 1 and coincides with the direction in which a pair of side faces 2E, 2F of the laminate 2 face each other. The Z direction is the height (T) direction of the multilayer ceramic capacitor 1 and coincides with the direction in which the upper surface 2C and the lower surface 2D of the laminate 2 face each other and the stacking direction of the laminate 2. The length direction is an example of a direction approximately orthogonal to the stacking direction of the laminate 2, and the two end faces 2A, 2B face the length direction.

[0015] The laminate 2 has six surfaces: an upper surface 2C, a lower surface 2D, a pair of end surfaces 2A and 2B, and a pair of side surfaces 2E and 2F. The upper surface 2C and the lower surface 2D are generally flat surfaces that face each other in the stacking direction, the pair of end surfaces 2A and 2B are generally flat surfaces that face each other in the length direction, and the pair of side surfaces 2E and 2F are generally flat surfaces that face each other in the width direction. The upper surface 2C and the lower surface 2D are examples of two main surfaces of the laminate 2 that face the stacking direction.

[0016] The laminate 2 has a laminated structure in which dielectric layers 22, which are mainly composed of a ceramic material that functions as a dielectric, and internal electrode layers 23 are alternately stacked.

[0017] The internal electrode layers 23 have a substantially rectangular shape when viewed from the front in the stacking direction, and face each other in the stacking direction across the dielectric layer 22. One end 231 of the internal electrode layers 23 is drawn out alternately to the end faces 2A, 2B along the stacking direction and connected to the external electrodes 3 a, 3 b.

[0018] The internal electrode layers 23 are mainly composed of base metals such as Ni (nickel), Cu (copper), and Sn (tin). Noble metals such as Pt (platinum), Pd (palladium), Ag (silver), and Au (gold), or alloys containing these metals, may also be used as the internal electrode layers 23. The thickness of the internal electrode layers 23 is, for example, 0.05 to 0.6 μm or less.

[0019] The dielectric layer 22 is, for example, a compound represented by the general formula ABO ３The main phase is a ceramic material having a perovskite structure represented by the formula: ３－α (α indicates a small number). For example, the ceramic material includes BaTiO ３ (barium titanate), CaZrO ３ (Calcium zirconate), CaTiO ３ (Calcium titanate), SrTiO ３ (strontium titanate), MgTiO ３ (magnesium titanate), Ba that forms a perovskite structure １-ｘ－ｙ Ca ｘ Sr ｙ Ti １－ｚ Zr ｚ O ３ (0≦x≦1, 0≦y≦1, 0≦z≦1) and the like. １-ｘ－ｙ Ca ｘ Sr ｙ Ti １－ｚ Zr ｚ O ３ are barium strontium titanate, barium calcium titanate, barium zirconate, barium titanate zirconate, calcium titanate zirconate, barium calcium titanate zirconate, etc. The thickness of the dielectric layer 22 is, for example, 0.3 to 4.0 μm or less.

[0020] As shown in FIG. 2 , the laminate 2 has a capacitance-forming portion 27 and a pair of end margins 24 that constitute a region of the laminate structure. The capacitance-forming portion 27 is a region where the internal electrode layers 23 connected to different external electrodes 3 a, 3 b face each other via the dielectric layer so as to form a capacitance. The end margins 24 are regions located on the end faces 2A, 2B side as viewed from the capacitance-forming portion 27. The boundary between the capacitance-forming portion 27 and the end margins 24 is determined by the longitudinal position of the end portions 230 of the internal electrode layers 23 that are not drawn out to the end faces 2A, 2B. Therefore, the end margins 24 include a region where the internal electrode layers 23 connected to the common external electrodes 3 a, 3 b face each other.

[0021] The laminate 2 further has a pair of cover layers 20, 21 laminated so as to sandwich the capacitance forming portion 27 and the end margin portion 24 from both sides in the stacking direction, and a pair of side margin portions 40, 41 provided so as to sandwich the capacitance forming portion 27 and the end margin portion 24 from both sides in the width direction. The cover layers 20, 21 form an upper surface 2C and a lower surface 2D of the laminate 2. The cover layers 20, 21 extend in the length direction and width direction, covering the capacitance forming portion 27 and the end margin portion 24 from both sides in the stacking direction.

[0022] The side margins 40, 41 form the side surfaces 2E, 2F of the laminate 2. The side margins 40, 41 extend along the length direction and sandwich the capacitance forming portion 27 and the cover layers 20, 21 from both sides in the width direction, as shown in Fig. 3. The side margins 40, 41 are mainly composed of the same ceramic material as the dielectric layer 22.

[0023] The end margin portion 24 is mainly composed of the same ceramic material as the dielectric layer 22. As will be described later, the end margin portion 24 has a higher density of flat ceramic particles than the capacitance forming portion 27. Therefore, even if an electric field concentrates at the end portion 230 when a voltage is applied to the external electrodes 3 a, 3 b, the effect of this concentration can be reduced.

[0024] The external electrodes 3a, 3b cover end faces 2A, 2B of the laminate 2 that face each other in the longitudinal direction of the multilayer ceramic capacitor 1. The external electrodes 3a, 3b extend to regions 2Ca, 2Cb, 2Da, 2Db, 2Ea, 2Eb, 2Fa, and 2Fb adjacent to the end faces 2A and 2B on the top face 2C, bottom face 2D, and side faces 2E and 2F. However, the external electrodes 3a, 3b are spaced apart from each other on the surfaces of the top face 2C, bottom face 2D, and side faces 2E and 2F.

[0025] The external electrodes 3a, 3b are primarily composed of a metal such as Cu, Ni, Al (aluminum), or Zn (zinc), or an alloy of two or more of these metals (e.g., an alloy of Cu and Ni). They also contain ceramics such as a glass component for densifying the external electrodes 3a, 3b and a co-material for controlling the sinterability of the external electrodes 3a, 3b. The glass component is an oxide of Ba (barium), Sr (strontium), Ca (calcium), Zn (zinc), Al, Si (silicon), or B (boron). The co-material is primarily composed of, for example, the same ceramic material as the primary component of the dielectric layer 22. A plating film primarily composed of a base metal such as Ni, Cu, or Sn may be formed on the surface of the external electrodes 3a, 3b. A conductive resin film such as an epoxy resin or a urethane resin may also be formed on the surface of the plating film.

[0026] 2, the external electrodes 3a, 3b covering adjacent regions 2Ca, 2Cb, 2Da, 2Db in the upper surface 2C and the lower surface 2D are inclined above and below in the stacking direction so as to form a generally V-shape with respect to the laminate 2, and sandwich the end margin 24 and the longitudinal ends of the cover layers 20, 21 from above and below in the stacking direction. As will be described later, in the manufacturing process of the multilayer ceramic capacitor 1, when the laminate 2 is fired, the external electrodes 3a, 3b are sintered before the dielectric layers 22 and end margins 24, and pressure is applied to the end margins 24 and the ends of the adjacent dielectric layers 22, making it possible to form the flat ceramic particles that make up these electrodes at a high density.

[0027] (Electric Field Within the Laminate) Figure 5 is a cross-sectional view showing an example of an electric field generated within the laminate 2 when a voltage is applied to the multilayer ceramic capacitor 1 from the external electrodes 3a, 3b. Figure 5 shows electric field lines (see dotted lines) within the two dielectric layers 22u, 22d in a portion of the cross section of the laminate 2 shown in Figure 2. In Figure 5, components common to those in Figure 2 are designated by the same reference numerals, and their description will be omitted.

[0028] The dielectric layer 22u is sandwiched between the internal electrode layers 23u and 23m, and the dielectric layer 22d is sandwiched between the internal electrode layers 23m and 23d in the stacking direction of the laminate 2. The end margins 24 are provided on the end face 2A side of the end 230 of the internal electrode layer 23m and on the end face 2B side of the end 230 of the internal electrode layers 23u and 23d, respectively.

[0029] An electric field is generated between the external electrode 3a and the internal electrode layers 23u, 23d, which have opposite polarities, and between the external electrode 3b and the internal electrode layer 23m. The electric field is concentrated more at the ends 230 of the internal electrode layers 23u, 23m, 23d that are not connected to the external electrodes 3a, 3b than at other parts. For this reason, dielectric breakdown may occur in the end margins 24 adjacent to the ends 230 and in the vicinity thereof, reducing reliability.

[0030] Therefore, dielectric breakdown is suppressed by forming the dielectric region of the end margin portion 24 with flat ceramic particles that are denser than the region of the capacitance forming portion 27. The microstructures of the central region Pc in the capacitance forming portion 27 and the end region Pe in the end margin portion 24 will be described below as examples.

[0031] (Microstructure of Dielectric Region) Fig. 6 is a cross-sectional view showing an example of the microstructure of the central region Pc of the dielectric layer 22 in the longitudinal direction of the laminate 2. Fig. 7 is a cross-sectional view showing an example of the microstructure of the end region Pe of the dielectric layer 22 on the end margin 24 side in the longitudinal direction of the laminate 2. That is, Fig. 6 shows an example of the microstructure of the central region Pc in the capacitance forming portion 27, and Fig. 7 shows an example of the microstructure of the end region Pe in the end margin 24. In Figs. 6 and 7, components common to Fig. 4 are designated by the same reference numerals, and descriptions thereof will be omitted.

[0032] The central region Pc contains, as the ceramic material, more highly isotropic ceramic particles 220 than less isotropic, flat-shaped ceramic particles 221, whereas the edge region Pe contains, as the ceramic material, more less isotropic, flat-shaped ceramic particles 221 than more isotropic ceramic particles 220. The edge region Pe contains a higher density of flat-shaped ceramic particles 221 than other dielectric regions such as the central region Pc.

[0033] The grain boundaries between the flat ceramic particles 221 form longer conductive paths than the grain boundaries between the highly isotropic ceramic particles 220. Therefore, the insulation resistance of the edge regions Pe is higher than the insulation resistance of other dielectric regions such as the central region Pc, effectively suppressing dielectric breakdown. This improves the reliability of the multilayer ceramic capacitor 1.

[0034] The end region Pe includes, as an end margin portion 24, end portions 25, 26 of the dielectric layers 22u, 22d and an adjacent portion 28 adjacent to the end portion 230 of the internal electrode layer 23m in the longitudinal direction. The end portions 25, 26 of the dielectric layers 22u, 22d are regions closer to the external electrode 3b than the end portion 230 of the internal electrode layer 23m in the longitudinal direction. The adjacent portion 28 is a region sandwiched between the end portions 25, 26 of the dielectric layers 22u, 22d on both sides in the stacking direction. The end portion 230 of the internal electrode layer 23m refers to, for example, a range of 10 μm from the end face on the external electrode 3b side toward the center.

[0035] As can be seen from Figure 5, the electric field lines are generated most densely in the end margin portion 24. Therefore, by including flat ceramic particles 221 in the end margin portion 24 at a higher density than in the dielectric region of the capacitance-forming portion 27, it is possible to effectively improve the insulation characteristics. Furthermore, if the dielectric region of the capacitance-forming portion 27 includes flat ceramic particles 221 at the same density as in the end margin portion 24, this is not preferable because it results in insufficient grain growth and makes it difficult to obtain the required capacitance. Note that flat ceramic particles 221 refer to particles whose ratio of the major axis to the minor axis is, for example, 1.2 or more.

[0036] The density of the ceramic particles 220, 221 can be measured by, for example, taking images of the cross section as shown in Figures 6 and 7 using a scanning electron microscope (SEM). For example, the number of ceramic particles 220, 221 per unit area can be calculated as the density in each of the capacitance forming portion 27 and the end margin portion 24.

[0037] Furthermore, the distribution of the flat ceramic particles 221 can be defined by the ratio of the number (n) of flat ceramic particles 221 to the number (N) of all ceramic particles 220, 221 per unit area in a cross section imaged by SEM. The ratio (n / N) of the number in each of the capacitance forming portion 27 and the end margin portion 24 is calculated. The ratio of the number in the end margin portion 24 is greater than the ratio of the number in the capacitance forming portion 27. As a result, the end margin portion 24 is formed of flat ceramic particles with a higher density than the capacitance forming portion 27, thereby suppressing dielectric breakdown.

[0038] The flat ceramic particles 221 are arranged such that their longitudinal direction is along the length direction of the laminate 2. Therefore, compared to, for example, a case where the longitudinal direction of the flat ceramic particles 221 is along the stacking direction of the laminate 2, the distance of the interface between the flat ceramic particles 221 between the end 230 of the internal electrode layer 23 m and the external electrode 3 b is extended, and the insulation resistance can be increased.

[0039] Furthermore, the ratio of the major axis to the minor axis of the flat ceramic particles 221 is preferably 1.3 or more. This ratio ensures a sufficient grain boundary distance, thereby further improving the reliability of the multilayer ceramic capacitor 1. The minor axis and major axis of the flat ceramic particles 221 can be measured by imaging a cross section of the multilayer ceramic capacitor 1 with an SEM.

[0040] (Manufacturing Process of Multilayer Ceramic Capacitor) Fig. 8 is a flowchart showing an example of a manufacturing process of the multilayer ceramic capacitor 1. This manufacturing process is an example of a method for manufacturing a multilayer ceramic electronic component.

[0041] 9 is a cross-sectional view showing the green sheet forming step St1, the internal electrode pattern forming step St2, the end margin forming step St3, and the lamination and pressure bonding step St4. FIG. 9 shows a cross section along the lamination direction and the length direction of the multilayer ceramic capacitor 1.

[0042] (Green Sheet Formation Process) First, the green sheet formation process St1 is performed. In the green sheet formation process St1, green sheets 7a and 7b are formed by applying a ceramic slurry to a substrate (not shown). The ceramic slurry is obtained by wet-mixing a dielectric material obtained by adding various additive compounds (such as sintering aids) to ceramic powder, a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer. The ceramic slurry is then applied to the substrate by, for example, a die coater method or a doctor blade method, to form green sheets 7a and 7b, which are then dried. The substrate is, for example, a PET (polyethylene terephthalate) film.

[0043] The additive compounds for the ceramic powder include oxides of Mg (magnesium), Mn (manganese), V (vanadium), Cr (chromium), rare earth elements (Y (yttrium), Sm (samarium), Eu (europium), Gd (gadolinium), Tb (terbium), Dy (dysprosium), Ho (holmium), Er (erbium), Tm (thulium), and Yb (ytterbium)), as well as oxides or glasses of Co (cobalt), Ni, Li (lithium), B (boron), Na (sodium), K (potassium), and Si (silicon).

[0044] (Internal Electrode Pattern Forming Process) Next, the internal electrode pattern forming process St2 is performed. In the internal electrode pattern forming process St2, the internal electrode patterns 6a and 6b are formed by applying conductive paste to the green sheets 7a and 7b, respectively. The internal electrode patterns 6a and 6b become the internal electrode layers 23 after firing. The internal electrode patterns 6a and 6b are shifted from each other by half a pitch in the X direction.

[0045] In the internal electrode pattern forming process St2, a metal conductive paste containing an organic binder for forming the internal electrodes is printed on the green sheets 7a and 7b by gravure printing or the like, thereby forming multiple internal electrode patterns 6a and 6b at a distance from each other. A dielectric is added to the conductive paste as a co-material. The internal electrode patterns 6a and 6b may be formed by a vacuum deposition method such as sputtering, without being limited to printing. (Margin Layer Forming Process) Next, the margin layer forming process St3 is performed. In the margin layer forming process St3, a ceramic slurry similar to that described above is applied to the stepped portions formed by the internal electrode patterns 6a and 6b on the green sheets 7a and 7b. The ceramic slurry is applied in a reverse pattern to the internal electrode patterns 6a and 6b. This forms a margin layer 8 to fill the stepped portions. The margin layer 8 becomes part of the end margin portion 24 after firing.

[0046] (Laminating and Press-bonding Step) Next, the laminating and press-bonding step St4 is performed. In the laminating and press-bonding step St4, a plurality of green sheets 7a, 7b are alternately laminated and pressed together.

[0047] The plurality of green sheets 7a, 7b are sandwiched and pressed between other green sheets 7c, 7d, which will become cover layers 20, 21 after firing, from above and below in the stacking direction. An internal electrode pattern 6b is formed on the surface of the bottommost green sheet 7d by the same method as in the internal electrode pattern forming step St2. Examples of pressing means include, but are not limited to, an isostatic press.

[0048] (Cutting Process) Next, the cutting process St5 is performed. In the cutting process St5, the pressed green sheets 7a to 7d are cut, for example, with a blade along multiple cut lines LW extending vertically and horizontally at regular intervals. This separates the green sheets 7a to 7d into multiple pre-fired laminates 2. FIG. 9 shows the cut lines LW along the width direction of the laminate 2. The cut lines LW pass through approximately the center of the margin layer 8 in the longitudinal direction. The ends of the green sheets 7a, 7b and the internal electrode patterns 6a, 6b that overlap the cut margin layer 8 in the stacking direction become end margin portions 24 after firing. Furthermore, the ends of the internal electrode patterns 6a, 6b are exposed on the end faces 2A, 2B, which are the cut surfaces of the laminate 2. The processes from the green sheet formation process St1 to the cutting process St5 are an example of a process for forming a substantially rectangular parallelepiped laminate 2 in which unsintered internal electrode layers 23 and dielectric layers 22 are alternately stacked.

[0049] (External Electrode Forming Process) Next, the external electrode forming process St6 is performed. The external electrode forming process St6 is an example of a process for forming unsintered external electrodes 3a, 3b by applying a conductive paste to the end faces 2A, 2B, the upper face 2C, and the lower face 2D of the laminate 2. The conductive paste contains, for example, metal powder, glass frit, a binder, and a solvent. Furthermore, a co-material whose main component is ceramic is added to the conductive paste to adjust sinterability.

[0050] In the external electrode formation process St6, conductive paste is applied to each end face 2A, 2B of the laminate 2, and to adjacent regions 2Ca, 2Cb, 2Da, 2Db, 2Ea, 2Eb, 2Fa, and 2Fb on the end face 2A, 2B side of the upper face 2C, lower face 2D, and each side face 2E, 2F. Thus, the conductive paste is applied to the adjacent regions 2Ca, 2Cb, 2Da, and 2Db so as to sandwich the end margin portion 24 of the laminate 2 before firing from above and below in the stacking direction. The conductive paste becomes the external electrodes 3a and 3b after firing. A dipping method, for example, is used as a means for applying the conductive paste.

[0051] (Firing Step) Next, the firing step St7 is performed. The firing step St7 is an example of a step of firing the laminate on which the unfired external electrodes 3a, 3b are formed.

[0052] The laminate 2 before firing is heated to 250 to 500°C in N ２ After the binder is removed in this atmosphere, the laminate is fired for about one hour at a firing temperature of 1200°C or higher in a reducing atmosphere with an oxygen partial pressure of 0.003 Pa. This sinters the conductive paste that will become the external electrodes 3a, 3b, and also sinters the particles in the pre-fired laminate 2. In the sintered laminate 2, the green sheets 7a to 7d become the dielectric layer 22 and cover layers 20, 21, and the internal electrode patterns 6a, 6b become internal electrode layers 23. Furthermore, the ends of the green sheets 7a, 7b and the internal electrode patterns 6a, 6b that overlap the margin layer 8 in the stacking direction become end margin portions 24 after firing, and the remaining central portions of the green sheets 7a, 7b and the internal electrode patterns 6a, 6b become capacitance-forming portions 27 after firing.

[0053] The external electrodes 3a, 3b are formed on adjacent regions 2Ca, 2Cb, 2Da, 2Db on the upper surface 2C and the lower surface 2D, sandwiching both longitudinal ends of the laminate 2 from above and below in the stacking direction. Therefore, pressure is applied from the external electrodes 3a, 3b, which were sintered before the end margins 24 and the dielectric layers 22, to the end margins 24 and the regions of the dielectric layers 22 on the end faces 2A, 2B sides during sintering. In response to this pressure, the ceramic grains constituting the end margins 24 receive stress from above and below in the stacking direction, causing grain growth so as to extend in the longitudinal direction. This results in the formation of a microstructure as shown in FIGS. 6 and 7.

[0054] In order for the end margin portions 24 to contain flat ceramic particles 221 at a higher density than the capacitance-forming portions 27, the duration of pressure application is controlled by the amount of co-material added to the conductive paste that forms the external electrodes 3 a, 3 b. For example, assuming that the dielectric region in the laminate 2 is sintered at 1100°C, pressure can be applied to the end margin portions 24 for a longer period of time when the pressure of the external electrodes 3 a, 3 b is applied from 700°C than when it is applied from 900°C. In the end margin portions 24, the longer pressure is applied, the more flat ceramic particles 221 grow.

[0055] The smaller the amount of co-material added, the lower the sintering temperature of the conductive paste, ensuring a longer pressure application time. Specifically, the weight ratio of the ceramic co-material to the weight of the main component metal in the conductive paste is determined so that the sintering temperature of the conductive paste is appropriate. For example, a weight ratio of 100:7 is preferable. Thus, in the firing step St7, pressure is applied from the fired external electrodes 3a, 3b on the adjacent regions 2Ca, 2Cb, 2Da, and 2Db on the upper surface 2C and the lower surface 2D to the unsintered end margin portion 24 for a time corresponding to the amount of co-material added, so that the ratio of the number of flat-shaped ceramic particles 221 to the number of all ceramic particles 220, 221 per unit area in the end margin portion 24 in the cross section of the laminate 2 along the stacking direction and the direction approximately perpendicular to the stacking direction is greater than the ratio of the number of flat-shaped ceramic particles 221 to the number of all ceramic particles 220, 221 per unit area in the capacitance-forming portion 27.

[0056] Furthermore, in the firing step St7, after the conductive paste is sintered to form the external electrodes 3a, 3b, pressure is applied from above and below in the stacking direction to the dielectric layers 22 and end margin portions 24 at both ends in the longitudinal direction of the laminate 2. Therefore, the stress caused by the contraction of the internal electrode layers 23 due to sintering is reduced by the pressure from the external electrodes 3a, 3b. Therefore, the occurrence of cracks in the laminate 2 due to stress is suppressed.

[0057] Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and changes are possible within the scope of the gist of the present invention as described in the claims.

[0058] REFERENCE SIGNS LIST 1 Multilayer ceramic capacitor 2 Laminate 3a, 3b External electrodes 6a, 6b Internal electrode patterns 7a to 7d Green sheets 8 Margin layer 22 Dielectric layer 23 Internal electrode layer 24 End margin portion 220, 221 Ceramic particles 25, 26, 230, 231 End portion

Claims

1. A multilayer ceramic electronic component comprising: a laminate having a substantially rectangular parallelepiped shape in which internal electrode layers and dielectric layers are alternately stacked; and a pair of external electrodes connected to the internal electrode layers alternately drawn out to two end faces of the six faces of the laminate, the two end faces facing in a direction substantially perpendicular to the stacking direction of the laminate; the laminate having a capacitance forming portion in which the internal electrode layers connected to different external electrodes face each other via the dielectric layer to form a capacitance, and an end margin portion located on the end face side as viewed from the capacitance forming portion in the substantially perpendicular direction; and in a cross section of the laminate taken along the stacking direction and the substantially perpendicular direction, a ratio of the number of flat ceramic particles to the number of all ceramic particles per unit area in the end margin portion is greater than a ratio of the number of the flat ceramic particles to the number of all ceramic particles per unit area in the capacitance forming portion.

2. The multilayer ceramic electronic component according to claim 1, wherein the flat ceramic particles are arranged so that their longitudinal direction is aligned approximately along the perpendicular direction.

3. The multilayer ceramic electronic component according to claim 1 or 2, wherein the ratio of the major axis to the minor axis of said flat ceramic particles is 1.3 or more.

4. The method includes the steps of forming a laminate having a substantially rectangular parallelepiped shape in which unsintered internal electrode layers and dielectric layers are alternately stacked; forming unsintered external electrodes by applying a conductive paste containing a common material mainly composed of ceramic to two end faces of the six faces of the laminate, which face a direction substantially perpendicular to the stacking direction of the laminate and from which the first ends of the internal electrode layers are alternately pulled out, and to two main faces of the laminate facing the stacking direction; and firing the laminate on which the external electrodes are formed. In the step of forming the external electrodes, the conductive paste is applied to adjacent areas of the end faces on the two main faces so as to sandwich, from above and below in the stacking direction, end margin portions located on the end face side in the substantially perpendicular direction of a capacitance forming portion in the laminate in which the internal electrode layers connected to different external electrodes face each other via the dielectric layer to form a capacitance, A method for manufacturing a laminated ceramic electronic component, characterized in that in the process of firing the laminate, pressure is applied from the fired external electrode on the adjacent region to the unsintered end margin portion for a time corresponding to the amount of the common material added, so that in a cross section of the laminate along the stacking direction and the approximately perpendicular direction, the ratio of the number of flat ceramic particles to the number of all ceramic particles per unit area in the end margin portion is greater than the ratio of the number of the flat ceramic particles to the number of all ceramic particles per unit area in the capacitance forming portion.

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